From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 0C3C13990 for ; Thu, 14 Apr 2016 11:57:59 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 14 Apr 2016 02:57:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,484,1455004800"; d="scan'208";a="958497757" Received: from gklab-246-018.igk.intel.com (HELO stargo) ([10.217.246.18]) by fmsmga002.fm.intel.com with SMTP; 14 Apr 2016 02:57:57 -0700 Received: by stargo (sSMTP sendmail emulation); Thu, 14 Apr 2016 11:59:38 +0200 From: Piotr Azarewicz To: helin.zhang@intel.com, konstantin.ananyev@intel.com Cc: dev@dpdk.org, Piotr Azarewicz Date: Thu, 14 Apr 2016 11:59:30 +0200 Message-Id: <1460627970-20864-1-git-send-email-piotrx.t.azarewicz@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [dpdk-dev] [PATCH v1 1/1] ixgbe: fix queue stop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Apr 2016 09:58:00 -0000 It should be checked if queue enable bit is clear. CID 13215 : Wrong operator used (CONSTANT_EXPRESSION_RESULT) operator_confusion: txdctl | 33554432 is always 1/true regardless of the values of its operand. This occurs as the logical second operand of '&&'. CID 13216 : Wrong operator used (CONSTANT_EXPRESSION_RESULT) operator_confusion: rxdctl | 33554432 is always 1/true regardless of the values of its operand. This occurs as the logical second operand of '&&'. Coverity issue: 13215 Coverity issue: 13216 Fixes: 029fd06d40fa ("ixgbe: queue start and stop") Signed-off-by: Piotr Azarewicz --- drivers/net/ixgbe/ixgbe_rxtx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 9fb38a6..8483e51 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -4813,12 +4813,12 @@ ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) rxdctl &= ~IXGBE_RXDCTL_ENABLE; IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl); - /* Wait until RX Enable ready */ + /* Wait until RX Enable bit clear */ poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS; do { rte_delay_ms(1); rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); - } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE)); + } while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE)); if (!poll_ms) PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d", rx_queue_id); @@ -4914,14 +4914,14 @@ ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) txdctl &= ~IXGBE_TXDCTL_ENABLE; IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); - /* Wait until TX Enable ready */ + /* Wait until TX Enable bit clear */ if (hw->mac.type == ixgbe_mac_82599EB) { poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS; do { rte_delay_ms(1); txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); - } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE)); + } while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE)); if (!poll_ms) PMD_INIT_LOG(ERR, "Could not disable " "Tx Queue %d", tx_queue_id); -- 1.7.9.5