From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id E6C5DFFA for ; Thu, 21 Apr 2016 10:56:00 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP; 21 Apr 2016 01:56:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,512,1455004800"; d="scan'208";a="789230872" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga003.jf.intel.com with ESMTP; 21 Apr 2016 01:55:59 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id u3L8tvXx011894; Thu, 21 Apr 2016 16:55:57 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u3L8trNC018854; Thu, 21 Apr 2016 16:55:55 +0800 Received: (from beileixi@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u3L8trRN018850; Thu, 21 Apr 2016 16:55:53 +0800 From: Beilei Xing To: wenzhuo.lu@intel.com Cc: dev@dpdk.org, Beilei Xing Date: Thu, 21 Apr 2016 16:55:48 +0800 Message-Id: <1461228948-18820-1-git-send-email-beilei.xing@intel.com> X-Mailer: git-send-email 1.7.4.1 Subject: [dpdk-dev] [PATCH] e1000: configure VLAN TPID X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Apr 2016 08:56:01 -0000 This patch enables configuring the ether types of both inner and outer VLANs. Note that TPID of single or inner VLAN is read only. Signed-off-by: Beilei Xing --- drivers/net/e1000/igb_ethdev.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index e0053fe..c957fbe 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -86,6 +86,14 @@ #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000 +/* CTRL_EXT bit mask*/ +#define E1000_CTRL_EXT_EXT_VLAN (1 << 26) + +/* VLAN Ether Type bit mask */ +#define E1000_VET_VET_EXT 0xFFFF0000 + +#define E1000_VET_VET_EXT_SHIFT 16 + static int eth_igb_configure(struct rte_eth_dev *dev); static int eth_igb_start(struct rte_eth_dev *dev); static void eth_igb_stop(struct rte_eth_dev *dev); @@ -2242,13 +2250,33 @@ eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, { struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t reg = ETHER_TYPE_VLAN; + uint32_t reg; + uint32_t qinq; int ret = 0; + qinq = E1000_READ_REG(hw, E1000_CTRL_EXT); + qinq &= E1000_CTRL_EXT_EXT_VLAN; + switch (vlan_type) { case ETH_VLAN_TYPE_INNER: - reg |= (tpid << 16); - E1000_WRITE_REG(hw, E1000_VET, reg); + if (qinq) + PMD_DRV_LOG(WARNING, + "inner vlan ether type is read-only\n"); + else { + PMD_DRV_LOG(ERR, "not set QinQ on yet\n"); + ret = -EIO; + } + break; + case ETH_VLAN_TYPE_OUTER: + if (qinq) { + reg = E1000_READ_REG(hw, E1000_VET); + reg = (reg & (~E1000_VET_VET_EXT)) | + ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT); + E1000_WRITE_REG(hw, E1000_VET, reg); + } else + PMD_DRV_LOG(WARNING, + "single vlan ether type is read-only\n"); + break; default: ret = -EINVAL; -- 2.5.0