From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-gw3-out.broadcom.com (mail-gw3-out.broadcom.com [216.31.210.64]) by dpdk.org (Postfix) with ESMTP id 1B5235AB8 for ; Tue, 7 Jun 2016 00:09:30 +0200 (CEST) X-IronPort-AV: E=Sophos;i="5.26,429,1459839600"; d="scan'208";a="96478855" Received: from mail-irv-18.broadcom.com ([10.15.198.37]) by mail-gw3-out.broadcom.com with ESMTP; 06 Jun 2016 15:28:32 -0700 Received: from mail-irva-12.broadcom.com (mail-irva-12.broadcom.com [10.11.16.101]) by mail-irv-18.broadcom.com (Postfix) with ESMTP id E9BFF82025; Mon, 6 Jun 2016 15:09:29 -0700 (PDT) Received: from DPDK-C1.broadcom.com (dhcp-10-13-115-104.irv.broadcom.com [10.13.115.104]) by mail-irva-12.broadcom.com (Postfix) with ESMTP id 6EF8B127643; Mon, 6 Jun 2016 15:09:28 -0700 (PDT) From: Stephen Hurd To: dev@dpdk.org, ajit.khaparde@broadcom.com, bruce.richardson@intel.com Date: Mon, 6 Jun 2016 15:08:27 -0700 Message-Id: <1465250923-78695-23-git-send-email-stephen.hurd@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465250923-78695-1-git-send-email-stephen.hurd@broadcom.com> References: <1465250923-78695-1-git-send-email-stephen.hurd@broadcom.com> Subject: [dpdk-dev] [PATCH v4 23/39] bnxt: add HWRM stats context allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jun 2016 22:09:31 -0000 From: Ajit Khaparde Add HWRM API code to allocate a statistics context in the ASIC. This API will be called by the previously submitted "add statistics operations patch". v4: Address review comments and fix issues pointed out by checkpatch. Signed-off-by: Ajit Khaparde Reviewed-by: David Christensen Signed-off-by: Stephen Hurd --- drivers/net/bnxt/bnxt_hwrm.c | 52 ++++++++++++++++++++ drivers/net/bnxt/bnxt_hwrm.h | 3 ++ drivers/net/bnxt/hsi_struct_def_dpdk.h | 89 ++++++++++++++++++++++++++++++++++ 3 files changed, 144 insertions(+) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 7f39db0..5d0fbf1 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -525,6 +525,31 @@ int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) return rc; } +int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, + struct bnxt_cp_ring_info *cpr, unsigned int idx) +{ + int rc; + struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 }; + struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; + + HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp); + + req.update_period_ms = rte_cpu_to_le_32(1000); + + req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); + req.stats_dma_addr = + rte_cpu_to_le_64(cpr->hw_stats_map); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + + HWRM_CHECK_RESULT; + + cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id); + bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id; + + return rc; +} + int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic) { int rc = 0, i, j; @@ -701,6 +726,33 @@ int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp) return 0; } +int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp) +{ + unsigned int i; + int rc = 0; + + for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) { + struct bnxt_tx_queue *txq; + struct bnxt_rx_queue *rxq; + struct bnxt_cp_ring_info *cpr; + unsigned int idx = i + 1; + + if (i >= bp->rx_cp_nr_rings) { + txq = bp->tx_queues[i - bp->rx_cp_nr_rings]; + cpr = txq->cp_ring; + } else { + rxq = bp->rx_queues[i]; + cpr = rxq->cp_ring; + } + + rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx); + + if (rc) + return rc; + } + return rc; +} + void bnxt_free_hwrm_resources(struct bnxt *bp) { /* Release memzone */ diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 915cf2a..f41361e 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -59,6 +59,8 @@ int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags); int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr); +int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, + struct bnxt_cp_ring_info *cpr, unsigned int idx); int bnxt_hwrm_ver_get(struct bnxt *bp); @@ -70,6 +72,7 @@ int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic); int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic); +int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp); int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp); void bnxt_free_hwrm_resources(struct bnxt *bp); int bnxt_alloc_hwrm_resources(struct bnxt *bp); diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index f8f6a3f..28362c9 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -99,6 +99,7 @@ struct ctx_hw_stats64 { #define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91)) #define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92)) #define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93)) +#define HWRM_STAT_CTX_ALLOC (UINT32_C(0xb0)) #define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3)) #define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0)) @@ -3183,6 +3184,94 @@ struct hwrm_queue_qportcfg_input { uint16_t unused_0; } __attribute__((packed)); +/* hwrm_stat_ctx_alloc */ +/* + * Description: This command allocates and does basic preparation for a stat + * context. + */ + +/* Input (32 bytes) */ +struct hwrm_stat_ctx_alloc_input { + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t req_type; + + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t cmpl_ring; + + /* This value indicates the command sequence number. */ + uint16_t seq_id; + + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint16_t target_id; + + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t resp_addr; + + /* This is the address for statistic block. */ + uint64_t stats_dma_addr; + + /* + * The statistic block update period in ms. e.g. 250ms, 500ms, 750ms, + * 1000ms. + */ + uint32_t update_period_ms; + + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ +struct hwrm_stat_ctx_alloc_output { + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t error_code; + + /* This field returns the type of original request. */ + uint16_t req_type; + + /* This field provides original sequence number of the command. */ + uint16_t seq_id; + + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t resp_len; + + /* This is the statistics context ID value. */ + uint32_t stat_ctx_id; + + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + /* hwrm_stat_ctx_clr_stats */ /* Description: This command clears statistics of a context. */ -- 1.9.1