From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-0016ce01.pphosted.com (mx0b-0016ce01.pphosted.com [67.231.156.153]) by dpdk.org (Postfix) with ESMTP id A741DC5BC for ; Thu, 16 Jun 2016 07:48:20 +0200 (CEST) Received: from pps.filterd (m0085408.ppops.net [127.0.0.1]) by mx0b-0016ce01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u5G5lV4S022836; Wed, 15 Jun 2016 22:48:19 -0700 Received: from avcashub1.qlogic.com ([198.186.0.117]) by mx0b-0016ce01.pphosted.com with ESMTP id 23ghmn70cv-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 15 Jun 2016 22:48:19 -0700 Received: from avluser05.qlc.com (10.1.113.115) by qlc.com (10.1.4.192) with Microsoft SMTP Server id 14.3.235.1; Wed, 15 Jun 2016 22:48:18 -0700 Received: (from rmody@localhost) by avluser05.qlc.com (8.14.4/8.14.4/Submit) id u5G5mImU023311; Wed, 15 Jun 2016 22:48:18 -0700 X-Authentication-Warning: avluser05.qlc.com: rmody set sender to rasesh.mody@qlogic.com using -f From: Rasesh Mody To: CC: , , Harish Patil Date: Wed, 15 Jun 2016 22:47:09 -0700 Message-ID: <1466056031-23225-8-git-send-email-rasesh.mody@qlogic.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1466056031-23225-1-git-send-email-rasesh.mody@qlogic.com> References: <1466056031-23225-1-git-send-email-rasesh.mody@qlogic.com> MIME-Version: 1.0 Content-Type: text/plain disclaimer: bypass X-Proofpoint-Virus-Version: vendor=nai engine=5800 definitions=8197 signatures=670729 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1606160068 Subject: [dpdk-dev] [PATCH v2 7/9] qede: add 100g mode support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Jun 2016 05:48:21 -0000 From: Harish Patil Change details: - Add device id to the PCI table - Add polling for the slowpath events for CMT mode device - Add prerequisites to allow 100g mode o Min number of queues needed is 2 o Only even number of queues are allowed - Update documentation Signed-off-by: Harish Patil --- config/common_base | 2 +- doc/guides/nics/qede.rst | 8 ++--- drivers/net/qede/qede_ethdev.c | 64 ++++++++++++++++++++++++++++++++++++++++ drivers/net/qede/qede_ethdev.h | 4 ++- 4 files changed, 72 insertions(+), 6 deletions(-) diff --git a/config/common_base b/config/common_base index aeb572e..ee4cf4d 100644 --- a/config/common_base +++ b/config/common_base @@ -297,7 +297,7 @@ CONFIG_RTE_LIBRTE_PMD_BOND=y CONFIG_RTE_LIBRTE_BOND_DEBUG_ALB=n CONFIG_RTE_LIBRTE_BOND_DEBUG_ALB_L1=n -# QLogic 25G/40G PMD +# QLogic 25G/40G/100G PMD # CONFIG_RTE_LIBRTE_QEDE_PMD=n CONFIG_RTE_LIBRTE_QEDE_DEBUG_INIT=n diff --git a/doc/guides/nics/qede.rst b/doc/guides/nics/qede.rst index c5fbd83..f7ca8eb 100644 --- a/doc/guides/nics/qede.rst +++ b/doc/guides/nics/qede.rst @@ -55,7 +55,7 @@ Supported Features - TSS - Multiple MAC address - Default pause flow control -- SR-IOV VF +- SR-IOV VF for 25G/40G modes Non-supported Features ---------------------- @@ -70,13 +70,13 @@ Non-supported Features Supported QLogic Adapters ------------------------- -- QLogic FastLinQ QL4xxxx 25G/40G CNAs +- QLogic FastLinQ QL4xxxx 25G/40G/100G CNAs. Prerequisites ------------- -- Requires firmware version **8.7.x.** and management - firmware version **8.7.x or higher**. Firmware may be available +- Requires firmware version **8.7.x.** and management firmware + version **8.7.x or higher**. Firmware may be available inbox in certain newer Linux distros under the standard directory ``E.g. /lib/firmware/qed/qed_init_values_zipped-8.7.7.0.bin`` diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index c2d030c..d32f7b3 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -7,10 +7,12 @@ */ #include "qede_ethdev.h" +#include /* Globals */ static const struct qed_eth_ops *qed_ops; static const char *drivername = "qede pmd"; +static int64_t timer_period = 1; static const struct rte_eth_xstats qede_eth_stats[] = { {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)}, @@ -498,6 +500,21 @@ static int qede_dev_configure(struct rte_eth_dev *eth_dev) return -EINVAL; } + /* Check requirements for 100G mode */ + if (edev->num_hwfns > 1) { + if (eth_dev->data->nb_rx_queues < 2) { + DP_NOTICE(edev, false, + "100G mode requires minimum two queues\n"); + return -EINVAL; + } + + if ((eth_dev->data->nb_rx_queues % 2) != 0) { + DP_NOTICE(edev, false, + "100G mode requires even number of queues\n"); + return -EINVAL; + } + } + qdev->num_rss = eth_dev->data->nb_rx_queues; /* Initial state */ @@ -680,6 +697,26 @@ static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_REGULAR); } +static void qede_poll_sp_sb_cb(void *param) +{ + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; + struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); + struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); + int rc; + + qede_interrupt_action(ECORE_LEADING_HWFN(edev)); + qede_interrupt_action(&edev->hwfns[1]); + + rc = rte_eal_alarm_set(timer_period * US_PER_S, + qede_poll_sp_sb_cb, + (void *)eth_dev); + if (rc != 0) { + DP_ERR(edev, "Unable to start periodic" + " timer rc %d\n", rc); + assert(false && "Unable to start periodic timer"); + } +} + static void qede_dev_close(struct rte_eth_dev *eth_dev) { struct qede_dev *qdev = eth_dev->data->dev_private; @@ -712,6 +749,9 @@ static void qede_dev_close(struct rte_eth_dev *eth_dev) rte_intr_callback_unregister(ð_dev->pci_dev->intr_handle, qede_interrupt_handler, (void *)eth_dev); + if (edev->num_hwfns > 1) + rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); + qdev->state = QEDE_CLOSE; } @@ -1238,9 +1278,26 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) params.drv_eng = QEDE_ENGINEERING_VERSION; strncpy((char *)params.name, "qede LAN", QED_DRV_VER_STR_SIZE); + /* For CMT mode device do periodic polling for slowpath events. + * This is required since uio device uses only one MSI-x + * interrupt vector but we need one for each engine. + */ + if (edev->num_hwfns > 1) { + rc = rte_eal_alarm_set(timer_period * US_PER_S, + qede_poll_sp_sb_cb, + (void *)eth_dev); + if (rc != 0) { + DP_ERR(edev, "Unable to start periodic" + " timer rc %d\n", rc); + return -EINVAL; + } + } + rc = qed_ops->common->slowpath_start(edev, ¶ms); if (rc) { DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); + rte_eal_alarm_cancel(qede_poll_sp_sb_cb, + (void *)eth_dev); return -ENODEV; } @@ -1249,6 +1306,8 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) DP_ERR(edev, "Cannot get device_info rc %d\n", rc); qed_ops->common->slowpath_stop(edev); qed_ops->common->remove(edev); + rte_eal_alarm_cancel(qede_poll_sp_sb_cb, + (void *)eth_dev); return -ENODEV; } @@ -1274,6 +1333,8 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) DP_ERR(edev, "Failed to allocate MAC address\n"); qed_ops->common->slowpath_stop(edev); qed_ops->common->remove(edev); + rte_eal_alarm_cancel(qede_poll_sp_sb_cb, + (void *)eth_dev); return -ENOMEM; } @@ -1389,6 +1450,9 @@ static struct rte_pci_id pci_id_qede_map[] = { { QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25) }, + { + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100) + }, {.vendor_id = 0,} }; diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h index 64d5f08..b080f5f 100644 --- a/drivers/net/qede/qede_ethdev.h +++ b/drivers/net/qede/qede_ethdev.h @@ -81,7 +81,7 @@ struct ecore_dev *edev = &qdev->edev; \ } -/************* QLogic 25G/40G vendor/devices ids *************/ +/************* QLogic 25G/40G/100G vendor/devices ids *************/ #define PCI_VENDOR_ID_QLOGIC 0x1077 #define CHIP_NUM_57980E 0x1634 @@ -90,6 +90,7 @@ #define CHIP_NUM_57980S_40 0x1634 #define CHIP_NUM_57980S_25 0x1656 #define CHIP_NUM_57980S_IOV 0x1664 +#define CHIP_NUM_57980S_100 0x1644 #define PCI_DEVICE_ID_NX2_57980E CHIP_NUM_57980E #define PCI_DEVICE_ID_NX2_57980S CHIP_NUM_57980S @@ -97,6 +98,7 @@ #define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40 #define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25 #define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV +#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100 extern char fw_file[]; -- 1.7.10.3