From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 6DC34C700 for ; Fri, 17 Jun 2016 13:18:42 +0200 (CEST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP; 17 Jun 2016 04:18:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,483,1459839600"; d="scan'208";a="123835081" Received: from sie-lab-212-116.ir.intel.com (HELO silpixa00378492.ir.intel.com) ([10.237.212.116]) by fmsmga004.fm.intel.com with ESMTP; 17 Jun 2016 04:18:41 -0700 From: Pablo de Lara To: dev@dpdk.org Cc: declan.doherty@intel.com, Pablo de Lara Date: Fri, 17 Jun 2016 12:24:46 +0100 Message-Id: <1466162692-24654-6-git-send-email-pablo.de.lara.guarch@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1466162692-24654-1-git-send-email-pablo.de.lara.guarch@intel.com> References: <1462543429-26741-1-git-send-email-pablo.de.lara.guarch@intel.com> <1466162692-24654-1-git-send-email-pablo.de.lara.guarch@intel.com> Subject: [dpdk-dev] [PATCH v2 05/11] snow3g: add missing feature flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Jun 2016 11:18:43 -0000 The underlying libsso library supports different instruction sets (SSE4.1, AVX), so feature flags of the crypto device must be updated to reflect this. Signed-off-by: Pablo de Lara --- drivers/crypto/snow3g/rte_snow3g_pmd.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/snow3g/rte_snow3g_pmd.c b/drivers/crypto/snow3g/rte_snow3g_pmd.c index b90d27d..2f974f7 100644 --- a/drivers/crypto/snow3g/rte_snow3g_pmd.c +++ b/drivers/crypto/snow3g/rte_snow3g_pmd.c @@ -555,6 +555,18 @@ cryptodev_snow3g_create(const char *name, struct rte_cryptodev *dev; char crypto_dev_name[RTE_CRYPTODEV_NAME_MAX_LEN]; struct snow3g_private *internals; + uint64_t cpu_flags = 0; + + /* Check CPU for supported vector instruction set */ + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX)) + cpu_flags |= RTE_CRYPTODEV_FF_CPU_AVX; + else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1)) + cpu_flags |= RTE_CRYPTODEV_FF_CPU_SSE; + else { + SNOW3G_LOG_ERR("Vector instructions are not supported by CPU"); + return -EFAULT; + } + /* Create a unique device name. */ if (create_unique_device_name(crypto_dev_name, @@ -578,7 +590,8 @@ cryptodev_snow3g_create(const char *name, dev->enqueue_burst = snow3g_pmd_enqueue_burst; dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | - RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING; + RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | + cpu_flags; internals = dev->data->dev_private; -- 2.5.0