[dpdk-dev] [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver

[dpdk-dev] [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver

[Deepak Kumar Jain]

This patchset adds support of aes-sha384-hmac
in Intel(R) QuickAssist Technology driver.

This patchset depends on following patchset:
"crypto/qat: add aes-sha224-hmac capability to Intel QAT driver"
(http://dpdk.org/dev/patchwork/patch/15226/)

Jain, Deepak K (2):
  crypto/qat: add aes-sha384-hmac capability to Intel QAT driver
  app/test: add test cases for aes-sha384-hmac for Intel QAT driver

 app/test/test_cryptodev_aes.c                    |  6 +++--
 doc/guides/cryptodevs/qat.rst                    |  1 +
 drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 ++++++++++++++++++++++++
 drivers/crypto/qat/qat_crypto.c                  | 10 ++++---
 4 files changed, 44 insertions(+), 6 deletions(-)

-- 
2.5.5

[dpdk-dev] [PATCH 1/2] crypto/qat: add aes-sha384-hmac capability to Intel QAT driver

[Deepak Kumar Jain]

From: "Jain, Deepak K" <deepak.k.jain@intel.com>

enabled support of aes-sha384-hmac in Intel(R) QuickAssist driver

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
---
 doc/guides/cryptodevs/qat.rst                    |  1 +
 drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 ++++++++++++++++++++++++
 drivers/crypto/qat/qat_crypto.c                  | 10 ++++---
 3 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 7f630be..78a734f 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -55,6 +55,7 @@ Hash algorithms:
 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 77e6548..af8c176 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -77,6 +77,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA384_STATE1_SZ,
+						QAT_HW_DEFAULT_ALIGNMENT);
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
@@ -114,6 +117,8 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 		return ICP_QAT_HW_SHA224_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		return ICP_QAT_HW_SHA256_STATE1_SZ;
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		return ICP_QAT_HW_SHA384_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		return ICP_QAT_HW_SHA512_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_MD5:
@@ -138,6 +143,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 		return SHA256_CBLOCK;
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		return SHA256_CBLOCK;
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		return SHA512_CBLOCK;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		return SHA512_CBLOCK;
 	case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
@@ -187,6 +194,17 @@ static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
 	return 0;
 }
 
+static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)
+{
+	SHA512_CTX ctx;
+
+	if (!SHA384_Init(&ctx))
+		return -EFAULT;
+	SHA512_Transform(&ctx, data_in);
+	rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
+	return 0;
+}
+
 static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
 {
 	SHA512_CTX ctx;
@@ -252,6 +270,13 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
 			*hash_state_out_be32 =
 				rte_bswap32(*(((uint32_t *)digest)+i));
 		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		if (partial_hash_sha384(data_in, digest))
+			return -EFAULT;
+		for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
+			*hash_state_out_be64 =
+				rte_bswap64(*(((uint64_t *)digest)+i));
+		break;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		if (partial_hash_sha512(data_in, digest))
 			return -EFAULT;
@@ -616,6 +641,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
 		}
 		state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
 		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
+			authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+			PMD_DRV_LOG(ERR, "(SHA)precompute failed");
+			return -EFAULT;
+		}
+		state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
+		break;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
 			authkey, authkeylen, cdesc->cd_cur_ptr,	&state1_size)) {
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index e872759..a474512 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -533,15 +533,18 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 	case RTE_CRYPTO_AUTH_SHA1_HMAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 		break;
+	case RTE_CRYPTO_AUTH_SHA224_HMAC:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
+		break;
 	case RTE_CRYPTO_AUTH_SHA256_HMAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
 		break;
+	case RTE_CRYPTO_AUTH_SHA384_HMAC:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
+		break;
 	case RTE_CRYPTO_AUTH_SHA512_HMAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 		break;
-	case RTE_CRYPTO_AUTH_SHA224_HMAC:
-		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
-		break;
 	case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
 		break;
@@ -560,7 +563,6 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 	case RTE_CRYPTO_AUTH_SHA512:
 	case RTE_CRYPTO_AUTH_SHA224:
 	case RTE_CRYPTO_AUTH_SHA384:
-	case RTE_CRYPTO_AUTH_SHA384_HMAC:
 	case RTE_CRYPTO_AUTH_MD5:
 	case RTE_CRYPTO_AUTH_AES_CCM:
 	case RTE_CRYPTO_AUTH_AES_GMAC:
-- 
2.5.5

[dpdk-dev] [PATCH 2/2] app/test: add test cases for aes-sha384-hmac for Intel QAT driver

[Deepak Kumar Jain]

From: "Jain, Deepak K" <deepak.k.jain@intel.com>

Added aes-sha384-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
---
 app/test/test_cryptodev_aes.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/app/test/test_cryptodev_aes.c b/app/test/test_cryptodev_aes.c
index 6ad2674..e19c45b 100644
--- a/app/test/test_cryptodev_aes.c
+++ b/app/test/test_cryptodev_aes.c
@@ -226,14 +226,16 @@ static const struct aes_test_case aes_test_cases[] = {
 		.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
 		.test_data = &aes_test_data_9,
 		.op_mask = AES_TEST_OP_ENC_AUTH_GEN,
-		.pmd_mask = AES_TEST_TARGET_PMD_MB
+		.pmd_mask = AES_TEST_TARGET_PMD_MB |
+			AES_TEST_TARGET_PMD_QAT
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA384 Decryption Digest "
 			"Verify",
 		.test_data = &aes_test_data_9,
 		.op_mask = AES_TEST_OP_AUTH_VERIFY_DEC,
-		.pmd_mask = AES_TEST_TARGET_PMD_MB
+		.pmd_mask = AES_TEST_TARGET_PMD_MB |
+			AES_TEST_TARGET_PMD_QAT
 	},
 };
 
-- 
2.5.5

Re: [dpdk-dev] [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver

[De Lara Guarch, Pablo]

Hi Deepak,

> -----Original Message-----
> From: Jain, Deepak K
> Sent: Thursday, August 18, 2016 6:26 AM
> To: De Lara Guarch, Pablo; Trahe, Fiona; Griffin, John
> Cc: dev@dpdk.org; Jain, Deepak K
> Subject: [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver
> 
> This patchset adds support of aes-sha384-hmac
> in Intel(R) QuickAssist Technology driver.
> 
> This patchset depends on following patchset:
> "crypto/qat: add aes-sha224-hmac capability to Intel QAT driver"
> (http://dpdk.org/dev/patchwork/patch/15226/)
> 
> Jain, Deepak K (2):
>   crypto/qat: add aes-sha384-hmac capability to Intel QAT driver
>   app/test: add test cases for aes-sha384-hmac for Intel QAT driver
> 
>  app/test/test_cryptodev_aes.c                    |  6 +++--
>  doc/guides/cryptodevs/qat.rst                    |  1 +
>  drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33
> ++++++++++++++++++++++++
>  drivers/crypto/qat/qat_crypto.c                  | 10 ++++---
>  4 files changed, 44 insertions(+), 6 deletions(-)
> 
> --
> 2.5.5

Could you send a v2 with a release notes update?

Thanks,
Pablo

Re: [dpdk-dev] [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver

[Jain, Deepak K]

HI Pablo,

> -----Original Message-----
> From: De Lara Guarch, Pablo
> Sent: Wednesday, September 7, 2016 7:02 PM
> To: Jain, Deepak K <deepak.k.jain@intel.com>; Trahe, Fiona
> <fiona.trahe@intel.com>; Griffin, John <john.griffin@intel.com>
> Cc: dev@dpdk.org
> Subject: RE: [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver
> 
> Hi Deepak,
> 
> > -----Original Message-----
> > From: Jain, Deepak K
> > Sent: Thursday, August 18, 2016 6:26 AM
> > To: De Lara Guarch, Pablo; Trahe, Fiona; Griffin, John
> > Cc: dev@dpdk.org; Jain, Deepak K
> > Subject: [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver
> >
> > This patchset adds support of aes-sha384-hmac in Intel(R) QuickAssist
> > Technology driver.
> >
> > This patchset depends on following patchset:
> > "crypto/qat: add aes-sha224-hmac capability to Intel QAT driver"
> > (http://dpdk.org/dev/patchwork/patch/15226/)
> >
> > Jain, Deepak K (2):
> >   crypto/qat: add aes-sha384-hmac capability to Intel QAT driver
> >   app/test: add test cases for aes-sha384-hmac for Intel QAT driver
> >
> >  app/test/test_cryptodev_aes.c                    |  6 +++--
> >  doc/guides/cryptodevs/qat.rst                    |  1 +
> >  drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33
> > ++++++++++++++++++++++++
> >  drivers/crypto/qat/qat_crypto.c                  | 10 ++++---
> >  4 files changed, 44 insertions(+), 6 deletions(-)
> >
> > --
> > 2.5.5
> 
> Could you send a v2 with a release notes update?
> 
Agreed. I will send v2 with release notes.

> Thanks,
> Pablo

[dpdk-dev] [PATCH v2 0/2] add aes-sha384-hmac support to Intel QAT driver

[Deepak Kumar Jain]

This patchset adds support of aes-sha384-hmac in Intel(R) QuickAssist Technology driver.

This patchset depends on following patchset:
"crypto/qat: add aes-sha224-hmac capability to Intel QAT driver"
(http://dpdk.org/dev/patchwork/patch/15754/)

Jain, Deepak K (2):
  crypto/qat: add aes-sha224-hmac capability to Intel QAT driver
  app/test: add test cases for aes-sha224-hmac for Intel QAT driver

Changes from V1:
* Added new feature information in release_16_11.rst file.
* Added information about sha224-hmac in capabilities.

 app/test/test_cryptodev_aes.c                    |  6 +++--
 doc/guides/cryptodevs/qat.rst                    |  1 +
 doc/guides/rel_notes/release_16_11.rst           |  1 +
 drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 ++++++++++++++++++++++++
 drivers/crypto/qat/qat_crypto.c                  | 25 +++++++++++++++++-
 5 files changed, 63 insertions(+), 3 deletions(-)

-- 
2.5.5

[dpdk-dev] [PATCH v2 1/2] crypto/qat: add aes-sha224-hmac capability to Intel QAT driver

[Deepak Kumar Jain]

From: "Jain, Deepak K" <deepak.k.jain@intel.com>

Added support of aes-sha224-hmac in Intel(R) QuickAssist driver

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
---
 doc/guides/cryptodevs/qat.rst                    |  1 +
 doc/guides/rel_notes/release_16_11.rst           |  1 +
 drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 ++++++++++++++++++++++++
 drivers/crypto/qat/qat_crypto.c                  | 25 +++++++++++++++++-
 4 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 485abb4..7f630be 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -53,6 +53,7 @@ Cipher algorithms:
 Hash algorithms:
 
 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
diff --git a/doc/guides/rel_notes/release_16_11.rst b/doc/guides/rel_notes/release_16_11.rst
index 4f7d784..040e250 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -40,6 +40,7 @@ New Features
   The QAT PMD was updated with changes including the following:
 
   * Added support for MD5_HMAC algorithm.
+  * Added support for SHA224-HMAC algorithm.
 
 
 Resolved Issues
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 521a9c4..77e6548 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -71,6 +71,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 	case ICP_QAT_HW_AUTH_ALGO_SHA1:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA1_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
+	case ICP_QAT_HW_AUTH_ALGO_SHA224:
+		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA224_STATE1_SZ,
+						QAT_HW_DEFAULT_ALIGNMENT);
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
@@ -107,6 +110,8 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 	switch (qat_hash_alg) {
 	case ICP_QAT_HW_AUTH_ALGO_SHA1:
 		return ICP_QAT_HW_SHA1_STATE1_SZ;
+	case ICP_QAT_HW_AUTH_ALGO_SHA224:
+		return ICP_QAT_HW_SHA224_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		return ICP_QAT_HW_SHA256_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
@@ -129,6 +134,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 	switch (qat_hash_alg) {
 	case ICP_QAT_HW_AUTH_ALGO_SHA1:
 		return SHA_CBLOCK;
+	case ICP_QAT_HW_AUTH_ALGO_SHA224:
+		return SHA256_CBLOCK;
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		return SHA256_CBLOCK;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
@@ -158,6 +165,17 @@ static int partial_hash_sha1(uint8_t *data_in, uint8_t *data_out)
 	return 0;
 }
 
+static int partial_hash_sha224(uint8_t *data_in, uint8_t *data_out)
+{
+	SHA256_CTX ctx;
+
+	if (!SHA224_Init(&ctx))
+		return -EFAULT;
+	SHA256_Transform(&ctx, data_in);
+	rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
+	return 0;
+}
+
 static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
 {
 	SHA256_CTX ctx;
@@ -220,6 +238,13 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
 			*hash_state_out_be32 =
 				rte_bswap32(*(((uint32_t *)digest)+i));
 		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA224:
+		if (partial_hash_sha224(data_in, digest))
+			return -EFAULT;
+		for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
+			*hash_state_out_be32 =
+				rte_bswap32(*(((uint32_t *)digest)+i));
+		break;
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		if (partial_hash_sha256(data_in, digest))
 			return -EFAULT;
@@ -575,6 +600,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
 		}
 		state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
 		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA224:
+		if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
+			authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+			PMD_DRV_LOG(ERR, "(SHA)precompute failed");
+			return -EFAULT;
+		}
+		state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
+		break;
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256,
 			authkey, authkeylen, cdesc->cd_cur_ptr,	&state1_size)) {
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index ba1daa7..a9a3ef7 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -90,6 +90,27 @@ static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
 			}, }
 		}, }
 	},
+	{	/* SHA224 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
+				.block_size = 64,
+					.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 28,
+					.max = 28,
+					.increment = 0
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
 	{	/* SHA256 HMAC */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
@@ -539,6 +560,9 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 	case RTE_CRYPTO_AUTH_SHA512_HMAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 		break;
+	case RTE_CRYPTO_AUTH_SHA224_HMAC:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
+		break;
 	case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
 		break;
@@ -556,7 +580,6 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 	case RTE_CRYPTO_AUTH_SHA256:
 	case RTE_CRYPTO_AUTH_SHA512:
 	case RTE_CRYPTO_AUTH_SHA224:
-	case RTE_CRYPTO_AUTH_SHA224_HMAC:
 	case RTE_CRYPTO_AUTH_SHA384:
 	case RTE_CRYPTO_AUTH_SHA384_HMAC:
 	case RTE_CRYPTO_AUTH_MD5:
-- 
2.5.5

Re: [dpdk-dev] [PATCH v2 1/2] crypto/qat: add aes-sha224-hmac capability to Intel QAT driver

[Trahe, Fiona]

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Deepak Kumar Jain
> Sent: Monday, September 12, 2016 8:47 PM
> To: dev@dpdk.org
> Cc: De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>; Jain, Deepak K
> <deepak.k.jain@intel.com>
> Subject: [dpdk-dev] [PATCH v2 1/2] crypto/qat: add aes-sha224-hmac
> capability to Intel QAT driver
> 
> From: "Jain, Deepak K" <deepak.k.jain@intel.com>
> 
> Added support of aes-sha224-hmac in Intel(R) QuickAssist driver
> 
> Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

[dpdk-dev] [PATCH v2 2/2] app/test: add test cases for aes-sha224-hmac for Intel QAT driver

[Deepak Kumar Jain]

From: "Jain, Deepak K" <deepak.k.jain@intel.com>

Added aes-sha224-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
---
 app/test/test_cryptodev_aes.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/app/test/test_cryptodev_aes.c b/app/test/test_cryptodev_aes.c
index bf832b6..6ad2674 100644
--- a/app/test/test_cryptodev_aes.c
+++ b/app/test/test_cryptodev_aes.c
@@ -211,14 +211,16 @@ static const struct aes_test_case aes_test_cases[] = {
 		.test_descr = "AES-128-CBC HMAC-SHA224 Encryption Digest",
 		.test_data = &aes_test_data_8,
 		.op_mask = AES_TEST_OP_ENC_AUTH_GEN,
-		.pmd_mask = AES_TEST_TARGET_PMD_MB
+		.pmd_mask = AES_TEST_TARGET_PMD_MB |
+			AES_TEST_TARGET_PMD_QAT
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
 			"Verify",
 		.test_data = &aes_test_data_8,
 		.op_mask = AES_TEST_OP_AUTH_VERIFY_DEC,
-		.pmd_mask = AES_TEST_TARGET_PMD_MB
+		.pmd_mask = AES_TEST_TARGET_PMD_MB |
+			AES_TEST_TARGET_PMD_QAT
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
-- 
2.5.5

Re: [dpdk-dev] [PATCH v2 2/2] app/test: add test cases for aes-sha224-hmac for Intel QAT driver

[Trahe, Fiona]

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Deepak Kumar Jain
> Sent: Monday, September 12, 2016 8:47 PM
> To: dev@dpdk.org
> Cc: De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>; Jain, Deepak K
> <deepak.k.jain@intel.com>
> Subject: [dpdk-dev] [PATCH v2 2/2] app/test: add test cases for aes-sha224-
> hmac for Intel QAT driver
> 
> From: "Jain, Deepak K" <deepak.k.jain@intel.com>
> 
> Added aes-sha224-hmac algorithm to test file for Intel(R) QuickAssist
> Technology Driver
> 
> Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

[dpdk-dev] [PATCH v2 0/2] add aes-sha384-hmac support to Intel QAT driver

[Deepak Kumar Jain]

This patchset adds support of aes-sha384-hmac in Intel(R) QuickAssist Technology driver.

This patchset depends on following patchset:
"crypto/qat: add aes-sha224-hmac capability to Intel QAT driver"
(http://dpdk.org/dev/patchwork/patch/15776/)


Jain, Deepak K (2):
  crypto/qat: add aes-sha384-hmac capability to Intel QAT driver
  app/test: add test cases for aes-sha384-hmac for Intel QAT driver

Changes from V1:
* Added new feature information in release_16_11.rst file.
* Added information about sha384-hmac in capabilities.

 app/test/test_cryptodev_aes.c                    |  6 +++--
 doc/guides/cryptodevs/qat.rst                    |  1 +
 doc/guides/rel_notes/release_16_11.rst           |  1 +
 drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 ++++++++++++++++++++++++
 drivers/crypto/qat/qat_crypto.c                  | 31 +++++++++++++++++++---
 5 files changed, 66 insertions(+), 6 deletions(-)

-- 
2.5.5

[dpdk-dev] [PATCH v2 1/2] crypto/qat: add aes-sha384-hmac capability to Intel QAT driver

[Deepak Kumar Jain]

From: "Jain, Deepak K" <deepak.k.jain@intel.com>

enabled support of aes-sha384-hmac in Intel(R) QuickAssist driver

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
---
 doc/guides/cryptodevs/qat.rst                    |  1 +
 doc/guides/rel_notes/release_16_11.rst           |  1 +
 drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 ++++++++++++++++++++++++
 drivers/crypto/qat/qat_crypto.c                  | 31 +++++++++++++++++++---
 4 files changed, 62 insertions(+), 4 deletions(-)

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 7f630be..78a734f 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -55,6 +55,7 @@ Hash algorithms:
 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
diff --git a/doc/guides/rel_notes/release_16_11.rst b/doc/guides/rel_notes/release_16_11.rst
index 040e250..9b2f102 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -41,6 +41,7 @@ New Features
 
   * Added support for MD5_HMAC algorithm.
   * Added support for SHA224-HMAC algorithm.
+  * Added support for SHA384-HMAC algorithm.
 
 
 Resolved Issues
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 77e6548..af8c176 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -77,6 +77,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA384_STATE1_SZ,
+						QAT_HW_DEFAULT_ALIGNMENT);
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
@@ -114,6 +117,8 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 		return ICP_QAT_HW_SHA224_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		return ICP_QAT_HW_SHA256_STATE1_SZ;
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		return ICP_QAT_HW_SHA384_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		return ICP_QAT_HW_SHA512_STATE1_SZ;
 	case ICP_QAT_HW_AUTH_ALGO_MD5:
@@ -138,6 +143,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 		return SHA256_CBLOCK;
 	case ICP_QAT_HW_AUTH_ALGO_SHA256:
 		return SHA256_CBLOCK;
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		return SHA512_CBLOCK;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		return SHA512_CBLOCK;
 	case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
@@ -187,6 +194,17 @@ static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
 	return 0;
 }
 
+static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)
+{
+	SHA512_CTX ctx;
+
+	if (!SHA384_Init(&ctx))
+		return -EFAULT;
+	SHA512_Transform(&ctx, data_in);
+	rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
+	return 0;
+}
+
 static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
 {
 	SHA512_CTX ctx;
@@ -252,6 +270,13 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
 			*hash_state_out_be32 =
 				rte_bswap32(*(((uint32_t *)digest)+i));
 		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		if (partial_hash_sha384(data_in, digest))
+			return -EFAULT;
+		for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
+			*hash_state_out_be64 =
+				rte_bswap64(*(((uint64_t *)digest)+i));
+		break;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		if (partial_hash_sha512(data_in, digest))
 			return -EFAULT;
@@ -616,6 +641,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
 		}
 		state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
 		break;
+	case ICP_QAT_HW_AUTH_ALGO_SHA384:
+		if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
+			authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+			PMD_DRV_LOG(ERR, "(SHA)precompute failed");
+			return -EFAULT;
+		}
+		state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
+		break;
 	case ICP_QAT_HW_AUTH_ALGO_SHA512:
 		if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
 			authkey, authkeylen, cdesc->cd_cur_ptr,	&state1_size)) {
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index a9a3ef7..60e2ba2 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -132,6 +132,27 @@ static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
 			}, }
 		}, }
 	},
+	{	/* SHA384 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 128,
+					.max = 128,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 48,
+					.max = 48,
+					.increment = 0
+					},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
 	{	/* SHA512 HMAC */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {
@@ -554,15 +575,18 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 	case RTE_CRYPTO_AUTH_SHA1_HMAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 		break;
+	case RTE_CRYPTO_AUTH_SHA224_HMAC:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
+		break;
 	case RTE_CRYPTO_AUTH_SHA256_HMAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
 		break;
+	case RTE_CRYPTO_AUTH_SHA384_HMAC:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
+		break;
 	case RTE_CRYPTO_AUTH_SHA512_HMAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
 		break;
-	case RTE_CRYPTO_AUTH_SHA224_HMAC:
-		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
-		break;
 	case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
 		break;
@@ -581,7 +605,6 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 	case RTE_CRYPTO_AUTH_SHA512:
 	case RTE_CRYPTO_AUTH_SHA224:
 	case RTE_CRYPTO_AUTH_SHA384:
-	case RTE_CRYPTO_AUTH_SHA384_HMAC:
 	case RTE_CRYPTO_AUTH_MD5:
 	case RTE_CRYPTO_AUTH_AES_CCM:
 	case RTE_CRYPTO_AUTH_AES_GMAC:
-- 
2.5.5

Re: [dpdk-dev] [PATCH v2 1/2] crypto/qat: add aes-sha384-hmac capability to Intel QAT driver

[Trahe, Fiona]

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Deepak Kumar Jain
> Sent: Monday, September 12, 2016 8:51 PM
> To: dev@dpdk.org
> Cc: De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>; Jain, Deepak K
> <deepak.k.jain@intel.com>
> Subject: [dpdk-dev] [PATCH v2 1/2] crypto/qat: add aes-sha384-hmac
> capability to Intel QAT driver
> 
> From: "Jain, Deepak K" <deepak.k.jain@intel.com>
> 
> enabled support of aes-sha384-hmac in Intel(R) QuickAssist driver
> 
> Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com> 

Acked-by: Fiona Trahe <fiona.trahe@intel.com>

[dpdk-dev] [PATCH v2 2/2] app/test: add test cases for aes-sha384-hmac for Intel QAT driver

[Deepak Kumar Jain]

From: "Jain, Deepak K" <deepak.k.jain@intel.com>

Added aes-sha384-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
---
 app/test/test_cryptodev_aes.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/app/test/test_cryptodev_aes.c b/app/test/test_cryptodev_aes.c
index 6ad2674..e19c45b 100644
--- a/app/test/test_cryptodev_aes.c
+++ b/app/test/test_cryptodev_aes.c
@@ -226,14 +226,16 @@ static const struct aes_test_case aes_test_cases[] = {
 		.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
 		.test_data = &aes_test_data_9,
 		.op_mask = AES_TEST_OP_ENC_AUTH_GEN,
-		.pmd_mask = AES_TEST_TARGET_PMD_MB
+		.pmd_mask = AES_TEST_TARGET_PMD_MB |
+			AES_TEST_TARGET_PMD_QAT
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA384 Decryption Digest "
 			"Verify",
 		.test_data = &aes_test_data_9,
 		.op_mask = AES_TEST_OP_AUTH_VERIFY_DEC,
-		.pmd_mask = AES_TEST_TARGET_PMD_MB
+		.pmd_mask = AES_TEST_TARGET_PMD_MB |
+			AES_TEST_TARGET_PMD_QAT
 	},
 };
 
-- 
2.5.5

Re: [dpdk-dev] [PATCH v2 2/2] app/test: add test cases for aes-sha384-hmac for Intel QAT driver

[Trahe, Fiona]

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Deepak Kumar Jain
> Sent: Monday, September 12, 2016 8:51 PM
> To: dev@dpdk.org
> Cc: De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>; Jain, Deepak K
> <deepak.k.jain@intel.com>
> Subject: [dpdk-dev] [PATCH v2 2/2] app/test: add test cases for aes-sha384-
> hmac for Intel QAT driver
> 
> From: "Jain, Deepak K" <deepak.k.jain@intel.com>
> 
> Added aes-sha384-hmac algorithm to test file for Intel(R) QuickAssist
> Technology Driver
> 
> Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

Acked-by: Fiona Trahe <fiona.trahe@intel.com>

Re: [dpdk-dev] [PATCH v2 0/2] add aes-sha384-hmac support to Intel QAT driver

[De Lara Guarch, Pablo]

> -----Original Message-----
> From: Jain, Deepak K
> Sent: Monday, September 12, 2016 12:51 PM
> To: dev@dpdk.org
> Cc: De Lara Guarch, Pablo; Jain, Deepak K
> Subject: [PATCH v2 0/2] add aes-sha384-hmac support to Intel QAT driver
> 
> This patchset adds support of aes-sha384-hmac in Intel(R) QuickAssist
> Technology driver.
> 
> This patchset depends on following patchset:
> "crypto/qat: add aes-sha224-hmac capability to Intel QAT driver"
> (http://dpdk.org/dev/patchwork/patch/15776/)
> 
> 
> Jain, Deepak K (2):
>   crypto/qat: add aes-sha384-hmac capability to Intel QAT driver
>   app/test: add test cases for aes-sha384-hmac for Intel QAT driver
> 
> Changes from V1:
> * Added new feature information in release_16_11.rst file.
> * Added information about sha384-hmac in capabilities.
> 
>  app/test/test_cryptodev_aes.c                    |  6 +++--
>  doc/guides/cryptodevs/qat.rst                    |  1 +
>  doc/guides/rel_notes/release_16_11.rst           |  1 +
>  drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33
> ++++++++++++++++++++++++
>  drivers/crypto/qat/qat_crypto.c                  | 31 +++++++++++++++++++---
>  5 files changed, 66 insertions(+), 6 deletions(-)
> 
> --
> 2.5.5

Applied to dpdk-next-crypto.
Thanks,

Pablo

Re: [dpdk-dev] [PATCH v2 0/2] add aes-sha384-hmac support to Intel QAT driver

[Liu, Yong]

Tested-by: Yong Liu <yong.liu@intel.com>

- Tested Branch: dpdk-next-crypto/master
- Tested Commit: 3e329d659b62097d15ec86ff92acc8effaf28cd2
- OS: Fedora20 3.11.10-301.fc20.x86_64
- GCC: gcc version 4.8.3 20140911
- CPU: Intel(R) Xeon(R) CPU E5-2699 v3 @ 2.30GHz
- NIC: Intel Corporation Device Fortville [8086:1583]
- QAT: Intel Corporation Coleto Creek PCIe Endpoint [8086:0435]
- Default x86_64-native-linuxapp-gcc configuration
- Prerequisites:
- Total 2 cases, 2 passed, 0 failed

- Prerequisites command / instruction:
  Enable CONFIG_RTE_LIBRTE_PMD_QAT in config/common_base and rebuild dpdk
  Bind QAT VF devices to igb_uio

- Case: 
  Description: SHA384_HMAC authentication unit test 
  Command / instruction:
    Start test application with normal eal parameter.
      ./$RTE_TARGET/app/test -c f -n 4 -- -i
    Run crypto QAT unit test suite and verify SHA384_HMAC cases passed

- Case: 
  Description: l2fwd_crypto with SHA384_HMAC authentication test
  Command / instruction:
    Start l2fwd_crypto with QAT technology enable.
    Authentication method is SHA384_HMAC, auth key is also inputted in.
    Authentication key length for SHA384_HMAC should be 128 bytes.
      ./examples/l2fwd-crypto/build/app/l2fwd-crypto -c0xf -n4 -- -p0x1 \
        --chain HASH_ONLY --cdev_type ANY --auth_algo SHA384_HMAC \
        --auth_op GENERATE --auth_key $auth_key

    Send 65 packets with random 64 bytes payload and capture forwarded packets.
    Check all forwarded packets contained of 48 bytes hashed value.
    Check hash values are same as calculated value.

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Deepak Kumar Jain
> Sent: Tuesday, September 13, 2016 3:51 AM
> To: dev@dpdk.org
> Cc: De Lara Guarch, Pablo; Jain, Deepak K
> Subject: [dpdk-dev] [PATCH v2 0/2] add aes-sha384-hmac support to Intel
> QAT driver
> 
> This patchset adds support of aes-sha384-hmac in Intel(R) QuickAssist
> Technology driver.
> 
> This patchset depends on following patchset:
> "crypto/qat: add aes-sha224-hmac capability to Intel QAT driver"
> (http://dpdk.org/dev/patchwork/patch/15776/)
> 
> 
> Jain, Deepak K (2):
>   crypto/qat: add aes-sha384-hmac capability to Intel QAT driver
>   app/test: add test cases for aes-sha384-hmac for Intel QAT driver
> 
> Changes from V1:
> * Added new feature information in release_16_11.rst file.
> * Added information about sha384-hmac in capabilities.
> 
>  app/test/test_cryptodev_aes.c                    |  6 +++--
>  doc/guides/cryptodevs/qat.rst                    |  1 +
>  doc/guides/rel_notes/release_16_11.rst           |  1 +
>  drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33
> ++++++++++++++++++++++++
>  drivers/crypto/qat/qat_crypto.c                  | 31
> +++++++++++++++++++---
>  5 files changed, 66 insertions(+), 6 deletions(-)
> 
> --
> 2.5.5