From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 47DAC2BA5 for ; Tue, 18 Oct 2016 03:32:11 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 17 Oct 2016 18:32:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,359,1473145200"; d="scan'208";a="1046117172" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.239.129.103]) by orsmga001.jf.intel.com with ESMTP; 17 Oct 2016 18:32:01 -0700 From: Qi Zhang To: jingjing.wu@intel.com, helin.zhang@intel.com Cc: dev@dpdk.org, Qi Zhang Date: Tue, 18 Oct 2016 02:29:40 +0800 Message-Id: <1476728982-39985-2-git-send-email-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1476728982-39985-1-git-send-email-qi.z.zhang@intel.com> References: <1476728982-39985-1-git-send-email-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 1/3] net/i40e: fix out of order Rx read issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Oct 2016 01:32:11 -0000 In vPMD, when load Rx desc with _mm_loadu_si128, volatile point will be cast into non-volatile point. So GCC is allowed to reorder the load instructions, while Rx read's correctness is reply on these load instructions to follow a backward sequence strictly, so we add compile barrier to prevent compiler reorder. Fixes: 9ed94e5bb04e ("i40e: add vector Rx") Signed-off-by: Qi Zhang --- v2: - fix check-git-log.sh warning. - add more detail commit message. drivers/net/i40e/i40e_rxtx_vec.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/i40e/i40e_rxtx_vec.c b/drivers/net/i40e/i40e_rxtx_vec.c index 0ee0241..ab63501 100644 --- a/drivers/net/i40e/i40e_rxtx_vec.c +++ b/drivers/net/i40e/i40e_rxtx_vec.c @@ -305,6 +305,7 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, /* Read desc statuses backwards to avoid race condition */ /* A.1 load 4 pkts desc */ descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3)); + rte_compiler_barrier(); /* B.2 copy 2 mbuf point into rx_pkts */ _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1); @@ -313,8 +314,10 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]); descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2)); + rte_compiler_barrier(); /* B.1 load 2 mbuf point */ descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1)); + rte_compiler_barrier(); descs[0] = _mm_loadu_si128((__m128i *)(rxdp)); /* B.2 copy 2 mbuf point into rx_pkts */ -- 2.7.4