From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 93AC24B79 for ; Fri, 9 Dec 2016 15:40:36 +0100 (CET) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP; 09 Dec 2016 06:40:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,324,1477983600"; d="scan'208";a="40776106" Received: from dpdk2.sh.intel.com ([10.239.128.246]) by fmsmga005.fm.intel.com with ESMTP; 09 Dec 2016 06:40:35 -0800 From: Jingjing Wu To: dev@dpdk.org Cc: jingjing.wu@intel.com, helin.zhang@intel.com Date: Fri, 9 Dec 2016 22:39:09 +0800 Message-Id: <1481294364-83505-17-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1481294364-83505-1-git-send-email-jingjing.wu@intel.com> References: <1480727953-92137-1-git-send-email-jingjing.wu@intel.com> <1481294364-83505-1-git-send-email-jingjing.wu@intel.com> Subject: [dpdk-dev] [PATCH v2 16/31] net/i40e/base: use BIT() macro instead of bit fields X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Dec 2016 14:40:37 -0000 Signed-off-by: Jingjing Wu --- drivers/net/i40e/base/i40e_adminq_cmd.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h index 1884758..cef02b1 100644 --- a/drivers/net/i40e/base/i40e_adminq_cmd.h +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h @@ -1823,11 +1823,11 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */ #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 u8 fec_config; -#define I40E_AQ_SET_FEC_ABILITY_KR (1 << 0) -#define I40E_AQ_SET_FEC_ABILITY_RS (1 << 1) -#define I40E_AQ_SET_FEC_REQUEST_KR (1 << 2) -#define I40E_AQ_SET_FEC_REQUEST_RS (1 << 3) -#define I40E_AQ_SET_FEC_AUTO (1 << 4) +#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) +#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) +#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) +#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) +#define I40E_AQ_SET_FEC_AUTO BIT(4) #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) u8 reserved; -- 2.4.11