From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 59CC210C23 for ; Wed, 21 Dec 2016 10:52:27 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 21 Dec 2016 01:52:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,382,1477983600"; d="scan'208";a="1084967614" Received: from dpdk4.bj.intel.com ([172.16.182.178]) by fmsmga001.fm.intel.com with ESMTP; 21 Dec 2016 01:52:25 -0800 From: Wei Dai To: dev@dpdk.org Cc: helin.zhang@intel.com, konstantin.ananyev@intel.com, Wei Dai Date: Wed, 21 Dec 2016 17:48:12 +0800 Message-Id: <1482313694-31602-29-git-send-email-wei.dai@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1482313694-31602-1-git-send-email-wei.dai@intel.com> References: <1482313694-31602-1-git-send-email-wei.dai@intel.com> Subject: [dpdk-dev] [PATCH v2 28/30] net/ixgbe/base: add write flush required by Inphi PHY X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Dec 2016 09:52:28 -0000 This patch updates the configuration of PHY from Inphi (www.inphi.com) to flush the register write with a reg read. The Inphi PHY is configured in ixgbe_setup_mac_link_sfp_x550a. The Inphy PHY setup flow has been updated to read configuration reg, write only linear/non-linear, and then read (write flush). Signed-off-by: Wei Dai --- drivers/net/ixgbe/base/ixgbe_x550.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c index 4a98530..a57ba74 100644 --- a/drivers/net/ixgbe/base/ixgbe_x550.c +++ b/drivers/net/ixgbe/base/ixgbe_x550.c @@ -2834,12 +2834,26 @@ s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, /* Configure CS4227/CS4223 LINE side to proper mode. */ reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; + + ret_val = hw->phy.ops.read_reg(hw, reg_slice, + IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); + + if (ret_val != IXGBE_SUCCESS) + return ret_val; + + reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | + (IXGBE_CS4227_EDC_MODE_SR << 1)); + if (setup_linear) reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; else reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; ret_val = hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); + + /* Flush previous write with a read */ + ret_val = hw->phy.ops.read_reg(hw, reg_slice, + IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); } return ret_val; } -- 2.7.4