From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 0E6E110CC8 for ; Wed, 21 Dec 2016 23:12:57 +0100 (CET) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP; 21 Dec 2016 14:12:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,385,1477983600"; d="scan'208";a="45546295" Received: from dwdohert-dpdk.ir.intel.com ([163.33.210.152]) by fmsmga005.fm.intel.com with ESMTP; 21 Dec 2016 14:12:56 -0800 From: Declan Doherty To: dev@dpdk.org Cc: Declan Doherty Date: Wed, 21 Dec 2016 22:05:00 +0000 Message-Id: <1482357900-8382-2-git-send-email-declan.doherty@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1482357900-8382-1-git-send-email-declan.doherty@intel.com> References: <1480671985-3677-1-git-send-email-declan.doherty@intel.com> <1482357900-8382-1-git-send-email-declan.doherty@intel.com> Subject: [dpdk-dev] [PATCH v2] crypto/aesni_mb: enablement of avx512 support in IPsec_mb library X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Dec 2016 22:12:58 -0000 Release v0.44 of Intel(R) Multi-Buffer Crypto for IPsec library adds support for AVX512 instructions. This patch enables the new AVX512 accelerated functions from the aesni_mb_pmd crypto poll mode driver. This patch set requires that the aesni_mb_pmd is linked against the version 0.44 or greater of the Multi-Buffer Crypto for IPsec library. Signed-off-by: Declan Doherty --- drivers/crypto/aesni_mb/aesni_mb_ops.h | 28 +++++++++++++++++++++++++++- drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 7 ++++++- lib/librte_cryptodev/rte_cryptodev.h | 2 ++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/aesni_mb/aesni_mb_ops.h b/drivers/crypto/aesni_mb/aesni_mb_ops.h index 0c119bf..2d41d73 100644 --- a/drivers/crypto/aesni_mb/aesni_mb_ops.h +++ b/drivers/crypto/aesni_mb/aesni_mb_ops.h @@ -44,7 +44,8 @@ enum aesni_mb_vector_mode { RTE_AESNI_MB_NOT_SUPPORTED = 0, RTE_AESNI_MB_SSE, RTE_AESNI_MB_AVX, - RTE_AESNI_MB_AVX2 + RTE_AESNI_MB_AVX2, + RTE_AESNI_MB_AVX512 }; typedef void (*md5_one_block_t)(void *data, void *digest); @@ -203,6 +204,31 @@ static const struct aesni_mb_ops job_ops[] = { aes_xcbc_expand_key_avx2 } } + }, + [RTE_AESNI_MB_AVX512] = { + .job = { + init_mb_mgr_avx512, + get_next_job_avx512, + submit_job_avx512, + get_completed_job_avx512, + flush_job_avx512 + }, + .aux = { + .one_block = { + md5_one_block_avx512, + sha1_one_block_avx512, + sha224_one_block_avx512, + sha256_one_block_avx512, + sha384_one_block_avx512, + sha512_one_block_avx512 + }, + .keyexp = { + aes_keyexp_128_avx512, + aes_keyexp_192_avx512, + aes_keyexp_256_avx512, + aes_xcbc_expand_key_avx512 + } + } } }; diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c index f07cd07..c400b17 100644 --- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c +++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c @@ -613,7 +613,9 @@ cryptodev_aesni_mb_create(const char *name, } /* Check CPU for supported vector instruction set */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + vector_mode = RTE_AESNI_MB_AVX512; + else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) vector_mode = RTE_AESNI_MB_AVX2; else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX)) vector_mode = RTE_AESNI_MB_AVX; @@ -660,6 +662,9 @@ cryptodev_aesni_mb_create(const char *name, case RTE_AESNI_MB_AVX2: dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX2; break; + case RTE_AESNI_MB_AVX512: + dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX512; + break; default: break; } diff --git a/lib/librte_cryptodev/rte_cryptodev.h b/lib/librte_cryptodev/rte_cryptodev.h index 8f63e8f..29d8eec 100644 --- a/lib/librte_cryptodev/rte_cryptodev.h +++ b/lib/librte_cryptodev/rte_cryptodev.h @@ -225,6 +225,8 @@ struct rte_cryptodev_capabilities { /**< Utilises CPU AES-NI instructions */ #define RTE_CRYPTODEV_FF_HW_ACCELERATED (1ULL << 7) /**< Operations are off-loaded to an external hardware accelerator */ +#define RTE_CRYPTODEV_FF_CPU_AVX512 (1ULL << 8) +/**< Utilises CPU SIMD AVX512 instructions */ /** -- 2.5.5