From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <Jerin.Jacob@cavium.com> Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0068.outbound.protection.outlook.com [104.47.33.68]) by dpdk.org (Postfix) with ESMTP id 29A0A4CC5 for <dev@dpdk.org>; Tue, 27 Dec 2016 10:51:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=5Hlu3zInO94yGxf/MIs6LYGYQrMN6WNeozkVJdHYkIo=; b=OPsG6nK12L3O2vbBYQIUfEegW9gfmZfmDjgwTVE02ZTtzTUnhlo4KrdFkkU+j4OxiQI3LOh5wZjwglDoDDya0ADq3zP3G21fyGqbkOCD+8U2SkfsV8JNiBB3zda5ui320RSoMFpQMYZ0dcuhs4u5yLN1v+rak7cik/ee94NEHcw= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.Jacob@cavium.com; Received: from localhost.localdomain.localdomain (202.83.56.97) by BLUPR0701MB1713.namprd07.prod.outlook.com (10.163.85.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.803.11; Tue, 27 Dec 2016 09:51:17 +0000 From: Jerin Jacob <jerin.jacob@caviumnetworks.com> To: <dev@dpdk.org> CC: <konstantin.ananyev@intel.com>, <thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>, <jianbo.liu@linaro.org>, <viktorin@rehivetech.com>, <santosh.shukla@caviumnetworks.com>, Jerin Jacob <jerin.jacob@caviumnetworks.com> Date: Tue, 27 Dec 2016 15:19:16 +0530 Message-ID: <1482832175-27199-11-git-send-email-jerin.jacob@caviumnetworks.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1482832175-27199-1-git-send-email-jerin.jacob@caviumnetworks.com> References: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com> <1482832175-27199-1-git-send-email-jerin.jacob@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [202.83.56.97] X-ClientProxiedBy: PN1PR01CA0001.INDPRD01.PROD.OUTLOOK.COM (10.164.137.8) To BLUPR0701MB1713.namprd07.prod.outlook.com (10.163.85.14) X-MS-Office365-Filtering-Correlation-Id: 5e2c8607-8f32-4817-8404-08d42e3de8e2 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:BLUPR0701MB1713; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1713; 3:5BM1QFqdI3wo+BxRo5kLS+GiA61WZZik9yr9lNaQEiDxyrAMMD+pHZEEkftKj+oIkw6eMVDkZdF43XT64wkZNzsswIj3wWMdIgss84cp958GmGGaz3RWji/j1UL5tKY8wuZBRiXPgrD9J6obz+c9o2QQ8YBjEWVzxt1eT7+VKVv/5unjyfUpytC5/QK6tGpWsgeRs65KhjCljPW9+ty7i1KqrZV84jz03xI+hNixqyifcxqCqCl2ZqsfR5FppEUTC53VRRjddj9b3GiUSsLTbA== X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1713; 25:1pgNXuWaDgdm9MSRTjV00IXn+/LyVrV/+I7p1h1q1cfzV6b6VHcDIXh7GEWZCqO3fqZz1kkS/PoQy0mhep2jGLY6B4W+3slhbnsxePq6dOHGqMjnpF9qVaE09xTOhLRmyw2bNiU2jALusWUNZnl+3QvHlog/yA0w6sErX4BH+/jpMzq7Ko6zzK+gZ4GI3OwsrIR6Ro+Bek456xutDFSrBiMJ0raMX17Sr6O9Mee5VmDNU4n8kP/P/5j2Y2Mt+9vfg4tfbya3m11ZdqG76POGO8rD/mpn8/vk3TbBh2499+1fBi6vVauPMv9yKhatE/44NhKViU39UFwvd6VVAoVm+5EFW+JTXAnAuR8WKLAsYId7RWVSraX7K9BZVOfZRq6aYzaORVZvoR5FG6IxhdG298jXz8k4JZG/HlxVI6eOzzdXFf7Eem3I1CAaSAMcJETh0yeqJ9RdE26HJtaDi0DqUF4+jZ2txZX/uPVFO8l9aEQa+sSscKSNyKt53MW3iLslX5cNoc+49K/2qJ6gJTFrfe2+5zn3WDQc7sL0N9pJBA1w8giLwL3yMemaefrm8+hB4puHKP4odOsNOTPfePeVhD75w20Eik+hX6OrYw/UjiB4K7W2IqxmluKtjWgIj97VTBdUsin8PvKx+CUAt5AMwNsFSZbKU3jATosVmoCy2FFyClvRllCb1bF6XgTDoLeaWdyZvrnTUT3U6DmgJVfC2yQoBcda2mi/Vk4DCMAIOKN/J4ISdFffZ02bBNEwZZqpuVxmv2p5c/Sm/ONFSkADzimVjwNZBq3Ot+fUzHrTPcjRxbPD5ASwYkhRsreQmBrV X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1713; 31:z6sLmuPtslgM0DTuEfkMOszgQVaqeZrl1sU3zYBjeB5I5em+hyxnWoZhLQezpNRmX02beXZEcyNlfuV7+lbMjXa/kFcwVlPV4tS0xPwm11HDiOhBwjDoiSxh9+W2S0kFcM03AOJ72AlSFRoliTyUqC+WK4jT9rHZ8Le4ijHagcjakNYh7+WSdDeuHxpwl+mAT9Y/nMvZerKJeIhULih+FUiV234nXRH3KLbQtI5vxDnQzApIv6jnqlJbPZ2SO0WGhsSFXreifW/3BPWVUCtolq+cANLUKNUg3PpHMMY9omQ=; 20:nbiFepROAX1+uh7y3Hv+z6s1PZvUtHzo/Dw51DRvw7DNJ9ltnNasz4pMpd1uvY5R9S5zISpHFWkEHJjL9avS6rsieD3N4W4bQjQwI+tp8oXYTd1GeKwfkZbm6rJGa+u0DvFaneaIzqlNFbqvVZS2zeFnkBqyvS8Yk6D3f4S83pBpdR12N0kDp1oFEip8cBFOGzgOI2zipiDwjPvPUC7GCxWXovucRu8TqW6ICWlOJVNHHEaWiZctYe3MHSlqy43spZ1dotmHudT37tKb3JTBaxLpN4b9r4N7ZGLknFQLweshxx87ec8PV2aJI66LWZtXwzL/xmU2mRsUKLr7gAoB0TiEUzl5aGyIZrC0al+m1RR9JssaqT4vrqlKSHwYFkL+ieCf7EoOBYDcZON2TZQeMAt7uJMvk44JxwPLkqvDnyKVw/r28Kq/Jrp/nm921yzuPY32jalo3Eq/W6E3Rw7OoJ/jUOZGf52MivjMGHjhEuqqtiX97Rx6Yo3IcMtsiCpmtT8qN0H6n4GExmmxGq1EukAEodZ2FW8xAGYmvy0xrg3ELTWzCEJb9FcruDlWAblmOHlcP3dbdwNCS/F7FeTRVFzd+UNEi6f6mc18C1LUUwE= X-Microsoft-Antispam-PRVS: <BLUPR0701MB1713FFE734A212432DD9DB6A81690@BLUPR0701MB1713.namprd07.prod.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040375)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(6041248)(20161123555025)(20161123560025)(20161123558021)(20161123564025)(20161123562025)(6072148); SRVR:BLUPR0701MB1713; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1713; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1713; 4:v4y1YkXcYX5QjAiVppl9A7ER6IaVUQu7uXXag67Ywq2dc6g4UjW4oF+Q4Ipajc5A//2nvyL6OziFaDZfX2zb3kSar8YIzjH2usEcGXWX0x3REXv0KyzMh3TT/UzqQDUZ/XrLamokNbRc+fV15TJsFarFo7coQUVoZyPtt8Pt6NrX2tpb5WwCYF722vkV3K4xTeefeR0towebxxqYRDjfYjlT6s/8v61TIiVrtSQjxWVfTbsP5ce6OMLNz2HtrFQF/Y6nNVJ4UQS49KHP7MzhiwxK2dO9xFI6ibJN711ytQztxFmFlEvcTrd+K0p5oxBEBOyLE7PDljjqeobkSj2lNICyi8YLZSgxKdkbxxgMl+6nd8GsTc/JtE8imEedozj1LwimGa/JxbhmrKVBtzQEUAE7pzuTUch3JybaBSnEoBPiS1LmVR9mp0y8vRA/w3lvUqMBP3X2qieBmPULbifYpA/CT/QjLaXiiuESZmNxqrHi/ODu2XS/SvUUHz3Doyqz0soDxmFHhCplitv4SOblN83pNH81zXzh8LeD3ax70h20XYSL6EQDz8IOSKNpxzBy6Pt+352ex97/nBowWOV+92oAv+78PKWc2MuRQEFdXsU= X-Forefront-PRVS: 0169092318 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4630300001)(6069001)(6009001)(7916002)(39450400003)(199003)(189002)(4001430100002)(3846002)(4326007)(6116002)(50986999)(76176999)(5003940100001)(6506006)(6512006)(6486002)(92566002)(2351001)(50466002)(110136003)(305945005)(8676002)(66066001)(2906002)(101416001)(81156014)(81166006)(42186005)(50226002)(68736007)(106356001)(36756003)(97736004)(33646002)(107886002)(48376002)(105586002)(38730400001)(7736002)(6916009)(5660300001)(42882006)(47776003)(25786008)(189998001)(2950100002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1713; H:localhost.localdomain.localdomain; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; Received-SPF: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1713; 23:KhrQKSIneNNeqgaQl6hr9Yjq/bk+TE9mmSaCAX+?= =?us-ascii?Q?UVm0gvhhu9GbXIf6igsiByn2i5GjPf90XduOBUm0ATFT7AufVkkTotqfMYvk?= =?us-ascii?Q?TnQr9eEAXuFFveYvu0JtQ4MX9/DU0Bhf38tDTk9cYbRPIvWZEzwJfoIw38Ih?= =?us-ascii?Q?8WOv0jscoJYQzXJyy7eYzYvYpt+gyocYnnJ5HBR5mtvv7dOwdhMuy3EvaPtr?= =?us-ascii?Q?vTOJocbegevJa2PALxWCeuvdsP+QRO2ornUrbKFCabMiutSBWlrhKUDwZKYV?= =?us-ascii?Q?+MBOgnc1A6XluNdYD6YkcGaVpVfmNxg8wSD2CmlyNwvU9IIEi+RhkIqgWxc+?= =?us-ascii?Q?5+mwaXtIM49dlzYB4MUOWowSQfMWC9nL0xedOoSXIT3utDq3CYUWuA1zlss3?= =?us-ascii?Q?DQz+kkFM5bRC8QmsXN7rpACz4CSx1qNmj8TWtNMgnHIbTaQvfz8MWllPJRgt?= =?us-ascii?Q?NtwXCcD2X/VDKfg0laW0SVaojIAnCH9gqOx9VHlnQcmUX8nQogT2EcadvNm8?= =?us-ascii?Q?gsw2flY6QSDyjV2t9IRTg05Tkm8JeF1iyC8DVRKfCRH+/g1mjibIBo8K7DLc?= =?us-ascii?Q?lZtbFsiSLTN1MN1+z5jqV6F1c/4Mv4ebh1j+KM9nYs+f9sBNzwlTKh7q+AwC?= =?us-ascii?Q?92cR8vXtSSg9tzK7LdMBXgeLvdgtrfXjR5W9f4V2vLLcZHsNVUJ4loQgVd/k?= =?us-ascii?Q?XUEotPTjmD2pz6RZQv+1q/eAD23Qed7eErYsUAwCxCg4zEBzBFU3LdtL/oSx?= =?us-ascii?Q?X8Mj8NcwrqSMJQjid4IJMKhQuL0rZ1kWlLVVvdOp9AAwgT5EamsXlRJyJXGJ?= =?us-ascii?Q?oZECuMX4jPxat/8KVaFehv4yb2Laq3Jusi5lKHSZUyAuHpLc4ICWWc0jG3e4?= =?us-ascii?Q?DyfNVLfNnut9bJQ/Scu+IDrbCz4G8gGOG2bCSW/1XoKKrqwZWajlLaW7uWjQ?= =?us-ascii?Q?OG5Hx8lhXoXmHbLeECo2Brm07eA+twdRu+d6oJ5e/lTu0BHlTsvlzoxt5c3z?= =?us-ascii?Q?CiLstBPT90ASXfXM4aDmmWWOzviwZ8EhwQfbwZ8NeUNOaYvHEruvc5LFpa69?= =?us-ascii?Q?3YUPzM877ndPNiQd+ZGSOLuUmEDL3M9b3RupWPxXYtyyCNGJcfQU2SA+CvM7?= =?us-ascii?Q?dJ01fCuKNn5O6MYErrg+dSikORx0cgqap?= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1713; 6:jh3BSNHskjkXPh1ccLkSLOa3ZR9w20eIAgsMvAYQ39uiAv7oNR+Pa18S8jWyWYVN1pZVLkwdUMP0GvECo79j90SV4xMgeajHOxBw5xFFA5qOPdAPpRrtCi/39zAN4zf6rBI2qq0tLQNbGOBEHwp+ZQCI2kbpV0onVsCJezLC5oYcdPiefQVXxrzWiu2vXcDF3hSRa1SQezh65fBsZBpvVBMcgOE3ZjpO9yiEjtskYO7GobFb3Ffa2oLkYaeZwWX3D5wnoG19P4Q6ljsAE57ZrjWV/RYwdpq9V0IYQ2XumPyEQrFGprf9+xweC843J6sZHBk/ikSFbIgJFs2fDHzNQRM4PXAf95CeskyN1Ok716I8peTHSOSpzg490QPYYLFHX7XYuC/te8ZUD/QaaXm+gVfJUsrrcaoaDlrQXj99u9g=; 5:uaGBqYLepuZM+cC20DZFcCHJxjz5N41ablgcD9V6c47XG1qx0e+l2sYYLWLB7tWvO42+VwrPoFokCsaek2ZkxHpVLFT5zQj0TsmDJLRLeLdLM2AR+MQmGQoW8NRUqBC93sEpJcOTfb/3jCuz7/QYiQ==; 24:nW/SLy5FTQGlH6NgE2Fnm6tPCaek3uPZwRogx+cDd2yARP1uQB7nmUGahUbBIrvyUZxggGSJNCZi0vB2JVVcb1b/psRyhT0dCPm80teLp5s= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1713; 7:6tfCrhnmiV95NuffmRoxtvf6jrBsI0tx9rqJGYDKibY41edOIpFtjmIACS/RtQ/T+4vYuRIUPXC4SRL+X/t+rrncneUdhtxy6ZaLipOfa6JN5mLgE34sXvUahzub94MMhTi/ATb9QvTxzunx9bNwxnpe0u/F+mXv7ZA0PLdJ9V2o9Zklq5Px9zPHGO65FEXSoi8uTsWpfjXHYWNPOyikB73qq0WZQbMuLE2mwRWfrzUNBILjDghzAK8QY47IFr54/wKEMCiOcyix0cn957LYsLo/yKFPsaKP/kj5Kezxab2VF6xeQ399xoeMdox5CGWLyCwr+hhGceg0v22VzQaPw+m4xvGvh33OgY3w44VYcCF8w61EsfN5XmPnLOJto1d3nQDwD+/68VW0SRy3ckujw4LbA65HTITwsBRIWI7XfkA/VTqBGtHzf88lfagtwicKTS6xzHENq4++ocF4anTKQQ== X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Dec 2016 09:51:17.4600 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1713 Subject: [dpdk-dev] [PATCH v2 10/29] eal: introduce I/O device memory read/write operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <http://dpdk.org/ml/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://dpdk.org/ml/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <http://dpdk.org/ml/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Tue, 27 Dec 2016 09:51:21 -0000 This commit introduces 8-bit, 16-bit, 32bit, 64bit I/O device memory read/write operations along with the relaxed versions. The weakly-ordered machine like ARM needs additional I/O barrier for device memory read/write access over PCI bus. By introducing the eal abstraction for I/O device memory read/write access, The drivers can access I/O device memory in architecture agnostic manner. The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access. Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> --- doc/api/doxy-api-index.md | 3 +- lib/librte_eal/common/Makefile | 3 +- lib/librte_eal/common/include/generic/rte_io.h | 263 +++++++++++++++++++++++++ 3 files changed, 267 insertions(+), 2 deletions(-) create mode 100644 lib/librte_eal/common/include/generic/rte_io.h diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index 99a1b7a..47a3580 100644 --- a/doc/api/doxy-api-index.md +++ b/doc/api/doxy-api-index.md @@ -70,7 +70,8 @@ There are many libraries, so their headers may be grouped by topics: [branch prediction] (@ref rte_branch_prediction.h), [cache prefetch] (@ref rte_prefetch.h), [byte order] (@ref rte_byteorder.h), - [CPU flags] (@ref rte_cpuflags.h) + [CPU flags] (@ref rte_cpuflags.h), + [I/O access] (@ref rte_io.h) - **CPU multicore**: [interrupts] (@ref rte_interrupts.h), diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile index a92c984..6498c15 100644 --- a/lib/librte_eal/common/Makefile +++ b/lib/librte_eal/common/Makefile @@ -43,7 +43,8 @@ INC += rte_pci_dev_feature_defs.h rte_pci_dev_features.h INC += rte_malloc.h rte_keepalive.h rte_time.h GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h -GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h +GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h rte_io.h + # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk ARCH_DIR ?= $(RTE_ARCH) ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h)) diff --git a/lib/librte_eal/common/include/generic/rte_io.h b/lib/librte_eal/common/include/generic/rte_io.h new file mode 100644 index 0000000..edfebf8 --- /dev/null +++ b/lib/librte_eal/common/include/generic/rte_io.h @@ -0,0 +1,263 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Cavium networks. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Cavium networks nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_IO_H_ +#define _RTE_IO_H_ + +/** + * @file + * I/O device memory operations + * + * This file defines the generic API for I/O device memory read/write operations + */ + +#include <stdint.h> +#include <rte_common.h> +#include <rte_atomic.h> + +#ifdef __DOXYGEN__ + +/** + * Read a 8-bit value from I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint8_t +rte_read8_relaxed(const volatile void *addr); + +/** + * Read a 16-bit value from I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint16_t +rte_read16_relaxed(const volatile void *addr); + +/** + * Read a 32-bit value from I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint32_t +rte_read32_relaxed(const volatile void *addr); + +/** + * Read a 64-bit value from I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint64_t +rte_read64_relaxed(const volatile void *addr); + +/** + * Write a 8-bit value to I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ + +static inline void +rte_write8_relaxed(uint8_t value, volatile void *addr); + +/** + * Write a 16-bit value to I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_write16_relaxed(uint16_t value, volatile void *addr); + +/** + * Write a 32-bit value to I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_write32_relaxed(uint32_t value, volatile void *addr); + +/** + * Write a 64-bit value to I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_write64_relaxed(uint64_t value, volatile void *addr); + +/** + * Read a 8-bit value from I/O device memory address *addr*. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint8_t +rte_read8(const volatile void *addr); + +/** + * Read a 16-bit value from I/O device memory address *addr*. + * + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint16_t +rte_read16(const volatile void *addr); + +/** + * Read a 32-bit value from I/O device memory address *addr*. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint32_t +rte_read32(const volatile void *addr); + +/** + * Read a 64-bit value from I/O device memory address *addr*. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint64_t +rte_read64(const volatile void *addr); + +/** + * Write a 8-bit value to I/O device memory address *addr*. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ + +static inline void +rte_write8(uint8_t value, volatile void *addr); + +/** + * Write a 16-bit value to I/O device memory address *addr*. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_write16(uint16_t value, volatile void *addr); + +/** + * Write a 32-bit value to I/O device memory address *addr*. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_write32(uint32_t value, volatile void *addr); + +/** + * Write a 64-bit value to I/O device memory address *addr*. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_write64(uint64_t value, volatile void *addr); + +#endif /* __DOXYGEN__ */ + +#endif /* _RTE_IO_H_ */ -- 2.5.5