From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0076.outbound.protection.outlook.com [104.47.32.76]) by dpdk.org (Postfix) with ESMTP id 136B5F973 for ; Tue, 21 Feb 2017 10:28:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=F7vgLu9ZicTcZBEQThZxmWhc1i+geCQJtdfm7KTnrm4=; b=nnnLJoM10FCJGJq1gIYKzKK+uW5YEEY0pIlruzZNDcHxBSyKFZbyhzR1LutzKZydmPgv4n/6iQGQnMtdO+DRU4qO3sJwMMoZ1s1bFKJ9ZNQM5uKnlxv9rmL7a8bKBA3mod007hOME4C3GGdJNQSDQNYZoMe/nN1ntX49CBoDizM= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Shijith.Thotton@cavium.com; Received: from lio357.in.caveonetworks.com (14.140.2.178) by SN1PR07MB2285.namprd07.prod.outlook.com (10.164.47.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.919.13; Tue, 21 Feb 2017 09:28:52 +0000 From: Shijith Thotton To: dev@dpdk.org Cc: Jerin Jacob , Derek Chickles , Venkat Koppula , Mallesham Jatharakonda Date: Tue, 21 Feb 2017 14:56:31 +0530 Message-Id: <1487669225-30091-17-git-send-email-shijith.thotton@caviumnetworks.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1487669225-30091-1-git-send-email-shijith.thotton@caviumnetworks.com> References: <1487669225-30091-1-git-send-email-shijith.thotton@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [14.140.2.178] X-ClientProxiedBy: MA1PR01CA0089.INDPRD01.PROD.OUTLOOK.COM (10.174.56.29) To SN1PR07MB2285.namprd07.prod.outlook.com (10.164.47.155) X-MS-Office365-Filtering-Correlation-Id: 4e333f77-d056-45c7-ec4e-08d45a3c0e88 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001);SRVR:SN1PR07MB2285; X-Microsoft-Exchange-Diagnostics: 1; SN1PR07MB2285; 3:C6PSSb6yf9NB/Qdkj6dgJfxpB3UHXkjohCThQdUvLVIvOUwsl51/d2V3U6yOf53QP8Nbx/LV5dB3VtuF1eRJspQn2d70Gv6Hz3cu1vZx0vY7fRrmoXZJ4qXGnmFMjuMkAYYcAAlKCzHzEijj7zP2WJi2y9s1tvNCzGs9p2U97ovgJViDrXzSVMx6sLlmxaSu2QQIQD1qM7R0Luw5GUocTBOgv1yL14rRGaUeGHzsKmA2/8Rk4MrKb5QYA2AkGPwSF8brzDYtGxPwvStW/grxYQ==; 25:eW2HQmXsmROATp+RsnaOyMxmvVtUO1f1dBVYRIKlf5CK3L7p0ksfmeKr5A8U1103bOEUXVkhkQ2a5U4jT2wcGGLzy3eLmxgxSUMyFXJ3EvA4oFan0DZO3X04MW3K2bF0HOez0pbmlXTMvS8i9IgnM7K4OvjfEgt6hPL68JOR9Brost+e7nrvZJ5ISHNcVjc3CYKNb4r/anhmuRScAGtLa2ZA6ofRCLeDzgFtzMpUONwCDZnsDHzd79FGVtStZ0LkEBm0cX9GCGmdZ7eEEyj4XTzZC2c1DWqtcU9avypHzT9jW0eaOba/+msbZ4KrNA6KmKQbAKTDNosageHqnDjUWrX4s7ouILvu6falmucxY/ssVvYhBDCsz6M8J0i10+O97iEtU4K762XSg11mml98oxMAQphBL9AY6MlpS3QHnRx603fi3+gg/yl7aBqZWCHtHn27+56EABdjimFsEi/RJQ== X-Microsoft-Exchange-Diagnostics: 1; SN1PR07MB2285; 31:ts47Do5Wp0Vt4MQAibaVzIahhFnYHJ6Yal+YzFmDmZTukEIC4d+YsWjM+9kUCXSny46nYj4gSqZa1R/lP1jfzO7EztYIdusJsFdbLs1kgTmYjPfbOKGSQpuimllKzpOZOXZOWnykJBWSYNye/X0j0XeTZd16cnRtXBslCehXj4d06ZGwuO3dGPrWRRbhXwlJyEFciKvVJCA7yOBW2cF/x55JllZQ+kocUrdedJsQ7i0=; 20:YiuNoZ0T/rSsw6uE+PU/sgWY0E7tPC+6BMoKQfOWJzo4pt7t+lQA0tsAN2VwAsiTr9WXMrxBMbdAz4+WVcwWV6+LY0LyGXCZLbPLx1vTwQBX1glp5MDMzp7R/GBEfH1nS5bTdYQ4x3exNVgJxMH57YtYq8jlXCIpfsldRp67sQcWPwUqswPMLA88UISaIcbVZl9Q+bL/yIrLA2Uau4lA+KXMBI3BdyYwmHBC6qXs3B3qjRRIFyzK/ALGfNxiyHaSvYVr9G960Qczd+0XFzRI8pDVpKwMh5pjJL2J73AIjFZeJbTzD/6bZVRXqE2lLIf/IbNYyCublKIrq4M0+pMzI3tq7Zt9BwUWLi1kwu9D+mw5ulMpEh0P8ktZ8iPhE+56hdzyNhEdqfJHi+CgvVS/t/4z9KKd6W9Cld2uSySa/ZWOCNy4vtH0A+PxCZR1iSAkZZpoMZXWhGZmVNcDJ7iD2CjC0WwAwRV0E6wIVV2030aU1LJDIiRGd0YvSYMQWrjjcuXJErCSlmcIH7nICuAPGs2nNEOvCkSq7tv4En/geoEFjqV1DNaiJHJbopzYdDIDF7jnbG5xBFxZJgHsbXoB1ZVC0OBbp+ZNGGCuQVwIwkw= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040375)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6041248)(20161123555025)(20161123564025)(20161123562025)(20161123560025)(20161123558025)(6072148); SRVR:SN1PR07MB2285; BCL:0; PCL:0; RULEID:; SRVR:SN1PR07MB2285; X-Microsoft-Exchange-Diagnostics: 1; SN1PR07MB2285; 4:j7Q5iLL5CBVUN5dHMw7Jv7aTF+X/B3lueP5raNLypoMzjPwG20oVWPyPMzaL9Oy480stjSWK8yL5ttwsA5427GRpnF28bxevOI66jZ47dhKoqY/gsWs0/qWcOePGgOQ19qF3V5Ha2iJ4lnlXUPufwLw94eMfB5bvJ4ZftdQrSKCt0NOBsO1l5dMu4B35ihV1gSgWjJ1ajH8Qz9NOHZG8Ep0lihS4TGoV95W4Y4hNxZMNmw5d3/bGVsz8t/2bZOakRa+jPHZ3nquWQgU1BDgiNAamDLYB06MjfpSKA2qIJcK9bwkXj514+3i/X2d2zqXhmXDymaoov6xduIb1+EO/SyqEsAPtqWxWYk+WT6InUZKyUhrQ+Vp7MIfjBFOQJK6LQe7zmcH6wZYJ3fNuFPUfI+ohBwYJs62y5lxUCmFDbpuliELG+ix6Kg2Ea1CpAk2rKmVXVdPk/PtvGMYPDPovYFYAkd2B0mXZnpVwo+5zqC9svABEKXzrAPoSBPcjwNhwUL6VbzwmXz2qk8s6QslaK6MjL3AROUKGWd2xCm/B6t20A3aZnWS4X8uF3rv5zC9LFMTZjFXH51Rtd1wF2AW+s9d/BxtwaXRl8YRYnPUcOn0= X-Forefront-PRVS: 0225B0D5BC X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4630300001)(979002)(6009001)(7916002)(39450400003)(39410400002)(39830400002)(189002)(199003)(50226002)(81166006)(42186005)(2361001)(101416001)(81156014)(305945005)(3846002)(6116002)(5009440100003)(8676002)(105586002)(7736002)(53936002)(36756003)(110136004)(106356001)(6506006)(25786008)(38730400002)(2351001)(92566002)(48376002)(6486002)(97736004)(50466002)(5003940100001)(189998001)(68736007)(2906002)(4326007)(33646002)(76176999)(54906002)(5660300001)(6666003)(6916009)(50986999)(2950100002)(6512007)(4720700003)(42882006)(66066001)(47776003)(7099028)(110426004)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:SN1PR07MB2285; H:lio357.in.caveonetworks.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; Received-SPF: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; SN1PR07MB2285; 23:97AEST8Qgv33NR3vvB3h7qlJidd3e4BIvq+DN2HP9?= =?us-ascii?Q?Lk9J7m/xcyVgK1cq04dgqv+A1nPIW4MTK3jcMpgn1ZwsVaEvSlciCPW+yttB?= =?us-ascii?Q?I1oiz7AKatYU89Nh5uQS31B1PhzxZieUVZoEvWR/UigBF1idBFn4oEyJ1Hul?= =?us-ascii?Q?F2l/wPzfy8Saf4jTW/STFH2MXr2W8lm373nH9eS1EvjCpc7NS4rC2Cnf+fPW?= =?us-ascii?Q?Ebt4wVzd4CNI/vtPQo/++ZV1+TpJ7n4d9pigj7XjfrWIVW82VzIkxxgj5V4Q?= =?us-ascii?Q?w2nVzHsLMtSzfACoyitnJstkdZns7y5YdMLZFV6jqgwlv+Qe9HPmPNUBvrya?= =?us-ascii?Q?7Y3OAu/z3J+G/HAqr+gtU5Qx9WJPtiNR3YF68+2AtxEg7Qj3Y6bWBWFFFG7p?= =?us-ascii?Q?iyw30eIaNVihZ3XdUIPKC/bQdIMf6PfKlvMlws6p5EFMCWBilTrfinnhnaCe?= =?us-ascii?Q?31qOzWDplED46mDbnRx7t0tnCFxO36COPLdj//77u7NANr/nnwo9T19MtZ3o?= =?us-ascii?Q?FXDIgnaS48ZusmSUzBU4x3nWKkxR7ZZBUqORd3jhPaebGVYfmCuW4AUzOs8+?= =?us-ascii?Q?GITbVRMYmu3kKRHG7h52z65eu2aseeJgMlWKZR5OWsAkE/EoMMo3A3SRs2FK?= =?us-ascii?Q?YwE7fdKKblFkhAJ4l+M2ZvdIAfcRqnaiHazJopVr+NBCww4FGCGtwd4Eanzd?= =?us-ascii?Q?WcYjVAHG7EobD1cIiWi98Kp53m+HycQjBSJcsmWOgrvuUygLR4QV0WKFe/7C?= =?us-ascii?Q?U6zTBbVD1QJ54yKPAWcRw8SQROZbBtUAieMYGcMReEi/XYZg1PPwSE+DE2d2?= =?us-ascii?Q?q3rQjbcfOGqtkw/0v97re14oLuiRiiXMrOvw0w9d1U+4sQg3tXLWSaeJesMd?= =?us-ascii?Q?EPydhvlyJ3cyWWwLbHpS0Dlqd3fOqyGxkVzljkQ3oRoZx8EGH3ao6MVCYZC0?= =?us-ascii?Q?LLwiQfHdyEcPPIUx/W9Mp4mcL0M4GG5mqkB7jLf9+2LwDoOebrco2Cs0hfls?= =?us-ascii?Q?b5Ph4/aEgNrHMGshgckYtiZDuPXXzy/ckiM9r7L3TcOa40mhUNAKGsEd+k6m?= =?us-ascii?Q?h4WYE92g5BeFeS3oEl0QCHuuIZwO+KM0HI/8jQcUAYFHtR9EO8O1phGu1FPv?= =?us-ascii?Q?YZOxw+a14K/nnNPmGU0T6jWBktIXEpdsKvZO7R/CCV9i8arotA/ZmtRppYWK?= =?us-ascii?Q?db9m7zZMAgA49TBTr3QxInucsHxDLeo+2lPMRBwjm9Wnm2BrZzDmwtO1WNQ7?= =?us-ascii?Q?51gWMW+yH+vQd6M0O8mGDq6TorTFRk9ukhxhG+r5nrqJnLoyRpSSrnAdPDng?= =?us-ascii?Q?2uRRNye/CSw/Jp+O0rpNZqPMC30us5Q9aAlFD+U67gYXuVMwZdxcoxrJjijj?= =?us-ascii?Q?GrpDfP4H8kon6M1eVtecH7ArK5fPYXlB95aWhvUg43eybn1?= X-Microsoft-Exchange-Diagnostics: 1; SN1PR07MB2285; 6:iQZy4a+o0SwqnijZpIsf3TA0l5q0EcZI7t65ZjzLGxWvr5o6C26iAtx3zw6PLyvL2jhu77h/kHGXFlQCqhSyg6zhjVs27oMJxg9z9iiiujY/IzTn46rF7fdeoXpq5MJGN4CCeTE9a9S8bzEktiwqY6GjND0TGl/P+89OqXpy1zuB8sJ98SgX9SQXGntEc+Z8rnBTA7dYG1r+/LQU5lkWhS0GHRKS8qbncjE/w5p9zYrhPkx7SCelJ+Bb0RHWvIYMBLb6JkC7zVkeFU3F5FQkteu3HaArOQyMO4ICWzOSdhtMOCS/yFLIenpqpC1HpSI6FwAmTFn7BlIFy2wWBNFfgJIK3nJ7U0EE/1WNydQPoAhgpEbvNEjvoUqy1rYXjjJnHKWq/KEX8ypqnuGe4QdwUA==; 5:cgO1EmKMVr0eNuL8eolUEst8OpFRJYG4zNKf1CqBuMDp7elRRn2Ge/WQihN7d3/wtkcfpG/G3u/MadZsD+tpr9niBHPubPpavZZFLZjZSRYTCnHqXLIi1GeFZLzLmevPM42oI2wXucP8cKv+QhqfsA==; 24:6Vb1cmZdjtLZkyWAfJW8MkoqKDt5Dw5tVCu1uDLIlO4vDZYdPiZ3qdV57v7NxIHrIeXtW6QahC7r/hWJw6puLyNtccOHGftiTik8ZZcywLY= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; SN1PR07MB2285; 7:wfZjk9doRcGhTa3rqf5sc7xMezwnPz2uKblpqK0qHdDqmwLxaQ6YWJksv+sKOgHtF3yMf1xrnUAlBURFIHrpgzSgqCixOizhq7a9ao/Iql6rTjsrwMnTRpiRhbfZFgikEzlzSgHlQnMD+dgfe3zE3uheUZB4kfnBOi5C6uE/cag+ZQD1HLKqveCBZbfwAT324SfyT/xtxCrUuHFMhtJ2TMnRlAj5laG9ue9gtHN18sC2bM6LdslOv9/CQSw+WE6XmImyHoPDArYlbOciE1/vfrip+1Lp3csfnDL4nAT0NnGWLw92sprA+P8WnWKdrnAJL7mw8HZQqcV2xdke1NguHg== X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2017 09:28:52.9786 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR07MB2285 Subject: [dpdk-dev] [PATCH 16/50] net/liquidio: add APIs to allocate and free IQ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Feb 2017 09:28:57 -0000 Add APIs to allocate and free instruction queue. Allocates instruction queue 0 initially to send device configurations commands and later re- allocates as per application requirement during tx queue setup. Signed-off-by: Shijith Thotton Signed-off-by: Jerin Jacob Signed-off-by: Derek Chickles Signed-off-by: Venkat Koppula Signed-off-by: Mallesham Jatharakonda --- drivers/net/liquidio/Makefile | 1 + drivers/net/liquidio/base/lio_hw_defs.h | 12 ++ drivers/net/liquidio/lio_ethdev.c | 8 ++ drivers/net/liquidio/lio_rxtx.c | 206 ++++++++++++++++++++++++++++++++ drivers/net/liquidio/lio_rxtx.h | 57 +++++++++ drivers/net/liquidio/lio_struct.h | 112 ++++++++++++++++- 6 files changed, 395 insertions(+), 1 deletion(-) create mode 100644 drivers/net/liquidio/lio_rxtx.c create mode 100644 drivers/net/liquidio/lio_rxtx.h diff --git a/drivers/net/liquidio/Makefile b/drivers/net/liquidio/Makefile index 451f49d..de2ef9b 100644 --- a/drivers/net/liquidio/Makefile +++ b/drivers/net/liquidio/Makefile @@ -51,6 +51,7 @@ VPATH += $(RTE_SDK)/drivers/net/liquidio/base # all source are stored in SRCS-y # SRCS-$(CONFIG_RTE_LIBRTE_LIO_PMD) += lio_ethdev.c +SRCS-$(CONFIG_RTE_LIBRTE_LIO_PMD) += lio_rxtx.c SRCS-$(CONFIG_RTE_LIBRTE_LIO_PMD) += lio_23xx_vf.c SRCS-$(CONFIG_RTE_LIBRTE_LIO_PMD) += lio_mbox.c diff --git a/drivers/net/liquidio/base/lio_hw_defs.h b/drivers/net/liquidio/base/lio_hw_defs.h index 890ef17..2262de3 100644 --- a/drivers/net/liquidio/base/lio_hw_defs.h +++ b/drivers/net/liquidio/base/lio_hw_defs.h @@ -76,6 +76,18 @@ enum lio_card_type { #define LIO_23XX_NAME "23xx" +#define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \ + ((cfg)->default_config->num_def_tx_descs) + +#define LIO_IQ_INSTR_TYPE(cfg) ((cfg)->default_config->iq.instr_type) + +/* The following config values are fixed and should not be modified. */ + +/* Maximum number of Instruction queues */ +#define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF + +#define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES + #define LIO_DEVICE_NAME_LEN 32 #define LIO_BASE_MAJOR_VERSION 1 #define LIO_BASE_MINOR_VERSION 5 diff --git a/drivers/net/liquidio/lio_ethdev.c b/drivers/net/liquidio/lio_ethdev.c index 23dfa43..3b11993 100644 --- a/drivers/net/liquidio/lio_ethdev.c +++ b/drivers/net/liquidio/lio_ethdev.c @@ -39,6 +39,7 @@ #include "lio_logs.h" #include "lio_23xx_vf.h" #include "lio_ethdev.h" +#include "lio_rxtx.h" static void lio_check_pf_hs_response(void *lio_dev) @@ -127,6 +128,11 @@ goto error; } + if (lio_setup_instr_queue0(lio_dev)) { + lio_dev_err(lio_dev, "Failed to setup instruction queue 0\n"); + goto error; + } + dpdk_queues = (int)lio_dev->sriov_info.rings_per_vf; lio_dev->max_tx_queues = dpdk_queues; @@ -137,6 +143,8 @@ error: if (lio_dev->mbox[0]) lio_dev->fn_list.free_mbox(lio_dev); + if (lio_dev->instr_queue[0]) + lio_free_instr_queue0(lio_dev); return -1; } diff --git a/drivers/net/liquidio/lio_rxtx.c b/drivers/net/liquidio/lio_rxtx.c new file mode 100644 index 0000000..de98fc6 --- /dev/null +++ b/drivers/net/liquidio/lio_rxtx.c @@ -0,0 +1,206 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2017 Cavium, Inc.. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Cavium, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include "lio_logs.h" +#include "lio_struct.h" +#include "lio_ethdev.h" +#include "lio_rxtx.h" + +static void +lio_dma_zone_free(struct lio_device *lio_dev, const struct rte_memzone *mz) +{ + const struct rte_memzone *mz_tmp; + int ret = 0; + + if (mz == NULL) { + lio_dev_err(lio_dev, "Memzone NULL\n"); + return; + } + + mz_tmp = rte_memzone_lookup(mz->name); + if (mz_tmp == NULL) { + lio_dev_err(lio_dev, "Memzone %s Not Found\n", mz->name); + return; + } + + ret = rte_memzone_free(mz); + if (ret) + lio_dev_err(lio_dev, "Memzone free Failed ret %d\n", ret); +} + +/** + * lio_init_instr_queue() + * @param lio_dev - pointer to the lio device structure. + * @param txpciq - queue to be initialized. + * + * Called at driver init time for each input queue. iq_conf has the + * configuration parameters for the queue. + * + * @return Success: 0 Failure: -1 + */ +static int +lio_init_instr_queue(struct lio_device *lio_dev, + union octeon_txpciq txpciq, + uint32_t num_descs, unsigned int socket_id) +{ + uint32_t iq_no = (uint32_t)txpciq.s.q_no; + struct lio_instr_queue *iq; + uint32_t instr_type; + uint32_t q_size; + + instr_type = LIO_IQ_INSTR_TYPE(lio_dev); + + q_size = instr_type * num_descs; + iq = lio_dev->instr_queue[iq_no]; + iq->iq_mz = rte_eth_dma_zone_reserve(lio_dev->eth_dev, + "instr_queue", iq_no, q_size, + RTE_CACHE_LINE_SIZE, + socket_id); + if (iq->iq_mz == NULL) { + lio_dev_err(lio_dev, "Cannot allocate memory for instr queue %d\n", + iq_no); + return -1; + } + + iq->base_addr_dma = iq->iq_mz->phys_addr; + iq->base_addr = (uint8_t *)iq->iq_mz->addr; + + iq->max_count = num_descs; + + /* Initialize a list to holds requests that have been posted to Octeon + * but has yet to be fetched by octeon + */ + iq->request_list = rte_zmalloc_socket("request_list", + sizeof(*iq->request_list) * + num_descs, + RTE_CACHE_LINE_SIZE, + socket_id); + if (iq->request_list == NULL) { + lio_dev_err(lio_dev, "Alloc failed for IQ[%d] nr free list\n", + iq_no); + lio_dma_zone_free(lio_dev, iq->iq_mz); + return -1; + } + + lio_dev_dbg(lio_dev, "IQ[%d]: base: %p basedma: %lx count: %d\n", + iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma, + iq->max_count); + + iq->lio_dev = lio_dev; + iq->txpciq.txpciq64 = txpciq.txpciq64; + iq->fill_cnt = 0; + iq->host_write_index = 0; + iq->lio_read_index = 0; + iq->flush_index = 0; + + rte_atomic64_set(&iq->instr_pending, 0); + + /* Initialize the spinlock for this instruction queue */ + rte_spinlock_init(&iq->lock); + rte_spinlock_init(&iq->post_lock); + + rte_atomic64_clear(&iq->iq_flush_running); + + lio_dev->io_qmask.iq |= (1ULL << iq_no); + + /* Set the 32B/64B mode for each input queue */ + lio_dev->io_qmask.iq64B |= ((instr_type == 64) << iq_no); + iq->iqcmd_64B = (instr_type == 64); + + return 0; +} + +int +lio_setup_instr_queue0(struct lio_device *lio_dev) +{ + union octeon_txpciq txpciq; + uint32_t num_descs = 0; + uint32_t iq_no = 0; + + num_descs = LIO_NUM_DEF_TX_DESCS_CFG(lio_dev); + + lio_dev->num_iqs = 0; + + lio_dev->instr_queue[0] = rte_zmalloc(NULL, + sizeof(struct lio_instr_queue), 0); + if (lio_dev->instr_queue[0] == NULL) + return -ENOMEM; + + lio_dev->instr_queue[0]->q_index = 0; + lio_dev->instr_queue[0]->app_ctx = (void *)(size_t)0; + txpciq.txpciq64 = 0; + txpciq.s.q_no = iq_no; + txpciq.s.pkind = lio_dev->pfvf_hsword.pkind; + txpciq.s.use_qpg = 0; + txpciq.s.qpg = 0; + if (lio_init_instr_queue(lio_dev, txpciq, num_descs, SOCKET_ID_ANY)) { + rte_free(lio_dev->instr_queue[0]); + lio_dev->instr_queue[0] = NULL; + return -1; + } + + lio_dev->num_iqs++; + + return 0; +} + +/** + * lio_delete_instr_queue() + * @param lio_dev - pointer to the lio device structure. + * @param iq_no - queue to be deleted. + * + * Called at driver unload time for each input queue. Deletes all + * allocated resources for the input queue. + */ +static void +lio_delete_instr_queue(struct lio_device *lio_dev, uint32_t iq_no) +{ + struct lio_instr_queue *iq = lio_dev->instr_queue[iq_no]; + + rte_free(iq->request_list); + iq->request_list = NULL; + lio_dma_zone_free(lio_dev, iq->iq_mz); +} + +void +lio_free_instr_queue0(struct lio_device *lio_dev) +{ + lio_delete_instr_queue(lio_dev, 0); + rte_free(lio_dev->instr_queue[0]); + lio_dev->instr_queue[0] = NULL; + lio_dev->num_iqs--; +} diff --git a/drivers/net/liquidio/lio_rxtx.h b/drivers/net/liquidio/lio_rxtx.h new file mode 100644 index 0000000..33f178b --- /dev/null +++ b/drivers/net/liquidio/lio_rxtx.h @@ -0,0 +1,57 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2017 Cavium, Inc.. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Cavium, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _LIO_RXTX_H_ +#define _LIO_RXTX_H_ + +#include +#include + +#include +#include + +#include "lio_struct.h" + +struct lio_request_list { + uint32_t reqtype; + void *buf; +}; + +/** Setup instruction queue zero for the device + * @param lio_dev which lio device to setup + * + * @return 0 if success. -1 if fails + */ +int lio_setup_instr_queue0(struct lio_device *lio_dev); +void lio_free_instr_queue0(struct lio_device *lio_dev); +#endif /* _LIO_RXTX_H_ */ diff --git a/drivers/net/liquidio/lio_struct.h b/drivers/net/liquidio/lio_struct.h index e8b6e1d..29059a5 100644 --- a/drivers/net/liquidio/lio_struct.h +++ b/drivers/net/liquidio/lio_struct.h @@ -50,7 +50,110 @@ struct lio_version { uint16_t reserved; }; -struct lio_device; +/** The txpciq info passed to host from the firmware */ +union octeon_txpciq { + uint64_t txpciq64; + + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t q_no : 8; + uint64_t port : 8; + uint64_t pkind : 6; + uint64_t use_qpg : 1; + uint64_t qpg : 11; + uint64_t aura_num : 10; + uint64_t reserved : 20; +#else + uint64_t reserved : 20; + uint64_t aura_num : 10; + uint64_t qpg : 11; + uint64_t use_qpg : 1; + uint64_t pkind : 6; + uint64_t port : 8; + uint64_t q_no : 8; +#endif + } s; +}; + +/** The instruction (input) queue. + * The input queue is used to post raw (instruction) mode data or packet + * data to Octeon device from the host. Each input queue for + * a LIO device has one such structure to represent it. + */ +struct lio_instr_queue { + /** A spinlock to protect access to the input ring. */ + rte_spinlock_t lock; + + rte_spinlock_t post_lock; + + struct lio_device *lio_dev; + + uint32_t pkt_in_done; + + rte_atomic64_t iq_flush_running; + + /** Flag that indicates if the queue uses 64 byte commands. */ + uint32_t iqcmd_64B:1; + + /** Queue info. */ + union octeon_txpciq txpciq; + + uint32_t rsvd:17; + + uint32_t status:8; + + /** Maximum no. of instructions in this queue. */ + uint32_t max_count; + + /** Index in input ring where the driver should write the next packet */ + uint32_t host_write_index; + + /** Index in input ring where Octeon is expected to read the next + * packet. + */ + uint32_t lio_read_index; + + /** This index aids in finding the window in the queue where Octeon + * has read the commands. + */ + uint32_t flush_index; + + /** This field keeps track of the instructions pending in this queue. */ + rte_atomic64_t instr_pending; + + /** Pointer to the Virtual Base addr of the input ring. */ + uint8_t *base_addr; + + struct lio_request_list *request_list; + + /** Octeon doorbell register for the ring. */ + void *doorbell_reg; + + /** Octeon instruction count register for this ring. */ + void *inst_cnt_reg; + + /** Number of instructions pending to be posted to Octeon. */ + uint32_t fill_cnt; + + /** DMA mapped base address of the input descriptor ring. */ + uint64_t base_addr_dma; + + /** Application context */ + void *app_ctx; + + /* network stack queue index */ + int q_index; + + /* Memory zone */ + const struct rte_memzone *iq_mz; +}; + +struct lio_io_enable { + uint64_t iq; + uint64_t oq; + uint64_t iq64B; +}; + struct lio_fn_list { int (*setup_mbox)(struct lio_device *); void (*free_mbox)(struct lio_device *); @@ -170,6 +273,13 @@ struct lio_device { struct lio_fn_list fn_list; + uint32_t num_iqs; + + /** The input instruction queues */ + struct lio_instr_queue *instr_queue[LIO_MAX_POSSIBLE_INSTR_QUEUES]; + + struct lio_io_enable io_qmask; + struct lio_sriov_info sriov_info; struct lio_pf_vf_hs_word pfvf_hsword; -- 1.8.3.1