From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 782EB4CE4 for ; Wed, 1 Mar 2017 07:04:47 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 28 Feb 2017 22:04:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,223,1484035200"; d="scan'208";a="829601256" Received: from dpdk26.sh.intel.com ([10.239.128.228]) by FMSMGA003.fm.intel.com with ESMTP; 28 Feb 2017 22:04:45 -0800 From: Wenzhuo Lu To: dev@dpdk.org Cc: Wenzhuo Lu Date: Wed, 1 Mar 2017 14:04:47 +0800 Message-Id: <1488348292-118243-5-git-send-email-wenzhuo.lu@intel.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1488348292-118243-1-git-send-email-wenzhuo.lu@intel.com> References: <1488348292-118243-1-git-send-email-wenzhuo.lu@intel.com> Subject: [dpdk-dev] [PATCH 4/9] net/ixgbe/base: add bit for enabling L3/L4 filtering X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Mar 2017 06:04:48 -0000 Add a L3/L4 filtering definition of register MRQC for the future use. Signed-off-by: Wenzhuo Lu --- drivers/net/ixgbe/base/ixgbe_type.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h index bb1f85b..6acd966 100644 --- a/drivers/net/ixgbe/base/ixgbe_type.h +++ b/drivers/net/ixgbe/base/ixgbe_type.h @@ -2622,6 +2622,7 @@ enum { #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ +#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 /* Enable L3/L4 Tx switch */ #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 -- 1.9.3