From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0049.outbound.protection.outlook.com [104.47.33.49]) by dpdk.org (Postfix) with ESMTP id 6BC26F60E for ; Fri, 3 Mar 2017 08:14:04 +0100 (CET) Received: from BN3PR0301CA0084.namprd03.prod.outlook.com (10.160.152.180) by DM2PR0301MB0734.namprd03.prod.outlook.com (10.160.97.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.933.12; Fri, 3 Mar 2017 07:14:02 +0000 Received: from BY2FFO11OLC010.protection.gbl (2a01:111:f400:7c0c::198) by BN3PR0301CA0084.outlook.office365.com (2a01:111:e400:401e::52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.947.12 via Frontend Transport; Fri, 3 Mar 2017 07:14:01 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; caviumnetworks.com; dkim=none (message not signed) header.d=none; caviumnetworks.com; dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11OLC010.mail.protection.outlook.com (10.1.15.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.933.11 via Frontend Transport; Fri, 3 Mar 2017 07:14:00 +0000 Received: from bf-netperf1.idc ([10.232.134.28]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id v237D50K005035; Fri, 3 Mar 2017 00:13:58 -0700 From: Hemant Agrawal To: CC: , , , , , Date: Fri, 3 Mar 2017 18:16:34 +0530 Message-ID: <1488545223-25739-18-git-send-email-hemant.agrawal@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1488545223-25739-1-git-send-email-hemant.agrawal@nxp.com> References: <1487205586-6785-1-git-send-email-hemant.agrawal@nxp.com> <1488545223-25739-1-git-send-email-hemant.agrawal@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131329988410298327; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(336005)(7916002)(39850400002)(39450400003)(39380400002)(39400400002)(39410400002)(39840400002)(39860400002)(2980300002)(1110001)(1109001)(339900001)(199003)(189002)(9170700003)(50986999)(81166006)(551934003)(189998001)(5660300001)(5003940100001)(53936002)(106466001)(105606002)(2351001)(92566002)(104016004)(85426001)(6666003)(8676002)(110136004)(33646002)(6916009)(54906002)(50466002)(47776003)(50226002)(76176999)(626004)(48376002)(77096006)(8656002)(356003)(8936002)(575784001)(2906002)(2950100002)(4326008)(38730400002)(36756003)(86362001)(305945005); DIR:OUT; SFP:1101; SCL:1; SRVR:DM2PR0301MB0734; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:ovrnspm; A:1; MX:1; PTR:InfoDomainNonexistent; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11OLC010; 1:hR9La68ePgoyiwEPuZrIBWygdJ9MM91tzwZ5xhJO4vh74iUvklYQ0deo5HNriLA9dsrSiuK4iBMa3ns+Dl0BEo/aw4PB7RiZUK3ajfDSZzIQ//QBCLCB+/IjOnu5qELntL4tb09U6y/4zaL8o2rBVs/C/U+lETxSMX+WHX1Dhbkg/850xcTAstpdumVy4y0znN49YPsGkmpCac+VFzo38bf2D0XSufD8ZCfi7oKltaNtVcD6IpJV/1cvSYdbbE7/LcQQ3J3cWwe8LFTilsTznGYYYY2giX6HNS2HcwXV3fs3SsVD16+tD54Smjm1emEXGHxp0C1sqEmuGoZ6cu2DGuPz5nls2KPm12gf0lTuSdn5teTadbtajiH60XL06TT/KG/K3MeAYeMu6PX5TZHOA+yNMVOyQ0q4TzNqMypKuf9+yPqP2+cKUDehIKxh3ZIeJ6LOvr/EqFkVgM7lcRRQ4c2WmjVTxHz7Ct6kYFeA271ksIWhyzBSxh6k4ysp37dBczfs53GLr8B7/MJXmHzXkQxONUBBG3LRAwcGnOVRUQbll7mQTNzmo5JCiHmfICSKS5ywmgN1X6fOo7T1o5oEqXlAysn7NPX1h4gJxz5WzPyXuXTPHPnsK1RCZuq1TqpfbQ8uyPqlgvnOJtBMsrj8lA== MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 0085fc8b-af54-431d-4fd7-08d46204de04 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:DM2PR0301MB0734; X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0734; 3:Hr64zJrUF5EBz8yaZwzD1xGmACsek/+1CO4AIgBMEtATa3EeF19xm6MRujfUdkLI/07pWp8gzwWTIk4xb7o7TyVb8Grjj57cjdycaFMeG570pYkTeyUpwH3fPJ+SVVTTtXvDOibh8P94OfrXPjL6CHEN6U1gn4jVSktb1ePCQq4MJVeIYqtrF3YBG+fNLRifsJhQHsZ59tE/345NPFbYPWc5rRVissGyGRYdx+ei/N/qnx6q166puM4q6elzvN4ZaLCnzKg3A+f/uFwoWw5aA8a+o41u2MA1JQ/S7cBenlWLX4eAm5BOba3QGDle3TQqM0JfMWXNpGRsEUX8Y8TFlfaMW2HJwGZeChO3r9qqYFgufPLVjefxitK4dUj3LfrK; 25:jpnlR8PHrXaVFl28LwGeb6b4PYJI27AdXZxakU1U3LHyAE+FRoz93zoGW4Nl9nJU7WMXG8UZxxyHAN80qZPC+kTNL+rHmeWuha0MKPnW688rneASyTSU1efecSmGKi699KKdxhh45DDUpgHCFyetrMiG2NUE+ZrhWnx6rMJmIia+UD1mY0FF3EmDD25IIF2h1hLWmCO+OJ66qfvV8s/QeMaHim+Eizdy/wCPeETkzYlcXjEoxScA9Ggm/zHaSuLfZqbcs7DzJjpNUfji3t8M/I04+ejLhoMV1C4iKgjWMNobTFDLOYwUpNVNIQ6+VuSy9XS627Va37l0N1pv0kK1OPQO5MtWoIBWIrZesZPpADQ0fcpriJlCOWOcnlKLaoJhOJ6sDkneWmTHbHKcyuKq5CHosvkhx5vSA3emaQWpsBMJoWbV7Jyl1zR6PRZBOiry5XxSPya310D9zXO/gSgd7g== X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0734; 31:ixxuppJtcuFZ540cd1T4W1IqFsjLVaF/OvK/Xqic4eaP7/OU2Be9DiLO0OOH5FKLTkQ8DCe5DgYYEDQY/bJHIzMprfHz2Wmc5yUAKittejHuGSo+bUpoWQyPzg9NbpO4FWtKqoMEi78fdAK6DGTILCBZROMxMhvqzWC7i7VVZ0eryfMkZ+VjuZzulHqB8ygFAeUZjmd9g3zBg6ARuCy96D3Bxc57Vdmt8360tkcjQMgX+hbSO49v3Lns6x+n+LMt9ZqqvnAzs7Azj7bkqXVTH3yzg3mvnMEf2b5DVSxe9Gc= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(275809806118684); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6095060)(601004)(2401047)(13015025)(13017025)(13023025)(13024025)(13018025)(8121501046)(5005006)(3002001)(10201501046)(6055026)(6096035)(20161123563025)(20161123565025)(20161123556025)(20161123559025)(20161123561025); SRVR:DM2PR0301MB0734; BCL:0; PCL:0; RULEID:(400006); SRVR:DM2PR0301MB0734; X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0734; 4:cKqOdyhG8Koh5dwjDg2wvidodVejykjrU8cnMrLRJTbyerrJPPdQbw1vtogfC4PyCCnu24zKsmn5gOl/wkU3VzLNPlhbG++Zv1FZL+qQNUryd5+HWJYqiJieI+tiwunb9Ox1V9bJC4ViSFwIoIOPrn4/m4c9Lbn0IKwKLLG3LSFPWdRV8EcoLyopcbFKjZLzU+q4HcSIdf7AeAdq62ZyukIZjS0e4BEJEtPq/VYe+9kVJf3LoZT15QVM6KeTJBLc6+ClwP4Mk4IAeQicZfOOfV//mDYHEtLic/NnmYtCTgPGhn8/tLWfaX45B2eWlQq/xw5qh0ZqTGiHyRZg7Dk/73uBp6uxKwF5VBbm9y2Lhu00MjyCguYknOodBL6kQ+mCYKz6D3hKitGxBLxCpKW+0SvKKMkNzQXgn5m3Oozno2etNKScH0xRznaRX9oWYqPsZNDGapAu4/RYOModkFGl7B/C46b9m4CZiUNOhTYeTQZYaKW88H28ESddZSYPhBTJtwvSFRfNd+GoMwjEDCjI185qdQbBn7Gx2wvUq9XQf/vW1EUgaAAqExX05P0myl5DDrS/m/DUe5J6nTC8tt8XaQGKtka/xGx0QVfh6KgImbxItMNBWJCRu3l3+PKhNNz1s/KUuQ60EhzSI5UmpxCSLHPaPdUtRxvvIOiIBsSrIodQtBF58k64ewBoUhHiClV7zQGebBM/95J256tLtU2it4JXMUKetOx745IuFxLgTKHTjx+xQzSP6y2BqudxX5kDn/2YDy72/THiqg5BwG6K8A== X-Forefront-PRVS: 0235CBE7D0 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM2PR0301MB0734; 23:JptrhsY9nT3uppcF2wsOzfedzN7G+zwdbj37fJm?= =?us-ascii?Q?coDn0sN2bgfkG0ulQRPDSvoVpve5gcc4tAahlT4KgaEkS4KHNEyVc9u1DKdF?= =?us-ascii?Q?yyALf76fTer1K4VMGeYpKCsQ2fq56vV4Lk6CqhhAdISroL+bHB8YrvkyvHmn?= =?us-ascii?Q?T53xUpBnEecPHv6q5RFIzrPA41w7Ph+j5sWwQHWXVLO8CjpfMPf8XtYZxkoH?= =?us-ascii?Q?PHIpVLb9fmZOsVjow3MzKTFORpg655g1ExS2tzDCyXRTc3SZymOWDfNFAEOh?= =?us-ascii?Q?eKdmI+hGjfmY/9R7GRJmzakovx1xNQJEt+++e8elovO8KWGQvLKB3XWV5zNx?= =?us-ascii?Q?O0ckW/lOBOxKxcyip5395V7J5VAWbSR2NG/7gKiI1Ef9JFKDW3NJH3cLsaLb?= =?us-ascii?Q?oefbj2ujWC7xZaRfFqJK7yNpNNPO05E9FVAauSj4Dran9OwGJurdHgHP88uS?= =?us-ascii?Q?EDAcyvzbVXr+9sfO+m4eCyKNKjq1yo2R15dQCBoYAVHyc87y/9CKo0FOaMnW?= =?us-ascii?Q?R5b2oOcGsSNI4/kxNB382hOXN/SuMdSTC7gIXh2HsiZeBLu0zepmXVOxU6KS?= =?us-ascii?Q?JFCrE61oGs00QtzIPF81cq+1TAjpITHxLVcLj1wW0vRMdmEQQyKA2dNirmyf?= =?us-ascii?Q?kR4zALd/y3M2+CIuNb0oXYATyfm5xcXDuKJeSZF5iJlA0CIjktJ7G77OahQ7?= =?us-ascii?Q?g36NNmMNYUUvuxJ+YM//pB/S5tIN9WiMra1gfviO4DqiappaFNEkEcQbstE4?= =?us-ascii?Q?AR/DhPgBfNJiXLFaGV50wXo63Ht1tWKXUR9Rp2LbTx2gD9hmiKVYcsNGE77e?= =?us-ascii?Q?Td399MFGedI3FkZkm5Jec6EGPuDikc2/NR3bT/JBstr52kmNU+SIhQFYe6yT?= =?us-ascii?Q?xqe129cooGEJ0yyEgMYnlErm4fgZI4BnElcrlHzmr4Zr/Yu+H5GKA+c2PTPp?= =?us-ascii?Q?hVDbI1w0jAQKB+9agYqTKeR7+XW/DZgn1TkKKdjlqdyA03OB5Jcj65RAwEuS?= =?us-ascii?Q?WvP3+4BKffBzK3mLFjjz31C2QBnnFDk7mo9g1rZm3jQVqqh/DFRQsp5a3UPo?= =?us-ascii?Q?F35LUSTdhT1fbWn22jxPCJCK8kSF+xyLYrKKKjrOOQtvv02CRLNsqzy6ACO+?= =?us-ascii?Q?YCo0tx5OBRDWkt/maGT7B84JbI2nu4ANRwgsdq5npLFb7CCRRPvzQAPmrWPv?= =?us-ascii?Q?UacUnNa9XPaoEAOa9LEGAGFLG7Jfam2GlFjuknVm1AN+/+smixVvSVn8syPA?= =?us-ascii?Q?86qPRVbC0OZo+RLuo6mENX3Bn66c5m/h3MJgSv0o+UWV+6x2xdK7L8pJADH4?= =?us-ascii?Q?P5yoqQsLpYkjN1GmfvUYJagw=3D?= X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0734; 6:oTOYTu8Ekhqofslf3pCEHUO2VDHiLVegnUraIlaWNdjxfiqFe9DNX19sRNgGI3jopd216tFCNwxk6LDxCmP9vKE/ZtHMXnxJx+JIFqzkGldkehdrPu+YodoTbdVoYhMrsq9n+ELoZt6Uk0370MvZeoXrpTb5xzbxM7kzs/Qr6tTIJbfdeWDi4tdiq6IC63I4hrkbo8juj9JVgqC79bOH6VejQ1CiKYTAmSyOdtd/E4qS8zDxPTr9+TFSQGOeFGTboc7LxsllF4iwl0E+AcX2KO5WxdXMIzZIq4wPtJ98zhZ6GsM3cs6edPmFlO18x4BE337P4gYojaNqeOt0tCPsEPEKaBuZzec2EvzC61xSctZMtFdCS74eWcsUg1Ym4RIHfhbjJake/tencCwhvjwsGfmHwlvAMxp3vy6wEDYxjBU=; 5:n1IljJbrkagt6cPmGjZ6gN+oosb7U+YPyJskU++EirCKe0aTN0iGNECdF0iT5oZ1ZOelihyrai8zHgunoGk0Y5MhbpWUkFGbLBTOnmwb9Oso/ElOCq1oCRA8LmUOvQC3UJOjuTrXu06qEO5ZbAG1aJ6A9xOvaLYRjctZYIUiX/GsCueoXf2jKgGB2PvD14ST; 24:jAKrV4FT+oHxblch/2+sSNAsJB4vMOgWMUQKh+SZpc3/MIck3llBl4ZHQK12OUZu1xPS/3XMn97+Mpp1ckhhtYahzXz8d75qaZLW6eT+xh8= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0734; 7:6dsHGraKgfyZZR/4cpbY7MN8jW2P4SalAw80PqXBSEqXiQfwG3EOXQ19ZJTl3PyulpMQS8yfRNJi4pzM4m3PxZhXNdokQJsOzmXnzJjTuVxsTo61Dq6pJV59neYXaPyzGEvM2zYBjjav3yMoVlxY4EjmCrrXJbVC39ESeFd4leNzI34xEA5onWYhqxBd//GdzavFJYgsQK2xJkyyXja+IwImY/y9G74oFhRsbJAWB18MT1txemVJ3CiK+qJm3/1iVJqx1lxPn6NkF5gvfd8NfXle9+7PuADl7w5KAlEn+yd32o0A/DOztbp3R11HjLR6HEhbIf2f1imNMKoZgsDEww== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2017 07:14:00.8270 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB0734 Subject: [dpdk-dev] [PATCHv8 17/46] bus/fslmc: dpio portal driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Mar 2017 07:14:04 -0000 The portal driver is bound to DPIO objects discovered on the fsl-mc bus and provides services that: - allow other drivers, such as the Ethernet driver, to enqueue and dequeue frames for their respective objects A system will typically allocate 1 DPIO object per CPU to allow queuing operations to happen simultaneously across all CPUs. Signed-off-by: Hemant Agrawal --- drivers/bus/Makefile | 2 + drivers/bus/fslmc/Makefile | 1 + drivers/bus/fslmc/fslmc_vfio.c | 17 +- drivers/bus/fslmc/fslmc_vfio.h | 5 + drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 364 ++++++++++++++++++++++++++++ drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 60 +++++ drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 68 ++++++ drivers/bus/fslmc/rte_bus_fslmc_version.map | 2 + 8 files changed, 518 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_dpio.c create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_dpio.h create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 60e9764..8f7864b 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -31,6 +31,8 @@ include $(RTE_SDK)/mk/rte.vars.mk +CONFIG_RTE_LIBRTE_FSLMC_BUS = $(CONFIG_RTE_LIBRTE_DPAA2_PMD) + DIRS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc include $(RTE_SDK)/mk/rte.subdir.mk diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile index 90edaad..10740b5 100644 --- a/drivers/bus/fslmc/Makefile +++ b/drivers/bus/fslmc/Makefile @@ -68,6 +68,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += \ mc/dpio.c \ mc/mc_sys.c +SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpio.c SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc_vfio.c SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc_bus.c diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c index 0d4c0a2..2d7bcd9 100644 --- a/drivers/bus/fslmc/fslmc_vfio.c +++ b/drivers/bus/fslmc/fslmc_vfio.c @@ -61,6 +61,9 @@ #include "rte_fslmc.h" #include "fslmc_vfio.h" +#include "portal/dpaa2_hw_pvt.h" +#include "portal/dpaa2_hw_dpio.h" + #define VFIO_MAX_CONTAINERS 1 #define FSLMC_VFIO_LOG(level, fmt, args...) \ @@ -261,12 +264,13 @@ int fslmc_vfio_process_group(void) struct fslmc_vfio_device *vdev; struct vfio_device_info device_info = { .argsz = sizeof(device_info) }; char *temp_obj, *object_type, *mcp_obj, *dev_name; - int32_t object_id, i, dev_fd; + int32_t object_id, i, dev_fd, ret; DIR *d; struct dirent *dir; char path[PATH_MAX]; int64_t v_addr; int ndev_count; + int dpio_count = 0; struct fslmc_vfio_group *group = &vfio_groups[0]; static int process_once; @@ -409,9 +413,20 @@ int fslmc_vfio_process_group(void) fslmc_bus_add_device(dev); } + if (!strcmp(object_type, "dpio")) { + ret = dpaa2_create_dpio_device(vdev, + &device_info, + object_id); + if (!ret) + dpio_count++; + } } closedir(d); + ret = dpaa2_affine_qbman_swp(); + if (ret) + FSLMC_VFIO_LOG(DEBUG, "Error in affining qbman swp %d", ret); + return 0; FAILURE: diff --git a/drivers/bus/fslmc/fslmc_vfio.h b/drivers/bus/fslmc/fslmc_vfio.h index 5e58211..39994dd 100644 --- a/drivers/bus/fslmc/fslmc_vfio.h +++ b/drivers/bus/fslmc/fslmc_vfio.h @@ -71,4 +71,9 @@ int vfio_dmamap_mem_region( int fslmc_vfio_setup_group(void); int fslmc_vfio_process_group(void); +/* create dpio device */ +int dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev, + struct vfio_device_info *obj_info, + int object_id); + #endif /* _FSLMC_VFIO_H_ */ diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c new file mode 100644 index 0000000..dd6de4c --- /dev/null +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -0,0 +1,364 @@ +/*- + * BSD LICENSE + * + * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (c) 2016 NXP. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Freescale Semiconductor, Inc nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "dpaa2_hw_pvt.h" +#include "dpaa2_hw_dpio.h" + +#define NUM_HOST_CPUS RTE_MAX_LCORE + +struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE]; +RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); + +TAILQ_HEAD(dpio_device_list, dpaa2_dpio_dev); +static struct dpio_device_list *dpio_dev_list; /*!< DPIO device list */ +static uint32_t io_space_count; + +/*Stashing Macros default for LS208x*/ +static int dpaa2_core_cluster_base = 0x04; +static int dpaa2_cluster_sz = 2; + +/* For LS208X platform There are four clusters with following mapping: + * Cluster 1 (ID = x04) : CPU0, CPU1; + * Cluster 2 (ID = x05) : CPU2, CPU3; + * Cluster 3 (ID = x06) : CPU4, CPU5; + * Cluster 4 (ID = x07) : CPU6, CPU7; + */ +/* For LS108X platform There are two clusters with following mapping: + * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3; + * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7; + */ + +/* Set the STASH Destination depending on Current CPU ID. + * e.g. Valid values of SDEST are 4,5,6,7. Where, + * CPU 0-1 will have SDEST 4 + * CPU 2-3 will have SDEST 5.....and so on. + */ +static int +dpaa2_core_cluster_sdest(int cpu_id) +{ + int x = cpu_id / dpaa2_cluster_sz; + + if (x > 3) + x = 3; + + return dpaa2_core_cluster_base + x; +} + +static int +configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) +{ + struct qbman_swp_desc p_des; + struct dpio_attr attr; + + dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io)); + if (!dpio_dev->dpio) { + PMD_INIT_LOG(ERR, "Memory allocation failure\n"); + return -1; + } + + PMD_DRV_LOG(DEBUG, "\t Allocated DPIO Portal[%p]", dpio_dev->dpio); + dpio_dev->dpio->regs = dpio_dev->mc_portal; + if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id, + &dpio_dev->token)) { + PMD_INIT_LOG(ERR, "Failed to allocate IO space\n"); + free(dpio_dev->dpio); + return -1; + } + + if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) { + PMD_INIT_LOG(ERR, "Failed to reset dpio\n"); + dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + free(dpio_dev->dpio); + return -1; + } + + if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) { + PMD_INIT_LOG(ERR, "Failed to Enable dpio\n"); + dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + free(dpio_dev->dpio); + return -1; + } + + if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW, + dpio_dev->token, &attr)) { + PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n"); + dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + free(dpio_dev->dpio); + return -1; + } + + PMD_INIT_LOG(DEBUG, "Qbman Portal ID %d", attr.qbman_portal_id); + PMD_INIT_LOG(DEBUG, "Portal CE adr 0x%lX", attr.qbman_portal_ce_offset); + PMD_INIT_LOG(DEBUG, "Portal CI adr 0x%lX", attr.qbman_portal_ci_offset); + + /* Configure & setup SW portal */ + p_des.block = NULL; + p_des.idx = attr.qbman_portal_id; + p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr); + p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr); + p_des.irq = -1; + p_des.qman_version = attr.qbman_version; + + dpio_dev->sw_portal = qbman_swp_init(&p_des); + if (dpio_dev->sw_portal == NULL) { + PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n"); + dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + free(dpio_dev->dpio); + return -1; + } + + PMD_INIT_LOG(DEBUG, "QBMan SW Portal 0x%p\n", dpio_dev->sw_portal); + + return 0; +} + +static int +dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev) +{ + int sdest; + int cpu_id, ret; + + /* Set the Stashing Destination */ + cpu_id = rte_lcore_id(); + if (cpu_id < 0) { + cpu_id = rte_get_master_lcore(); + if (cpu_id < 0) { + RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n"); + return -1; + } + } + /* Set the STASH Destination depending on Current CPU ID. + * Valid values of SDEST are 4,5,6,7. Where, + * CPU 0-1 will have SDEST 4 + * CPU 2-3 will have SDEST 5.....and so on. + */ + + sdest = dpaa2_core_cluster_sdest(cpu_id); + PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d", + dpio_dev->index, cpu_id, sdest); + + ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW, + dpio_dev->token, sdest); + if (ret) { + PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret); + return -1; + } + + return 0; +} + +static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) +{ + struct dpaa2_dpio_dev *dpio_dev = NULL; + int ret; + + /* Get DPIO dev handle from list using index */ + TAILQ_FOREACH(dpio_dev, dpio_dev_list, next) { + if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count)) + break; + } + if (!dpio_dev) + return NULL; + + PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu", + dpio_dev, dpio_dev->index, syscall(SYS_gettid)); + + ret = dpaa2_configure_stashing(dpio_dev); + if (ret) + PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed"); + + return dpio_dev; +} + +int +dpaa2_affine_qbman_swp(void) +{ + unsigned int lcore_id = rte_lcore_id(); + uint64_t tid = syscall(SYS_gettid); + + if (lcore_id == LCORE_ID_ANY) + lcore_id = rte_get_master_lcore(); + /* if the core id is not supported */ + else if (lcore_id >= RTE_MAX_LCORE) + return -1; + + if (dpaa2_io_portal[lcore_id].dpio_dev) { + PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared" + " between thread %lu and current %lu", + dpaa2_io_portal[lcore_id].dpio_dev, + dpaa2_io_portal[lcore_id].dpio_dev->index, + dpaa2_io_portal[lcore_id].net_tid, + tid); + RTE_PER_LCORE(_dpaa2_io).dpio_dev + = dpaa2_io_portal[lcore_id].dpio_dev; + rte_atomic16_inc(&dpaa2_io_portal + [lcore_id].dpio_dev->ref_count); + dpaa2_io_portal[lcore_id].net_tid = tid; + + PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu", + dpaa2_io_portal[lcore_id].dpio_dev, + dpaa2_io_portal[lcore_id].dpio_dev->index, + tid); + return 0; + } + + /* Populate the dpaa2_io_portal structure */ + dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(); + + if (dpaa2_io_portal[lcore_id].dpio_dev) { + RTE_PER_LCORE(_dpaa2_io).dpio_dev + = dpaa2_io_portal[lcore_id].dpio_dev; + dpaa2_io_portal[lcore_id].net_tid = tid; + + return 0; + } else { + return -1; + } +} + +int +dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev, + struct vfio_device_info *obj_info, + int object_id) +{ + struct dpaa2_dpio_dev *dpio_dev; + struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)}; + + if (obj_info->num_regions < NUM_DPIO_REGIONS) { + PMD_INIT_LOG(ERR, "ERROR, Not sufficient number " + "of DPIO regions.\n"); + return -1; + } + + if (!dpio_dev_list) { + dpio_dev_list = malloc(sizeof(struct dpio_device_list)); + if (!dpio_dev_list) { + PMD_INIT_LOG(ERR, "Memory alloc failed in DPIO list\n"); + return -1; + } + + /* Initialize the DPIO List */ + TAILQ_INIT(dpio_dev_list); + } + + dpio_dev = malloc(sizeof(struct dpaa2_dpio_dev)); + if (!dpio_dev) { + PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n"); + return -1; + } + + PMD_DRV_LOG(INFO, "\t Aloocated DPIO [%p]", dpio_dev); + dpio_dev->dpio = NULL; + dpio_dev->hw_id = object_id; + dpio_dev->vfio_fd = vdev->fd; + rte_atomic16_init(&dpio_dev->ref_count); + /* Using single portal for all devices */ + dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX]; + + reg_info.index = 0; + if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + PMD_INIT_LOG(ERR, "vfio: error getting region info\n"); + return -1; + } + + PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset); + PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size); + dpio_dev->ce_size = reg_info.size; + dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size, + PROT_WRITE | PROT_READ, MAP_SHARED, + dpio_dev->vfio_fd, reg_info.offset); + + /* Create Mapping for QBMan Cache Enabled area. This is a fix for + * SMMU fault for DQRR statshing transaction. + */ + if (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr, + reg_info.offset, reg_info.size)) { + PMD_INIT_LOG(ERR, "DMAMAP for Portal CE area failed.\n"); + return -1; + } + + reg_info.index = 1; + if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + PMD_INIT_LOG(ERR, "vfio: error getting region info\n"); + return -1; + } + + PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset); + PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size); + dpio_dev->ci_size = reg_info.size; + dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size, + PROT_WRITE | PROT_READ, MAP_SHARED, + dpio_dev->vfio_fd, reg_info.offset); + + if (configure_dpio_qbman_swp(dpio_dev)) { + PMD_INIT_LOG(ERR, + "Fail to configure the dpio qbman portal for %d\n", + dpio_dev->hw_id); + return -1; + } + + io_space_count++; + dpio_dev->index = io_space_count; + TAILQ_INSERT_HEAD(dpio_dev_list, dpio_dev, next); + + return 0; +} diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h new file mode 100644 index 0000000..682f3fa --- /dev/null +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h @@ -0,0 +1,60 @@ +/*- + * BSD LICENSE + * + * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (c) 2016 NXP. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Freescale Semiconductor, Inc nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DPAA2_HW_DPIO_H_ +#define _DPAA2_HW_DPIO_H_ + +#include +#include + +struct dpaa2_io_portal_t { + struct dpaa2_dpio_dev *dpio_dev; + struct dpaa2_dpio_dev *sec_dpio_dev; + uint64_t net_tid; + uint64_t sec_tid; +}; + +/*! Global per thread DPIO portal */ +RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); + +#define DPAA2_PER_LCORE_DPIO RTE_PER_LCORE(_dpaa2_io).dpio_dev +#define DPAA2_PER_LCORE_PORTAL DPAA2_PER_LCORE_DPIO->sw_portal + +#define DPAA2_PER_LCORE_SEC_DPIO RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev +#define DPAA2_PER_LCORE_SEC_PORTAL DPAA2_PER_LCORE_SEC_DPIO->sw_portal + +/* Affine a DPIO portal to current processing thread */ +int dpaa2_affine_qbman_swp(void); + + +#endif /* _DPAA2_HW_DPIO_H_ */ diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h new file mode 100644 index 0000000..6b44314 --- /dev/null +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -0,0 +1,68 @@ +/*- + * BSD LICENSE + * + * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (c) 2016 NXP. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Freescale Semiconductor, Inc nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DPAA2_HW_PVT_H_ +#define _DPAA2_HW_PVT_H_ + +#include +#include + + +#define MC_PORTAL_INDEX 0 +#define NUM_DPIO_REGIONS 2 + +struct dpaa2_dpio_dev { + TAILQ_ENTRY(dpaa2_dpio_dev) next; + /**< Pointer to Next device instance */ + uint16_t index; /**< Index of a instance in the list */ + rte_atomic16_t ref_count; + /**< How many thread contexts are sharing this.*/ + struct fsl_mc_io *dpio; /** handle to DPIO portal object */ + uint16_t token; + struct qbman_swp *sw_portal; /** SW portal object */ + const struct qbman_result *dqrr[4]; + /**< DQRR Entry for this SW portal */ + void *mc_portal; /**< MC Portal for configuring this device */ + uintptr_t qbman_portal_ce_paddr; + /**< Physical address of Cache Enabled Area */ + uintptr_t ce_size; /**< Size of the CE region */ + uintptr_t qbman_portal_ci_paddr; + /**< Physical address of Cache Inhibit Area */ + uintptr_t ci_size; /**< Size of the CI region */ + int32_t vfio_fd; /**< File descriptor received via VFIO */ + int32_t hw_id; /**< An unique ID of this DPIO device instance */ +}; + +/*! Global MCP list */ +extern void *(*rte_mcp_ptr_list); +#endif diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map index 463c658..2110b71 100644 --- a/drivers/bus/fslmc/rte_bus_fslmc_version.map +++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map @@ -1,6 +1,7 @@ DPDK_17.05 { global: + dpaa2_affine_qbman_swp; dpbp_disable; dpbp_enable; dpbp_get_attributes; @@ -14,6 +15,7 @@ DPDK_17.05 { dpio_reset; dpio_set_stashing_destination; mc_send_command; + per_lcore__dpaa2_io; qbman_check_command_complete; qbman_eq_desc_clear; qbman_eq_desc_set_no_orp; -- 1.9.1