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Sat, 25 Mar 2017 06:27:05 +0000 From: Shijith Thotton To: Ferruh Yigit Cc: dev@dpdk.org, Jerin Jacob , Derek Chickles , Venkat Koppula , Srisivasubramanian S , Mallesham Jatharakonda Date: Sat, 25 Mar 2017 11:54:16 +0530 Message-Id: <1490423097-6797-6-git-send-email-shijith.thotton@caviumnetworks.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1490423097-6797-1-git-send-email-shijith.thotton@caviumnetworks.com> References: <1488454371-3342-1-git-send-email-shijith.thotton@caviumnetworks.com> <1490423097-6797-1-git-send-email-shijith.thotton@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [14.140.2.178] X-ClientProxiedBy: BM1PR01CA0117.INDPRD01.PROD.OUTLOOK.COM (10.174.208.33) To CY1PR07MB2280.namprd07.prod.outlook.com (10.164.112.158) X-MS-Office365-Filtering-Correlation-Id: 4e7a77ee-3863-47cd-7a27-08d47347f668 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001);SRVR:CY1PR07MB2280; X-Microsoft-Exchange-Diagnostics: 1; CY1PR07MB2280; 3:qZav2yag9SrHxR4+pxj2iMUVcsNjs8TJ2tHm05mZVSkogt3qwQzmwYvC1KhjUSG5/xlNt4bDZGWurFVtKL6MIwZwsdMBhf/Bmm4sUYUXgxO2Au98EFu9d7Y0XoGI6CNyo30aztV9CzBaVC/mR4enve0xFFQThpUtUXSHckwlxYXzvHZNrV1VqmoUyHYReKPFIo3aqGZEf7lyHpihYMCfi2MGfravdD7A2Ajh9qdy67WDAq9QKhZiZlEaoi6Jo4BmAgfoCeIoq0AYaMRlOm5dfg==; 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CY1PR07MB2280; 6:rA/B5tMKUU+1uJOAiJ21pyI9gvNUlxkYQI2W59kWdR2qLSP2GVvd3MVKwfKKguy7Y4lMLrm7/T6+4kVTz7uO1XuYCgHNLARtOCLwo/hpjKOfEoM9ILX0UMWUOt5/4JtDkn9KNCoh47FX6RJiPKqjlsCn0r3J/0oTnT5LMbxj2LrM9Ws8DiQjtkDTAv9zg3tzsQiCVWkvUfLKy8F3AbN+I1pKA+zdorMAg08rDW0cQeAeU49G3pL9pipNOYCsovZMN4HGW0kYzpcdznctUVN3rnaCK3rPp80jfcXq1s9wbn6eIEGJk1Oy9lv4gLjP8uaB+aiGycUub/vnsf2IEYZ6uWAwxFS6Ezv3H7z+xkaev8vuliszmTlDwL9b+aK5lutRPQkjKYKeygwntyhwytSsOA==; 5:6WIeuhW6UBM7aUVJb8Bk35RyoG0KyeH1/Pf3AuCxu+LkQQM25H7dwKBdnExD+QQC/yKxzjpURgdLUsBJa5LRZc/0nQSmB3QEEmIokZ73NJ1EOWJbbK2RNePBEMYropHzDOJVB134A+xEXkgtCSltBg==; 24:JnXEvsJ5p/nSH/Du+ATdtareiTk/D1LtI78iEabQXa90KeJyWf+/+ajOXFixUzqtNRuPlie6lYs5mvl4Rmpeh1jqBBTOl2lgV5vBWTEMNp0= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; CY1PR07MB2280; 7:MY4y66BftPBi+i09RNxPt8Zt1YxxBSIGGw/QKRRRc6UFmjTLHj6T6ziIWLVD+Pt4MsjBZ2Ptq4+bNlFUVpbqlSIiZmnAyzMoPhCRHOIHaYZIjhgDdcntJwM7De5PD9bIaFH/pK4n2mgmty6ium1Gh8+oEUtVNTR2Gy0VnoLyNcp9kdhfIFlzA8lSS31UCkWAoym141vl+wvN4xCPAZu8rjSl2xshIW8ouoLtsZ8SkMtBO/FkpVBnyHeLMLFPq2rLr6GQtZ0CTskRbGqoZSGcpKB+kM1zWwp4xvdRwZGDywl5cPfCkZzoKLqa8vRR6UTkXB2Z+6FnRwjcsiKtZKlWxg== X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Mar 2017 06:27:05.3485 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR07MB2280 Subject: [dpdk-dev] [PATCH v3 05/46] net/liquidio/base: macros to read and write register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 25 Mar 2017 06:27:10 -0000 Signed-off-by: Shijith Thotton Signed-off-by: Jerin Jacob Signed-off-by: Derek Chickles Signed-off-by: Venkat Koppula Signed-off-by: Srisivasubramanian S Signed-off-by: Mallesham Jatharakonda --- drivers/net/liquidio/base/lio_hw_defs.h | 67 +++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/net/liquidio/base/lio_hw_defs.h b/drivers/net/liquidio/base/lio_hw_defs.h index db42f3e..9a7a894 100644 --- a/drivers/net/liquidio/base/lio_hw_defs.h +++ b/drivers/net/liquidio/base/lio_hw_defs.h @@ -34,6 +34,8 @@ #ifndef _LIO_HW_DEFS_H_ #define _LIO_HW_DEFS_H_ +#include + #ifndef PCI_VENDOR_ID_CAVIUM #define PCI_VENDOR_ID_CAVIUM 0x177D #endif @@ -41,4 +43,69 @@ #define LIO_CN23XX_VF_VID 0x9712 #define LIO_DEVICE_NAME_LEN 32 + +/* Routines for reading and writing CSRs */ +#ifdef RTE_LIBRTE_LIO_DEBUG_REGS +#define lio_write_csr(lio_dev, reg_off, value) \ + do { \ + typeof(lio_dev) _dev = lio_dev; \ + typeof(reg_off) _reg_off = reg_off; \ + typeof(value) _value = value; \ + PMD_REGS_LOG(_dev, \ + "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \ + (unsigned long)_reg_off, \ + (unsigned long)_value); \ + rte_write32(_value, _dev->hw_addr + _reg_off); \ + } while (0) + +#define lio_write_csr64(lio_dev, reg_off, val64) \ + do { \ + typeof(lio_dev) _dev = lio_dev; \ + typeof(reg_off) _reg_off = reg_off; \ + typeof(val64) _val64 = val64; \ + PMD_REGS_LOG( \ + _dev, \ + "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \ + (unsigned long)_reg_off, \ + (unsigned long long)_val64); \ + rte_write64(_val64, _dev->hw_addr + _reg_off); \ + } while (0) + +#define lio_read_csr(lio_dev, reg_off) \ + ({ \ + typeof(lio_dev) _dev = lio_dev; \ + typeof(reg_off) _reg_off = reg_off; \ + uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \ + PMD_REGS_LOG(_dev, \ + "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \ + (unsigned long)_reg_off, \ + (unsigned long)val); \ + val; \ + }) + +#define lio_read_csr64(lio_dev, reg_off) \ + ({ \ + typeof(lio_dev) _dev = lio_dev; \ + typeof(reg_off) _reg_off = reg_off; \ + uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \ + PMD_REGS_LOG( \ + _dev, \ + "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \ + (unsigned long)_reg_off, \ + (unsigned long long)val64); \ + val64; \ + }) +#else +#define lio_write_csr(lio_dev, reg_off, value) \ + rte_write32(value, (lio_dev)->hw_addr + (reg_off)) + +#define lio_write_csr64(lio_dev, reg_off, val64) \ + rte_write64(val64, (lio_dev)->hw_addr + (reg_off)) + +#define lio_read_csr(lio_dev, reg_off) \ + rte_read32((lio_dev)->hw_addr + (reg_off)) + +#define lio_read_csr64(lio_dev, reg_off) \ + rte_read64((lio_dev)->hw_addr + (reg_off)) +#endif #endif /* _LIO_HW_DEFS_H_ */ -- 1.8.3.1