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HE1PR05MB1914; 6:/6xueL0+ardnRbT7kREcq4mv4IDKTykYGVKxO1ORilXOAjshAYvWcZdV3/nBD9a0cs4q48H7vagwT2yiRPOJPftAK4zOx+LPuj0p1VDJb8jQjQkP9bsE3+giNso9bTh5jElgk9sXHoGRue1cTF0gIUxzZsRpeZIb9Bx/1CdbhbOACgvcPxZWz58Ww20iBjSwBIa7wLWrXCL16nndPjY5LRUdHGX46FM08lVK+zS71WI+Pkq8QTetWx+WjEa2PJZDE+G+rCxsvoRe+Gi9SlsuWE7XOjz4Jt8vvFP7eSBv5lbUmtRh9wmf5lFjHocmXGdsi/5aniffz515ztbUC3iqng==; 5:DplZmV5wfiwjM5jI57ToyRhOFGY1gBXnc3dKzt+LkDePd02uI5nGz7St6Vu3pmrVROXYoihZYQ0JiwUEAi2sEuQY1m26bqx7O8MZogFyALFDohEnP98yv2nDPP25VJtE8nymiiTot9b9Jt5nXI+R/g==; 24:dZ90Pl2EoYou81DpAfhLObKvI2TI9vajQMcQmB4my+jF08K6HnABHe5n79j5EohRPEQaMGbYViprzo38vmotsCr2vevHgUdgbK9FJhRc/C4=; 7:Spy5EoYFSxa+2vF+IQ0h+0DdH4cMLE2YeHVnnigwlGOtCaWLSMUpxNxLETJZvbyOOweYPR1BkLzdiuL8G2LBvYkox3MdkgZoYuHiHnM9Kdg77YK64Xfj8E8Ntsi7iA+YYvUXtxKUM2TBILpj7blAF9e3DSah18CbFwu4jfQfNM2Bpf/24g5WrZ1jLmCwxFDx9w25vQmliDCifivvSA6vwYgZSb4vN6aIx+u1d8wkDJY= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2017 11:21:51.1691 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a47545f-db85-4711-7d55-08d51b9a9767 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR05MB1914 Subject: [dpdk-dev] [PATCH v3] net/mlx4: fix no Rx interrupts X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Oct 2017 11:21:54 -0000 This commit addresses the issue of rx interrupts support with the new Rx datapath introduced in DPDK version 17.11. In order to generate an Rx interrupt an event queue is armed with the consumer index of the Rx completion queue. Since version 17.11 this index is handled by the PMD so it is now the responsibility of the PMD to write this value when enabling Rx interrupts. Fixes: 6681b845034c ("net/mlx4: add Rx bypassing Verbs") Signed-off-by: Moti Haimovsky --- V3: Modifications according to code review by nelio laranjeiro. * mlx4_arm_cq is now a routine returning void. * cq_db_reg is now part of mlx4_cq with pre-calculated address. * MLX4_CQ_DB_CI_MASK is used instead of 0xffffff for consistency reasons. * Re-arranged variables order in mlx4_sq data structure to avoid holes in it. V2: * Rebased on top of ff3397e9 ("net/mlx4: relax Rx queue configuration order") --- drivers/net/mlx4/mlx4_intr.c | 40 +++++++++++++++++++++++++++++++++++----- drivers/net/mlx4/mlx4_prm.h | 12 +++++++++++- drivers/net/mlx4/mlx4_rxq.c | 7 ++++++- drivers/net/mlx4/mlx4_rxtx.c | 5 +++-- 4 files changed, 55 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx4/mlx4_intr.c b/drivers/net/mlx4/mlx4_intr.c index 3806322..b17d109 100644 --- a/drivers/net/mlx4/mlx4_intr.c +++ b/drivers/net/mlx4/mlx4_intr.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include "mlx4.h" @@ -239,6 +240,35 @@ } /** + * MLX4 CQ notification . + * + * @param rxq + * Pointer to receive queue structure. + * @param solicited + * Is request solicited or not. + */ +static void +mlx4_arm_cq(struct rxq *rxq, int solicited) +{ + struct mlx4_cq *cq = &rxq->mcq; + uint64_t doorbell; + uint32_t sn = cq->arm_sn & MLX4_CQ_DB_GEQ_N_MASK; + uint32_t ci = cq->cons_index & MLX4_CQ_DB_CI_MASK; + uint32_t cmd = solicited ? MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT; + + *cq->arm_db = rte_cpu_to_be_32(sn << 28 | cmd | ci); + /* + * Make sure that the doorbell record in host memory is + * written before ringing the doorbell via PCI MMIO. + */ + rte_wmb(); + doorbell = sn << 28 | cmd | cq->cqn; + doorbell <<= 32; + doorbell |= ci; + rte_write64(rte_cpu_to_be_64(doorbell), cq->cq_db_reg); +} + +/** * Uninstall interrupt handler. * * @param priv @@ -333,6 +363,7 @@ WARN("unable to disable interrupt on rx queue %d", idx); } else { + rxq->mcq.arm_sn++; ibv_ack_cq_events(rxq->cq, 1); } return -ret; @@ -353,15 +384,14 @@ mlx4_rx_intr_enable(struct rte_eth_dev *dev, uint16_t idx) { struct rxq *rxq = dev->data->rx_queues[idx]; - int ret; + int ret = 0; - if (!rxq || !rxq->channel) + if (!rxq || !rxq->channel) { ret = EINVAL; - else - ret = ibv_req_notify_cq(rxq->cq, 0); - if (ret) { rte_errno = ret; WARN("unable to arm interrupt on rx queue %d", idx); + } else { + mlx4_arm_cq(rxq, 0); } return -ret; } diff --git a/drivers/net/mlx4/mlx4_prm.h b/drivers/net/mlx4/mlx4_prm.h index 3a77502..d8c822e 100644 --- a/drivers/net/mlx4/mlx4_prm.h +++ b/drivers/net/mlx4/mlx4_prm.h @@ -78,6 +78,11 @@ enum { MLX4_CQE_L2_TUNNEL_IPOK = (int)(1u << 31), }; +/* Completion queue events, numbers and masks. */ +#define MLX4_CQ_DB_GEQ_N_MASK 0x3 +#define MLX4_CQ_DB_CI_MASK 0xffffff +#define MLX4_CQ_DOORBELL 0x20 + /* Send queue information. */ struct mlx4_sq { uint8_t *buf; /**< SQ buffer. */ @@ -95,11 +100,16 @@ struct mlx4_sq { /* Completion queue information. */ struct mlx4_cq { + void *cq_uar; /**< CQ user access region. */ + void *cq_db_reg; /**< CQ doorbell register. */ + uint32_t *set_ci_db; /**< Pointer to the completion queue doorbell. */ + uint32_t *arm_db; /**< Pointer to doorbell for arming Rx events. */ uint8_t *buf; /**< Pointer to the completion queue buffer. */ uint32_t cqe_cnt; /**< Number of entries in the queue. */ uint32_t cqe_64:1; /**< CQ entry size is 64 bytes. */ uint32_t cons_index; /**< Last queue entry that was handled. */ - uint32_t *set_ci_db; /**< Pointer to the completion queue doorbell. */ + uint32_t cqn; /**< CQ number. */ + int arm_sn; /**< Rx event counter. */ }; /** diff --git a/drivers/net/mlx4/mlx4_rxq.c b/drivers/net/mlx4/mlx4_rxq.c index ad55934..7fe21b6 100644 --- a/drivers/net/mlx4/mlx4_rxq.c +++ b/drivers/net/mlx4/mlx4_rxq.c @@ -510,7 +510,7 @@ void mlx4_rss_detach(struct mlx4_rss *rss) struct rte_mbuf *(*elts)[elts_n] = rxq->elts; struct mlx4dv_obj mlxdv; struct mlx4dv_rwq dv_rwq; - struct mlx4dv_cq dv_cq; + struct mlx4dv_cq dv_cq = { .comp_mask = MLX4DV_CQ_MASK_UAR, }; const char *msg; struct ibv_cq *cq = NULL; struct ibv_wq *wq = NULL; @@ -604,6 +604,11 @@ void mlx4_rss_detach(struct mlx4_rss *rss) rxq->mcq.cqe_cnt = dv_cq.cqe_cnt; rxq->mcq.set_ci_db = dv_cq.set_ci_db; rxq->mcq.cqe_64 = (dv_cq.cqe_size & 64) ? 1 : 0; + rxq->mcq.arm_db = dv_cq.arm_db; + rxq->mcq.arm_sn = dv_cq.arm_sn; + rxq->mcq.cqn = dv_cq.cqn; + rxq->mcq.cq_uar = dv_cq.cq_uar; + rxq->mcq.cq_db_reg = (uint8_t *)dv_cq.cq_uar + MLX4_CQ_DOORBELL; /* Update doorbell counter. */ rxq->rq_ci = elts_n / sges_n; rte_wmb(); diff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c index 36173ad..67dc712 100644 --- a/drivers/net/mlx4/mlx4_rxtx.c +++ b/drivers/net/mlx4/mlx4_rxtx.c @@ -200,7 +200,7 @@ struct pv { * the ring consumer. */ cq->cons_index = cons_index; - *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & 0xffffff); + *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK); rte_wmb(); sq->tail = sq->tail + nr_txbbs; /* Update the list of packets posted for transmission. */ @@ -829,7 +829,8 @@ struct pv { rxq->rq_ci = rq_ci >> sges_n; rte_wmb(); *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci); - *rxq->mcq.set_ci_db = rte_cpu_to_be_32(rxq->mcq.cons_index & 0xffffff); + *rxq->mcq.set_ci_db = + rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK); /* Increment packets counter. */ rxq->stats.ipackets += i; return i; -- 1.8.3.1