From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR02-HE1-obe.outbound.protection.outlook.com (mail-eopbgr10089.outbound.protection.outlook.com [40.107.1.89]) by dpdk.org (Postfix) with ESMTP id BB6F81B319 for ; Mon, 30 Oct 2017 11:08:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=HKjZdIi4yv7Db/3vALAoq7Wm4sa2wS8cSMoB1R76jME=; b=j4uOKWBYZFRwrOhVdSrVllgY6Ynoy9lfE4bREFwhNZXnEz0pHTQKaYJ8CSoHnjpLIEiHHvf1+6oeps1dOOhMthPSXlpcAIsAgfG2bQzVUv8CeBieMe1zfq4uQTYqmvxFyLO5P1I/CjS8+LUlwu8VNB53yyQziQydTuVc/EflRvk= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=matan@mellanox.com; Received: from mellanox.com (37.142.13.130) by VI1PR0502MB3662.eurprd05.prod.outlook.com (2603:10a6:803:f::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.178.6; Mon, 30 Oct 2017 10:07:59 +0000 From: Matan Azrad To: Adrien Mazarguil Cc: dev@dpdk.org, Ophir Munk Date: Mon, 30 Oct 2017 10:07:25 +0000 Message-Id: <1509358049-18854-4-git-send-email-matan@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1509358049-18854-1-git-send-email-matan@mellanox.com> References: <1508768520-4810-1-git-send-email-ophirmu@mellanox.com> <1509358049-18854-1-git-send-email-matan@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [37.142.13.130] X-ClientProxiedBy: VI1PR08CA0217.eurprd08.prod.outlook.com (2603:10a6:802:15::26) To VI1PR0502MB3662.eurprd05.prod.outlook.com (2603:10a6:803:f::17) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 08233b80-16ea-4105-2cac-08d51f7e1a05 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(48565401081)(4534020)(4602075)(2017052603199); SRVR:VI1PR0502MB3662; X-Microsoft-Exchange-Diagnostics: 1; VI1PR0502MB3662; 3:N1RHUkqPheB4ojgxlykAgDqb2WO1q+OtxDIU7+ouIUfYxjE4Zw08ihbpVp4UpLodCnZwWSthnnP4gHRj4v57pPFMTeaTo1XHt/gxWpBWWPiNtRfm0YdUjI5PsCzD8dlUiPWPppEIdW6hpYA3Sz6q55Rdp8GWhdXTRTQiuGZdXNPYZBBcVDGwaVaEcX+cpQIQtoT3A2LAvhedrggOo1UPx5L08hgGcN11bzkZR+BvTamFznHIQTbGqzE0iUuGnXMX; 25:EUP0xQQPggJUZmUZLwRkiUp45aZGyZnGl76Mi21tfI2imzbrG2Q7nomBaqKCGXgS+XXDx9CTmS8hO5173cL/SSSO4n12o0uSbbiYWLHnZlhYwoJWtS0FWaqlKcqI77zLzdXNDxybIs7bn6d97vBnHtLLehfSvyzBfAH3DourAaT8Kq4QDXu4C4ysSMM16l+v2peE9f/gV21X1f0l4ny6IpCNWIM/XQDpqzC1kdulaPOgSYKbMtNtaoppOYdt1k91jX7Fieu4skNyYoaNNmoWyrg92Fm4lpY7q7pFk1KRqJ51iKvcT1GYuGdsS8sFS00+CExXFkx4K89A7Jxf3a9c1Q==; 31:+NmH2tcD6QHSuKIRVVzLP8f//busM2ok66g9b3lqtIOp/G6h2nkyXtXgmMR4qWEoKQtPjsiBRPKlVHSDalEgdluo6XTWGDcsL1g4Bnyg+JolXqmwn1IlepE/SBjjZCwMPIjrmSzQTEW1y+72Jxozavb/abSSsfspvzE6OuRdGTZ/rf+05uYjnPFicKdDwnXBbP6QH79uSm3tR9V4Ab0KmOerF2fCoFAkqyaqOPVLUIQ= X-MS-TrafficTypeDiagnostic: VI1PR0502MB3662: X-LD-Processed: a652971c-7d2e-4d9b-a6a4-d149256f461b,ExtAddr X-Microsoft-Exchange-Diagnostics: 1; VI1PR0502MB3662; 20:dwFBXyJgmXC9Hrz/JwfI3FI0HRiqPjrE9kEyZxS2IyTcGC0xCXw1uOkQmiH1CSwZQ7P+c6xug8vnVDlWNNDbCm/jfMukD3u+yRzVgqOnl5weVB/uTKxmqpOu2bWchawB8/Dx8KOGGhF4akLH2jMyRszXqPC2kV/sVXkc5a48zDkAHsiKmZ5PMDtRS4N4T6obi4HuuXeHQ25Xpgc92wHy7zNRCqNIkGJQ6mxok2w9oXby5zti6LDNIoI/Wsx0dq1NixZrNio30Snrx+ZmdsWK/uYne9SX3wb/NdEb4HgyH1YjgnTsTYNWm5dGkE/QbKvc7vfhxn6frk207WUlzGG7ZNm1QWQ5T+RkOtSkSE1QG3dqO5RKG2hYm84gvqVz+m1jMn0jgUOlVJcr+jfwdTI5JptLpu1Zey1O+KYWYT85TYDiKYSxIfybVZdU5kDvxsOXr8HOGVbvIkritul51A6TMK5nNxBkuSiqTmD5cESgnoMmgAssfiBg04R8eQ68bmu8; 4:jB3hiBhaNsRf+lbuZum7OZlU0vgLocuelEbbRzjoZB9K1SjSBDXlXBT2sxzzGMWL5CVpj94XZoNZ7FJYECs0nFClcGInGrbE92NMPjqjbXXNKJUIpc+a51bMvF0y3bPrZKAg+FKYiXhLcXLtdQOrMgXY2PeqBtaTGH7U2kQJ2XAnMstWepWNSsmsSNGU/0wyHiOevjam0q51OJh5HkjIl+8KMpyxiiWeH5/ZjsX4IvngI/rDmCUpoT7kJN3ovtG0Y4bVQVqcaIFAmHxPWse7qaMqwx/xKjqkgAsiRDbEEoiz4zzI5uA+kEx0zSE+bVXH X-Exchange-Antispam-Report-Test: UriScan:(60795455431006); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(8121501046)(5005006)(3002001)(93006095)(93001095)(3231020)(10201501046)(100000703101)(100105400095)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123558100)(20161123555025)(20161123562025)(20161123560025)(20161123564025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:VI1PR0502MB3662; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:VI1PR0502MB3662; X-Forefront-PRVS: 0476D4AB88 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(376002)(346002)(199003)(189002)(16526018)(97736004)(66066001)(47776003)(21086003)(5660300001)(4326008)(50226002)(316002)(53936002)(55016002)(4720700003)(6666003)(16586007)(6916009)(48376002)(36756003)(50466002)(2906002)(7736002)(305945005)(2950100002)(106356001)(101416001)(6116002)(3846002)(69596002)(68736007)(33026002)(81156014)(81166006)(8676002)(105586002)(189998001)(33646002)(107886003)(478600001)(8936002)(5003940100001)(25786009)(86362001)(76176999)(50986999); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0502MB3662; H:mellanox.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; Received-SPF: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; VI1PR0502MB3662; 23:Zs7z3skThq3Smjo65SevmrVVbe97QhOrVEH1Uc5?= =?us-ascii?Q?MX9N7gX22X/+kuuzcXgyCWb7Zc52eh2Teenanprc3t8ooplk3qmsk65LQ+SD?= =?us-ascii?Q?TaAl//LkHUKkweqJyjxfymUgqMBsWoHVppXHySyygNojGrsQZY9OrviXK8CJ?= =?us-ascii?Q?X269z+t41dfSaVDdmCRPxzXWn0XmtcSH+8kHrL3uyajG5QAG+Dv+zlnYNWEy?= =?us-ascii?Q?/XfMOg9m7PQMx0Aa2UwdAxWUtNtV52I1MF3Zsve1+UK6NH7KvSxhV4gOsJm6?= =?us-ascii?Q?khX3y54fZl1vCSI7dSOgkW2Z3hdTXcpoDX6RtOb01akD1LLlGblnyB7NnyoB?= =?us-ascii?Q?YbJV7My4L9WDnedUiHLxAcvgO7dOL8u0zM2n2TLWhXmDacItm9NV0Ld324Y5?= =?us-ascii?Q?r0AexrQnS48g4ZgJEydARa8Sr7+YEPzzFlQJVuyTAVwIgAZSMdu2Lj7pKOB5?= =?us-ascii?Q?xNFQ68nJ82g+zehkmf9d+9+aaGQwKisHZJyqe8MS7ZMBikYoOQIL3XqXW7tX?= =?us-ascii?Q?CxyeRojy1usq2vkMiFZ3kHddqeHEDBpxbBmQWicJCJ5wPZoGlkbVmzs/nU1O?= =?us-ascii?Q?nUkOfJPVfMmJR0Xr0bYTSeuhKyEMSB+ShqWcHYkpWtpawkiHKC7UFVB/ixrS?= =?us-ascii?Q?n8iF7LfMIVxNLAKf/qU0cZoal5nTsbSrxRFylvm12PnRK6nRjlDb4v89q1fO?= =?us-ascii?Q?eMDbJEdurvsd+d3YKZmX5S5gb25cyYJ/dD+QMYsi/BNhFrR9fBuSsfg248JM?= =?us-ascii?Q?W0xLgc7tdzUGvaExIoG3dB5JDVBXLHo3hNSo9Fzszcvz29Q5BpqGm/r/a5oP?= =?us-ascii?Q?OMiJm7YqeGwpSrvM9j3QXbchlvoQOagSg7fjhHAgFDcTKK9Fq/AWXY/3YvG5?= =?us-ascii?Q?12I9M2jAEbkZX8WiX9F6xExyZlOB+O8Es9z1169o1ZwLhtwlleYAVKSQw1hJ?= =?us-ascii?Q?kg14U3wOmbU/ERt41xAKSehvK7/dRiVjblLlGVmSr1nTZzjnl7MmOxAZANrw?= =?us-ascii?Q?8/o6HodcbIFCrGUieGUkgkGBuJ6sOWzBdpx6GgLZJqMTGVsIqb6wpMeqJWjK?= =?us-ascii?Q?xNrz6Pi3H8rWjHgv9n+ps6NtCQFxZZuxkgIQSbt5uwoeXUcLwd3CiJSGcZn1?= =?us-ascii?Q?hzQQHge+VEiRpf2GmEh2+5xS9PVR4rA4znrDxIVbLDojb+dVyL6r2Ag=3D?= =?us-ascii?Q?=3D?= X-Microsoft-Exchange-Diagnostics: 1; VI1PR0502MB3662; 6:eROG+1NbdxpSWxiiwty0uHwCRZEhoOaTupLf04XQNTpZgv8aBP3H+lFCvZYTflkNoBPETg4N7EQaNel7B9dvQKUM3a3L3G080UrEGqFselByWV7sasJdWSvnfdFXaEhVfgvaboqSwgFvc/Jg5xL9LljOwkRRRKU4U4iIejD778I1MzOsBiwYjihO5p6q5K4ftfr83G1+u3Cy31Png95SPBFgdua3cA0jO32NeLzbSsPgFy7srtz9vRT23gxZSWWcHlne7Z+DYqY6+TO0+pKCyXlpbkLP+/14W/irfgiYvjSrPSwGDgZoy2EbW53xbThGoFtTL1n5d/jNIhRo4Der1oTHqRVOn0YrHSwzuw92p+k=; 5:/fRT9zt9BIYrZ4pYGGMhyeWB+jds3ebIGHcxp1zqge7GPErKS+LbShkivrN6TjfD4efxTgv3M2PbvUtd1AC1tp7q3/hoQiVLJNMlE9IThIdLM47645s8moWpm9MBw2PqTAz3tkyx6VXsFQ7YeAwtW2NLyfHgyibmNyOtTYSwqKI=; 24:QaSeWtFxpQR9F7otPPvpXTlq85k74Hf6Bw1D/HBjQKYsM4GH/dpIGdFakmhUAWJjl+4aSoAUltIKUlJSfeFkXvpJd03YcxYy8xJQ7E1GYao=; 7:gPmyuBI39+w6zUK47NpTfhhF08VHvtbKsPIeb8oQRH9SsC0PQG8+6zG+CUOiTrBgf/VcoNW+FfKLfsedUzvtuwtYabR94ylPTYE2BOgYb54AEFwzDIxcsduvcUce6eAPVOortnDyJqHwweuvgDCMNJa+JYH6HFruOOR7ZnYk5NLAvJ9X3XsJWjZ8Jubo/VGqsz0MJtxmMf/G6BUIb+Hg0vEkt2lRT8dLAA3nX4cvBu87RvfREUsIMe/fhksM2U2e SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2017 10:07:59.9898 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08233b80-16ea-4105-2cac-08d51f7e1a05 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0502MB3662 Subject: [dpdk-dev] [PATCH v3 3/7] net/mlx4: merge Tx path functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Oct 2017 10:08:02 -0000 Merge tx_burst and mlx4_post_send functions to prevent double asking about WQ remain space. Signed-off-by: Matan Azrad --- drivers/net/mlx4/mlx4_rxtx.c | 357 +++++++++++++++++++++---------------------- 1 file changed, 172 insertions(+), 185 deletions(-) diff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c index f89df46..a8d8e81 100644 --- a/drivers/net/mlx4/mlx4_rxtx.c +++ b/drivers/net/mlx4/mlx4_rxtx.c @@ -239,185 +239,6 @@ struct pv { } /** - * Posts a single work request to a send queue. - * - * @param txq - * Target Tx queue. - * @param pkt - * Packet to transmit. - * - * @return - * 0 on success, negative errno value otherwise and rte_errno is set. - */ -static inline int -mlx4_post_send(struct txq *txq, struct rte_mbuf *pkt) -{ - struct mlx4_wqe_ctrl_seg *ctrl; - struct mlx4_wqe_data_seg *dseg; - struct mlx4_sq *sq = &txq->msq; - struct rte_mbuf *buf; - union { - uint32_t flags; - uint16_t flags16[2]; - } srcrb; - uint32_t head_idx = sq->head & sq->txbb_cnt_mask; - uint32_t lkey; - uintptr_t addr; - uint32_t owner_opcode = MLX4_OPCODE_SEND; - uint32_t byte_count; - int wqe_real_size; - int nr_txbbs; - struct pv *pv = (struct pv *)txq->bounce_buf; - int pv_counter = 0; - - /* Calculate the needed work queue entry size for this packet. */ - wqe_real_size = sizeof(struct mlx4_wqe_ctrl_seg) + - pkt->nb_segs * sizeof(struct mlx4_wqe_data_seg); - nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size); - /* - * Check that there is room for this WQE in the send queue and that - * the WQE size is legal. - */ - if (((sq->head - sq->tail) + nr_txbbs + - sq->headroom_txbbs) >= sq->txbb_cnt || - nr_txbbs > MLX4_MAX_WQE_TXBBS) { - return -ENOSPC; - } - /* Get the control and data entries of the WQE. */ - ctrl = (struct mlx4_wqe_ctrl_seg *)mlx4_get_send_wqe(sq, head_idx); - dseg = (struct mlx4_wqe_data_seg *)((uintptr_t)ctrl + - sizeof(struct mlx4_wqe_ctrl_seg)); - /* Fill the data segments with buffer information. */ - for (buf = pkt; buf != NULL; buf = buf->next, dseg++) { - addr = rte_pktmbuf_mtod(buf, uintptr_t); - rte_prefetch0((volatile void *)addr); - /* Handle WQE wraparound. */ - if (unlikely(dseg >= (struct mlx4_wqe_data_seg *)sq->eob)) - dseg = (struct mlx4_wqe_data_seg *)sq->buf; - dseg->addr = rte_cpu_to_be_64(addr); - /* Memory region key for this memory pool. */ - lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf)); -#ifndef NDEBUG - if (unlikely(lkey == (uint32_t)-1)) { - /* MR does not exist. */ - DEBUG("%p: unable to get MP <-> MR association", - (void *)txq); - /* - * Restamp entry in case of failure. - * Make sure that size is written correctly - * Note that we give ownership to the SW, not the HW. - */ - ctrl->fence_size = (wqe_real_size >> 4) & 0x3f; - mlx4_txq_stamp_freed_wqe(sq, head_idx, - (sq->head & sq->txbb_cnt) ? 0 : 1); - return -EFAULT; - } -#endif /* NDEBUG */ - dseg->lkey = rte_cpu_to_be_32(lkey); - if (likely(buf->data_len)) { - byte_count = rte_cpu_to_be_32(buf->data_len); - } else { - /* - * Zero length segment is treated as inline segment - * with zero data. - */ - byte_count = RTE_BE32(0x80000000); - } - /* - * If the data segment is not at the beginning of a - * Tx basic block (TXBB) then write the byte count, - * else postpone the writing to just before updating the - * control segment. - */ - if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) { - /* - * Need a barrier here before writing the byte_count - * fields to make sure that all the data is visible - * before the byte_count field is set. - * Otherwise, if the segment begins a new cacheline, - * the HCA prefetcher could grab the 64-byte chunk and - * get a valid (!= 0xffffffff) byte count but stale - * data, and end up sending the wrong data. - */ - rte_io_wmb(); - dseg->byte_count = byte_count; - } else { - /* - * This data segment starts at the beginning of a new - * TXBB, so we need to postpone its byte_count writing - * for later. - */ - pv[pv_counter].dseg = dseg; - pv[pv_counter++].val = byte_count; - } - } - /* Write the first DWORD of each TXBB save earlier. */ - if (pv_counter) { - /* Need a barrier here before writing the byte_count. */ - rte_io_wmb(); - for (--pv_counter; pv_counter >= 0; pv_counter--) - pv[pv_counter].dseg->byte_count = pv[pv_counter].val; - } - /* Fill the control parameters for this packet. */ - ctrl->fence_size = (wqe_real_size >> 4) & 0x3f; - /* - * For raw Ethernet, the SOLICIT flag is used to indicate that no ICRC - * should be calculated. - */ - txq->elts_comp_cd -= nr_txbbs; - if (unlikely(txq->elts_comp_cd <= 0)) { - txq->elts_comp_cd = txq->elts_comp_cd_init; - srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT | - MLX4_WQE_CTRL_CQ_UPDATE); - } else { - srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT); - } - /* Enable HW checksum offload if requested */ - if (txq->csum && - (pkt->ol_flags & - (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) { - const uint64_t is_tunneled = (pkt->ol_flags & - (PKT_TX_TUNNEL_GRE | - PKT_TX_TUNNEL_VXLAN)); - - if (is_tunneled && txq->csum_l2tun) { - owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM | - MLX4_WQE_CTRL_IL4_HDR_CSUM; - if (pkt->ol_flags & PKT_TX_OUTER_IP_CKSUM) - srcrb.flags |= - RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM); - } else { - srcrb.flags |= RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM | - MLX4_WQE_CTRL_TCP_UDP_CSUM); - } - } - if (txq->lb) { - /* - * Copy destination MAC address to the WQE, this allows - * loopback in eSwitch, so that VFs and PF can communicate - * with each other. - */ - srcrb.flags16[0] = *(rte_pktmbuf_mtod(pkt, uint16_t *)); - ctrl->imm = *(rte_pktmbuf_mtod_offset(pkt, uint32_t *, - sizeof(uint16_t))); - } else { - ctrl->imm = 0; - } - ctrl->srcrb_flags = srcrb.flags; - /* - * Make sure descriptor is fully written before - * setting ownership bit (because HW can start - * executing as soon as we do). - */ - rte_wmb(); - ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode | - ((sq->head & sq->txbb_cnt) ? - MLX4_BIT_WQE_OWN : 0)); - sq->head += nr_txbbs; - return 0; -} - -/** * DPDK callback for Tx. * * @param dpdk_txq @@ -440,7 +261,8 @@ struct pv { unsigned int bytes_sent = 0; unsigned int i; unsigned int max; - int err; + struct mlx4_sq *sq = &txq->msq; + struct pv *pv = (struct pv *)txq->bounce_buf; assert(txq->elts_comp_cd != 0); mlx4_txq_complete(txq); @@ -459,6 +281,21 @@ struct pv { (((elts_head + 1) == elts_n) ? 0 : elts_head + 1); struct txq_elt *elt_next = &(*txq->elts)[elts_head_next]; struct txq_elt *elt = &(*txq->elts)[elts_head]; + uint32_t owner_opcode = MLX4_OPCODE_SEND; + struct mlx4_wqe_ctrl_seg *ctrl; + struct mlx4_wqe_data_seg *dseg; + struct rte_mbuf *sbuf; + union { + uint32_t flags; + uint16_t flags16[2]; + } srcrb; + uint32_t head_idx = sq->head & sq->txbb_cnt_mask; + uint32_t lkey; + uintptr_t addr; + uint32_t byte_count; + int wqe_real_size; + int nr_txbbs; + int pv_counter = 0; /* Clean up old buffer. */ if (likely(elt->buf != NULL)) { @@ -477,18 +314,168 @@ struct pv { } while (tmp != NULL); } RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf); - /* Post the packet for sending. */ - err = mlx4_post_send(txq, buf); - if (unlikely(err)) { + + /* + * Calculate the needed work queue entry size + * for this packet. + */ + wqe_real_size = sizeof(struct mlx4_wqe_ctrl_seg) + + buf->nb_segs * sizeof(struct mlx4_wqe_data_seg); + nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size); + /* + * Check that there is room for this WQE in the send + * queue and that the WQE size is legal. + */ + if (((sq->head - sq->tail) + nr_txbbs + + sq->headroom_txbbs) >= sq->txbb_cnt || + nr_txbbs > MLX4_MAX_WQE_TXBBS) { elt->buf = NULL; - goto stop; + break; } + /* Get the control and data entries of the WQE. */ + ctrl = (struct mlx4_wqe_ctrl_seg *) + mlx4_get_send_wqe(sq, head_idx); + dseg = (struct mlx4_wqe_data_seg *)((uintptr_t)ctrl + + sizeof(struct mlx4_wqe_ctrl_seg)); + /* Fill the data segments with buffer information. */ + for (sbuf = buf; sbuf != NULL; sbuf = sbuf->next, dseg++) { + addr = rte_pktmbuf_mtod(sbuf, uintptr_t); + rte_prefetch0((volatile void *)addr); + /* Handle WQE wraparound. */ + if (unlikely(dseg >= + (struct mlx4_wqe_data_seg *)sq->eob)) + dseg = (struct mlx4_wqe_data_seg *)sq->buf; + dseg->addr = rte_cpu_to_be_64(addr); + /* Memory region key (big endian). */ + lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf)); + dseg->lkey = rte_cpu_to_be_32(lkey); +#ifndef NDEBUG + if (unlikely(dseg->lkey == + rte_cpu_to_be_32((uint32_t)-1))) { + /* MR does not exist. */ + DEBUG("%p: unable to get MP <-> MR association", + (void *)txq); + /* + * Restamp entry in case of failure. + * Make sure that size is written correctly + * Note that we give ownership to the SW, + * not the HW. + */ + ctrl->fence_size = (wqe_real_size >> 4) & 0x3f; + mlx4_txq_stamp_freed_wqe(sq, head_idx, + (sq->head & sq->txbb_cnt) ? 0 : 1); + elt->buf = NULL; + break; + } +#endif /* NDEBUG */ + if (likely(sbuf->data_len)) { + byte_count = rte_cpu_to_be_32(sbuf->data_len); + } else { + /* + * Zero length segment is treated as inline + * segment with zero data. + */ + byte_count = RTE_BE32(0x80000000); + } + /* + * If the data segment is not at the beginning + * of a Tx basic block (TXBB) then write the + * byte count, else postpone the writing to + * just before updating the control segment. + */ + if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) { + /* + * Need a barrier here before writing the + * byte_count fields to make sure that all the + * data is visible before the byte_count field + * is set. otherwise, if the segment begins a + * new cacheline, the HCA prefetcher could grab + * the 64-byte chunk and get a valid + * (!= 0xffffffff) byte count but stale data, + * and end up sending the wrong data. + */ + rte_io_wmb(); + dseg->byte_count = byte_count; + } else { + /* + * This data segment starts at the beginning of + * a new TXBB, so we need to postpone its + * byte_count writing for later. + */ + pv[pv_counter].dseg = dseg; + pv[pv_counter++].val = byte_count; + } + } + /* Write the first DWORD of each TXBB save earlier. */ + if (pv_counter) { + /* Need a barrier before writing the byte_count. */ + rte_io_wmb(); + for (--pv_counter; pv_counter >= 0; pv_counter--) + pv[pv_counter].dseg->byte_count = + pv[pv_counter].val; + } + /* Fill the control parameters for this packet. */ + ctrl->fence_size = (wqe_real_size >> 4) & 0x3f; + /* + * For raw Ethernet, the SOLICIT flag is used to indicate + * that no ICRC should be calculated. + */ + txq->elts_comp_cd -= nr_txbbs; + if (unlikely(txq->elts_comp_cd <= 0)) { + txq->elts_comp_cd = txq->elts_comp_cd_init; + srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT | + MLX4_WQE_CTRL_CQ_UPDATE); + } else { + srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT); + } + /* Enable HW checksum offload if requested */ + if (txq->csum && + (buf->ol_flags & + (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) { + const uint64_t is_tunneled = (buf->ol_flags & + (PKT_TX_TUNNEL_GRE | + PKT_TX_TUNNEL_VXLAN)); + + if (is_tunneled && txq->csum_l2tun) { + owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM | + MLX4_WQE_CTRL_IL4_HDR_CSUM; + if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM) + srcrb.flags |= + RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM); + } else { + srcrb.flags |= + RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM | + MLX4_WQE_CTRL_TCP_UDP_CSUM); + } + } + if (txq->lb) { + /* + * Copy destination MAC address to the WQE, this allows + * loopback in eSwitch, so that VFs and PF can + * communicate with each other. + */ + srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *)); + ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *, + sizeof(uint16_t))); + } else { + ctrl->imm = 0; + } + ctrl->srcrb_flags = srcrb.flags; + /* + * Make sure descriptor is fully written before + * setting ownership bit (because HW can start + * executing as soon as we do). + */ + rte_wmb(); + ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode | + ((sq->head & sq->txbb_cnt) ? + MLX4_BIT_WQE_OWN : 0)); + sq->head += nr_txbbs; elt->buf = buf; bytes_sent += buf->pkt_len; ++elts_comp; elts_head = elts_head_next; } -stop: /* Take a shortcut if nothing must be sent. */ if (unlikely(i == 0)) return 0; -- 1.8.3.1