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HE1PR0502MB3659; 6:CvgZ5dwH8W0JZPuGd8Sv1xybi12K63jsNJ6GwY4G9EZ11KJkl8Wwkljkvs9CfJtgyrUQPkxTVTnMUU7RjlkjONRxivqEAwHas6I4RtaR2D+k9uhObgxKax6ibYdq10gEaUk5u4tqWVjY9rtZ7E0bZNhAzUWlgs1U40Cp44qq+DrUCYzvyuvtbTadqBLB1cwnoX6LbI5kBDBEavLGitue8BbTOj7M1TtYOoPURH8XD3Y5blHPgYDy+DFW9CPymnSQZqvUt+Txf1+6PFJrOOlt2Fx8y8gNGnvy2R2dImstTRVCR6S9ZEh+JQNazZwN0Nj8Rf2Ath3kKjuvqdHgrpAzeaJOAYnuFAT6XvYKeAQUbPI=; 5:WhE3UUVt16bd+VdaYhrAZ7Mym+vKIVF1MM6aHJPPgEfGdWjZ59ZzEVTFzTrOq4DZOZ/Lyrj9UWOfmm+qpcYPr0xiST2s9I99OrdJYy2K3N6t1n3V3Ym8CbZs1IqgQye4/nq6Bk7FTbbY0ixhCD3E5TdRzLnHp8gHrz/Do1SuEkk=; 24:rDYCg5jcWkUeGEp/1X8YhdW+n7z0HgEMUXiXphAjatwlvGa68WL9LlYTMQIXaHgGAJ5z5Za2UQlEqhY2Ckm6oqI3mhSxEcakLfF37hGrgOY=; 7:Hb/yP8yD0OVoE3AeuDyQqU2e875+dTZR09Q4G7SkVXUEUlIEbmwOULW6XrokNfhFPb6mgU5zA6ZzUD7JKZ4YSoz6tHeO4PRYt1jF6M948qvdnlHV73D3EYaaXR336qz10J8jT7gxmItwNrFMvd1Z39i1v03aJEPMA+TT9tOIIpAlnBZGbPAYuK8kNL8aS1etjDzZyFO/lIBgI/xCWOjNBR1Pf1JAI4EDwSRBnu43om1dY1X9AjvrLu6j1andTk0n SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2017 16:43:22.6742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16e76704-417a-408e-67e5-08d52210d531 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0502MB3659 Subject: [dpdk-dev] [PATCH v5 8/8] net/mlx4: mitigate Tx path memory barriers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Nov 2017 16:43:25 -0000 Replace most of the memory barriers by IO memory barriers since they are all targeted to the DRAM; This improves code efficiency for systems which force store order between different addresses. Only the doorbell register store should be protected by memory barrier since it is targeted to the PCI memory domain. Limit pre byte count store IO memory barrier for systems with cache line size smaller than 64B (TXBB size). This patch improves Tx performance by 0.2MPPS for one segment 64B packets via 1 queue with 1 core test. Signed-off-by: Matan Azrad Acked-by: Adrien Mazarguil --- drivers/net/mlx4/mlx4_rxtx.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c index 20060ce..5f8adec 100644 --- a/drivers/net/mlx4/mlx4_rxtx.c +++ b/drivers/net/mlx4/mlx4_rxtx.c @@ -168,7 +168,7 @@ struct pv { /* * Make sure we read the CQE after we read the ownership bit. */ - rte_rmb(); + rte_io_rmb(); #ifndef NDEBUG if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_ERROR)) { @@ -196,14 +196,9 @@ struct pv { } while (1); if (unlikely(pkts == 0)) return 0; - /* - * Update CQ. - * To prevent CQ overflow we first update CQ consumer and only then - * the ring consumer. - */ + /* Update CQ. */ cq->cons_index = cons_index; *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK); - rte_wmb(); sq->tail = sq->tail + nr_txbbs; /* Update the list of packets posted for transmission. */ elts_comp -= pkts; @@ -320,6 +315,7 @@ struct pv { * control segment. */ if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) { +#if RTE_CACHE_LINE_SIZE < 64 /* * Need a barrier here before writing the byte_count * fields to make sure that all the data is visible @@ -330,6 +326,7 @@ struct pv { * data, and end up sending the wrong data. */ rte_io_wmb(); +#endif /* RTE_CACHE_LINE_SIZE */ dseg->byte_count = byte_count; } else { /* @@ -471,8 +468,7 @@ struct pv { break; } #endif /* NDEBUG */ - /* Need a barrier here before byte count store. */ - rte_io_wmb(); + /* Never be TXBB aligned, no need compiler barrier. */ dseg->byte_count = rte_cpu_to_be_32(buf->data_len); /* Fill the control parameters for this packet. */ ctrl->fence_size = (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f; @@ -534,7 +530,7 @@ struct pv { * setting ownership bit (because HW can start * executing as soon as we do). */ - rte_wmb(); + rte_io_wmb(); ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode | ((sq->head & sq->txbb_cnt) ? MLX4_BIT_WQE_OWN : 0)); -- 1.8.3.1