From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id B5BFE1B673; Fri, 3 Nov 2017 12:21:25 +0100 (CET) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Nov 2017 04:21:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,338,1505804400"; d="scan'208";a="145558127" Received: from dpdk-lixiaoyun.sh.intel.com ([10.67.111.136]) by orsmga004.jf.intel.com with ESMTP; 03 Nov 2017 04:21:23 -0700 From: Xiaoyun Li To: wenzhuo.lu@intel.com Cc: qiming.yang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com, dev@dpdk.org, Xiaoyun Li , stable@dpdk.org Date: Fri, 3 Nov 2017 19:17:38 +0800 Message-Id: <1509707858-25322-1-git-send-email-xiaoyun.li@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [dpdk-dev] [PATCH] net/e1000: fix cannot getting Rx interrupts issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Nov 2017 11:21:26 -0000 When using VFIO and MSIX interrupt mode, cannot get Rx interrupts. Because the interrupt vectors that are used by VFIO are not enabled. This patch fixes this issue. Fixes: c3cd3de0ab50 ("igb: enable Rx queue interrupts for PF") Cc: stable@dpdk.org Signed-off-by: Xiaoyun Li --- drivers/net/e1000/igb_ethdev.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index 003bdf0..dc70d22 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -5387,7 +5387,14 @@ eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) { struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t mask = 1 << queue_id; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + uint32_t vec = E1000_MISC_VEC_ID; + + if (rte_intr_allow_others(intr_handle)) + vec = E1000_RX_VEC_START; + + uint32_t mask = 1 << (queue_id + vec); E1000_WRITE_REG(hw, E1000_EIMC, mask); E1000_WRITE_FLUSH(hw); @@ -5402,7 +5409,12 @@ eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; - uint32_t mask = 1 << queue_id; + uint32_t vec = E1000_MISC_VEC_ID; + + if (rte_intr_allow_others(intr_handle)) + vec = E1000_RX_VEC_START; + + uint32_t mask = 1 << (queue_id + vec); uint32_t regval; regval = E1000_READ_REG(hw, E1000_EIMS); -- 2.7.4