From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by dpdk.org (Postfix) with ESMTP id 3B00D1B3DC for ; Fri, 10 Nov 2017 02:51:33 +0100 (CET) Received: by mail-pf0-f196.google.com with SMTP id e64so5633320pfk.9 for ; Thu, 09 Nov 2017 17:51:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4OEDQ3qCogMJ7UT5+L9kc5LqeWqqwLdV9SguvMpaniU=; b=n0pB2x06WTY6vLgIxO7I/8qz3N7IpyYt6hofSy3cc80KuMvl9V6NdrsSI1mTL3MWbL j9ZWM6p5XDPmlcF6i51z/xmyAA7oBetcf4ayRm5vD4nJ1LLrDx0nJ/kxagLDABTNlgTL eCgibdZBfC/Dkq0yxgPUZd+zpk6xepXsViel3EZfC4kLyjGtRjn1umg21xN51rzWxJtc ITOKZrfz8wyyS2P62irfekeSrzcVP83KkoMTFzBFffylcJhCb2di/pRG0d4hzn6yehv3 zrFgF54gucEDV6bvSnPMM/IiWLEirOZnhNStyo0/8u8VtJg6ze67EwHTySJ04rNlRxEq DoYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4OEDQ3qCogMJ7UT5+L9kc5LqeWqqwLdV9SguvMpaniU=; b=lTJQ0MY4rI/dAuHeQYz9UYWPZycKizMqonIZH5UGWPKSN/JD5ni3x8HNHo0XFvq03r vkJHYg3eT7V8phpfJdsYoyngp29MBq2H9UsmhhVP0Bpyj1kiPIFrDmcN/gNwRm3+/d02 LUcwbFzplmiss071W51anJZw/ELeNA60WomCj6SNFlWFp6gi11jmgE1ag58qusnlemPC YL3sR6Kk80bVmzQWmqkZCTMEvI0q+WnJrBwGHJ0FodGd2IrFpCgdQ6PxXauOIqDgnyny xVJ3SXAv3FtiUNkzrUF7QuGbIzozbj5GaZBFYblQ8XZyR+4FJ6X78UmXhAtxeSps+a/8 ihyw== X-Gm-Message-State: AJaThX5nrjLA2rWBtXDtRqNvvEq0G37ZGXnQzGwdujT5kVVq0tu+H1oz PHN1+pQSvMFzFR3ntcTc5NE= X-Google-Smtp-Source: ABhQp+R0ohUGqGYXatg/EDse/GIlW/kkN6cHH2PIimR0ZhiE6xnIX4+oEkiEXuT8wqX63dDGLe2phQ== X-Received: by 10.99.63.7 with SMTP id m7mr2297137pga.359.1510278692456; Thu, 09 Nov 2017 17:51:32 -0800 (PST) Received: from nfv-demo01.hxtcorp.net ([38.106.11.25]) by smtp.gmail.com with ESMTPSA id f6sm12361026pgo.11.2017.11.09.17.51.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Nov 2017 17:51:31 -0800 (PST) From: Jia He To: jerin.jacob@caviumnetworks.com, dev@dpdk.org, olivier.matz@6wind.com Cc: konstantin.ananyev@intel.com, bruce.richardson@intel.com, jianbo.liu@arm.com, hemant.agrawal@nxp.com, Jia He Date: Fri, 10 Nov 2017 01:51:08 +0000 Message-Id: <1510278669-8489-1-git-send-email-hejianet@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510118764-29697-1-git-send-email-hejianet@gmail.com> References: <1510118764-29697-1-git-send-email-hejianet@gmail.com> Subject: [dpdk-dev] [PATCH v5 0/1] fix race condition in enqueue/dequeue because of cpu reorder X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Nov 2017 01:51:33 -0000 We watched a rte panic of mbuf_autotest in our qualcomm arm64 server due to a possible race condition. To fix this race condition, rmb() is needed to add between the 2 loads. Already fuctionally tested on the machines as follows: - on X86 - on arm64 --- Changelog V5: split it into 2 patchset due to the milestone concerns, this is the 1st one V4: split into small patches V3: arch specific implementation for enqueue/dequeue barrier V2: let users choose whether using load_acquire/store_release V1: rte_smp_rmb() between 2 loads Jia He (4): eal/arm64: remove the braces {} for dmb() and dsb() ring: guarantee load/load order in enqueue and dequeue ring: introduce new header file to include common functions ring: introduce new header file to support C11 memory model config/common_armv8a_linuxapp | 2 + .../common/include/arch/arm/rte_atomic_64.h | 4 +- lib/librte_eventdev/rte_event_ring.h | 6 +- lib/librte_ring/Makefile | 4 +- lib/librte_ring/rte_ring.h | 161 ++--------------- lib/librte_ring/rte_ring_c11_mem.h | 185 ++++++++++++++++++++ lib/librte_ring/rte_ring_generic.h | 194 +++++++++++++++++++++ 7 files changed, 404 insertions(+), 152 deletions(-) create mode 100644 lib/librte_ring/rte_ring_c11_mem.h create mode 100644 lib/librte_ring/rte_ring_generic.h -- 2.7.4