From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id CD8B81B287 for ; Fri, 17 Nov 2017 11:01:46 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Nov 2017 02:01:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,408,1505804400"; d="scan'208";a="6047087" Received: from dpdk6.bj.intel.com ([172.16.182.87]) by orsmga001.jf.intel.com with ESMTP; 17 Nov 2017 02:01:43 -0800 From: Wei Dai To: jingjing.wu@intel.com, beilei.xing@intel.com Cc: dev@dpdk.org, Wei Dai Date: Fri, 17 Nov 2017 17:47:04 +0800 Message-Id: <1510912024-56215-1-git-send-email-wei.dai@intel.com> X-Mailer: git-send-email 2.7.5 Subject: [dpdk-dev] [PATCH] net/i40e: determine number of queues per VF during run time X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Nov 2017 10:01:47 -0000 Without this patch, the number of queues per i40e VF is defined as 4 by CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4 in config/common_base. It is fixed value determined in building time and can't be changed during run time. With this patch, the number of queues per i40e VF can be determinated during run time. For example, if the PCI address of an i40e VF is aaaa:bb.cc, with the EAL parameter -w aaaa:bb.cc,i40e-queue-num-per-vf=8 , the number of queues per VF is 8. If there is no "i40e-queue-num-per-vf" setting in EAL parameters, it is 4 by default as before. And if the value after the "i40e-queue-num-per-vf" is invalid, it is set as 4 forcibly. The valid values include 1, 2, 4, 8, 16 . Signed-off-by: Wei Dai --- config/common_base | 1 - drivers/net/i40e/i40e_ethdev.c | 68 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 66 insertions(+), 3 deletions(-) diff --git a/config/common_base b/config/common_base index e74febe..4e20389 100644 --- a/config/common_base +++ b/config/common_base @@ -208,7 +208,6 @@ CONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=y CONFIG_RTE_LIBRTE_I40E_INC_VECTOR=y CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF=64 -CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4 CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM=4 # interval up to 8160 us, aligned to 2 (or default value) CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1 diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 811cc9f..0d14f52 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -3971,6 +3971,68 @@ i40e_get_cap(struct i40e_hw *hw) return ret; } +static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev) +{ +#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 +#define I40E_QUEUE_NUM_PER_VF_ARG "i40e-queue-num-per-vf" +#define IS_POWER_OF_2(n) (n && !(n & (n - 1))) + + struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); + char *s; + char *ps0, *ps1, *pv; + char *end; + unsigned long value; + + if (!is_i40e_supported(dev)) + return -ENOTSUP; + + /* set default queue number per VF as 4 */ + pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF; + + if (dev->device->devargs == NULL) + return 0; + + s = rte_zmalloc(__func__, strlen(dev->device->devargs->args) + 1, 0); + if (s == NULL) + return -(ENOMEM); + strcpy(s, dev->device->devargs->args); + + ps0 = s; + do { + while (isblank(*ps0)) + ps0++; + pv = strchr(ps0, '='); + if (pv == NULL) + break; + ps1 = pv - 1; + *pv++ = 0; + + while (isblank(*ps1)) + *ps1-- = 0; + + if (!strcmp(ps0, I40E_QUEUE_NUM_PER_VF_ARG)) { + errno = 0; + value = strtoul(pv, &end, 0); + if ((errno != 0) || (end == pv)) + break; + if ((value <= 16) && (IS_POWER_OF_2(value))) + pf->vf_nb_qp_max = (uint16_t)value; + else + PMD_DRV_LOG(ERR, "Wrong VF queue number = %lu," + " it must be power of 2 and equal or" + " less than 16 !", value); + break; + } + ps0 = strchr(pv, ','); + if (ps0 == NULL) + break; + ps0++; + } while (1); + + rte_free(s); + return 0; +} + static int i40e_pf_parameter_init(struct rte_eth_dev *dev) { @@ -3983,6 +4045,9 @@ i40e_pf_parameter_init(struct rte_eth_dev *dev) PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV"); return -EINVAL; } + + i40e_pf_config_vf_rxq_number(dev); + /* Add the parameter init for LFC */ pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME; pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER; @@ -3992,7 +4057,6 @@ i40e_pf_parameter_init(struct rte_eth_dev *dev) pf->max_num_vsi = hw->func_caps.num_vsis; pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF; pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; - pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF; /* FDir queue/VSI allocation */ pf->fdir_qp_offset = 0; @@ -4022,7 +4086,7 @@ i40e_pf_parameter_init(struct rte_eth_dev *dev) pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps; if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) { pf->flags |= I40E_FLAG_SRIOV; - pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF; + pf->vf_nb_qps = pf->vf_nb_qp_max; pf->vf_num = pci_dev->max_vfs; PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, in total %u queues", -- 2.7.5