From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM03-BY2-obe.outbound.protection.outlook.com (mail-by2nam03on0040.outbound.protection.outlook.com [104.47.42.40]) by dpdk.org (Postfix) with ESMTP id ABB75324A for ; Thu, 30 Nov 2017 14:11:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=ZhvJ+U1upgwAqLJtf3c/yYkmZpEnx4d0L8HLXgT79Ic=; b=0Xs4eyK3Omhb6fRk2DH3WzHS0xgfQewNHTaHF6uxZhXi/GvQ7cAJ4ohzooWZhZKXtxLpEIBQNC8YiuyyEgbDnlnAI6LRueR8KimIKRkOdjXFEE10uk1myIf+oKoIgc7Pc6EWrjfRl0TUqUlTNZmJRb9KG1pwPEFinCTcWqsHK3c= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Ravi1.Kumar@amd.com; Received: from wallaby-smavila.amd.com (202.56.249.162) by DM5PR12MB1514.namprd12.prod.outlook.com (10.172.39.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.282.5; Thu, 30 Nov 2017 13:11:44 +0000 From: Ravi Kumar To: dev@dpdk.org Date: Thu, 30 Nov 2017 08:11:00 -0500 Message-Id: <1512047472-118050-4-git-send-email-Ravi1.kumar@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512047472-118050-1-git-send-email-Ravi1.kumar@amd.com> References: <1512047472-118050-1-git-send-email-Ravi1.kumar@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [202.56.249.162] X-ClientProxiedBy: MA1PR01CA0077.INDPRD01.PROD.OUTLOOK.COM (10.174.56.17) To DM5PR12MB1514.namprd12.prod.outlook.com (10.172.39.146) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e2abadd4-c9db-4aed-457d-08d537f3e856 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; 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DM5PR12MB1514; 20:ndlfomu9GSFcOvgCy5cc4kTehAaZPxxhjwFPSwFJcOWTH6fpprsrQ5prJl3WZ8Wosy4tKIJlWfQfVO+UmlDtbXl8dgbv+vjhHUgLtzdvimSbFRufGMSiJM0/Z0dnH1vGrPwOpjjBK45IQ6h5MGfgmjFnnNfmmGsF3wxJ59VJzVvgh4H1XDQws4EG9S8SHVLif7yecKrZkmgN4EE53RZQehrD2qObEy7CY6Y4tIwWGL6SgzDGMZKRyToo0WjoOwLi X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2017 13:11:44.9373 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2abadd4-c9db-4aed-457d-08d537f3e856 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1514 Subject: [dpdk-dev] [PATCH 04/16] net/axgbe: add structures for MAC initialization and reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Nov 2017 13:11:48 -0000 Signed-off-by: Ravi Kumar --- drivers/net/axgbe/Makefile | 1 + drivers/net/axgbe/axgbe_dev.c | 167 +++++++++++++++++++ drivers/net/axgbe/axgbe_ethdev.c | 291 ++++++++++++++++++++++++++++++++ drivers/net/axgbe/axgbe_ethdev.h | 349 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 808 insertions(+) create mode 100644 drivers/net/axgbe/axgbe_dev.c diff --git a/drivers/net/axgbe/Makefile b/drivers/net/axgbe/Makefile index c8a1e87..ce2485d 100644 --- a/drivers/net/axgbe/Makefile +++ b/drivers/net/axgbe/Makefile @@ -142,5 +142,6 @@ LIBABIVER := 1 # all source are stored in SRCS-y # SRCS-$(CONFIG_RTE_LIBRTE_AXGBE_PMD) += axgbe_ethdev.c +SRCS-$(CONFIG_RTE_LIBRTE_AXGBE_PMD) += axgbe_dev.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c new file mode 100644 index 0000000..8bf3b82 --- /dev/null +++ b/drivers/net/axgbe/axgbe_dev.c @@ -0,0 +1,167 @@ +/*- + * Copyright(c) 2014-2017 Advanced Micro Devices, Inc. + * All rights reserved. + * + * AMD 10Gb Ethernet driver + * + * This file is available to you under your choice of the following two + * licenses: + * + * License 1: GPLv2 + * + * Copyright (c) 2017 Advanced Micro Devices, Inc. + * + * This file is free software; you may copy, redistribute and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * This file incorporates work covered by the following copyright and + * permission notice: + * + * Copyright (c) 2013 Synopsys, Inc. + * + * The Synopsys DWC ETHER XGMAC Software Driver and documentation + * (hereinafter "Software") is an unsupported proprietary work of Synopsys, + * Inc. unless otherwise expressly agreed to in writing between Synopsys + * and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product + * under any End User Software License Agreement or Agreement for Licensed + * Product with Synopsys or any supplement thereto. Permission is hereby + * granted, free of charge, to any person obtaining a copy of this software + * annotated with this license and the Software, to deal in the Software + * without restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished + * to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * License 2: Modified BSD + * + * Copyright (c) 2017 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file incorporates work covered by the following copyright and + * permission notice: + * + * Copyright (c) 2013 Synopsys, Inc. + * + * The Synopsys DWC ETHER XGMAC Software Driver and documentation + * (hereinafter "Software") is an unsupported proprietary work of Synopsys, + * Inc. unless otherwise expressly agreed to in writing between Synopsys + * and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product + * under any End User Software License Agreement or Agreement for Licensed + * Product with Synopsys or any supplement thereto. Permission is hereby + * granted, free of charge, to any person obtaining a copy of this software + * annotated with this license and the Software, to deal in the Software + * without restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished + * to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "axgbe_ethdev.h" +#include "axgbe_common.h" +#include "axgbe_phy.h" + +static int __axgbe_exit(struct axgbe_port *pdata) +{ + unsigned int count = 2000; + + /* Issue a software reset */ + AXGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); + rte_delay_us(10); + + /* Poll Until Poll Condition */ + while (--count && AXGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) + rte_delay_us(500); + + if (!count) + return -EBUSY; + + return 0; +} + +static int axgbe_exit(struct axgbe_port *pdata) +{ + int ret; + + /* To guard against possible incorrectly generated interrupts, + * issue the software reset twice. + */ + ret = __axgbe_exit(pdata); + if (ret) + return ret; + + return __axgbe_exit(pdata); +} + +void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if) +{ + hw_if->exit = axgbe_exit; +} diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index 7f2fbbf..08897e0 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -126,6 +126,8 @@ */ #include "axgbe_ethdev.h" +#include "axgbe_common.h" +#include "axgbe_phy.h" static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev); @@ -141,6 +143,190 @@ static const struct rte_pci_id pci_id_axgbe_map[] = { { .vendor_id = 0, }, }; +static struct axgbe_version_data axgbe_v2a = { + .xpcs_access = AXGBE_XPCS_ACCESS_V2, + .mmc_64bit = 1, + .tx_max_fifo_size = 229376, + .rx_max_fifo_size = 229376, + .tx_tstamp_workaround = 1, + .ecc_support = 1, + .i2c_support = 1, +}; + +static struct axgbe_version_data axgbe_v2b = { + .xpcs_access = AXGBE_XPCS_ACCESS_V2, + .mmc_64bit = 1, + .tx_max_fifo_size = 65536, + .rx_max_fifo_size = 65536, + .tx_tstamp_workaround = 1, + .ecc_support = 1, + .i2c_support = 1, +}; + +static void axgbe_get_all_hw_features(struct axgbe_port *pdata) +{ + unsigned int mac_hfr0, mac_hfr1, mac_hfr2; + struct axgbe_hw_features *hw_feat = &pdata->hw_feat; + + mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); + mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); + mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); + + memset(hw_feat, 0, sizeof(*hw_feat)); + + hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); + + /* Hardware feature register 0 */ + hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); + hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); + hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); + hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); + hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); + hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); + hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); + hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); + hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); + hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); + hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); + hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, + ADDMACADRSEL); + hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); + hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); + + /* Hardware feature register 1 */ + hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, + RXFIFOSIZE); + hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, + TXFIFOSIZE); + hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, + MAC_HWF1R, ADVTHWORD); + hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); + hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); + hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); + hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); + hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); + hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); + hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); + hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, + HASHTBLSZ); + hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, + L3L4FNUM); + + /* Hardware feature register 2 */ + hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); + hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); + hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); + hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); + hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); + hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, + AUXSNAPNUM); + + /* Translate the Hash Table size into actual number */ + switch (hw_feat->hash_table_size) { + case 0: + break; + case 1: + hw_feat->hash_table_size = 64; + break; + case 2: + hw_feat->hash_table_size = 128; + break; + case 3: + hw_feat->hash_table_size = 256; + break; + } + + /* Translate the address width setting into actual number */ + switch (hw_feat->dma_width) { + case 0: + hw_feat->dma_width = 32; + break; + case 1: + hw_feat->dma_width = 40; + break; + case 2: + hw_feat->dma_width = 48; + break; + default: + hw_feat->dma_width = 32; + } + + /* The Queue, Channel and TC counts are zero based so increment them + * to get the actual number + */ + hw_feat->rx_q_cnt++; + hw_feat->tx_q_cnt++; + hw_feat->rx_ch_cnt++; + hw_feat->tx_ch_cnt++; + hw_feat->tc_cnt++; + + /* Translate the fifo sizes into actual numbers */ + hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); + hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); +} + +static void axgbe_init_all_fptrs(struct axgbe_port *pdata) +{ + axgbe_init_function_ptrs_dev(&pdata->hw_if); +} + +static void axgbe_set_counts(struct axgbe_port *pdata) +{ + /* Set all the function pointers */ + axgbe_init_all_fptrs(pdata); + + /* Populate the hardware features */ + axgbe_get_all_hw_features(pdata); + + /* Set default max values if not provided */ + if (!pdata->tx_max_channel_count) + pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; + if (!pdata->rx_max_channel_count) + pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; + + if (!pdata->tx_max_q_count) + pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; + if (!pdata->rx_max_q_count) + pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; + + /* Calculate the number of Tx and Rx rings to be created + * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set + * the number of Tx queues to the number of Tx channels + * enabled + * -Rx (DMA) Channels do not map 1-to-1 so use the actual + * number of Rx queues or maximum allowed + */ + pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, + pdata->tx_max_channel_count); + pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, + pdata->tx_max_q_count); + + pdata->tx_q_count = pdata->tx_ring_count; + + pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, + pdata->rx_max_channel_count); + + pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, + pdata->rx_max_q_count); +} + +static void axgbe_default_config(struct axgbe_port *pdata) +{ + pdata->pblx8 = DMA_PBL_X8_ENABLE; + pdata->tx_sf_mode = MTL_TSF_ENABLE; + pdata->tx_threshold = MTL_TX_THRESHOLD_64; + pdata->tx_pbl = DMA_PBL_32; + pdata->tx_osp_mode = DMA_OSP_ENABLE; + pdata->rx_sf_mode = MTL_RSF_ENABLE; + pdata->rx_threshold = MTL_RX_THRESHOLD_64; + pdata->rx_pbl = DMA_PBL_32; + pdata->pause_autoneg = 1; + pdata->tx_pause = 0; + pdata->rx_pause = 0; + pdata->phy_speed = SPEED_UNKNOWN; + pdata->power_down = 0; +} + /* * It returns 0 on success. */ @@ -150,8 +336,13 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) PMD_INIT_FUNC_TRACE(); struct axgbe_port *pdata; struct rte_pci_device *pci_dev; + uint32_t reg, mac_lo, mac_hi; + int ret; pdata = (struct axgbe_port *)eth_dev->data->dev_private; + /* initial state */ + axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); + axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); pdata->eth_dev = eth_dev; /* @@ -166,6 +357,106 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) pdata->pci_dev = pci_dev; rte_eth_copy_pci_info(eth_dev, pci_dev); + pdata->xgmac_regs = + (uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; + pdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET; + pdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET; + pdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; + + /* version specific driver data*/ + if (pci_dev->id.device_id == 0x1458) + pdata->vdata = &axgbe_v2a; + else + pdata->vdata = &axgbe_v2b; + + /* Configure the PCS indirect addressing support */ + reg = XPCS32_IOREAD(pdata, PCS_V2_WINDOW_DEF); + pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); + pdata->xpcs_window <<= 6; + pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); + pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); + pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; + pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; + pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; + PMD_INIT_LOG(DEBUG, + "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, + pdata->xpcs_window_size, pdata->xpcs_window_mask); + XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); + + /* Retrieve the MAC address */ + mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); + mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); + pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; + pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; + pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; + pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; + pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; + pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; + + eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", + ETHER_ADDR_LEN, 0); + if (!eth_dev->data->mac_addrs) { + PMD_INIT_LOG(ERR, + "Failed to alloc %u bytes needed to store MAC addr tbl", + ETHER_ADDR_LEN); + return -ENOMEM; + } + + if (!is_valid_assigned_ether_addr(&pdata->mac_addr)) + eth_random_addr(pdata->mac_addr.addr_bytes); + + /* Copy the permanent MAC address */ + ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); + + /* Clock settings */ + pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; + pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; + + /* Set the DMA coherency values */ + pdata->coherent = 1; + pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; + pdata->arcache = AXGBE_DMA_OS_ARCACHE; + pdata->awcache = AXGBE_DMA_OS_AWCACHE; + + /* Set the maximum channels and queues */ + reg = XP_IOREAD(pdata, XP_PROP_1); + pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); + pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); + pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); + pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); + + /* Set the hardware channel and queue counts */ + axgbe_set_counts(pdata); + + /* Set the maximum fifo amounts */ + reg = XP_IOREAD(pdata, XP_PROP_2); + pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); + pdata->tx_max_fifo_size *= 16384; + pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, + pdata->vdata->tx_max_fifo_size); + pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); + pdata->rx_max_fifo_size *= 16384; + pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, + pdata->vdata->rx_max_fifo_size); + /* Issue software reset to DMA */ + ret = pdata->hw_if.exit(pdata); + if (ret) + PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error"); + + /* Set default configuration data */ + axgbe_default_config(pdata); + + /* Set default max values if not provided */ + if (!pdata->tx_max_fifo_size) + pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; + if (!pdata->rx_max_fifo_size) + pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; + + pthread_mutex_init(&pdata->xpcs_mutex, NULL); + pthread_mutex_init(&pdata->i2c_mutex, NULL); + pthread_mutex_init(&pdata->an_mutex, NULL); + pthread_mutex_init(&pdata->phy_mutex, NULL); + PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id); diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index 5f8931f..5d20a1f 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -132,6 +132,263 @@ #include #include "axgbe_common.h" +#define AXGBE_MAX_DMA_CHANNELS 16 +#define AXGBE_MAX_QUEUES 16 +#define AXGBE_PRIORITY_QUEUES 8 +#define AXGBE_DMA_STOP_TIMEOUT 1 + +/* DMA cache settings - Outer sharable, write-back, write-allocate */ +#define AXGBE_DMA_OS_AXDOMAIN 0x2 +#define AXGBE_DMA_OS_ARCACHE 0xb +#define AXGBE_DMA_OS_AWCACHE 0xf + +/* DMA cache settings - System, no caches used */ +#define AXGBE_DMA_SYS_AXDOMAIN 0x3 +#define AXGBE_DMA_SYS_ARCACHE 0x0 +#define AXGBE_DMA_SYS_AWCACHE 0x0 + +/* PCI BAR mapping */ +#define AXGBE_AXGMAC_BAR 0 +#define AXGBE_XPCS_BAR 1 +#define AXGBE_MAC_PROP_OFFSET 0x1d000 +#define AXGBE_I2C_CTRL_OFFSET 0x1e000 + +/* PCI clock frequencies */ +#define AXGBE_V2_DMA_CLOCK_FREQ 500000000 +#define AXGBE_V2_PTP_CLOCK_FREQ 125000000 + +#define AXGMAC_FIFO_MIN_ALLOC 2048 +#define AXGMAC_FIFO_UNIT 256 +#define AXGMAC_FIFO_ALIGN(_x) \ + (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) +#define AXGMAC_FIFO_FC_OFF 2048 +#define AXGMAC_FIFO_FC_MIN 4096 + +#define AXGBE_TC_MIN_QUANTUM 10 + +/* Flow control queue count */ +#define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8 + +/* Flow control threshold units */ +#define AXGMAC_FLOW_CONTROL_UNIT 512 +#define AXGMAC_FLOW_CONTROL_ALIGN(_x) \ + (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \ + ~(AXGMAC_FLOW_CONTROL_UNIT - 1)) +#define AXGMAC_FLOW_CONTROL_VALUE(_x) \ + (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2) +#define AXGMAC_FLOW_CONTROL_MAX 33280 + +/* Maximum MAC address hash table size (256 bits = 8 bytes) */ +#define AXGBE_MAC_HASH_TABLE_SIZE 8 + +/* Receive Side Scaling */ +#define AXGBE_RSS_OFFLOAD ( \ + ETH_RSS_IPV4 | \ + ETH_RSS_NONFRAG_IPV4_TCP | \ + ETH_RSS_NONFRAG_IPV4_UDP | \ + ETH_RSS_IPV6 | \ + ETH_RSS_NONFRAG_IPV6_TCP | \ + ETH_RSS_NONFRAG_IPV6_UDP) + +#define AXGBE_RSS_HASH_KEY_SIZE 40 +#define AXGBE_RSS_MAX_TABLE_SIZE 256 +#define AXGBE_RSS_LOOKUP_TABLE_TYPE 0 +#define AXGBE_RSS_HASH_KEY_TYPE 1 + +/* Auto-negotiation */ +#define AXGBE_AN_MS_TIMEOUT 500 +#define AXGBE_LINK_TIMEOUT 5 + +#define AXGBE_SGMII_AN_LINK_STATUS BIT(1) +#define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) +#define AXGBE_SGMII_AN_LINK_SPEED_100 0x04 +#define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08 +#define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4) + +/* ECC correctable error notification window (seconds) */ +#define AXGBE_ECC_LIMIT 60 + +/* MDIO port types */ +#define AXGMAC_MAX_C22_PORT 3 + +/* Helper macro for descriptor handling + * Always use AXGBE_GET_DESC_DATA to access the descriptor data + * since the index is free-running and needs to be and-ed + * with the descriptor count value of the ring to index to + * the proper descriptor data. + */ +#define AXGBE_GET_DESC_DATA(_ring, _idx) \ + ((_ring)->rdata + \ + ((_idx) & ((_ring)->rdesc_count - 1))) + +struct axgbe_port; + +enum axgbe_state { + AXGBE_DOWN, + AXGBE_LINK_INIT, + AXGBE_LINK_ERR, + AXGBE_STOPPED, +}; + +enum axgbe_int { + AXGMAC_INT_DMA_CH_SR_TI, + AXGMAC_INT_DMA_CH_SR_TPS, + AXGMAC_INT_DMA_CH_SR_TBU, + AXGMAC_INT_DMA_CH_SR_RI, + AXGMAC_INT_DMA_CH_SR_RBU, + AXGMAC_INT_DMA_CH_SR_RPS, + AXGMAC_INT_DMA_CH_SR_TI_RI, + AXGMAC_INT_DMA_CH_SR_FBE, + AXGMAC_INT_DMA_ALL, +}; + +enum axgbe_int_state { + AXGMAC_INT_STATE_SAVE, + AXGMAC_INT_STATE_RESTORE, +}; + +enum axgbe_ecc_sec { + AXGBE_ECC_SEC_TX, + AXGBE_ECC_SEC_RX, + AXGBE_ECC_SEC_DESC, +}; + +enum axgbe_speed { + AXGBE_SPEED_1000 = 0, + AXGBE_SPEED_2500, + AXGBE_SPEED_10000, + AXGBE_SPEEDS, +}; + +enum axgbe_xpcs_access { + AXGBE_XPCS_ACCESS_V1 = 0, + AXGBE_XPCS_ACCESS_V2, +}; + +enum axgbe_an_mode { + AXGBE_AN_MODE_CL73 = 0, + AXGBE_AN_MODE_CL73_REDRV, + AXGBE_AN_MODE_CL37, + AXGBE_AN_MODE_CL37_SGMII, + AXGBE_AN_MODE_NONE, +}; + +enum axgbe_an { + AXGBE_AN_READY = 0, + AXGBE_AN_PAGE_RECEIVED, + AXGBE_AN_INCOMPAT_LINK, + AXGBE_AN_COMPLETE, + AXGBE_AN_NO_LINK, + AXGBE_AN_ERROR, +}; + +enum axgbe_rx { + AXGBE_RX_BPA = 0, + AXGBE_RX_XNP, + AXGBE_RX_COMPLETE, + AXGBE_RX_ERROR, +}; + +enum axgbe_mode { + AXGBE_MODE_KX_1000 = 0, + AXGBE_MODE_KX_2500, + AXGBE_MODE_KR, + AXGBE_MODE_X, + AXGBE_MODE_SGMII_100, + AXGBE_MODE_SGMII_1000, + AXGBE_MODE_SFI, + AXGBE_MODE_UNKNOWN, +}; + +enum axgbe_speedset { + AXGBE_SPEEDSET_1000_10000 = 0, + AXGBE_SPEEDSET_2500_10000, +}; + +enum axgbe_mdio_mode { + AXGBE_MDIO_MODE_NONE = 0, + AXGBE_MDIO_MODE_CL22, + AXGBE_MDIO_MODE_CL45, +}; + +struct axgbe_hw_if { + void (*config_flow_control)(struct axgbe_port *); + int (*config_rx_mode)(struct axgbe_port *); + + int (*init)(struct axgbe_port *); + + int (*read_mmd_regs)(struct axgbe_port *, int, int); + void (*write_mmd_regs)(struct axgbe_port *, int, int, int); + int (*set_speed)(struct axgbe_port *, int); + + int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int, + enum axgbe_mdio_mode); + int (*read_ext_mii_regs)(struct axgbe_port *, int, int); + int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t); + + /* For FLOW ctrl */ + int (*config_tx_flow_control)(struct axgbe_port *); + int (*config_rx_flow_control)(struct axgbe_port *); + + int (*exit)(struct axgbe_port *); +}; + +/* This structure contains flags that indicate what hardware features + * or configurations are present in the device. + */ +struct axgbe_hw_features { + /* HW Version */ + unsigned int version; + + /* HW Feature Register0 */ + unsigned int gmii; /* 1000 Mbps support */ + unsigned int vlhash; /* VLAN Hash Filter */ + unsigned int sma; /* SMA(MDIO) Interface */ + unsigned int rwk; /* PMT remote wake-up packet */ + unsigned int mgk; /* PMT magic packet */ + unsigned int mmc; /* RMON module */ + unsigned int aoe; /* ARP Offload */ + unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ + unsigned int eee; /* Energy Efficient Ethernet */ + unsigned int tx_coe; /* Tx Checksum Offload */ + unsigned int rx_coe; /* Rx Checksum Offload */ + unsigned int addn_mac; /* Additional MAC Addresses */ + unsigned int ts_src; /* Timestamp Source */ + unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ + + /* HW Feature Register1 */ + unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ + unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ + unsigned int adv_ts_hi; /* Advance Timestamping High Word */ + unsigned int dma_width; /* DMA width */ + unsigned int dcb; /* DCB Feature */ + unsigned int sph; /* Split Header Feature */ + unsigned int tso; /* TCP Segmentation Offload */ + unsigned int dma_debug; /* DMA Debug Registers */ + unsigned int rss; /* Receive Side Scaling */ + unsigned int tc_cnt; /* Number of Traffic Classes */ + unsigned int hash_table_size; /* Hash Table Size */ + unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ + + /* HW Feature Register2 */ + unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ + unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ + unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ + unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ + unsigned int pps_out_num; /* Number of PPS outputs */ + unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ +}; + +struct axgbe_version_data { + enum axgbe_xpcs_access xpcs_access; + unsigned int mmc_64bit; + unsigned int tx_max_fifo_size; + unsigned int rx_max_fifo_size; + unsigned int tx_tstamp_workaround; + unsigned int ecc_support; + unsigned int i2c_support; +}; + /* * Structure to store private data for each port. */ @@ -140,6 +397,98 @@ struct axgbe_port { struct rte_eth_dev *eth_dev; /* Pci dev info */ const struct rte_pci_device *pci_dev; + /* Version related data */ + struct axgbe_version_data *vdata; + + /* AXGMAC/XPCS related mmio registers */ + uint64_t xgmac_regs; /* AXGMAC CSRs */ + uint64_t xpcs_regs; /* XPCS MMD registers */ + uint64_t xprop_regs; /* AXGBE property registers */ + uint64_t xi2c_regs; /* AXGBE I2C CSRs */ + + /* XPCS indirect addressing lock */ + unsigned int xpcs_window_def_reg; + unsigned int xpcs_window_sel_reg; + unsigned int xpcs_window; + unsigned int xpcs_window_size; + unsigned int xpcs_window_mask; + + /* Flags representing axgbe_state */ + unsigned long dev_state; + + struct axgbe_hw_if hw_if; + + /* AXI DMA settings */ + unsigned int coherent; + unsigned int axdomain; + unsigned int arcache; + unsigned int awcache; + + unsigned int tx_max_channel_count; + unsigned int rx_max_channel_count; + unsigned int channel_count; + unsigned int tx_ring_count; + unsigned int tx_desc_count; + unsigned int rx_ring_count; + unsigned int rx_desc_count; + + unsigned int tx_max_q_count; + unsigned int rx_max_q_count; + unsigned int tx_q_count; + unsigned int rx_q_count; + + /* Tx/Rx common settings */ + unsigned int pblx8; + + /* Tx settings */ + unsigned int tx_sf_mode; + unsigned int tx_threshold; + unsigned int tx_pbl; + unsigned int tx_osp_mode; + unsigned int tx_max_fifo_size; + + /* Rx settings */ + unsigned int rx_sf_mode; + unsigned int rx_threshold; + unsigned int rx_pbl; + unsigned int rx_max_fifo_size; + unsigned int rx_buf_size; + + /* Device clocks */ + unsigned long sysclk_rate; + unsigned long ptpclk_rate; + + /* Keeps track of power mode */ + unsigned int power_down; + + /* Current PHY settings */ + int phy_link; + int phy_speed; + + pthread_mutex_t xpcs_mutex; + pthread_mutex_t i2c_mutex; + pthread_mutex_t an_mutex; + pthread_mutex_t phy_mutex; + + /* Flow control settings */ + unsigned int pause_autoneg; + unsigned int tx_pause; + unsigned int rx_pause; + unsigned int rx_rfa[AXGBE_MAX_QUEUES]; + unsigned int rx_rfd[AXGBE_MAX_QUEUES]; + unsigned int fifo; + + /* Receive Side Scaling settings */ + u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE]; + uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE]; + uint32_t rss_options; + int rss_enable; + + /* Hardware features of the device */ + struct axgbe_hw_features hw_feat; + + struct ether_addr mac_addr; }; +void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); #endif /* RTE_ETH_AXGBE_H_ */ -- 2.7.4