From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id C26BA2A58 for ; Fri, 1 Dec 2017 12:13:02 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Dec 2017 03:13:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,344,1508828400"; d="scan'208";a="8363014" Received: from sivswdev02.ir.intel.com (HELO localhost.localdomain) ([10.237.217.46]) by orsmga003.jf.intel.com with ESMTP; 01 Dec 2017 03:13:01 -0800 From: Konstantin Ananyev To: dev@dpdk.org Cc: Konstantin Ananyev Date: Fri, 1 Dec 2017 11:12:51 +0000 Message-Id: <1512126771-27503-2-git-send-email-konstantin.ananyev@intel.com> X-Mailer: git-send-email 1.7.0.7 In-Reply-To: <1512126771-27503-1-git-send-email-konstantin.ananyev@intel.com> References: <1512126771-27503-1-git-send-email-konstantin.ananyev@intel.com> To: dev@dpdk.org Subject: [dpdk-dev] [PATCH 2/2] eal/x86: Use lock-prefixed instructions to reduce cost of rte_smp_mb() X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Dec 2017 11:13:03 -0000 On x86 it is possible to use lock-prefixed instructions to get the similar effect as mfence. As pointed by Java guys, on most modern HW that gives a better performance than using mfence: https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ That patch adopts that technique for rte_smp_mb() implementation. On BDW 2.2 mb_autotest on single lcore reports 2X cycle reduction, i.e. from ~110 to ~55 cycles per operation. Signed-off-by: Konstantin Ananyev --- .../common/include/arch/x86/rte_atomic.h | 45 +++++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic.h b/lib/librte_eal/common/include/arch/x86/rte_atomic.h index 4eac66631..07b7fa7f7 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic.h @@ -55,12 +55,53 @@ extern "C" { #define rte_rmb() _mm_lfence() -#define rte_smp_mb() rte_mb() - #define rte_smp_wmb() rte_compiler_barrier() #define rte_smp_rmb() rte_compiler_barrier() +/* + * From Intel Software Development Manual; Vol 3; + * 8.2.2 Memory Ordering in P6 and More Recent Processor Families: + * ... + * . Reads are not reordered with other reads. + * . Writes are not reordered with older reads. + * . Writes to memory are not reordered with other writes, + * with the following exceptions: + * . streaming stores (writes) executed with the non-temporal move + * instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD); and + * . string operations (see Section 8.2.4.1). + * ... + * . Reads may be reordered with older writes to different locations but not + * with older writes to the same location. + * . Reads or writes cannot be reordered with I/O instructions, + * locked instructions, or serializing instructions. + * . Reads cannot pass earlier LFENCE and MFENCE instructions. + * . Writes ... cannot pass earlier LFENCE, SFENCE, and MFENCE instructions. + * . LFENCE instructions cannot pass earlier reads. + * . SFENCE instructions cannot pass earlier writes ... + * . MFENCE instructions cannot pass earlier reads, writes ... + * + * As pointed by Java guys, that makes possible to use lock-prefixed + * instructions to get the same effect as mfence and on most modern HW + * that gives a better perfomarnce than using mfence: + * https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ + * So below we use that technique for rte_smp_mb() implementation. + */ + +#ifdef RTE_ARCH_I686 +#define RTE_SP RTE_STR(esp) +#else +#define RTE_SP RTE_STR(rsp) +#endif + +#define RTE_MB_DUMMY_MEMP "-128(%%" RTE_SP ")" + +static __rte_always_inline void +rte_smp_mb(void) +{ + asm volatile("lock addl $0," RTE_MB_DUMMY_MEMP "; " ::: "memory"); +} + #define rte_io_mb() rte_mb() #define rte_io_wmb() rte_compiler_barrier() -- 2.13.5