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BN6PR12MB1508; 20:rrw12mrZbvTRh6L7A1phbSXErWLsxSUudFajgbs60XqdIuXc1WioS7wm78sV1iNNYSAaE7kkKL1IFA2znR43HEinwm3Er0PN+u+jRLtf1GQxr7b4pQ39cFbhk6jn5aY33s+pmbb4IiwZnHT7zSOW9JBwb83ZTEAuMdqngmD1ycnE+2BhyjH6SS4sIZ08D8z6WuSTJqpHXlO/2z2iY55rVnrwpN+hI5RtJeYlzg9Z++4MElLZrNeYZylyXo7mKXA0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2018 09:40:35.6855 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 394495f4-9656-45d2-f04b-08d554205fd1 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1508 Subject: [dpdk-dev] [PATCH v2 09/20] crypto/ccp: add ccp hwrng feature support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Jan 2018 09:40:38 -0000 Signed-off-by: Ravi Kumar --- drivers/crypto/ccp/ccp_dev.c | 20 ++++++++++++++++++++ drivers/crypto/ccp/ccp_dev.h | 11 +++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/crypto/ccp/ccp_dev.c b/drivers/crypto/ccp/ccp_dev.c index fee90e3..d8c0ab4 100644 --- a/drivers/crypto/ccp/ccp_dev.c +++ b/drivers/crypto/ccp/ccp_dev.c @@ -88,6 +88,26 @@ ccp_allot_queue(struct rte_cryptodev *cdev, int slot_req) return NULL; } +int +ccp_read_hwrng(uint32_t *value) +{ + struct ccp_device *dev; + + TAILQ_FOREACH(dev, &ccp_list, next) { + void *vaddr = (void *)(dev->pci.mem_resource[2].addr); + + while (dev->hwrng_retries++ < CCP_MAX_TRNG_RETRIES) { + *value = CCP_READ_REG(vaddr, TRNG_OUT_REG); + if (*value) { + dev->hwrng_retries = 0; + return 0; + } + } + dev->hwrng_retries = 0; + } + return -1; +} + static const struct rte_memzone * ccp_queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size, diff --git a/drivers/crypto/ccp/ccp_dev.h b/drivers/crypto/ccp/ccp_dev.h index cfb3b03..a5c9ef3 100644 --- a/drivers/crypto/ccp/ccp_dev.h +++ b/drivers/crypto/ccp/ccp_dev.h @@ -47,6 +47,7 @@ /**< CCP sspecific */ #define MAX_HW_QUEUES 5 +#define CCP_MAX_TRNG_RETRIES 10 /**< CCP Register Mappings */ #define Q_MASK_REG 0x000 @@ -223,6 +224,8 @@ struct ccp_device { /**< protection for shared lsb region allocation */ int qidx; /**< current queue index */ + int hwrng_retries; + /**< retry counter for CCP TRNG */ } __rte_cache_aligned; /**< CCP H/W engine related */ @@ -454,4 +457,12 @@ int ccp_probe_devices(const struct rte_pci_id *ccp_id); */ struct ccp_queue *ccp_allot_queue(struct rte_cryptodev *dev, int slot_req); +/** + * read hwrng value + * + * @param trng_value data pointer to write RNG value + * @return 0 on success otherwise -1 + */ +int ccp_read_hwrng(uint32_t *trng_value); + #endif /* _CCP_DEV_H_ */ -- 2.7.4