From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id DC3AA1B1EE for ; Tue, 9 Jan 2018 21:25:22 +0100 (CET) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id CF552800059; Tue, 9 Jan 2018 20:25:21 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 9 Jan 2018 12:25:17 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Tue, 9 Jan 2018 12:25:17 -0800 Received: from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com [10.17.10.10]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id w09KPFXo014178; Tue, 9 Jan 2018 20:25:15 GMT Received: from uklogin.uk.solarflarecom.com (localhost.localdomain [127.0.0.1]) by uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id w09KPF7A016277; Tue, 9 Jan 2018 20:25:15 GMT From: Andrew Rybchenko To: CC: Ferruh Yigit Date: Tue, 9 Jan 2018 20:24:54 +0000 Message-ID: <1515529495-16157-6-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <1515529495-16157-1-git-send-email-arybchenko@solarflare.com> References: <1514273271-19604-1-git-send-email-arybchenko@solarflare.com> <1515529495-16157-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 Content-Type: text/plain X-MDID: 1515529522-hNBnUqVRzlDU Subject: [dpdk-dev] [PATCH v2 5/6] net/sfc: support more options for a number of Rx descriptors X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Jan 2018 20:25:23 -0000 The number of Rx descriptors is not used as HW Rx ring size any more. It simply defines maximum fill level. Signed-off-by: Andrew Rybchenko Reviewed-by: Andy Moreton --- drivers/net/sfc/sfc_dp_rx.h | 8 ++++++++ drivers/net/sfc/sfc_ef10_rx.c | 30 +++++++++++++++++++++++++++--- drivers/net/sfc/sfc_ethdev.c | 4 ++++ drivers/net/sfc/sfc_rx.c | 4 ++++ 4 files changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/net/sfc/sfc_dp_rx.h b/drivers/net/sfc/sfc_dp_rx.h index 029ebaf..b817f34 100644 --- a/drivers/net/sfc/sfc_dp_rx.h +++ b/drivers/net/sfc/sfc_dp_rx.h @@ -103,6 +103,13 @@ struct sfc_dp_rx_qcreate_info { }; /** + * Get Rx datapath specific device info. + * + * @param dev_info Device info to be adjusted + */ +typedef void (sfc_dp_rx_get_dev_info_t)(struct rte_eth_dev_info *dev_info); + +/** * Get size of receive and event queue rings by the number of Rx * descriptors. * @@ -186,6 +193,7 @@ struct sfc_dp_rx { #define SFC_DP_RX_FEAT_SCATTER 0x1 #define SFC_DP_RX_FEAT_MULTI_PROCESS 0x2 #define SFC_DP_RX_FEAT_TUNNELS 0x4 + sfc_dp_rx_get_dev_info_t *get_dev_info; sfc_dp_rx_qsize_up_rings_t *qsize_up_rings; sfc_dp_rx_qcreate_t *qcreate; sfc_dp_rx_qdestroy_t *qdestroy; diff --git a/drivers/net/sfc/sfc_ef10_rx.c b/drivers/net/sfc/sfc_ef10_rx.c index ad84629..b651bd7 100644 --- a/drivers/net/sfc/sfc_ef10_rx.c +++ b/drivers/net/sfc/sfc_ef10_rx.c @@ -638,6 +638,19 @@ sfc_ef10_rx_qdesc_status(__rte_unused struct sfc_dp_rxq *dp_rxq, } +static sfc_dp_rx_get_dev_info_t sfc_ef10_rx_get_dev_info; +static void +sfc_ef10_rx_get_dev_info(struct rte_eth_dev_info *dev_info) +{ + /* + * Number of descriptors just defines maximum number of pushed + * descriptors (fill level). + */ + dev_info->rx_desc_lim.nb_min = SFC_RX_REFILL_BULK; + dev_info->rx_desc_lim.nb_align = SFC_RX_REFILL_BULK; +} + + static sfc_dp_rx_qsize_up_rings_t sfc_ef10_rx_qsize_up_rings; static int sfc_ef10_rx_qsize_up_rings(uint16_t nb_rx_desc, @@ -645,9 +658,19 @@ sfc_ef10_rx_qsize_up_rings(uint16_t nb_rx_desc, unsigned int *evq_entries, unsigned int *rxq_max_fill_level) { - *rxq_entries = nb_rx_desc; - *evq_entries = nb_rx_desc; - *rxq_max_fill_level = SFC_EF10_RXQ_LIMIT(*rxq_entries); + /* + * rte_ethdev API guarantees that the number meets min, max and + * alignment requirements. + */ + if (nb_rx_desc <= EFX_RXQ_MINNDESCS) + *rxq_entries = EFX_RXQ_MINNDESCS; + else + *rxq_entries = rte_align32pow2(nb_rx_desc); + + *evq_entries = *rxq_entries; + + *rxq_max_fill_level = RTE_MIN(nb_rx_desc, + SFC_EF10_RXQ_LIMIT(*evq_entries)); return 0; } @@ -809,6 +832,7 @@ struct sfc_dp_rx sfc_ef10_rx = { }, .features = SFC_DP_RX_FEAT_MULTI_PROCESS | SFC_DP_RX_FEAT_TUNNELS, + .get_dev_info = sfc_ef10_rx_get_dev_info, .qsize_up_rings = sfc_ef10_rx_qsize_up_rings, .qcreate = sfc_ef10_rx_qcreate, .qdestroy = sfc_ef10_rx_qdestroy, diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c index 1b700b1..fec91c3 100644 --- a/drivers/net/sfc/sfc_ethdev.c +++ b/drivers/net/sfc/sfc_ethdev.c @@ -170,6 +170,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) if (sa->tso) dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO; + /* Initialize to hardware limits */ dev_info->rx_desc_lim.nb_max = EFX_RXQ_MAXNDESCS; dev_info->rx_desc_lim.nb_min = EFX_RXQ_MINNDESCS; /* The RXQ hardware requires that the descriptor count is a power @@ -184,6 +185,9 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) * of 2, but tx_desc_lim cannot properly describe that constraint */ dev_info->tx_desc_lim.nb_align = EFX_TXQ_MINNDESCS; + + if (sa->dp_rx->get_dev_info != NULL) + sa->dp_rx->get_dev_info(dev_info); } static const uint32_t * diff --git a/drivers/net/sfc/sfc_rx.c b/drivers/net/sfc/sfc_rx.c index 387f855..b355ea3 100644 --- a/drivers/net/sfc/sfc_rx.c +++ b/drivers/net/sfc/sfc_rx.c @@ -933,6 +933,10 @@ sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index, &rxq_max_fill_level); if (rc != 0) goto fail_size_up_rings; + SFC_ASSERT(rxq_entries >= EFX_RXQ_MINNDESCS); + SFC_ASSERT(rxq_entries <= EFX_RXQ_MAXNDESCS); + SFC_ASSERT(rxq_entries >= nb_rx_desc); + SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc); rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf); if (rc != 0) -- 2.7.4