[dpdk-dev] [PATCH v2 0/2] Fix parameters and prefetch function on IBM POWER8

[dpdk-dev] [PATCH v2 0/2] Fix parameters and prefetch function on IBM POWER8

[Chao Zhu]

This patch set fixes CPU/memory parameters and correct wrong prefetch settings for IBM POWER8.
Changes in v2:
1. Move the parameter configuration to POWER specific configuration file
2. Remove the memeory channel number constraint instead of adding additional configuration flag.

Chao Zhu (2):
  Fix CPU and memory parameters on IBM POWER8
  Fix prefetch instruction on IBM POWER8

 config/defconfig_ppc_64-power8-linuxapp-gcc        |    2 ++
 lib/librte_eal/common/eal_common_options.c         |    3 +--
 .../common/include/arch/ppc_64/rte_prefetch.h      |    6 +++---
 3 files changed, 6 insertions(+), 5 deletions(-)

[dpdk-dev] [PATCH v2 1/2] Fix CPU and memory parameters on IBM POWER8

[Chao Zhu]

This patch fixes the max logic number and memory channel number settings
on IBM POWER8 platform.
1. The max number of logic cores of a POWER8 processor is 96. Normally,
   there are two sockets on a server. So the max number of logic cores
   are 192. So this parch set CONFIG_RTE_MAX_LCORE to 256.
2. The socket number on POWER8 little endian platform can be larger than 16.
   This patch set CONFIG_RTE_MAX_NUMA_NODES to 32 for POWER8.
3. Currently, the max number of memory channels are hardcoded to 4. However,
   on a POWER8 machine, the max number of memory channels are 8. This patch
   removes the constraint.

Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
---
 config/defconfig_ppc_64-power8-linuxapp-gcc |    2 ++
 lib/librte_eal/common/eal_common_options.c  |    3 +--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc
index a80a19e..9eb0cc4 100644
--- a/config/defconfig_ppc_64-power8-linuxapp-gcc
+++ b/config/defconfig_ppc_64-power8-linuxapp-gcc
@@ -36,6 +36,8 @@ CONFIG_RTE_ARCH="ppc_64"
 CONFIG_RTE_ARCH_PPC_64=y
 CONFIG_RTE_ARCH_64=y
 
+CONFIG_RTE_MAX_LCORE=256
+CONFIG_RTE_MAX_NUMA_NODES=32
 CONFIG_RTE_CACHE_LINE_SIZE=128
 
 CONFIG_RTE_TOOLCHAIN="gcc"
diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c
index 29942ea..2b418d5 100644
--- a/lib/librte_eal/common/eal_common_options.c
+++ b/lib/librte_eal/common/eal_common_options.c
@@ -797,8 +797,7 @@ eal_parse_common_option(int opt, const char *optarg,
 	/* force number of channels */
 	case 'n':
 		conf->force_nchannel = atoi(optarg);
-		if (conf->force_nchannel == 0 ||
-		    conf->force_nchannel > 4) {
+		if (conf->force_nchannel == 0) {
 			RTE_LOG(ERR, EAL, "invalid channel number\n");
 			return -1;
 		}
-- 
1.7.1

[dpdk-dev] [PATCH v2 2/2] Fix prefetch instruction on IBM POWER8

[Chao Zhu]

Current prefetch instruction (dcbt) implementation for IBM POWER8 has wrong
Touch Hint(TH) parameter. The current setting of TH=1 indicates to load data from
current cache line and an unlimited number of sequentially following cache lines.
TTH=0 means to load data from current cache line. rte_prefetch0 function is defined
to load one cache line, which means TH=0 is suited here.

Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
---
 .../common/include/arch/ppc_64/rte_prefetch.h      |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h b/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h
index bcc7185..9a1995e 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h
@@ -41,17 +41,17 @@ extern "C" {
 
 static inline void rte_prefetch0(const volatile void *p)
 {
-	asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+	asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p));
 }
 
 static inline void rte_prefetch1(const volatile void *p)
 {
-	asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+	asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p));
 }
 
 static inline void rte_prefetch2(const volatile void *p)
 {
-	asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
+	asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p));
 }
 
 static inline void rte_prefetch_non_temporal(const volatile void *p)
-- 
1.7.1

Re: [dpdk-dev] [PATCH v2 0/2] Fix parameters and prefetch function on IBM POWER8

[Thomas Monjalon]

2016-03-30 23:39, Chao Zhu:
> This patch set fixes CPU/memory parameters and correct wrong prefetch settings for IBM POWER8.
> Changes in v2:
> 1. Move the parameter configuration to POWER specific configuration file
> 2. Remove the memeory channel number constraint instead of adding additional configuration flag.
> 
> Chao Zhu (2):
>   Fix CPU and memory parameters on IBM POWER8
>   Fix prefetch instruction on IBM POWER8

Applied, thanks