From: Andrew Rybchenko <arybchenko@solarflare.com>
To: <dev@dpdk.org>
Cc: Andy Moreton <amoreton@solarflare.com>
Subject: [dpdk-dev] [PATCH 26/80] net/sfc/base: update hardware headers for Medford2
Date: Tue, 20 Feb 2018 07:33:44 +0000 [thread overview]
Message-ID: <1519112078-20113-27-git-send-email-arybchenko@solarflare.com> (raw)
In-Reply-To: <1519112078-20113-1-git-send-email-arybchenko@solarflare.com>
From: Andy Moreton <amoreton@solarflare.com>
The changes to efx_regs_ef10.h are auto-generated and include:
- Updated event RX_L4_CLASS which is now 2 bits (was 3).
The encoding of TCP, UDP and UNKNOWN are unchanged so
the narrower Medford2 field definition is compatible with
all controllers.
- Fix definition of FATSOv2 option descriptors. These were
added manually and differ from the auto-generated values
in some fields (not yet used in common code). The field
definitions have been corrected to agree with the Linux net
driver headers and SF-108452-SW.
The remaining changes adapt the common code to use the updated
headers.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_ev.c | 47 +++++++-
drivers/net/sfc/base/efx_regs_ef10.h | 207 ++++++++++++++++++++++++++++++-----
drivers/net/sfc/sfc_ef10_rx.c | 18 ++-
3 files changed, 237 insertions(+), 35 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_ev.c b/drivers/net/sfc/base/ef10_ev.c
index 36ff2cb..c7173c3 100644
--- a/drivers/net/sfc/base/ef10_ev.c
+++ b/drivers/net/sfc/base/ef10_ev.c
@@ -868,12 +868,23 @@ ef10_ev_rx(
#endif
size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
+ cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
- l4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS);
- cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
+
+ /*
+ * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
+ * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
+ * and values for all EF10 controllers.
+ */
+ EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
+ EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
+ EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
+ EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
+
+ l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
/* Drop this event */
@@ -952,10 +963,22 @@ ef10_ev_rx(
flags |= EFX_CKSUM_IPV4;
}
- if (l4_class == ESE_DZ_L4_CLASS_TCP) {
+ /*
+ * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
+ * only 2 bits wide on Medford2. Check it is safe to use the
+ * Medford2 field and values for all EF10 controllers.
+ */
+ EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
+ ESF_DE_RX_L4_CLASS_LBN);
+ EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
+ EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
+ EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
+ ESE_DE_L4_CLASS_UNKNOWN);
+
+ if (l4_class == ESE_FZ_L4_CLASS_TCP) {
EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
flags |= EFX_PKT_TCP;
- } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
+ } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
flags |= EFX_PKT_UDP;
} else {
@@ -967,10 +990,22 @@ ef10_ev_rx(
case ESE_DZ_L3_CLASS_IP6_FRAG:
flags |= EFX_PKT_IPV6;
- if (l4_class == ESE_DZ_L4_CLASS_TCP) {
+ /*
+ * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
+ * only 2 bits wide on Medford2. Check it is safe to use the
+ * Medford2 field and values for all EF10 controllers.
+ */
+ EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
+ ESF_DE_RX_L4_CLASS_LBN);
+ EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
+ EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
+ EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
+ ESE_DE_L4_CLASS_UNKNOWN);
+
+ if (l4_class == ESE_FZ_L4_CLASS_TCP) {
EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
flags |= EFX_PKT_TCP;
- } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
+ } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
flags |= EFX_PKT_UDP;
} else {
diff --git a/drivers/net/sfc/base/efx_regs_ef10.h b/drivers/net/sfc/base/efx_regs_ef10.h
index 5f97830..025dc08 100644
--- a/drivers/net/sfc/base/efx_regs_ef10.h
+++ b/drivers/net/sfc/base/efx_regs_ef10.h
@@ -24,7 +24,7 @@ extern "C" {
*/
#define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000
-/* hunta0,medforda0=pcie_pf_bar2 */
+/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face
@@ -38,7 +38,7 @@ extern "C" {
*/
#define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010
-/* hunta0,medforda0=pcie_pf_bar2 */
+/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4
#define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8
#define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face
@@ -54,7 +54,7 @@ extern "C" {
*/
#define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090
-/* hunta0,medforda0=pcie_pf_bar2 */
+/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_BIU_INT_ISR_REG_RESET 0x0
@@ -68,7 +68,7 @@ extern "C" {
*/
#define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200
-/* hunta0,medforda0=pcie_pf_bar2 */
+/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_MC_DB_LWRD_REG_RESET 0x0
@@ -82,7 +82,7 @@ extern "C" {
*/
#define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204
-/* hunta0,medforda0=pcie_pf_bar2 */
+/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_MC_DB_HWRD_REG_RESET 0x0
@@ -96,7 +96,7 @@ extern "C" {
*/
#define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400
-/* hunta0,medforda0=pcie_pf_bar2 */
+/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_EVQ_RPTR_REG_STEP 8192
#define ER_DZ_EVQ_RPTR_REG_ROWS 2048
#define ER_DZ_EVQ_RPTR_REG_RESET 0x0
@@ -109,12 +109,84 @@ extern "C" {
/*
+ * EVQ_RPTR_REG_64K(32bit):
+ *
+ */
+
+#define ER_FZ_EVQ_RPTR_REG_64K_OFST 0x00000400
+/* medford2a0=pf_dbell_bar */
+#define ER_FZ_EVQ_RPTR_REG_64K_STEP 65536
+#define ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048
+#define ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0
+
+
+#define ERF_FZ_EVQ_RPTR_VLD_LBN 15
+#define ERF_FZ_EVQ_RPTR_VLD_WIDTH 1
+#define ERF_FZ_EVQ_RPTR_LBN 0
+#define ERF_FZ_EVQ_RPTR_WIDTH 15
+
+
+/*
+ * EVQ_RPTR_REG_16K(32bit):
+ *
+ */
+
+#define ER_FZ_EVQ_RPTR_REG_16K_OFST 0x00000400
+/* medford2a0=pf_dbell_bar */
+#define ER_FZ_EVQ_RPTR_REG_16K_STEP 16384
+#define ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048
+#define ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0
+
+
+/* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */
+/* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */
+/* defined as ERF_FZ_EVQ_RPTR_LBN 0; */
+/* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */
+
+
+/*
+ * EVQ_TMR_REG_64K(32bit):
+ *
+ */
+
+#define ER_FZ_EVQ_TMR_REG_64K_OFST 0x00000420
+/* medford2a0=pf_dbell_bar */
+#define ER_FZ_EVQ_TMR_REG_64K_STEP 65536
+#define ER_FZ_EVQ_TMR_REG_64K_ROWS 2048
+#define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0
+
+
+#define ERF_FZ_TC_TIMER_MODE_LBN 14
+#define ERF_FZ_TC_TIMER_MODE_WIDTH 2
+#define ERF_FZ_TC_TIMER_VAL_LBN 0
+#define ERF_FZ_TC_TIMER_VAL_WIDTH 14
+
+
+/*
+ * EVQ_TMR_REG_16K(32bit):
+ *
+ */
+
+#define ER_FZ_EVQ_TMR_REG_16K_OFST 0x00000420
+/* medford2a0=pf_dbell_bar */
+#define ER_FZ_EVQ_TMR_REG_16K_STEP 16384
+#define ER_FZ_EVQ_TMR_REG_16K_ROWS 2048
+#define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0
+
+
+/* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */
+/* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */
+/* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */
+/* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */
+
+
+/*
* EVQ_TMR_REG(32bit):
*
*/
#define ER_DZ_EVQ_TMR_REG_OFST 0x00000420
-/* hunta0,medforda0=pcie_pf_bar2 */
+/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_EVQ_TMR_REG_STEP 8192
#define ER_DZ_EVQ_TMR_REG_ROWS 2048
#define ER_DZ_EVQ_TMR_REG_RESET 0x0
@@ -127,12 +199,28 @@ extern "C" {
/*
+ * RX_DESC_UPD_REG_16K(32bit):
+ *
+ */
+
+#define ER_FZ_RX_DESC_UPD_REG_16K_OFST 0x00000830
+/* medford2a0=pf_dbell_bar */
+#define ER_FZ_RX_DESC_UPD_REG_16K_STEP 16384
+#define ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048
+#define ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0
+
+
+#define ERF_FZ_RX_DESC_WPTR_LBN 0
+#define ERF_FZ_RX_DESC_WPTR_WIDTH 12
+
+
+/*
* RX_DESC_UPD_REG(32bit):
*
*/
#define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830
-/* hunta0,medforda0=pcie_pf_bar2 */
+/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_RX_DESC_UPD_REG_STEP 8192
#define ER_DZ_RX_DESC_UPD_REG_ROWS 2048
#define ER_DZ_RX_DESC_UPD_REG_RESET 0x0
@@ -141,13 +229,74 @@ extern "C" {
#define ERF_DZ_RX_DESC_WPTR_LBN 0
#define ERF_DZ_RX_DESC_WPTR_WIDTH 12
+
+/*
+ * RX_DESC_UPD_REG_64K(32bit):
+ *
+ */
+
+#define ER_FZ_RX_DESC_UPD_REG_64K_OFST 0x00000830
+/* medford2a0=pf_dbell_bar */
+#define ER_FZ_RX_DESC_UPD_REG_64K_STEP 65536
+#define ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048
+#define ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0
+
+
+/* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */
+/* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */
+
+
+/*
+ * TX_DESC_UPD_REG_64K(96bit):
+ *
+ */
+
+#define ER_FZ_TX_DESC_UPD_REG_64K_OFST 0x00000a10
+/* medford2a0=pf_dbell_bar */
+#define ER_FZ_TX_DESC_UPD_REG_64K_STEP 65536
+#define ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048
+#define ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0
+
+
+#define ERF_FZ_RSVD_LBN 76
+#define ERF_FZ_RSVD_WIDTH 20
+#define ERF_FZ_TX_DESC_WPTR_LBN 64
+#define ERF_FZ_TX_DESC_WPTR_WIDTH 12
+#define ERF_FZ_TX_DESC_HWORD_LBN 32
+#define ERF_FZ_TX_DESC_HWORD_WIDTH 32
+#define ERF_FZ_TX_DESC_LWORD_LBN 0
+#define ERF_FZ_TX_DESC_LWORD_WIDTH 32
+
+
+/*
+ * TX_DESC_UPD_REG_16K(96bit):
+ *
+ */
+
+#define ER_FZ_TX_DESC_UPD_REG_16K_OFST 0x00000a10
+/* medford2a0=pf_dbell_bar */
+#define ER_FZ_TX_DESC_UPD_REG_16K_STEP 16384
+#define ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048
+#define ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0
+
+
+/* defined as ERF_FZ_RSVD_LBN 76; */
+/* defined as ERF_FZ_RSVD_WIDTH 20 */
+/* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */
+/* defined as ERF_FZ_TX_DESC_WPTR_WIDTH 12 */
+/* defined as ERF_FZ_TX_DESC_HWORD_LBN 32; */
+/* defined as ERF_FZ_TX_DESC_HWORD_WIDTH 32 */
+/* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */
+/* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */
+
+
/*
* TX_DESC_UPD_REG(96bit):
*
*/
#define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10
-/* hunta0,medforda0=pcie_pf_bar2 */
+/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_TX_DESC_UPD_REG_STEP 8192
#define ER_DZ_TX_DESC_UPD_REG_ROWS 2048
#define ER_DZ_TX_DESC_UPD_REG_RESET 0x0
@@ -233,16 +382,24 @@ extern "C" {
#define ESF_DZ_RX_EV_SOFT2_WIDTH 2
#define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
#define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
-#define ESF_DZ_RX_L4_CLASS_LBN 45
-#define ESF_DZ_RX_L4_CLASS_WIDTH 3
-#define ESE_DZ_L4_CLASS_RSVD7 7
-#define ESE_DZ_L4_CLASS_RSVD6 6
-#define ESE_DZ_L4_CLASS_RSVD5 5
-#define ESE_DZ_L4_CLASS_RSVD4 4
-#define ESE_DZ_L4_CLASS_RSVD3 3
-#define ESE_DZ_L4_CLASS_UDP 2
-#define ESE_DZ_L4_CLASS_TCP 1
-#define ESE_DZ_L4_CLASS_UNKNOWN 0
+#define ESF_DE_RX_L4_CLASS_LBN 45
+#define ESF_DE_RX_L4_CLASS_WIDTH 3
+#define ESE_DE_L4_CLASS_RSVD7 7
+#define ESE_DE_L4_CLASS_RSVD6 6
+#define ESE_DE_L4_CLASS_RSVD5 5
+#define ESE_DE_L4_CLASS_RSVD4 4
+#define ESE_DE_L4_CLASS_RSVD3 3
+#define ESE_DE_L4_CLASS_UDP 2
+#define ESE_DE_L4_CLASS_TCP 1
+#define ESE_DE_L4_CLASS_UNKNOWN 0
+#define ESF_FZ_RX_FASTPD_INDCTR_LBN 47
+#define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1
+#define ESF_FZ_RX_L4_CLASS_LBN 45
+#define ESF_FZ_RX_L4_CLASS_WIDTH 2
+#define ESE_FZ_L4_CLASS_RSVD3 3
+#define ESE_FZ_L4_CLASS_UDP 2
+#define ESE_FZ_L4_CLASS_TCP 1
+#define ESE_FZ_L4_CLASS_UNKNOWN 0
#define ESF_DZ_RX_L3_CLASS_LBN 42
#define ESF_DZ_RX_L3_CLASS_WIDTH 3
#define ESE_DZ_L3_CLASS_RSVD7 7
@@ -419,6 +576,8 @@ extern "C" {
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
+#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
+#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
#define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
@@ -429,7 +588,7 @@ extern "C" {
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
-/* TX_TSO_FATSO2A_DESC */
+/* ES_TX_TSO_V2_DESC_A */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
#define ESF_DZ_TX_OPTION_TYPE_LBN 60
@@ -449,7 +608,7 @@ extern "C" {
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
-/* TX_TSO_FATSO2B_DESC */
+/* ES_TX_TSO_V2_DESC_B */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
#define ESF_DZ_TX_OPTION_TYPE_LBN 60
@@ -463,12 +622,10 @@ extern "C" {
#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
-#define ESF_DZ_TX_TSO_OUTER_IP_ID_LBN 16
-#define ESF_DZ_TX_TSO_OUTER_IP_ID_WIDTH 16
#define ESF_DZ_TX_TSO_TCP_MSS_LBN 32
#define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16
-#define ESF_DZ_TX_TSO_INNER_PE_CSUM_LBN 0
-#define ESF_DZ_TX_TSO_INNER_PE_CSUM_WIDTH 16
+#define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0
+#define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16
/* ES_TX_VLAN_DESC */
diff --git a/drivers/net/sfc/sfc_ef10_rx.c b/drivers/net/sfc/sfc_ef10_rx.c
index 0b3e8fb..f31a7e0 100644
--- a/drivers/net/sfc/sfc_ef10_rx.c
+++ b/drivers/net/sfc/sfc_ef10_rx.c
@@ -325,22 +325,32 @@ sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev,
SFC_ASSERT(false);
}
- switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L4_CLASS)) {
- case ESE_DZ_L4_CLASS_TCP:
+ /*
+ * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
+ * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
+ * and values for all EF10 controllers.
+ */
+ RTE_BUILD_BUG_ON(ESF_FZ_RX_L4_CLASS_LBN != ESF_DE_RX_L4_CLASS_LBN);
+ switch (EFX_QWORD_FIELD(rx_ev, ESF_FZ_RX_L4_CLASS)) {
+ case ESE_FZ_L4_CLASS_TCP:
+ RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_TCP != ESE_DE_L4_CLASS_TCP);
l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP :
RTE_PTYPE_INNER_L4_TCP;
ol_flags |=
(EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
break;
- case ESE_DZ_L4_CLASS_UDP:
+ case ESE_FZ_L4_CLASS_UDP:
+ RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UDP != ESE_DE_L4_CLASS_UDP);
l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP :
RTE_PTYPE_INNER_L4_UDP;
ol_flags |=
(EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
break;
- case ESE_DZ_L4_CLASS_UNKNOWN:
+ case ESE_FZ_L4_CLASS_UNKNOWN:
+ RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UNKNOWN !=
+ ESE_DE_L4_CLASS_UNKNOWN);
break;
default:
/* Unexpected Layer 4 class */
--
2.7.4
next prev parent reply other threads:[~2018-02-20 7:35 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-20 7:33 [dpdk-dev] [PATCH 00/80] net/sfc/base: update base driver Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 01/80] net/sfc: add missing defines for SAL annotation Andrew Rybchenko
2018-03-05 20:47 ` Ferruh Yigit
2018-02-20 7:33 ` [dpdk-dev] [PATCH 02/80] net/sfc/base: regenerate files with genfwdef after ID update Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 03/80] net/sfc/base: update autogenerated headers from firmwaresrc Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 04/80] net/sfc/base: add 3.3V and 12.0V current sensors Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 05/80] net/sfc/base: add Medford2 PCI IDs Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 06/80] net/sfc/base: add efsys option for Medford2 Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 07/80] net/sfc/base: add Medford2 support to NIC module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 08/80] net/sfc/base: correct PIO buffer dimensions for Medford2 Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 09/80] net/sfc/base: move RxDP config get to EF10 NIC code Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 10/80] net/sfc/base: add Medford2 support to EV module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 11/80] net/sfc/base: add Medford2 support to FILTER module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 12/80] net/sfc/base: add Medford2 support to INTR module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 13/80] net/sfc/base: add Medford2 support to MAC module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 14/80] net/sfc/base: add Medford2 support to MCDI module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 15/80] net/sfc/base: add Medford2 support to PHY module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 16/80] net/sfc/base: add Medford2 support to Rx module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 17/80] net/sfc/base: add Medford2 support to Tx module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 18/80] net/sfc/base: add Medford2 support to NVRAM module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 19/80] net/sfc/base: add Medford2 support to SRAM module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 20/80] net/sfc/base: add Medford2 support to BOOTCFG module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 21/80] net/sfc/base: add Medford2 support to VPD module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 22/80] net/sfc/base: add Medford2 support to MON module Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 23/80] net/sfc/base: support runtime VI window size Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 24/80] net/sfc/base: improve comments for EF10 ext port mapping Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 25/80] net/sfc/base: add method to make checksum option descriptors Andrew Rybchenko
2018-02-20 7:33 ` Andrew Rybchenko [this message]
2018-02-20 7:33 ` [dpdk-dev] [PATCH 27/80] net/sfc/base: refactoring eliminating code analysis warnings Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 28/80] net/sfc/base: fix too long line Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 29/80] net/sfc/base: update notes on interrupt testing on VFs Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 30/80] net/sfc/base: report memory BAR number Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 31/80] net/sfc/base: simplify loopback type checking Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 32/80] net/sfc/base: add support new link modes Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 33/80] net/sfc/base: add new loopback modes Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 34/80] net/sfc/base: add efsys macro to get memory region size Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 35/80] net/sfc/base: handle new speeds in linkchange events Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 36/80] net/sfc/base: refactor EF10 get datapath capabilities Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 37/80] net/sfc/base: retrieve number of MAC stats from NIC Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 38/80] net/sfc/base: improve robustness of MAC stats get via MCDI Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 39/80] net/sfc/base: use MAC stats DMA buffer size from caps Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 40/80] net/sfc/base: use MAC stats DMA buffer size when decoding Andrew Rybchenko
2018-02-20 7:33 ` [dpdk-dev] [PATCH 41/80] net/sfc/base: run mkconfig.py to add FEC MAC stats Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 42/80] net/sfc/base: decode Medford2 FEC stats if available Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 43/80] net/sfc/base: resolve code analysis warnings Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 44/80] net/sfc: size MAC stats DMA buffer to support Medford2 Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 45/80] net/sfc/base: remove MAC stats size define Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 46/80] net/sfc/base: use correct name for frame truncation event Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 47/80] net/sfc/base: add ef10 NIC board config method Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 48/80] net/sfc/base: move port config to ef10 NIC board config Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 49/80] net/sfc/base: move PF/VF " Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 50/80] net/sfc/base: move MAC address config to ef10 NIC board cfg Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 51/80] net/sfc/base: move legacy board " Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 52/80] net/sfc/base: move PHY/link " Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 53/80] net/sfc/base: move datapath " Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 54/80] net/sfc/base: move Rx config to ef10 NIC board config Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 55/80] net/sfc/base: move Tx " Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 56/80] net/sfc/base: move limits " Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 57/80] net/sfc/base: move vector " Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 58/80] net/sfc/base: move privilege " Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 59/80] net/sfc/base: move VI window size config to ef10 NIC board Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 60/80] net/sfc/base: remove obsolete comments Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 61/80] net/sfc/base: support FEC mode settings Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 62/80] net/sfc/base: support Medford2 event timer semantics Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 63/80] net/sfc/base: clarify port mode names and masks Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 64/80] net/sfc/base: group Medford external port mapping entries Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 65/80] net/sfc/base: add Medford2 support for external port numbers Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 66/80] net/sfc/base: add Medford2 support for licencing Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 67/80] net/sfc/base: add Medford2 support for tunnel encapsulations Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 68/80] net/sfc/base: provide a flag for controlling CTPIO mode Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 69/80] net/sfc/base: add 1.3V voltage and current sensors Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 70/80] net/sfc/base: document the event type for CTPIO sends Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 71/80] net/sfc/base: run genfwdef to update headers Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 72/80] net/sfc/base: add CTPIO statistics Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 73/80] net/sfc/base: add bit to indicate CTPIO availability Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 74/80] net/sfc/base: regenerate headers to pick up CTPIO stats Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 75/80] net/sfc/base: support " Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 76/80] net/sfc/base: add encapsulated TSOv2 capability Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 77/80] net/sfc/base: add outer IP ID parameter to TSOv2 descriptor Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 78/80] net/sfc/base: add firmware image layout option Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 79/80] net/sfc/base: add signed image layout support Andrew Rybchenko
2018-02-20 7:34 ` [dpdk-dev] [PATCH 80/80] net/sfc/base: sync MCDI headers and TLV layout Andrew Rybchenko
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