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Ie. for interfaces that @@ -127,13 +128,15 @@ static inline void out_be32(volatile void *__p, u32 val) *p = rte_cpu_to_be_32(val); } +#define hwsync() rte_rmb() +#define lwsync() rte_wmb() + #define dcbt_ro(p) __builtin_prefetch(p, 0) #define dcbt_rw(p) __builtin_prefetch(p, 1) +#if defined(RTE_ARCH_ARM64) #define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); } #define dcbz_64(p) dcbz(p) -#define hwsync() rte_rmb() -#define lwsync() rte_wmb() #define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); } #define dcbf_64(p) dcbf(p) #define dccivac(p) { asm volatile("dc civac, %0" : : "r"(p) : "memory"); } @@ -144,9 +147,27 @@ static inline void out_be32(volatile void *__p, u32 val) asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); \ } while (0) +#elif defined(RTE_ARCH_ARM) +#define dcbz(p) memset((p), 0, 32) +#define dcbz_64(p) memset((p), 0, 64) +#define dcbf(p) RTE_SET_USED(p) +#define dcbf_64(p) dcbf(p) +#define dccivac(p) RTE_SET_USED(p) +#define dcbit_ro(p) RTE_SET_USED(p) + +#else +#define dcbz(p) RTE_SET_USED(p) +#define dcbz_64(p) dcbz(p) +#define dcbf(p) RTE_SET_USED(p) +#define dcbf_64(p) dcbf(p) +#define dccivac(p) RTE_SET_USED(p) +#define dcbit_ro(p) RTE_SET_USED(p) +#endif + #define barrier() { asm volatile ("" : : : "memory"); } #define cpu_relax barrier +#if defined(RTE_ARCH_ARM64) static inline uint64_t mfatb(void) { uint64_t ret, ret_new, timeout = 200; @@ -160,6 +181,11 @@ static inline uint64_t mfatb(void) DPAA_BUG_ON(!timeout && (ret != ret_new)); return ret * 64; } +#else + +#define mfatb rte_rdtsc + +#endif /* Spin for a few cycles without bothering the bus */ static inline void cpu_spin(int cycles) -- 2.7.4