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7:RQOr95QTShtttR/J97vUFcupxpwNG3PV2FRV3XNKJUqSwGX9nGxnAFL3uZQqD31aRhSxP2Pc69yFQxOEYqP4RLelAZVW1aLHiHk+T+LsLo4NUCNmiolKJMl3BGViUQjPa3A1z6wz+XpmwgajHrUr/3PXcLgG6gP861rE4AXoyjRLNHCslSuKOLcgomqatkR89QIRppC3TGNWX+ZS6fAF4QbO95mxI/brsCuMhlk/OW71VsEXF9d8sJI0SNLq0Xo2; 20:UcNTGv9rQU9JKHGh9ALLRMlshGGZ53FO+bop57eecWhs0+AYqKDuSWaFrCvX6dUzqIovNO4vX7ikJVfx4fByouREpuozRC/axtLi40sH9MQ5DM46qKNVuMv2LZTppFCnhURYdajc4tL6VvV998qi3PXTAebnTP1sL3M1WotSo5lIbIxXqNxfgwXhEiH7LitxhGDXhKzf+6EOO/9xivurnm3X8TbUcxQ0dELZlOLnvDAc347b7NUfmvjnPdoxT50n X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2018 12:37:36.2408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c994c0ef-fd42-4042-7af1-08d59bbb2dc8 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1509 Subject: [dpdk-dev] [PATCH v5 16/18] net/axgbe: add support for build 32-bit mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Apr 2018 12:37:39 -0000 Signed-off-by: Ravi Kumar --- doc/guides/nics/features/axgbe.ini | 1 + drivers/net/axgbe/axgbe_common.h | 53 ++++++++++++++++++++++---------------- drivers/net/axgbe/axgbe_ethdev.c | 10 ++++--- drivers/net/axgbe/axgbe_ethdev.h | 8 +++--- drivers/net/axgbe/axgbe_rxtx.c | 12 ++++----- drivers/net/axgbe/axgbe_rxtx.h | 4 +-- 6 files changed, 50 insertions(+), 38 deletions(-) diff --git a/doc/guides/nics/features/axgbe.ini b/doc/guides/nics/features/axgbe.ini index 042ff1e..ab4da55 100644 --- a/doc/guides/nics/features/axgbe.ini +++ b/doc/guides/nics/features/axgbe.ini @@ -15,4 +15,5 @@ L3 checksum offload = Y L4 checksum offload = Y Basic stats = Y Linux UIO = Y +x86-32 = Y x86-64 = Y diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index 298e794..64c7a7f 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -1385,7 +1385,7 @@ do { \ * register definitions formed using the input names */ #define AXGMAC_IOREAD(_pdata, _reg) \ - rte_read32((void *)((_pdata)->xgmac_regs + (_reg))) + rte_read32((uint8_t *)((_pdata)->xgmac_regs) + (_reg)) #define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \ @@ -1393,7 +1393,8 @@ do { \ _reg##_##_field##_WIDTH) #define AXGMAC_IOWRITE(_pdata, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xgmac_regs + (_reg))) + rte_write32((_val), \ + (uint8_t *)((_pdata)->xgmac_regs) + (_reg)) #define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1409,8 +1410,8 @@ do { \ * base register value is calculated by the queue or traffic class number */ #define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \ - rte_read32((void *)((_pdata)->xgmac_regs + \ - MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))) + rte_read32((uint8_t *)((_pdata)->xgmac_regs) + \ + MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)) #define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ GET_BITS(AXGMAC_MTL_IOREAD((_pdata), (_n), (_reg)), \ @@ -1418,8 +1419,8 @@ do { \ _reg##_##_field##_WIDTH) #define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xgmac_regs + \ - MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))) + rte_write32((_val), (uint8_t *)((_pdata)->xgmac_regs) +\ + MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)) #define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ do { \ @@ -1435,7 +1436,7 @@ do { \ * base register value is obtained from the ring */ #define AXGMAC_DMA_IOREAD(_channel, _reg) \ - rte_read32((void *)((_channel)->dma_regs + (_reg))) + rte_read32((uint8_t *)((_channel)->dma_regs) + (_reg)) #define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \ @@ -1443,7 +1444,8 @@ do { \ _reg##_##_field##_WIDTH) #define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \ - rte_write32((_val), (void *)((_channel)->dma_regs + (_reg))) + rte_write32((_val), \ + (uint8_t *)((_channel)->dma_regs) + (_reg)) #define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ do { \ @@ -1468,16 +1470,18 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XPCS32_IOWRITE(_pdata, _off, _val) \ - rte_write32(_val, (void *)((_pdata)->xpcs_regs + (_off))) + rte_write32(_val, \ + (uint8_t *)((_pdata)->xpcs_regs) + (_off)) #define XPCS32_IOREAD(_pdata, _off) \ - rte_read32((void *)((_pdata)->xpcs_regs + (_off))) + rte_read32((uint8_t *)((_pdata)->xpcs_regs) + (_off)) #define XPCS16_IOWRITE(_pdata, _off, _val) \ - rte_write16(_val, (void *)((_pdata)->xpcs_regs + (_off))) + rte_write16(_val, \ + (uint8_t *)((_pdata)->xpcs_regs) + (_off)) #define XPCS16_IOREAD(_pdata, _off) \ - rte_read16((void *)((_pdata)->xpcs_regs + (_off))) + rte_read16((uint8_t *)((_pdata)->xpcs_regs) + (_off)) /* Macros for building, reading or writing register values or bits * within the register values of SerDes integration registers. @@ -1493,7 +1497,7 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XSIR0_IOREAD(_pdata, _reg) \ - rte_read16((void *)((_pdata)->sir0_regs + (_reg))) + rte_read16((uint8_t *)((_pdata)->sir0_regs) + (_reg)) #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ @@ -1501,7 +1505,8 @@ do { \ _reg##_##_field##_WIDTH) #define XSIR0_IOWRITE(_pdata, _reg, _val) \ - rte_write16((_val), (void *)((_pdata)->sir0_regs + (_reg))) + rte_write16((_val), \ + (uint8_t *)((_pdata)->sir0_regs) + (_reg)) #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1513,7 +1518,7 @@ do { \ } while (0) #define XSIR1_IOREAD(_pdata, _reg) \ - rte_read16((void *)((_pdata)->sir1_regs + _reg)) + rte_read16((uint8_t *)((_pdata)->sir1_regs) + _reg) #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ @@ -1521,7 +1526,8 @@ do { \ _reg##_##_field##_WIDTH) #define XSIR1_IOWRITE(_pdata, _reg, _val) \ - rte_write16((_val), (void *)((_pdata)->sir1_regs + (_reg))) + rte_write16((_val), \ + (uint8_t *)((_pdata)->sir1_regs) + (_reg)) #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1536,7 +1542,7 @@ do { \ * within the register values of SerDes RxTx registers. */ #define XRXTX_IOREAD(_pdata, _reg) \ - rte_read16((void *)((_pdata)->rxtx_regs + (_reg))) + rte_read16((uint8_t *)((_pdata)->rxtx_regs) + (_reg)) #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ @@ -1544,7 +1550,8 @@ do { \ _reg##_##_field##_WIDTH) #define XRXTX_IOWRITE(_pdata, _reg, _val) \ - rte_write16((_val), (void *)((_pdata)->rxtx_regs + (_reg))) + rte_write16((_val), \ + (uint8_t *)((_pdata)->rxtx_regs) + (_reg)) #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1569,7 +1576,7 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XP_IOREAD(_pdata, _reg) \ - rte_read32((void *)((_pdata)->xprop_regs + (_reg))) + rte_read32((uint8_t *)((_pdata)->xprop_regs) + (_reg)) #define XP_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XP_IOREAD((_pdata), (_reg)), \ @@ -1577,7 +1584,8 @@ do { \ _reg##_##_field##_WIDTH) #define XP_IOWRITE(_pdata, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xprop_regs + (_reg))) + rte_write32((_val), \ + (uint8_t *)((_pdata)->xprop_regs) + (_reg)) #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1602,7 +1610,7 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XI2C_IOREAD(_pdata, _reg) \ - rte_read32((void *)((_pdata)->xi2c_regs + (_reg))) + rte_read32((uint8_t *)((_pdata)->xi2c_regs) + (_reg)) #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \ @@ -1610,7 +1618,8 @@ do { \ _reg##_##_field##_WIDTH) #define XI2C_IOWRITE(_pdata, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xi2c_regs + (_reg))) + rte_write32((_val), \ + (uint8_t *)((_pdata)->xi2c_regs) + (_reg)) #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index 8c7b0ee..61a600c 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -589,10 +589,12 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) pdata->pci_dev = pci_dev; pdata->xgmac_regs = - (uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; - pdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET; - pdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET; - pdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; + (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; + pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs + + AXGBE_MAC_PROP_OFFSET); + pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs + + AXGBE_I2C_CTRL_OFFSET); + pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; /* version specific driver data*/ if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index e977448..7bd2900 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -445,10 +445,10 @@ struct axgbe_port { struct axgbe_version_data *vdata; /* AXGMAC/XPCS related mmio registers */ - uint64_t xgmac_regs; /* AXGMAC CSRs */ - uint64_t xpcs_regs; /* XPCS MMD registers */ - uint64_t xprop_regs; /* AXGBE property registers */ - uint64_t xi2c_regs; /* AXGBE I2C CSRs */ + void *xgmac_regs; /* AXGMAC CSRs */ + void *xpcs_regs; /* XPCS MMD registers */ + void *xprop_regs; /* AXGBE property registers */ + void *xi2c_regs; /* AXGBE I2C CSRs */ /* XPCS indirect addressing lock */ unsigned int xpcs_window_def_reg; diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index e96e2be..b302bdd 100644 --- a/drivers/net/axgbe/axgbe_rxtx.c +++ b/drivers/net/axgbe/axgbe_rxtx.c @@ -70,9 +70,9 @@ int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, rxq->queue_id = queue_idx; rxq->port_id = dev->data->port_id; rxq->nb_desc = rx_desc; - rxq->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + - (DMA_CH_INC * rxq->queue_id); - rxq->dma_tail_reg = (volatile uint32_t *)(rxq->dma_regs + + rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + + (DMA_CH_INC * rxq->queue_id)); + rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs + DMA_CH_RDTR_LO); rxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) ? 0 : ETHER_CRC_LEN); @@ -387,9 +387,9 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, txq->desc = tz->addr; txq->queue_id = queue_idx; txq->port_id = dev->data->port_id; - txq->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + - (DMA_CH_INC * txq->queue_id); - txq->dma_tail_reg = (volatile uint32_t *)(txq->dma_regs + + txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + + (DMA_CH_INC * txq->queue_id)); + txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs + DMA_CH_TDTR_LO); txq->cur = 0; txq->dirty = 0; diff --git a/drivers/net/axgbe/axgbe_rxtx.h b/drivers/net/axgbe/axgbe_rxtx.h index f221cc3..1ec6c2c 100644 --- a/drivers/net/axgbe/axgbe_rxtx.h +++ b/drivers/net/axgbe/axgbe_rxtx.h @@ -80,7 +80,7 @@ struct axgbe_rx_queue { /* Ring physical address */ uint64_t ring_phys_addr; /* Dma Channel register address */ - uint64_t dma_regs; + void *dma_regs; /* Dma channel tail register address*/ volatile uint32_t *dma_tail_reg; /* DPDK queue index */ @@ -127,7 +127,7 @@ struct axgbe_tx_queue { /* Physical address of ring */ uint64_t ring_phys_addr; /* Dma channel register space */ - uint64_t dma_regs; + void *dma_regs; /* Dma tail register address of ring*/ volatile uint32_t *dma_tail_reg; /* Tx queue index/id*/ -- 2.7.4