From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-f193.google.com (mail-pf1-f193.google.com [209.85.210.193]) by dpdk.org (Postfix) with ESMTP id 219811B56A for ; Sun, 5 Aug 2018 20:41:50 +0200 (CEST) Received: by mail-pf1-f193.google.com with SMTP id u24-v6so5709258pfn.13 for ; Sun, 05 Aug 2018 11:41:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=UuSSLQgsac014IU0t1DYQMa+kdpZUleoXElyc3U5m74=; b=O1SyXLtp/pUNFsFum4N/iipnb2k2bHb+t6kHR61thhxVVSfB/yy1AnHSwKSnOLbaeK kYik3Di2fe+6pe4QaCszqd/P6H4fGuf5PAij1WmhfHIj63Wa/nSvaYzMpFYVcJ9E1J/2 ayi6hPxPqH7k9pieBLr76NDXxKKD4kbNLjaoTmknIY0Tb0okUuOjFW8vaUnm73QdTVzA iuvf3Lk3P/IalBHVwioSfpcrX/3go6ae7nxHapNQMqZr5fYkv00FA1scTYsJTxsRLI3f IRwGs2mWQk0yOoDzsAMBZtFrKV+lCBoRWZQ3VvJ2rkSGLBcXzhcLa17H5fnn0UGjZx40 7gCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=UuSSLQgsac014IU0t1DYQMa+kdpZUleoXElyc3U5m74=; b=PudnVjDL9sx1HZ0Rzytq0CDlrvEYrjIUELSOMfhzfw0mgpsIgrRGd5uJakPBYPPcYu bLb/eQvvtljOlFiBP0s3kRK4lPoBCBajD9X0jIk1hX3ZDH3Dva1b5oEE7fAwY+kW+FdR OVRmIyedKCdJwC7hDeXlzmiAo+nIzAPhYnrpGCuJFhPAY8YFhIAiqaTxPUqBDPqc0oD9 xdaRZruquj0MURToBppMhSaFR/+tGZYIq8qOzHqFdL9S9r+ub9E+/MO7Q8PUIooP8ZWC YqjauuDL+INJxrGMdtZeyiiNHgsT8/t1c9V6PDRyeleopy290Z0/yGrdYMfaiX/3IIBk G6gQ== X-Gm-Message-State: AOUpUlE3ekjt0rPQl1azKDNjFQtF/WVGscfv3XhWS7XTeNloBKQccZiR MgnApEIYbjWwLDl6v7Rgmls= X-Google-Smtp-Source: AAOMgpdN36ata/mwXhM5T3dIB5x67PWdVOYtvPBlQ3uyLOzWQUVseBWGqSF1rjqtiLciCyAlH98S7w== X-Received: by 2002:a63:89c7:: with SMTP id v190-v6mr11553057pgd.194.1533494509196; Sun, 05 Aug 2018 11:41:49 -0700 (PDT) Received: from localhost.10.42.26 ([43.245.220.91]) by smtp.gmail.com with ESMTPSA id z19-v6sm16533084pgi.33.2018.08.05.11.41.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 Aug 2018 11:41:48 -0700 (PDT) From: Drocula To: maxime.coquelin@redhat.com Cc: dev@dpdk.org, Drocula Date: Sun, 5 Aug 2018 18:41:37 +0000 Message-Id: <1533494497-16253-1-git-send-email-quzeyao@gmail.com> X-Mailer: git-send-email 1.8.3.1 Subject: [dpdk-dev] [PATCH] bus/pci: check if 5-level paging is enabled when testing IOMMU address width X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 05 Aug 2018 18:41:50 -0000 The kernel version 4.14 released with the support of 5-level paging. When PML5 enabled, user-space virtual addresses uses up to 56 bits. see kernel's Documentation/x86/x86_64/mm.txt. Signed-off-by: Drocula --- drivers/bus/pci/linux/pci.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c index 004600f..8913d6d 100644 --- a/drivers/bus/pci/linux/pci.c +++ b/drivers/bus/pci/linux/pci.c @@ -4,6 +4,7 @@ #include #include +#include #include #include @@ -553,12 +554,34 @@ } #if defined(RTE_ARCH_X86) +/* + * Try to detect whether the system uses 5-level page table. + */ +static bool +system_uses_PML5(void) +{ + void *page_4k, *mask = (void *)0xf0000000000000; + page_4k = mmap(mask, 4096, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + + if (page_4k == (void *) -1) + return false; + munmap(page_4k, 4096); + + if ((unsigned long)page_4k & (unsigned long)mask) + return true; + return false; +} + static bool pci_one_device_iommu_support_va(struct rte_pci_device *dev) { #define VTD_CAP_MGAW_SHIFT 16 #define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT) -#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */ +/* From Documentation/x86/x86_64/mm.txt */ +#define X86_VA_WIDTH_PML4 47 +#define X86_VA_WIDTH_PML5 56 + struct rte_pci_addr *addr = &dev->addr; char filename[PATH_MAX]; FILE *fp; @@ -589,7 +612,7 @@ fclose(fp); mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1; - if (mgaw < X86_VA_WIDTH) + if (mgaw < (system_uses_PML5() ? X86_VA_WIDTH_PML5 : X86_VA_WIDTH_PML4)) return false; return true; -- 1.8.3.1