From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <Anoob.Joseph@cavium.com>
Received: from NAM01-SN1-obe.outbound.protection.outlook.com
(mail-sn1nam01on0084.outbound.protection.outlook.com [104.47.32.84])
by dpdk.org (Postfix) with ESMTP id CAB167D05
for <dev@dpdk.org>; Tue, 4 Sep 2018 06:03:35 +0200 (CEST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
bh=JOPF2NEMS2MQu17LoG5roAJUZ1ODsaEmlUE7APDV/8M=;
b=oQsX/XtcOQ8obaoS/MwfJ3iS0A++BZaRZvamzPSg9CFIc6v99nQ3IV5pxuHRhAqg+nYSXT4WK0xCd5D+AZSTa2sp5SlTY0UypTgzrfCO5abH9W+Pq1ShwhPcY5NOzGO2LhpKUT0b5FaUWOXfByfxNMV9q6AqnTYnxcIg7qeBC1I=
Authentication-Results: spf=none (sender IP is )
smtp.mailfrom=Anoob.Joseph@cavium.com;
Received: from ajoseph83.caveonetworks.com.com (115.113.156.2) by
BYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) with Microsoft
SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
15.20.1101.15; Tue, 4 Sep 2018 04:03:30 +0000
From: Anoob Joseph <ajoseph@caviumnetworks.com>
To: Akhil Goyal <akhil.goyal@nxp.com>,
Pablo de Lara <pablo.de.lara.guarch@intel.com>,
Thomas Monjalon <thomas@monjalon.net>
Cc: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>,
Jerin Jacob <jerin.jacob@caviumnetworks.com>,
Narayana Prasad <narayanaprasad.athreya@caviumnetworks.com>, dev@dpdk.org,
Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,
Anoob Joseph <anoob.joseph@caviumnetworks.com>,
Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>,
Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,
Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>,
Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
Date: Tue, 4 Sep 2018 09:29:11 +0530
Message-Id: <1536033560-21541-25-git-send-email-ajoseph@caviumnetworks.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>
References: <1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>
<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>
MIME-Version: 1.0
Content-Type: text/plain
X-Originating-IP: [115.113.156.2]
X-ClientProxiedBy: BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM
(2603:1096:b00:d::33) To BYAPR07MB4902.namprd07.prod.outlook.com
(2603:10b6:a02:ef::25)
X-MS-PublicTrafficType: Email
X-MS-Office365-Filtering-Correlation-Id: 6f300846-64b0-4d43-4e89-08d6121b6264
X-Microsoft-Antispam: BCL:0; PCL:0;
RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(2017052603328)(7153060)(7193020);
SRVR:BYAPR07MB4902;
X-Microsoft-Exchange-Diagnostics: 1; BYAPR07MB4902;
3:TilexfLNZLfCBgM4eEgPmniQG2CXEdUyOalj0Yp/lUpWU8SCGc/3lOGk6QQwLjBnl9waum8VeyhU9JnxGLV5n0nTrKYGFMdS6Vv4QV/DV4wgPswycyDqBzuI+WX46PYqglz5wYSHD6eyMA363tBHdS2kHXyh0vKKx120wvot5YSER4IRbTxqtD41B5fP66xIHzkKK36F8xqZ3LVpzXdtiJExOAnaTlrevITtMCV9pM0LUXs+c8j3uEUngHG6Cw0D;
25:pJRuICRcwpG5IuE2gtW0VAj5+k0w7Ka4f7XljCcWezRy2E1GS0QAQApdnJN2DSNldIJjxp5bPcMEv+33wvsJ3YzW02V1+XuFOD2zMzvdZOiMdILGNLhoeSdi8N4IVNdEkPNgpmBwK3poCfWGr5exC6AlSRjCDU2hvWLw0+Q09W/Gv+IJBohmM1nFQN5Q+w8sKJqnTvZjLqE1R3kIrmiNMqcaPBtkxJtWfGlQ6x8IPNeveD5N+VIYFI2R7YpigIgMDfoxohuayfkd1jSS+RNXh/y6JRc0VDRWP0Zynmm45srnsjJKw1++Wycb9R9mEKPkc64AKw2tjnWT0Gj6iVy2DQ==;
31:ji1ympyzYAKEXmd95rqGVBbjwpx0/2Lx+4w0KawSdNIohqVhYprfk5+ycRFgnIsN3bn+vnnSc4Sa9vwyVFW3UZe2cAYNofbfGr2P5AGwz+BOwDbH9gqTNIiVaj40KSdWlkuKreD9OyOWMJT+izUy7ajP+wHtk/oXZaa+m5l1GIn2tuhDdY7aXCf2fqLab3HzbfS4v0dE0B2mW2J5jr3ECeYMxvmCciXQTljDUpDKyIY=
X-MS-TrafficTypeDiagnostic: BYAPR07MB4902:
X-Microsoft-Exchange-Diagnostics: 1; BYAPR07MB4902;
20:YogXyyZDwVePdGuBTEzpwMv2rWbjsX4isDYbZN4XKL+caRFozdGrZMMYmnaIKHq1pLwS0O3pBlkjLh/o0vlu9jsAOiQSC55+KpLguJkL6QjndV2z7Ih5j4b55TjjGy2uNXUQ45kzUoPsDLPbcRvkgnLE71QjBpG/380swel2l9EO9gfO62iM7zbrC9jph+fCsHcLODo/7lVlN3w2MzMb0bTtBgq/N7rrfY9TrYwbDtqFWeXBxQ69O8e4ewOGaF0eIMx1NGrrpPDL8P4vmwTJujkiLgKReqocjMhaZmT2PMTS6vDGKomp7vh7Bxm70R2TQU6egxbiFSRddfjaXCRpmIryzJsHAyfRvRvxUPbtA9OzJMBF7vgiYqW4GStOP54pqkdoKrGrUk0F6jBxzPmos/CFqjNGx86iRZOSO6VeQiGe3sOCj3Q5s/lg4grQYM/x2XzLoyoXqGy/XMRRLGRBVY3/iLrODB44SW74Zt43/V6bc8Jogyjo3SngY4zTeo91RUGlshTKDx6xnTDn1H0fxDVz2AhjCtYnnsFRze28WJivbDQf381h/srUxYQle292AFne8hvdgajI67Ccu+V9oZyeosKXA1lXDAe0enGo0i0=;
4:vNdGrq8oANu95Lpe3nwjT10UInNNHyR1uHY9QVvmDxCVBlizyS4b1KjTYJj1Sq5N7UAnC94Q9ksmhzJa5R94S1vkXtvvL8/HCxh+YJJsfK1WI5uU4dzHIV2XC3Y6vzeZ0Dg3kzki1R1MMwbxbDyVzYC1IaHZxxdatCr5+Zvpu4NYxpAppmU4HtQ/FuKkrhjzex1oY5SDzhIKUK7solcD1vOWsc7JsxgZ68bu4h/9nQFxYxjLEoUv1r/anFAzsIM6HU8FKa0AIt7lx2I18qW9Gw==
X-Microsoft-Antispam-PRVS: <BYAPR07MB490290F14BF920A52FB85B20F8030@BYAPR07MB4902.namprd07.prod.outlook.com>
X-Exchange-Antispam-Report-Test: UriScan:;
X-MS-Exchange-SenderADCheck: 1
X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0;
RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(10201501046)(93006095)(3231311)(944501410)(52105095)(3002001)(149027)(150027)(6041310)(20161123562045)(20161123564045)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699016);
SRVR:BYAPR07MB4902; BCL:0; PCL:0; RULEID:; SRVR:BYAPR07MB4902;
X-Forefront-PRVS: 0785459C39
X-Forefront-Antispam-Report: SFV:NSPM;
SFS:(10009020)(366004)(396003)(136003)(346002)(376002)(39860400002)(199004)(189003)(26005)(51416003)(52116002)(76176011)(81166006)(305945005)(81156014)(7736002)(105586002)(316002)(6506007)(106356001)(6512007)(8936002)(446003)(54906003)(25786009)(6666003)(68736007)(50226002)(110136005)(53936002)(16586007)(42882007)(386003)(5660300001)(2906002)(72206003)(50466002)(6486002)(36756003)(6116002)(107886003)(2616005)(14444005)(186003)(3846002)(478600001)(66066001)(476003)(8676002)(47776003)(486006)(956004)(48376002)(11346002)(4326008)(97736004)(16526019)(32563001);
DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR07MB4902;
H:ajoseph83.caveonetworks.com.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords;
A:1; MX:1;
Received-SPF: None (protection.outlook.com: cavium.com does not designate
permitted sender hosts)
X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BYAPR07MB4902;
23:yZBPRt+QQnpdLZMcyfUlhYk7NQZeCpfdHkPtLRZ1k?=
=?us-ascii?Q?JfDj86Bqu+uPJ6X0hCjPDKOUh28Zp9SJdVo2GqVQJlBXt4v1TCFrEzdP8QYh?=
=?us-ascii?Q?fjiXYqTuzXw0AkUTxlGlVvoeXVlmLxxDH02hNvO64wI3yNIQrBRPhWw7CwiG?=
=?us-ascii?Q?e8FsFDXJyqkpPcIlq2xNTlSV7/5ZQgEL3mNH/wO70EvpDoUKY8ncHTh/v1V+?=
=?us-ascii?Q?gwRseSl/blFnZVow34Ts5hQ7OhvVo7zfJYA52SkzJlMuTs9sv+MFOam8/fbe?=
=?us-ascii?Q?se/jtrD0KOSGe4jrDXbEUeWEmymG14NtjsuCJGSMlY+g45OcC3oq50yEEcnU?=
=?us-ascii?Q?mipbWyyH3OMlGHjk7QkojMPxj+g5b1lgtc84WOocc0Bwx+xFNZfoEKGtnhKi?=
=?us-ascii?Q?WhRQU9THBAJVLIvN72n5eaJ+/lmjJh0TGQlOf/FN+1L1WHERbuHtJgEdvg59?=
=?us-ascii?Q?uh8uTvTHWQ3cZEtWOD/JOVSjk9T7rpYKIPvX7gb9TuQwBYsKMHkfRf068NFR?=
=?us-ascii?Q?Et8sjsG0nJ6iWkjqLpKb0f4n6OcCnByJwTQOM04rODU8DnOEgqsTYK1Q7R9B?=
=?us-ascii?Q?h5AG+fYv2ZDqzGRf7LLJKZWKxupGfkzbT+auwUXzzxtVQKgISLsIBviZjy6z?=
=?us-ascii?Q?UiSn0d3wyoWinbZT1oorxstzoffn4NDiQEddB9e3KbDen5TW7rWp7uoG2d5z?=
=?us-ascii?Q?yAA+kj+HwbUnHonUStTORaY3bVWgG/2uGg02wY3YuqG7jNGAMRkE5jTEtY2k?=
=?us-ascii?Q?QAm0P00f0bFuaMO45kIf1q2x5Ci6mpBclV74VX3qSJnJ9WMsmF3CaSDlJ21p?=
=?us-ascii?Q?KcFP3Dex8DrBg//uY/Rwp5iqc71NHBkj+ZZKIzy83K1YRitTS5eCc5B5nnzu?=
=?us-ascii?Q?ipw4gFTiep6TtCIvrfAs/z+LhNuBNwBwH5T+ekb2KXlwof/zVFUO4t0vdlaQ?=
=?us-ascii?Q?7lg/RKQiLoi3CZzzwRKyVshQd/032qajSX38GO8z9U6x06ay+urCLDdViNV6?=
=?us-ascii?Q?6AEJJiY8IXAjuVAuTYXAZd0ROfuEyRRDyaRCUbMcqMFXoLW7s6GePA+TiOPJ?=
=?us-ascii?Q?V0/o6JvugQ7shuV6i6iNmqycP8shcnGSa8iOPAA2i6TwHgwNztObxOQjmXa3?=
=?us-ascii?Q?VkTDtFfbDweEGCU6JyUsdWlENgmNAbG503XvAenlz39mJdf0TFNv1yxIlFHV?=
=?us-ascii?Q?6lf/YsiidVbRDiEIQKxmKndK72+Ex9DgDLMIJLbr4hvBR8HmCAVinplINCMT?=
=?us-ascii?Q?DRa96vWp8Al5dnqk9xZs3MJp2VIxHMxXbw13AU2?=
X-Microsoft-Antispam-Message-Info: YlhXwqsucSQu21GTFIQ41SVZ7VJwdwGYAqjhf7e2AeBzWZPscwEwUafDS/6DRKIL2VgCOiQI+w4bV7T1ZBKB1rW1TzUr6H6pb5PuqhhMdvUeNAKzTxKVKYfsioqyWhO9a34fvJTjia/icKYzKJDk4vWzxWBltD6+V7Hb6DKCk8aXx10h7gnWbg0oxCtmhaPb/OLPVeUGOS16/irEdPD4eUrbCBqpf8iphVNGYH6S0DJagGBYZlozpVFH79UPhY2EOFxrv0Age1VCG78nsuPRlqDpJEeOfqGYDB3ywuibigcf0PxtM8yRvolJl/rJ0Mc1ACJDEiB5iSAvydgcT+bLr2TYcYr9KWybhQIaArslUNk=
X-Microsoft-Exchange-Diagnostics: 1; BYAPR07MB4902;
6:RydUtiLYXkTxKS3swgc6wlTMY0SbhLBzLGcaf8jzh39B8ZP5P2irPlbConRVzzIHWLDzhyyZ5X34gO8xO2qXSPUCfpNtBOdP8MWJ+bTkDZu9P2P/Ca43FpDgaATDS/XYRUhwRS81anNBYJLQAQYncZr2uBlzVMN+bhz5mtDFa4gC4YXtKEibwCfatVoMeuuy2eAXmOC1MrEiDtQ1T1zoSVRhzagjcNOT6/IXz1YCaIQfzqINifq7H/4eWjkOwjuvIQEmridu8ZoSwI4vPP3Ld+woxJ5lqj54emHszFOsvB9GPcHlkRs8o/3LZC+wi+eUcj9hBL87cra+9RSGG6zjldvKCq+WWgOpKMNwprBeWyJiAOEnVN4OkXiGs0F+4JXbua5Zci2aPeO0SVs40xjuGOY0tu6OKZGHGeI5QynzAF0zup+QUXWmkvrYomGtiQBakanMX7Uv7Cj1gJY+wjQYLQ==;
5:GYpDrW8qHhF+TCBIiVgSFfH7AUQiSqJ1nye9BFbteBefCrd4WtxqFwP4Lb8GrTVhRvravyQHJMOQpGXLs7DWrI2mKyxaA6ZNg8e6vYUSKN2+Xd5x/flO5MyBb5M+vf2MJ7UIyHbUAIvdbzcOOOm5CTCpaoo/AhWS18irn00Dgnk=;
7:xnh0pZsfT8SCwpdJTLmivFrwmVnJl5MaFDOXcQa79iWRBtn6Dw5DSvozD9XrGTvmv9gQUv4gsf1HGrz+0+K7MIaeSSbv5GrY/A+z107HEyLyfaOPdaA0Ut2mr78Ox1XoCmQYX5bT+Tfltk1aEIJJE5o3pbzZK61kwxOKu9wL4sKJPputJIi+TZ82AcbpLCaj/ghwrgvhph47p+kmzaWbawLnmhcylICfFyFU6r7TCz4rV0YfDheFil6zSu3KG3RW
SpamDiagnosticOutput: 1:99
SpamDiagnosticMetadata: NSPM
X-OriginatorOrg: caviumnetworks.com
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2018 04:03:30.5224 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 6f300846-64b0-4d43-4e89-08d6121b6264
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB4902
Subject: [dpdk-dev] [PATCH v2 24/33] common/cpt: add support for zuc and
snow3g
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
X-List-Received-Date: Tue, 04 Sep 2018 04:03:36 -0000
From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Adding microcode interface for supporting ZUC and SNOW3G.
Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
drivers/common/cpt/cpt_ucode.h | 618 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 618 insertions(+)
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 6949d35..383dff2 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -1164,6 +1164,618 @@ cpt_dec_hmac_prep(uint32_t flags,
return 0;
}
+static __rte_always_inline int
+cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
+ uint64_t d_offs,
+ uint64_t d_lens,
+ fc_params_t *params,
+ void *op,
+ void **prep_req)
+{
+ uint32_t size;
+ int32_t inputlen, outputlen;
+ struct cpt_ctx *cpt_ctx;
+ uint32_t mac_len = 0;
+ uint8_t snow3g, j;
+ struct cpt_request_info *req;
+ buf_ptr_t *buf_p;
+ uint32_t encr_offset = 0, auth_offset = 0;
+ uint32_t encr_data_len = 0, auth_data_len = 0;
+ int flags, iv_len = 16, m_size;
+ void *m_vaddr, *c_vaddr;
+ uint64_t m_dma, c_dma, offset_ctrl;
+ uint64_t *offset_vaddr, offset_dma;
+ uint32_t *iv_s, iv[4];
+ vq_cmd_word0_t vq_cmd_w0;
+ vq_cmd_word3_t vq_cmd_w3;
+ opcode_info_t opcode;
+
+ buf_p = ¶ms->meta_buf;
+ m_vaddr = buf_p->vaddr;
+ m_dma = buf_p->dma_addr;
+ m_size = buf_p->size;
+
+ cpt_ctx = params->ctx_buf.vaddr;
+ flags = cpt_ctx->zsk_flags;
+ mac_len = cpt_ctx->mac_len;
+ snow3g = cpt_ctx->snow3g;
+
+ /*
+ * Save initial space that followed app data for completion code &
+ * alternate completion code to fall in same cache line as app data
+ */
+ m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+ m_dma += COMPLETION_CODE_SIZE;
+ size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+ (uint8_t *)m_vaddr;
+
+ c_vaddr = (uint8_t *)m_vaddr + size;
+ c_dma = m_dma + size;
+ size += sizeof(cpt_res_s_t);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* Reserve memory for cpt request info */
+ req = m_vaddr;
+
+ size = sizeof(struct cpt_request_info);
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* Initialising ctrl and opcode
+ * fields for cpt request
+ */
+
+ req->se_req = SE_CORE_REQ;
+ req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+ opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+ /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+ opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+ (0 << 3) | (flags & 0x7));
+
+ if (flags == 0x1) {
+ /*
+ * Microcode expects offsets in bytes
+ * TODO: Rounding off
+ */
+ auth_data_len = AUTH_DLEN(d_lens);
+
+ /* EIA3 or UIA2 */
+ auth_offset = AUTH_OFFSET(d_offs);
+ auth_offset = auth_offset / 8;
+
+ /* consider iv len */
+ auth_offset += iv_len;
+
+ inputlen = auth_offset +
+ (RTE_ALIGN(auth_data_len, 8) / 8);
+ outputlen = mac_len;
+
+ offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
+
+ } else {
+ /* EEA3 or UEA2 */
+ /*
+ * Microcode expects offsets in bytes
+ * TODO: Rounding off
+ */
+ encr_data_len = ENCR_DLEN(d_lens);
+
+
+ encr_offset = ENCR_OFFSET(d_offs);
+ encr_offset = encr_offset / 8;
+ /* consider iv len */
+ encr_offset += iv_len;
+
+ inputlen = encr_offset +
+ (RTE_ALIGN(encr_data_len, 8) / 8);
+ outputlen = inputlen;
+
+ /* iv offset is 0 */
+ offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+ }
+
+ /* IV */
+ iv_s = (flags == 0x1) ? params->auth_iv_buf :
+ params->iv_buf;
+
+ if (snow3g) {
+ /*
+ * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+ * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+ */
+
+ for (j = 0; j < 4; j++)
+ iv[j] = iv_s[3 - j];
+ } else {
+ /* ZUC doesn't need a swap */
+ for (j = 0; j < 4; j++)
+ iv[j] = iv_s[j];
+ }
+
+ /*
+ * GP op header, lengths are expected in bits.
+ */
+ vq_cmd_w0.u64 = 0;
+ vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+ vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+
+ /*
+ * In 83XX since we have a limitation of
+ * IV & Offset control word not part of instruction
+ * and need to be part of Data Buffer, we check if
+ * head room is there and then only do the Direct mode processing
+ */
+ if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+ (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+ void *dm_vaddr = params->bufs[0].vaddr;
+ uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+ /*
+ * This flag indicates that there is 24 bytes head room and
+ * 8 bytes tail room available, so that we get to do
+ * DIRECT MODE with limitation
+ */
+
+ offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+ OFF_CTRL_LEN - iv_len);
+ offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+ /* DPTR */
+ req->ist.ei1 = offset_dma;
+ /* RPTR should just exclude offset control word */
+ req->ist.ei2 = dm_dma_addr - iv_len;
+ req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+ + outputlen - iv_len);
+
+ vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+ vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+ if (likely(iv_len)) {
+ uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+ + OFF_CTRL_LEN);
+ memcpy(iv_d, iv, 16);
+ }
+
+ *offset_vaddr = offset_ctrl;
+ } else {
+ uint32_t i, g_size_bytes, s_size_bytes;
+ uint64_t dptr_dma, rptr_dma;
+ sg_comp_t *gather_comp;
+ sg_comp_t *scatter_comp;
+ uint8_t *in_buffer;
+ uint32_t *iv_d;
+
+ /*save space for iv */
+ offset_vaddr = m_vaddr;
+ offset_dma = m_dma;
+
+ m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+ m_dma += OFF_CTRL_LEN + iv_len;
+ m_size -= OFF_CTRL_LEN + iv_len;
+
+ opcode.s.major |= CPT_DMA_MODE;
+
+ vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+ /* DPTR has SG list */
+ in_buffer = m_vaddr;
+ dptr_dma = m_dma;
+
+ ((uint16_t *)in_buffer)[0] = 0;
+ ((uint16_t *)in_buffer)[1] = 0;
+
+ /* TODO Add error check if space will be sufficient */
+ gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+ /*
+ * Input Gather List
+ */
+ i = 0;
+
+ /* Offset control word followed by iv */
+
+ i = fill_sg_comp(gather_comp, i, offset_dma,
+ offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+ /* iv offset is 0 */
+ *offset_vaddr = offset_ctrl;
+
+ iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+ memcpy(iv_d, iv, 16);
+
+ /* input data */
+ size = inputlen - iv_len;
+ if (size) {
+
+ i = fill_sg_comp_from_iov(gather_comp, i,
+ params->src_iov,
+ 0, &size, NULL, 0);
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+ g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ /*
+ * Output Scatter List
+ */
+
+ i = 0;
+ scatter_comp =
+ (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+ if (flags == 0x1) {
+ /* IV in SLIST only for EEA3 & UEA2 */
+ iv_len = 0;
+ }
+
+ if (iv_len) {
+ i = fill_sg_comp(scatter_comp, i,
+ offset_dma + OFF_CTRL_LEN,
+ (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+ iv_len);
+ }
+
+ /* Add output data */
+ if (req_flags & VALID_MAC_BUF) {
+ size = outputlen - iv_len - mac_len;
+ if (size) {
+ i = fill_sg_comp_from_iov(scatter_comp, i,
+ params->dst_iov, 0,
+ &size, NULL, 0);
+
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+
+ /* mac data */
+ if (mac_len) {
+ i = fill_sg_comp_from_buf(scatter_comp, i,
+ ¶ms->mac_buf);
+ }
+ } else {
+ /* Output including mac */
+ size = outputlen - iv_len;
+ if (size) {
+ i = fill_sg_comp_from_iov(scatter_comp, i,
+ params->dst_iov, 0,
+ &size, NULL, 0);
+
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ }
+ ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+ s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+ /* This is DPTR len incase of SG mode */
+ vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* cpt alternate completion address saved earlier */
+ req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+ *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+ rptr_dma = c_dma - 8;
+
+ req->ist.ei1 = dptr_dma;
+ req->ist.ei2 = rptr_dma;
+ }
+
+ /* First 16-bit swap then 64-bit swap */
+ /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+ * to eliminate all the swapping
+ */
+ vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+ /* vq command w3 */
+ vq_cmd_w3.u64 = 0;
+ vq_cmd_w3.s.grp = 0;
+ vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+ offsetof(struct cpt_ctx, zs_ctx);
+
+ /* 16 byte aligned cpt res address */
+ req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+ *req->completion_addr = COMPLETION_CODE_INIT;
+ req->comp_baddr = c_dma;
+
+ /* Fill microcode part of instruction */
+ req->ist.ei0 = vq_cmd_w0.u64;
+ req->ist.ei3 = vq_cmd_w3.u64;
+
+ req->op = op;
+
+ *prep_req = req;
+ return 0;
+}
+
+static __rte_always_inline int
+cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
+ uint64_t d_offs,
+ uint64_t d_lens,
+ fc_params_t *params,
+ void *op,
+ void **prep_req)
+{
+ uint32_t size;
+ int32_t inputlen = 0, outputlen;
+ struct cpt_ctx *cpt_ctx;
+ uint8_t snow3g, iv_len = 16;
+ struct cpt_request_info *req;
+ buf_ptr_t *buf_p;
+ uint32_t encr_offset;
+ uint32_t encr_data_len;
+ int flags, m_size;
+ void *m_vaddr, *c_vaddr;
+ uint64_t m_dma, c_dma;
+ uint64_t *offset_vaddr, offset_dma;
+ uint32_t *iv_s, iv[4], j;
+ vq_cmd_word0_t vq_cmd_w0;
+ vq_cmd_word3_t vq_cmd_w3;
+ opcode_info_t opcode;
+
+ (void)req_flags;
+ buf_p = ¶ms->meta_buf;
+ m_vaddr = buf_p->vaddr;
+ m_dma = buf_p->dma_addr;
+ m_size = buf_p->size;
+
+ /*
+ * Microcode expects offsets in bytes
+ * TODO: Rounding off
+ */
+ encr_offset = ENCR_OFFSET(d_offs) / 8;
+ encr_data_len = ENCR_DLEN(d_lens);
+
+ cpt_ctx = params->ctx_buf.vaddr;
+ flags = cpt_ctx->zsk_flags;
+ snow3g = cpt_ctx->snow3g;
+ /*
+ * Save initial space that followed app data for completion code &
+ * alternate completion code to fall in same cache line as app data
+ */
+ m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+ m_dma += COMPLETION_CODE_SIZE;
+ size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+ (uint8_t *)m_vaddr;
+
+ c_vaddr = (uint8_t *)m_vaddr + size;
+ c_dma = m_dma + size;
+ size += sizeof(cpt_res_s_t);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* Reserve memory for cpt request info */
+ req = m_vaddr;
+
+ size = sizeof(struct cpt_request_info);
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* Initialising ctrl and opcode
+ * fields for cpt request
+ */
+
+ req->se_req = SE_CORE_REQ;
+ req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+ opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+ /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+ opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+ (0 << 3) | (flags & 0x7));
+
+ /* consider iv len */
+ encr_offset += iv_len;
+
+ inputlen = encr_offset +
+ (RTE_ALIGN(encr_data_len, 8) / 8);
+ outputlen = inputlen;
+
+ /* IV */
+ iv_s = params->iv_buf;
+ if (snow3g) {
+ /*
+ * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+ * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+ */
+
+ for (j = 0; j < 4; j++)
+ iv[j] = iv_s[3 - j];
+ } else {
+ /* ZUC doesn't need a swap */
+ for (j = 0; j < 4; j++)
+ iv[j] = iv_s[j];
+ }
+
+ /*
+ * GP op header, lengths are expected in bits.
+ */
+ vq_cmd_w0.u64 = 0;
+ vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+
+ /*
+ * In 83XX since we have a limitation of
+ * IV & Offset control word not part of instruction
+ * and need to be part of Data Buffer, we check if
+ * head room is there and then only do the Direct mode processing
+ */
+ if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+ (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+ void *dm_vaddr = params->bufs[0].vaddr;
+ uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+ /*
+ * This flag indicates that there is 24 bytes head room and
+ * 8 bytes tail room available, so that we get to do
+ * DIRECT MODE with limitation
+ */
+
+ offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+ OFF_CTRL_LEN - iv_len);
+ offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+ /* DPTR */
+ req->ist.ei1 = offset_dma;
+ /* RPTR should just exclude offset control word */
+ req->ist.ei2 = dm_dma_addr - iv_len;
+ req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+ + outputlen - iv_len);
+
+ vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+ vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+ if (likely(iv_len)) {
+ uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+ + OFF_CTRL_LEN);
+ memcpy(iv_d, iv, 16);
+ }
+
+ /* iv offset is 0 */
+ *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+ } else {
+ uint32_t i, g_size_bytes, s_size_bytes;
+ uint64_t dptr_dma, rptr_dma;
+ sg_comp_t *gather_comp;
+ sg_comp_t *scatter_comp;
+ uint8_t *in_buffer;
+ uint32_t *iv_d;
+
+ /* save space for offset and iv... */
+ offset_vaddr = m_vaddr;
+ offset_dma = m_dma;
+
+ m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+ m_dma += OFF_CTRL_LEN + iv_len;
+ m_size -= OFF_CTRL_LEN + iv_len;
+
+ opcode.s.major |= CPT_DMA_MODE;
+
+ vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+ /* DPTR has SG list */
+ in_buffer = m_vaddr;
+ dptr_dma = m_dma;
+
+ ((uint16_t *)in_buffer)[0] = 0;
+ ((uint16_t *)in_buffer)[1] = 0;
+
+ /* TODO Add error check if space will be sufficient */
+ gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+ /*
+ * Input Gather List
+ */
+ i = 0;
+
+ /* Offset control word */
+
+ /* iv offset is 0 */
+ *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+
+ i = fill_sg_comp(gather_comp, i, offset_dma, offset_vaddr,
+ OFF_CTRL_LEN + iv_len);
+
+ iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+ memcpy(iv_d, iv, 16);
+
+ /* Add input data */
+ size = inputlen - iv_len;
+ if (size) {
+ i = fill_sg_comp_from_iov(gather_comp, i,
+ params->src_iov,
+ 0, &size, NULL, 0);
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+ g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ /*
+ * Output Scatter List
+ */
+
+ i = 0;
+ scatter_comp =
+ (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+ /* IV */
+ i = fill_sg_comp(scatter_comp, i,
+ offset_dma + OFF_CTRL_LEN,
+ (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+ iv_len);
+
+ /* Add output data */
+ size = outputlen - iv_len;
+ if (size) {
+ i = fill_sg_comp_from_iov(scatter_comp, i,
+ params->dst_iov, 0,
+ &size, NULL, 0);
+
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+ s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+ /* This is DPTR len incase of SG mode */
+ vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* cpt alternate completion address saved earlier */
+ req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+ *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+ rptr_dma = c_dma - 8;
+
+ req->ist.ei1 = dptr_dma;
+ req->ist.ei2 = rptr_dma;
+ }
+
+ /* First 16-bit swap then 64-bit swap */
+ /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+ * to eliminate all the swapping
+ */
+ vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+ /* vq command w3 */
+ vq_cmd_w3.u64 = 0;
+ vq_cmd_w3.s.grp = 0;
+ vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+ offsetof(struct cpt_ctx, zs_ctx);
+
+ /* 16 byte aligned cpt res address */
+ req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+ *req->completion_addr = COMPLETION_CODE_INIT;
+ req->comp_baddr = c_dma;
+
+ /* Fill microcode part of instruction */
+ req->ist.ei0 = vq_cmd_w0.u64;
+ req->ist.ei3 = vq_cmd_w3.u64;
+
+ req->op = op;
+
+ *prep_req = req;
+ return 0;
+}
+
static __rte_always_inline void *
cpt_fc_dec_hmac_prep(uint32_t flags,
uint64_t d_offs,
@@ -1181,6 +1793,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,
if (likely(fc_type == FC_GEN)) {
ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
fc_params, op, &prep_req);
+ } else if (fc_type == ZUC_SNOW3G) {
+ ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
+ fc_params, op, &prep_req);
} else {
/*
* For AUTH_ONLY case,
@@ -1211,6 +1826,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
if (likely(fc_type == FC_GEN)) {
ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
fc_params, op, &prep_req);
+ } else if (fc_type == ZUC_SNOW3G) {
+ ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
+ fc_params, op, &prep_req);
} else {
ret = ERR_EIO;
}
--
2.7.4