[dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver

[dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver

[Anoob Joseph]

Ankur Dwivedi (4):
  crypto/cpt/base: add hardware enq/deq API for CPT
  crypto/cpt/base: add sym crypto session init API for CPT
  crypto/cpt/base: add sym crypto request prepare for CPT
  crypto/cpt: build with meson

Murthy NSSR (3):
  crypto/cpt/base: add request prepare API for ZUC and SNOW3G
  crypto/cpt/base: add request prepare API for Kasumi
  crypto/cpt/base: add prepare request API for HASH and HMAC

Nithin Dabilpuram (3):
  config: add Cavium CPT PMD skeleton
  crypto/cpt/base: add hardware definitions Cavium CPT
  crypto/cpt/base: add hardware initialization API for CPT

Ragothaman Jayaraman (3):
  crypto/cpt: adds the session related function callbacks
  crypto/cpt: adds the enqueue and dequeue callbacks
  doc: add Cavium's CPT guide

Srisivasubramanian Srinivasan (3):
  crypto/cpt: add driver initializations
  crypto/cpt: add the basic device callback functions
  crypto/cpt: adds some more callback functions for CPT

 MAINTAINERS                                |    7 +
 config/common_base                         |    8 +
 doc/guides/cryptodevs/cpt.rst              |  112 ++
 drivers/crypto/Makefile                    |    1 +
 drivers/crypto/cpt/Makefile                |   49 +
 drivers/crypto/cpt/base/cpt.h              |  231 +++
 drivers/crypto/cpt/base/cpt8xxx_device.c   |  200 ++
 drivers/crypto/cpt/base/cpt8xxx_device.h   |   85 +
 drivers/crypto/cpt/base/cpt_debug.h        |  231 +++
 drivers/crypto/cpt/base/cpt_device.c       |  383 ++++
 drivers/crypto/cpt/base/cpt_device.h       |  162 ++
 drivers/crypto/cpt/base/cpt_hw_types.h     |  836 +++++++++
 drivers/crypto/cpt/base/cpt_ops.c          | 2756 ++++++++++++++++++++++++++++
 drivers/crypto/cpt/base/cpt_request_mgr.c  |  424 +++++
 drivers/crypto/cpt/base/cpt_request_mgr.h  |   75 +
 drivers/crypto/cpt/base/cpt_vf_mbox.c      |  176 ++
 drivers/crypto/cpt/base/cpt_vf_mbox.h      |   60 +
 drivers/crypto/cpt/base/mcode_defines.h    |  215 +++
 drivers/crypto/cpt/cpt_pmd_cryptodev.c     |  271 +++
 drivers/crypto/cpt/cpt_pmd_logs.h          |   50 +
 drivers/crypto/cpt/cpt_pmd_ops.c           | 1936 +++++++++++++++++++
 drivers/crypto/cpt/cpt_pmd_ops.h           |   96 +
 drivers/crypto/cpt/meson.build             |   16 +
 drivers/crypto/cpt/rte_pmd_cpt_version.map |    4 +
 drivers/crypto/meson.build                 |    2 +-
 mk/rte.app.mk                              |    2 +-
 26 files changed, 8386 insertions(+), 2 deletions(-)
 create mode 100644 doc/guides/cryptodevs/cpt.rst
 create mode 100644 drivers/crypto/cpt/Makefile
 create mode 100644 drivers/crypto/cpt/base/cpt.h
 create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.c
 create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.h
 create mode 100644 drivers/crypto/cpt/base/cpt_debug.h
 create mode 100644 drivers/crypto/cpt/base/cpt_device.c
 create mode 100644 drivers/crypto/cpt/base/cpt_device.h
 create mode 100644 drivers/crypto/cpt/base/cpt_hw_types.h
 create mode 100644 drivers/crypto/cpt/base/cpt_ops.c
 create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.c
 create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.h
 create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.c
 create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.h
 create mode 100644 drivers/crypto/cpt/base/mcode_defines.h
 create mode 100644 drivers/crypto/cpt/cpt_pmd_cryptodev.c
 create mode 100644 drivers/crypto/cpt/cpt_pmd_logs.h
 create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.c
 create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.h
 create mode 100644 drivers/crypto/cpt/meson.build
 create mode 100644 drivers/crypto/cpt/rte_pmd_cpt_version.map

-- 
2.7.4

[dpdk-dev] [PATCH 01/16] config: add Cavium CPT PMD skeleton

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>

Add makefile and config file options.
Also add version map file and maintainers file to
claim responsibility.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 MAINTAINERS                                |  7 ++++++
 config/common_base                         |  8 ++++++
 drivers/crypto/Makefile                    |  1 +
 drivers/crypto/cpt/Makefile                | 40 ++++++++++++++++++++++++++++++
 drivers/crypto/cpt/rte_pmd_cpt_version.map |  4 +++
 mk/rte.app.mk                              |  2 +-
 6 files changed, 61 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/cpt/Makefile
 create mode 100644 drivers/crypto/cpt/rte_pmd_cpt_version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 4667fa7..1b4a8eb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -504,6 +504,13 @@ F: drivers/net/octeontx/
 F: doc/guides/nics/octeontx.rst
 F: doc/guides/nics/features/octeontx.ini
 
+Cavium CPT
+M: Ankur Dwivedi <ankur.dwivedi@cavium.com>
+M: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
+M: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
+F: drivers/crypto/cpt/
+F: doc/guides/cryptodevs/cpt.rst
+
 Chelsio cxgbe
 M: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
 F: drivers/net/cxgbe/
diff --git a/config/common_base b/config/common_base
index 6b0d1cb..85e03a8 100644
--- a/config/common_base
+++ b/config/common_base
@@ -631,6 +631,14 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
 CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
 
 #
+# Compile PMD for Cavium CPT Crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_CPT=n
+CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_INIT=n
+CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_TX=n
+
+#
 # Compile raw device support
 # EXPERIMENTAL: API may change without prior notice
 #
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 1d0c88e..a0515f3 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -22,5 +22,6 @@ ifeq ($(CONFIG_RTE_LIBRTE_DPAA_BUS),y)
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC) += dpaa_sec
 endif
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += virtio
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt
 
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile
new file mode 100644
index 0000000..b2d950d
--- /dev/null
+++ b/drivers/crypto/cpt/Makefile
@@ -0,0 +1,40 @@
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_cptvf.a
+
+# library version
+LIBABIVER := 1
+
+# build flags
+CFLAGS += $(WERROR_FLAGS)
+
+# external library include paths
+CFLAGS += -I$(LIBCRYPTO_THUNDERX_PATH)/include
+LDLIBS += -L$(LIBCRYPTO_THUNDERX_PATH) -lcrypto
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_cryptodev
+LDLIBS += -lrte_pci -lrte_bus_pci
+
+VPATH += $(RTE_SDK)/drivers/crypto/cpt/base
+
+CFLAGS += -O3
+#CFLAGS += -DAUTH_SOFT_COMPUTE_IPAD_OPAD
+#CFLAGS += -DCPT_DEBUG
+
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) +=
+
+# export include files
+SYMLINK-y-include +=
+
+# versioning export map
+EXPORT_MAP := rte_pmd_cpt_version.map
+
+# library dependencies
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_eal
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_cryptodev
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_mempool lib/librte_mbuf
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_malloc
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/cpt/rte_pmd_cpt_version.map b/drivers/crypto/cpt/rte_pmd_cpt_version.map
new file mode 100644
index 0000000..9b9ab1a
--- /dev/null
+++ b/drivers/crypto/cpt/rte_pmd_cpt_version.map
@@ -0,0 +1,4 @@
+DPDK_18.05 {
+
+	local: *;
+};
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 1e32c83..158066d 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -209,7 +209,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC)   += -lrte_pmd_dpaa_sec
 endif # CONFIG_RTE_LIBRTE_DPAA_BUS
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += -lrte_pmd_virtio_crypto
 endif # CONFIG_RTE_LIBRTE_CRYPTODEV
-
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CPT)   += -lrte_pmd_cptvf
 ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lrte_pmd_isal_comp
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lisal
-- 
1.9.3

Re: [dpdk-dev] [PATCH 01/16] config: add Cavium CPT PMD skeleton

[Jerin Jacob]

-----Original Message-----
> Date: Fri,  8 Jun 2018 22:15:10 +0530
> From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> To: Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara
>  <pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>
> Cc: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>, Ankur Dwivedi
>  <ankur.dwivedi@cavium.com>, Jerin Jacob <jerin.jacob@caviumnetworks.com>,
>  Murthy NSSR <Nidadavolu.Murthy@cavium.com>, Narayana Prasad
>  <narayanaprasad.athreya@caviumnetworks.com>, Ragothaman Jayaraman
>  <Ragothaman.Jayaraman@cavium.com>, Srisivasubramanian Srinivasan
>  <Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org
> Subject: [PATCH 01/16] config: add Cavium CPT PMD skeleton
> X-Mailer: git-send-email 2.7.4
> 
> From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> 
> Add makefile and config file options.
> Also add version map file and maintainers file to
> claim responsibility.
> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
> ---
>  MAINTAINERS                                |  7 ++++++
>  config/common_base                         |  8 ++++++
>  drivers/crypto/Makefile                    |  1 +
>  drivers/crypto/cpt/Makefile                | 40 ++++++++++++++++++++++++++++++
>  drivers/crypto/cpt/rte_pmd_cpt_version.map |  4 +++
>  mk/rte.app.mk                              |  2 +-
>  6 files changed, 61 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/crypto/cpt/Makefile
>  create mode 100644 drivers/crypto/cpt/rte_pmd_cpt_version.map
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4667fa7..1b4a8eb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -504,6 +504,13 @@ F: drivers/net/octeontx/
>  F: doc/guides/nics/octeontx.rst
>  F: doc/guides/nics/features/octeontx.ini
>  
> +Cavium CPT
> +M: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> +M: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> +M: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> +F: drivers/crypto/cpt/
> +F: doc/guides/cryptodevs/cpt.rst

Move this under crypto drivers section if it is not already the case.

> +
>  Chelsio cxgbe
>  M: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
>  F: drivers/net/cxgbe/
> diff --git a/config/common_base b/config/common_base
> index 6b0d1cb..85e03a8 100644
> --- a/config/common_base
> +++ b/config/common_base
> @@ -631,6 +631,14 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
>  CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
>  
>  #
> +# Compile PMD for Cavium CPT Crypto device
> +#
> +CONFIG_RTE_LIBRTE_PMD_CPT=n

Please enable this option  by default, If there are arm64 specific 
usage then please stub it out so that it can compile on 
all architectures. It will help to verify the API changes
across the architecture by author.(i.e author should not depend arm64
box to verify the compilation changes)
and enable distribution OS support like Ubuntu as they building with
default arm64 config.


> +CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_INIT=n
> +CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_RX=n
> +CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_TX=n

This config option is not required when we are using
dynamic debugging

> +
> +#
>  # Compile raw device support
>  # EXPERIMENTAL: API may change without prior notice
>  #
> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
> index 1d0c88e..a0515f3 100644
> --- a/drivers/crypto/Makefile
> +++ b/drivers/crypto/Makefile
> @@ -22,5 +22,6 @@ ifeq ($(CONFIG_RTE_LIBRTE_DPAA_BUS),y)
>  DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC) += dpaa_sec
>  endif
>  DIRS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += virtio
> +DIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt
>  
>  include $(RTE_SDK)/mk/rte.subdir.mk
> diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile
> new file mode 100644
> index 0000000..b2d950d
> --- /dev/null
> +++ b/drivers/crypto/cpt/Makefile
> @@ -0,0 +1,40 @@
> +
> +include $(RTE_SDK)/mk/rte.vars.mk
> +
> +# library name
> +LIB = librte_pmd_cptvf.a
> +
> +# library version
> +LIBABIVER := 1
> +
> +# build flags
> +CFLAGS += $(WERROR_FLAGS)
> +
> +# external library include paths
> +CFLAGS += -I$(LIBCRYPTO_THUNDERX_PATH)/include
> +LDLIBS += -L$(LIBCRYPTO_THUNDERX_PATH) -lcrypto

What is the external library dependency here? Does look like
it is documented in doc patch.

If there is something, I think, better to change LIBCRYPTO_THUNDERX_PATH
to LIBCRYPTO_OCTEONTX_PATH

> +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
> +LDLIBS += -lrte_cryptodev
> +LDLIBS += -lrte_pci -lrte_bus_pci
> +
> +VPATH += $(RTE_SDK)/drivers/crypto/cpt/base
> +
> +CFLAGS += -O3
> +#CFLAGS += -DAUTH_SOFT_COMPUTE_IPAD_OPAD
> +#CFLAGS += -DCPT_DEBUG

Remove commented out stuff.

> +
> +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) +=
> +
> +# export include files
> +SYMLINK-y-include +=
> +
> +# versioning export map
> +EXPORT_MAP := rte_pmd_cpt_version.map
> +
> +# library dependencies
> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_eal
> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_cryptodev
> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_mempool lib/librte_mbuf
> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_malloc
> +
> +include $(RTE_SDK)/mk/rte.lib.mk
> diff --git a/drivers/crypto/cpt/rte_pmd_cpt_version.map b/drivers/crypto/cpt/rte_pmd_cpt_version.map
> new file mode 100644
> index 0000000..9b9ab1a
> --- /dev/null
> +++ b/drivers/crypto/cpt/rte_pmd_cpt_version.map
> @@ -0,0 +1,4 @@
> +DPDK_18.05 {
> +
> +	local: *;
> +};
> diff --git a/mk/rte.app.mk b/mk/rte.app.mk
> index 1e32c83..158066d 100644
> --- a/mk/rte.app.mk
> +++ b/mk/rte.app.mk
> @@ -209,7 +209,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC)   += -lrte_pmd_dpaa_sec
>  endif # CONFIG_RTE_LIBRTE_DPAA_BUS
>  _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += -lrte_pmd_virtio_crypto
>  endif # CONFIG_RTE_LIBRTE_CRYPTODEV
> -
> +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CPT)   += -lrte_pmd_cptvf
>  ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
>  _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lrte_pmd_isal_comp
>  _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lisal


You can add meson build as well here on the same patch.


> -- 
> 1.9.3
> 

Re: [dpdk-dev] [PATCH 01/16] config: add Cavium CPT PMD skeleton

[De Lara Guarch, Pablo]

Hi Anoob,

> -----Original Message-----
> From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com]
> Sent: Thursday, June 14, 2018 3:57 AM
> To: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> Cc: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Thomas Monjalon
> <thomas@monjalon.net>; Nithin Dabilpuram <nithin.dabilpuram@cavium.com>;
> Ankur Dwivedi <ankur.dwivedi@cavium.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> Subject: Re: [PATCH 01/16] config: add Cavium CPT PMD skeleton
> 
> -----Original Message-----
> > Date: Fri,  8 Jun 2018 22:15:10 +0530
> > From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> > To: Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara
> > <pablo.de.lara.guarch@intel.com>, Thomas Monjalon
> > <thomas@monjalon.net>
> > Cc: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>, Ankur Dwivedi
> > <ankur.dwivedi@cavium.com>, Jerin Jacob
> > <jerin.jacob@caviumnetworks.com>,  Murthy NSSR
> > <Nidadavolu.Murthy@cavium.com>, Narayana Prasad
> > <narayanaprasad.athreya@caviumnetworks.com>, Ragothaman Jayaraman
> > <Ragothaman.Jayaraman@cavium.com>, Srisivasubramanian Srinivasan
> > <Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org
> > Subject: [PATCH 01/16] config: add Cavium CPT PMD skeleton
> > X-Mailer: git-send-email 2.7.4
> >
> > From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> >
> > Add makefile and config file options.
> > Also add version map file and maintainers file to claim
> > responsibility.
> >
> > Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> > Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> > Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> > Signed-off-by: Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>
> > Signed-off-by: Srisivasubramanian Srinivasan
> > <Srisivasubramanian.Srinivasan@cavium.com>
> > ---
> >  MAINTAINERS                                |  7 ++++++
> >  config/common_base                         |  8 ++++++
> >  drivers/crypto/Makefile                    |  1 +
> >  drivers/crypto/cpt/Makefile                | 40
> ++++++++++++++++++++++++++++++
> >  drivers/crypto/cpt/rte_pmd_cpt_version.map |  4 +++
> >  mk/rte.app.mk                              |  2 +-
> >  6 files changed, 61 insertions(+), 1 deletion(-)  create mode 100644
> > drivers/crypto/cpt/Makefile  create mode 100644
> > drivers/crypto/cpt/rte_pmd_cpt_version.map
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index 4667fa7..1b4a8eb 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -504,6 +504,13 @@ F: drivers/net/octeontx/
> >  F: doc/guides/nics/octeontx.rst
> >  F: doc/guides/nics/features/octeontx.ini
> >
> > +Cavium CPT
> > +M: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> > +M: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> > +M: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> > +F: drivers/crypto/cpt/
> > +F: doc/guides/cryptodevs/cpt.rst

Add the documentation file line in the patch where you actually add it.

> 
> Move this under crypto drivers section if it is not already the case.
> 
> > +
> >  Chelsio cxgbe
> >  M: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
> >  F: drivers/net/cxgbe/
> > diff --git a/config/common_base b/config/common_base index
> > 6b0d1cb..85e03a8 100644
> > --- a/config/common_base
> > +++ b/config/common_base
> > @@ -631,6 +631,14 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
> >  CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
> >
> >  #
> > +# Compile PMD for Cavium CPT Crypto device #
> > +CONFIG_RTE_LIBRTE_PMD_CPT=n
> 
> Please enable this option  by default, If there are arm64 specific usage then
> please stub it out so that it can compile on all architectures. It will help to verify
> the API changes across the architecture by author.(i.e author should not depend
> arm64 box to verify the compilation changes) and enable distribution OS support
> like Ubuntu as they building with default arm64 config.

Agreed. Actually, I thought this was disabled because of the dependency with libcrypto
(based on the Makefile below), but actually it is not needed.
Also, move this where the other crypto drivers are.

> 
> 
> > +CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_INIT=n
> > +CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_RX=n
> > +CONFIG_RTE_LIBRTE_PMD_CPT_DEBUG_TX=n
> 
> This config option is not required when we are using dynamic debugging
> 
> > +
> > +#
> >  # Compile raw device support
> >  # EXPERIMENTAL: API may change without prior notice  # diff --git
> > a/drivers/crypto/Makefile b/drivers/crypto/Makefile index
> > 1d0c88e..a0515f3 100644
> > --- a/drivers/crypto/Makefile
> > +++ b/drivers/crypto/Makefile
> > @@ -22,5 +22,6 @@ ifeq ($(CONFIG_RTE_LIBRTE_DPAA_BUS),y)
> >  DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC) += dpaa_sec  endif
> >  DIRS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += virtio
> > +DIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt
> >
> >  include $(RTE_SDK)/mk/rte.subdir.mk
> > diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile
> > new file mode 100644 index 0000000..b2d950d
> > --- /dev/null
> > +++ b/drivers/crypto/cpt/Makefile
> > @@ -0,0 +1,40 @@
> > +
> > +include $(RTE_SDK)/mk/rte.vars.mk
> > +
> > +# library name
> > +LIB = librte_pmd_cptvf.a
> > +
> > +# library version
> > +LIBABIVER := 1
> > +
> > +# build flags
> > +CFLAGS += $(WERROR_FLAGS)
> > +
> > +# external library include paths
> > +CFLAGS += -I$(LIBCRYPTO_THUNDERX_PATH)/include
> > +LDLIBS += -L$(LIBCRYPTO_THUNDERX_PATH) -lcrypto
> 
> What is the external library dependency here? Does look like it is documented in
> doc patch.
> 
> If there is something, I think, better to change LIBCRYPTO_THUNDERX_PATH to
> LIBCRYPTO_OCTEONTX_PATH

Is this needed? I don't see any dependency with libcrypto and I don't see this variable
documented in the driver guide.

> 
> > +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring LDLIBS +=
> > +-lrte_cryptodev LDLIBS += -lrte_pci -lrte_bus_pci
> > +
> > +VPATH += $(RTE_SDK)/drivers/crypto/cpt/base
> > +
> > +CFLAGS += -O3
> > +#CFLAGS += -DAUTH_SOFT_COMPUTE_IPAD_OPAD #CFLAGS += -
> DCPT_DEBUG
> 
> Remove commented out stuff.
> 
> > +
> > +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) +=
> > +
> > +# export include files
> > +SYMLINK-y-include +=
> > +
> > +# versioning export map
> > +EXPORT_MAP := rte_pmd_cpt_version.map
> > +
> > +# library dependencies
> > +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_eal
> > +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_cryptodev
> > +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_mempool
> > +lib/librte_mbuf
> > +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += lib/librte_malloc
> > +
> > +include $(RTE_SDK)/mk/rte.lib.mk
> > diff --git a/drivers/crypto/cpt/rte_pmd_cpt_version.map
> > b/drivers/crypto/cpt/rte_pmd_cpt_version.map
> > new file mode 100644
> > index 0000000..9b9ab1a
> > --- /dev/null
> > +++ b/drivers/crypto/cpt/rte_pmd_cpt_version.map
> > @@ -0,0 +1,4 @@
> > +DPDK_18.05 {
> > +

DPDK_18.08.

> > +	local: *;
> > +};
> > diff --git a/mk/rte.app.mk b/mk/rte.app.mk index 1e32c83..158066d
> > 100644
> > --- a/mk/rte.app.mk
> > +++ b/mk/rte.app.mk
> > @@ -209,7 +209,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC)   +=
> -lrte_pmd_dpaa_sec
> >  endif # CONFIG_RTE_LIBRTE_DPAA_BUS
> >  _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) +=
> > -lrte_pmd_virtio_crypto  endif # CONFIG_RTE_LIBRTE_CRYPTODEV
> > -
> > +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CPT)   += -lrte_pmd_cptvf

This should be inside ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y).

> >  ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
> >  _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lrte_pmd_isal_comp
> >  _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lisal
> 
> 
> You can add meson build as well here on the same patch.
> 
> 
> > --
> > 1.9.3
> >

[dpdk-dev] [PATCH 02/16] crypto/cpt/base: add hardware definitions Cavium CPT

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>

Adds hardware specific definitions for Cavium CPT device.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/base/cpt_hw_types.h  | 836 ++++++++++++++++++++++++++++++++
 drivers/crypto/cpt/base/mcode_defines.h | 215 ++++++++
 2 files changed, 1051 insertions(+)
 create mode 100644 drivers/crypto/cpt/base/cpt_hw_types.h
 create mode 100644 drivers/crypto/cpt/base/mcode_defines.h

diff --git a/drivers/crypto/cpt/base/cpt_hw_types.h b/drivers/crypto/cpt/base/cpt_hw_types.h
new file mode 100644
index 0000000..b4b2af1
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt_hw_types.h
@@ -0,0 +1,836 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __CPT_HW_TYPES_H
+#define __CPT_HW_TYPES_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <string.h>
+
+#define CPT_INST_SIZE	            (64)
+#define CPT_VQ_CHUNK_ALIGN	        (128) /**< 128 byte align */
+#define CPT_NEXT_CHUNK_PTR_SIZE     (8)
+#define CPT_INST_CHUNK_MAX_SIZE     (1023)
+
+#define CPT_PF_VF_MAILBOX_SIZE		(2)
+
+#define CPT_VF_INTR_MBOX_MASK   (1<<0)
+#define CPT_VF_INTR_DOVF_MASK   (1<<1)
+#define CPT_VF_INTR_IRDE_MASK   (1<<2)
+#define CPT_VF_INTR_NWRP_MASK   (1<<3)
+#define CPT_VF_INTR_SWERR_MASK  (1<<4)
+#define CPT_VF_INTR_HWERR_MASK  (1<<5)
+#define CPT_VF_INTR_FAULT_MASK  (1<<6)
+
+/*
+ * CPT_INST_S software command definitions
+ * Words EI (0-3)
+ */
+typedef union {
+	uint64_t u64;
+	struct {
+		uint16_t opcode;
+		uint16_t param1;
+		uint16_t param2;
+		uint16_t dlen;
+	} s;
+} vq_cmd_word0_t;
+
+typedef union {
+	uint64_t u64;
+	struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+		uint64_t grp	: 3;
+		uint64_t cptr	: 61;
+#else
+		uint64_t cptr	: 61;
+		uint64_t grp	: 3;
+#endif
+	} s;
+} vq_cmd_word3_t;
+
+typedef struct cpt_vq_command {
+	vq_cmd_word0_t cmd;
+	uint64_t dptr;
+	uint64_t rptr;
+	vq_cmd_word3_t cptr;
+} cpt_vq_cmd_t;
+
+/**
+ * Structure cpt_inst_s
+ *
+ * CPT Instruction Structure
+ * This structure specifies the instruction layout.
+ * Instructions are stored in memory
+ * as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
+ */
+typedef union cpt_inst_s {
+	uint64_t u[8];
+	struct cpt_inst_s_s {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_17_63        : 47;
+		uint64_t doneint               : 1;
+		/*< [ 16: 16] Done interrupt.
+		 * 0 = No interrupts related to this instruction.
+		 * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]
+		 * will be incremented, and based on the rules described
+		 * there an interrupt may occur.
+		 */
+		uint64_t reserved_0_15         : 16;
+#else /* Word 0 - Little Endian */
+		uint64_t reserved_0_15         : 16;
+		uint64_t doneint               : 1;
+		/*< [ 16: 16] Done interrupt.
+		 * 0 = No interrupts related to this instruction.
+		 * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]
+		 * will be incremented, and based on the rules described
+		 * there aninterrupt may occur.
+		 */
+		uint64_t reserved_17_63        : 47;
+#endif /* Word 0 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 1 - Big Endian */
+		uint64_t res_addr              : 64;
+		/*< [127: 64] Result IOVA.
+		 * If nonzero, specifies where to write CPT_RES_S.
+		 * If zero, no result structure will be written.
+		 * Address must be 16-byte aligned.
+
+		 * Bits <63:49> are ignored by hardware; software should
+		 *use a sign-extended bit <48> for forward compatibility.
+		 */
+#else /* Word 1 - Little Endian */
+		uint64_t res_addr              : 64;
+		/*< [127: 64] Result IOVA.
+		 * If nonzero, specifies where to write CPT_RES_S.
+		 * If zero, no result structure will be written.
+		 * Address must be 16-byte aligned.
+
+		 * Bits <63:49> are ignored by hardware; software should
+		 *use a sign-extended bit <48> for forward compatibility.
+		 */
+#endif /* Word 1 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 2 - Big Endian */
+		uint64_t reserved_172_191      : 20;
+		uint64_t grp                   : 10;
+		/*< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
+		 * use when CPT submits work to SSO.
+		 * For the SSO to not discard the add-work request, FPA_PF_MAP()
+		 * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
+		 */
+		uint64_t tt                    : 2;
+		/*< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
+		 * when CPT submits work to SSO.
+		 */
+		uint64_t tag                   : 32;
+		/*< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when
+		 * CPT submits work to SSO.
+		 */
+#else /* Word 2 - Little Endian */
+		uint64_t tag                   : 32;
+		/**< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when
+		 * CPT submits work to SSO.
+		 */
+		uint64_t tt                    : 2;
+		/**< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
+		 * when CPT submits work to SSO.
+		 */
+		uint64_t grp                   : 10;
+		/**< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
+		 * use when CPT submits work to SSO.
+		 * For the SSO to not discard the add-work request, FPA_PF_MAP()
+		 * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
+		 **/
+		uint64_t reserved_172_191      : 20;
+#endif /* Word 2 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 3 - Big Endian */
+		uint64_t wq_ptr                : 64;
+		/**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
+		 * work-queue entry that CPT submits work to SSO after all
+		 * context, output data, and result write operations are
+		 * visible to other CNXXXX units and the cores.
+		 * Bits <2:0> must be zero.
+		 * Bits <63:49> are ignored by hardware; software should use a
+		 * sign-extended bit <48> for forward compatibility.
+		 * Internal:Bits <63:49>, <2:0> are ignored by hardware,
+		 * treated as always 0x0.
+		 **/
+#else /* Word 3 - Little Endian */
+		uint64_t wq_ptr                : 64;
+		/**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
+		 * work-queue entry that CPT submits work to SSO after all
+		 * context, output data, and result write operations are
+		 * visible to other CNXXXX units and the cores.
+		 * Bits <2:0> must be zero.
+		 * Bits <63:49> are ignored by hardware; software should use a
+		 * sign-extended bit <48> for forward compatibility.
+		 * Internal: Bits <63:49>, <2:0> are ignored by hardware,
+		 * treated as always 0x0.
+		 **/
+#endif /* Word 3 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 4 - Big Endian */
+		union {
+			uint64_t ei0                   : 64;
+			/**< [319:256] Engine instruction word 0. Passed to the
+			 * AE/SE.
+			 **/
+			vq_cmd_word0_t vq_cmd_w0;
+		};
+#else /* Word 4 - Little Endian */
+		union {
+			uint64_t ei0                   : 64;
+			/**< [319:256] Engine instruction word 0. Passed to the
+			 * AE/SE.
+			 **/
+			vq_cmd_word0_t vq_cmd_w0;
+		};
+#endif /* Word 4 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 5 - Big Endian */
+		union {
+			uint64_t ei1                   : 64;
+			/**< [383:320] Engine instruction word 1. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t dptr;
+		};
+#else /* Word 5 - Little Endian */
+		union {
+			uint64_t ei1                   : 64;
+			/**< [383:320] Engine instruction word 1. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t dptr;
+		};
+#endif /* Word 5 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 6 - Big Endian */
+		union {
+			uint64_t ei2                   : 64;
+			/**< [447:384] Engine instruction word 2. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t rptr;
+		};
+#else /* Word 6 - Little Endian */
+		union {
+			uint64_t ei2                   : 64;
+			/**< [447:384] Engine instruction word 2. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t rptr;
+		};
+#endif /* Word 6 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 7 - Big Endian */
+		union {
+			uint64_t ei3                   : 64;
+			/**< [511:448] Engine instruction word 3. Passed to the
+			 * AE/SE.
+			 **/
+			vq_cmd_word3_t vq_cmd_w3;
+		};
+#else /* Word 7 - Little Endian */
+		union {
+			uint64_t ei3                   : 64;
+			/**< [511:448] Engine instruction word 3. Passed to the
+			 * AE/SE.
+			 **/
+			vq_cmd_word3_t vq_cmd_w3;
+		};
+#endif /* Word 7 - End */
+	} s;
+	struct cpt_inst_s_cn {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_17_63        : 47;
+		uint64_t doneint               : 1;
+		/**< [ 16: 16] Done interrupt.
+		 * 0 = No interrupts related to this instruction.
+		 * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE]
+		 * will be incremented,and based on the rules described there
+		 * an interrupt may occur.
+		 **/
+		uint64_t reserved_8_15         : 8;
+		uint64_t reserved_0_7          : 8;
+#else /* Word 0 - Little Endian */
+		uint64_t reserved_0_7          : 8;
+		uint64_t reserved_8_15         : 8;
+		uint64_t doneint               : 1;
+		/**< [ 16: 16] Done interrupt.
+		 * 0 = No interrupts related to this instruction.
+		 * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE]
+		 * will be incremented,and based on the rules described there
+		 * an interrupt may occur.
+		 **/
+		uint64_t reserved_17_63        : 47;
+#endif /* Word 0 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 1 - Big Endian */
+		uint64_t res_addr              : 64;
+		/**< [127: 64] Result IOVA.
+		 * If nonzero, specifies where to write CPT_RES_S.
+		 * If zero, no result structure will be written.
+		 * Address must be 16-byte aligned.
+		 *
+		 * Bits <63:49> are ignored by hardware; software should
+		 * use a sign-extended bit <48> for forward compatibility.
+		 **/
+#else /* Word 1 - Little Endian */
+		uint64_t res_addr              : 64;
+		/**< [127: 64] Result IOVA.
+		 * If nonzero, specifies where to write CPT_RES_S.
+		 * If zero, no result structure will be written.
+		 * Address must be 16-byte aligned.
+		 *
+		 * Bits <63:49> are ignored by hardware; software should
+		 * use a sign-extended bit <48> for forward compatibility.
+		 **/
+#endif /* Word 1 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 2 - Big Endian */
+		uint64_t reserved_172_191      : 20;
+		uint64_t grp                   : 10;
+		/**< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
+		 * use when CPT submits work to SSO. For the SSO to not discard
+		 * the add-work request, FPA_PF_MAP() must map [GRP] and
+		 * CPT()_PF_Q()_GMCTL[GMID] as valid.
+		 **/
+		uint64_t tt                    : 2;
+		/**< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
+		 * when CPT submits work to SSO.
+		 **/
+		uint64_t tag                   : 32;
+		/**< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use
+		 * when CPT submits work to SSO.
+		 **/
+#else /* Word 2 - Little Endian */
+		uint64_t tag                   : 32;
+		/**< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use
+		 * when CPT submits work to SSO.
+		 **/
+		uint64_t tt                    : 2;
+		/**< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
+		 * when CPT submits work to SSO.
+		 **/
+		uint64_t grp                   : 10;
+		/**< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
+		 * use when CPT submits work to SSO. For the SSO to not discard
+		 * the add-work request, FPA_PF_MAP() must map [GRP] and
+		 * CPT()_PF_Q()_GMCTL[GMID] as valid.
+		 **/
+		uint64_t reserved_172_191      : 20;
+#endif /* Word 2 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 3 - Big Endian */
+		uint64_t wq_ptr                : 64;
+		/**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a work
+		 * -queue entry that CPT submits work to SSO after all context,
+		 * output data, and result write operations are visible to other
+		 * CNXXXX units and the cores.
+
+		Bits <2:0> must be zero.  Bits <63:49> are ignored by hardware;
+		software should use a sign-extended bit <48> for forward
+		compatibility.
+
+Internal:
+Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.
+		 */
+#else /* Word 3 - Little Endian */
+		uint64_t wq_ptr                : 64;
+		/**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a work
+		 * -queue entry that CPT submits work to SSO after all context,
+		 * output data, and result write operations are visible to other
+		 * CNXXXX units and the cores.
+
+		Bits <2:0> must be zero.  Bits <63:49> are ignored by hardware;
+		software should use a sign-extended bit <48> for forward
+		compatibility.
+
+Internal:
+Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.
+		 */
+#endif /* Word 3 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 4 - Big Endian */
+		uint64_t ei0                   : 64;
+		/**< [319:256] Engine instruction word 0. Passed to the AE/SE.*/
+#else /* Word 4 - Little Endian */
+		uint64_t ei0                   : 64;
+		/**< [319:256] Engine instruction word 0. Passed to the AE/SE.*/
+#endif /* Word 4 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 5 - Big Endian */
+		uint64_t ei1                   : 64;
+		/**< [383:320] Engine instruction word 1. Passed to the AE/SE.*/
+#else /* Word 5 - Little Endian */
+		uint64_t ei1                   : 64;
+		/**< [383:320] Engine instruction word 1. Passed to the AE/SE.*/
+#endif /* Word 5 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 6 - Big Endian */
+		uint64_t ei2                   : 64;
+		/**< [447:384] Engine instruction word 2. Passed to the AE/SE.*/
+#else /* Word 6 - Little Endian */
+		uint64_t ei2                   : 64;
+		/**< [447:384] Engine instruction word 2. Passed to the AE/SE.*/
+#endif /* Word 6 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 7 - Big Endian */
+		uint64_t ei3                   : 64;
+		/**< [511:448] Engine instruction word 3. Passed to the AE/SE.*/
+#else /* Word 7 - Little Endian */
+		uint64_t ei3                   : 64;
+		/**< [511:448] Engine instruction word 3. Passed to the AE/SE.*/
+#endif /* Word 7 - End */
+	} cn;
+} cpt_inst_s_t;
+
+/**
+ * Structure cpt_res_s
+ *
+ * CPT Result Structure
+ * The CPT coprocessor writes the result structure after it completes a
+ * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each
+ * instruction completion produces exactly one result structure.
+ *
+ * This structure is stored in memory as little-endian unless
+ * CPT()_PF_Q()_CTL[INST_BE] is set.
+ */
+typedef union cpt_res_s {
+	uint64_t u[2];
+	struct cpt_res_s_s {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_17_63        : 47;
+		uint64_t doneint               : 1;
+		/**< [ 16: 16] Done interrupt. This bit is copied from the
+		 * corresponding instruction's CPT_INST_S[DONEINT].
+		 **/
+		uint64_t reserved_8_15         : 8;
+		uint64_t compcode              : 8;
+		/**< [  7:  0] Indicates completion/error status of the CPT
+		 * coprocessor for the associated instruction, as enumerated by
+		 * CPT_COMP_E. Core software may write the memory location
+		 * containing [COMPCODE] to 0x0 before ringing the doorbell, and
+		 * then poll for completion by checking for a nonzero value.
+
+		 Once the core observes a nonzero [COMPCODE] value in this case,
+		 the CPT coprocessor will have also completed L2/DRAM write
+		 operations.
+		  */
+#else /* Word 0 - Little Endian */
+		uint64_t compcode              : 8;
+		/**< [  7:  0] Indicates completion/error status of the CPT
+		 * coprocessor for the associated instruction, as enumerated by
+		 * CPT_COMP_E. Core software may write the memory location
+		 * containing [COMPCODE] to 0x0 before ringing the doorbell, and
+		 * then poll for completion by checking for a nonzero value.
+
+		Once the core observes a nonzero [COMPCODE] value in this case,
+		the CPT coprocessor will have also completed L2/DRAM write
+		operations.
+		 */
+		uint64_t reserved_8_15         : 8;
+		uint64_t doneint               : 1;
+		/**< [ 16: 16] Done interrupt. This bit is copied from the
+		 * corresponding instruction's CPT_INST_S[DONEINT].
+		 **/
+		uint64_t reserved_17_63        : 47;
+#endif /* Word 0 - End */
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 1 - Big Endian */
+		uint64_t reserved_64_127       : 64;
+#else /* Word 1 - Little Endian */
+		uint64_t reserved_64_127       : 64;
+#endif /* Word 1 - End */
+	} s;
+	/* struct cpt_res_s_s cn; */
+} cpt_res_s_t;
+
+/**
+ * Register (NCB) cpt#_vq#_ctl
+ *
+ * CPT VF Queue Control Registers
+ * This register configures queues. This register should be changed (other than
+ * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_ctl_s {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_1_63         : 63;
+		uint64_t ena                   : 1;
+		/**< [  0:  0](R/W/H) Enables the logical instruction queue.
+		 * See also CPT()_PF_Q()_CTL[CONT_ERR] and
+		 * CPT()_VQ()_INPROG[INFLIGHT].
+		 * 1 = Queue is enabled.
+		 * 0 = Queue is disabled.
+		 **/
+#else /* Word 0 - Little Endian */
+		uint64_t ena                   : 1;
+		/**< [  0:  0](R/W/H) Enables the logical instruction queue.
+		 * See also CPT()_PF_Q()_CTL[CONT_ERR] and
+		 * CPT()_VQ()_INPROG[INFLIGHT].
+		 * 1 = Queue is enabled.
+		 * 0 = Queue is disabled.
+		 **/
+		uint64_t reserved_1_63         : 63;
+#endif /* Word 0 - End */
+	} s;
+	/* struct cptx_vqx_ctl_s cn; */
+} cptx_vqx_ctl_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done
+ *
+ * CPT Queue Done Count Registers
+ * These registers contain the per-queue instruction done count.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_s {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		uint64_t done                  : 20;
+		/**< [ 19:  0](R/W/H) Done count. When CPT_INST_S[DONEINT] set
+		 * and that instruction completes,CPT()_VQ()_DONE[DONE] is
+		 * incremented when the instruction finishes. Write to this
+		 * field are for diagnostic use only; instead software writes
+		 * CPT()_VQ()_DONE_ACK with the number of decrements for this
+		 * field.
+
+		Interrupts are sent as follows:
+
+		 * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,
+		 * the interrupt coalescing timer is held to zero, and an
+		 * interrupt is not sent.
+
+		 * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt
+		 * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE
+		 * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()
+		 * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough
+		 * results have arrived, then the interrupt is sent.  Otherwise,
+		 * it is not sent due to coalescing.
+
+		* When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is
+		* written but this is not typical), the interrupt coalescing
+		* timer restarts.  Note after decrementing this interrupt
+		* equation is recomputed, for example if CPT()_VQ()_DONE[DONE]
+		* >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is
+		* zero, the interrupt will be resent immediately.  (This covers
+		* the race case between software acknowledging an interrupt and
+		* a result returning.)
+
+		* When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not
+		* sent, but the counting described above still occurs.
+
+		Since CPT instructions complete out-of-order, if software is
+		using completion interrupts the suggested scheme is to request a
+		DONEINT on each request, and when an interrupt arrives perform a
+		"greedy" scan for completions; even if a later command is
+		acknowledged first this will not result in missing a completion.
+
+		Software is responsible for making sure [DONE] does not overflow
+		; for example by insuring there are not more than 2^20-1
+		instructions in flight that may request interrupts.
+		 */
+#else /* Word 0 - Little Endian */
+		uint64_t done                  : 20;
+		/**< [ 19:  0](R/W/H) Done count. When CPT_INST_S[DONEINT] set
+		 * and that instruction completes,CPT()_VQ()_DONE[DONE] is
+		 * incremented when the instruction finishes. Write to this
+		 * field are for diagnostic use only; instead software writes
+		 * CPT()_VQ()_DONE_ACK with the number of decrements for this
+		 * field.
+
+		Interrupts are sent as follows:
+
+		 * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,
+		 * the interrupt coalescing timer is held to zero, and an
+		 * interrupt is not sent.
+
+		 * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt
+		 * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE
+		 * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()
+		 * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough
+		 * results have arrived, then the interrupt is sent.  Otherwise,
+		 * it is not sent due to coalescing.
+
+		* When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is
+		* written but this is not typical), the interrupt coalescing
+		* timer restarts.  Note after decrementing this interrupt
+		* equation is recomputed, for example if CPT()_VQ()_DONE[DONE]
+		* >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is
+		* zero, the interrupt will be resent immediately.  (This covers
+		* the race case between software acknowledging an interrupt and
+		* a result returning.)
+
+		* When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not
+		* sent, but the counting described above still occurs.
+
+		Since CPT instructions complete out-of-order, if software is
+		using completion interrupts the suggested scheme is to request a
+		DONEINT on each request, and when an interrupt arrives perform a
+		"greedy" scan for completions; even if a later command is
+		acknowledged first this will not result in missing a completion.
+
+		Software is responsible for making sure [DONE] does not overflow
+		; for example by insuring there are not more than 2^20-1
+		instructions in flight that may request interrupts.
+		 */
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+	/* struct cptx_vqx_done_s cn; */
+} cptx_vqx_done_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done_ack
+ *
+ * CPT Queue Done Count Ack Registers
+ * This register is written by software to acknowledge interrupts.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_ack_s {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		uint64_t done_ack              : 20;
+		/**< [ 19:  0](R/W/H) Number of decrements to CPT()_VQ()_DONE
+		 * [DONE]. Reads CPT()_VQ()_DONE[DONE].
+
+		Written by software to acknowledge interrupts. If CPT()_VQ()_
+		DONE[DONE] is still nonzero the interrupt will be re-sent if the
+		conditions described in CPT()_VQ()_DONE[DONE] are satisfied.
+		 */
+#else /* Word 0 - Little Endian */
+		uint64_t done_ack              : 20;
+		/**< [ 19:  0](R/W/H) Number of decrements to CPT()_VQ()_DONE
+		 * [DONE]. Reads CPT()_VQ()_DONE[DONE].
+
+		Written by software to acknowledge interrupts. If CPT()_VQ()_
+		DONE[DONE] is still nonzero the interrupt will be re-sent if the
+		conditions described in CPT()_VQ()_DONE[DONE] are satisfied.
+		 */
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+	/* struct cptx_vqx_done_ack_s cn; */
+} cptx_vqx_done_ack_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done_wait
+ *
+ * CPT Queue Done Interrupt Coalescing Wait Registers
+ * Specifies the per queue interrupt coalescing settings.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_wait_s {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_48_63        : 16;
+		uint64_t time_wait             : 16;
+		/**< [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =
+		 * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When
+		 * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is
+		 * disabled.
+		 **/
+		uint64_t reserved_20_31        : 12;
+		uint64_t num_wait              : 20;
+		/**< [ 19:  0](R/W) Number of messages hold-off. When
+		 * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as
+		 * 0x1.
+		 **/
+#else /* Word 0 - Little Endian */
+		uint64_t num_wait              : 20;
+		/**< [ 19:  0](R/W) Number of messages hold-off. When
+		 * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as
+		 * 0x1.
+		 **/
+		uint64_t reserved_20_31        : 12;
+		uint64_t time_wait             : 16;
+		/**< [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =
+		 * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When
+		 * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is
+		 * disabled.
+		 **/
+		uint64_t reserved_48_63        : 16;
+#endif /* Word 0 - End */
+	} s;
+	/* struct cptx_vqx_done_wait_s cn; */
+} cptx_vqx_done_wait_t;
+
+/**
+ * Register (NCB) cpt#_vq#_doorbell
+ *
+ * CPT Queue Doorbell Registers
+ * Doorbells for the CPT instruction queues.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_doorbell_s {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		uint64_t dbell_cnt             : 20;
+		/**< [ 19:  0](R/W/H) Number of instruction queue 64-bit words
+		 * to add to the CPT instruction doorbell count. Readback value
+		 * is the the current number of pending doorbell requests.
+
+		If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.
+
+		To reset the count back to zero, write one to clear
+		CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value of
+		2^20 minus the read [DBELL_CNT], then write one to
+		CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
+		CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].
+
+		Must be a multiple of 8.  All CPT instructions are 8 words and
+		require a doorbell count of multiple of 8.
+		 */
+#else /* Word 0 - Little Endian */
+		uint64_t dbell_cnt             : 20;
+		/**< [ 19:  0](R/W/H) Number of instruction queue 64-bit words
+		 * to add to the CPT instruction doorbell count. Readback value
+		 * is the the current number of pending doorbell requests.
+
+		If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.
+
+		To reset the count back to zero, write one to clear
+		CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value of
+		2^20 minus the read [DBELL_CNT], then write one to
+		CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
+		CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].
+
+		Must be a multiple of 8.  All CPT instructions are 8 words and
+		require a doorbell count of multiple of 8.
+		 */
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+	/* struct cptx_vqx_doorbell_s cn; */
+} cptx_vqx_doorbell_t;
+
+/**
+ * Register (NCB) cpt#_vq#_inprog
+ *
+ * CPT Queue In Progress Count Registers
+ * These registers contain the per-queue instruction in flight registers.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_inprog_s {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_8_63         : 56;
+		uint64_t inflight              : 8;
+		/**< [  7:  0](RO/H) Inflight count. Counts the number of
+		 * instructions for the VF for which CPT is fetching, executing
+		 * or responding to instructions. However this does not include
+		 * any interrupts that are awaiting software handling
+		 * (CPT()_VQ()_DONE[DONE] != 0x0).
+
+		A queue may not be reconfigured until:
+		1. CPT()_VQ()_CTL[ENA] is cleared by software.
+		2. [INFLIGHT] is polled until equals to zero.
+		 */
+#else /* Word 0 - Little Endian */
+		uint64_t inflight              : 8;
+		/**< [  7:  0](RO/H) Inflight count. Counts the number of
+		 * instructions for the VF for which CPT is fetching, executing
+		 * or responding to instructions. However this does not include
+		 * any interrupts that are awaiting software handling
+		 * (CPT()_VQ()_DONE[DONE] != 0x0).
+
+		A queue may not be reconfigured until:
+		1. CPT()_VQ()_CTL[ENA] is cleared by software.
+		2. [INFLIGHT] is polled until equals to zero.
+		 */
+		uint64_t reserved_8_63         : 56;
+#endif /* Word 0 - End */
+	} s;
+	/* struct cptx_vqx_inprog_s cn; */
+} cptx_vqx_inprog_t;
+
+/**
+ * Register (NCB) cpt#_vq#_misc_int
+ *
+ * CPT Queue Misc Interrupt Register
+ * These registers contain the per-queue miscellaneous interrupts.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_misc_int_s {
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_7_63         : 57;
+		uint64_t fault		       : 1;
+		/**< [  6:  6](R/W1C/H) Translation fault detected. */
+		uint64_t hwerr		       : 1;
+		/**< [  5:  5](R/W1C/H) Hardware error from engines. */
+		uint64_t swerr                 : 1;
+		/**< [  4:  4](R/W1C/H) Software error from engines. */
+		uint64_t nwrp                  : 1;
+		/**< [  3:  3](R/W1C/H) NCB result write response error. */
+		uint64_t irde                  : 1;
+		/**< [  2:  2](R/W1C/H) Instruction NCB read response error. */
+		uint64_t dovf                  : 1;
+		/**< [  1:  1](R/W1C/H) Doorbell overflow. */
+		uint64_t mbox                  : 1;
+		/**< [  0:  0](R/W1C/H) PF to VF mailbox interrupt. Set when
+		 * CPT()_VF()_PF_MBOX(0) is written.
+		 **/
+#else /* Word 0 - Little Endian */
+		uint64_t mbox                  : 1;
+		/**< [  0:  0](R/W1C/H) PF to VF mailbox interrupt. Set when
+		 * CPT()_VF()_PF_MBOX(0) is written.
+		 **/
+		uint64_t dovf                  : 1;
+		/**< [  1:  1](R/W1C/H) Doorbell overflow. */
+		uint64_t irde                  : 1;
+		/**< [  2:  2](R/W1C/H) Instruction NCB read response error. */
+		uint64_t nwrp                  : 1;
+		/**< [  3:  3](R/W1C/H) NCB result write response error. */
+		uint64_t swerr                 : 1;
+		/**< [  4:  4](R/W1C/H) Software error from engines. */
+		uint64_t hwerr		       : 1;
+		/**< [  5:  5](R/W1C/H) Hardware error from engines. */
+		uint64_t fault		       : 1;
+		/**< [  6:  6](R/W1C/H) Translation fault detected. */
+		uint64_t reserved_5_63         : 59;
+#endif /* Word 0 - End */
+	} s;
+	/* struct cptx_vqx_misc_int_s cn; */
+} cptx_vqx_misc_int_t;
+
+/**
+ * Register (NCB) cpt#_vq#_saddr
+ *
+ * CPT Queue Starting Buffer Address Registers
+ * These registers set the instruction buffer starting address.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_saddr_s	{
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* Word 0 - Big Endian */
+		uint64_t reserved_49_63        : 15;
+		uint64_t ptr                   : 43;
+		/**< [ 48:  6](R/W/H) Instruction buffer IOVA <48:6>
+		 * (64-byte aligned). When written, it is the initial buffer
+		 * starting address; when read, it is the next read pointer to
+		 * be requested from L2C. The PTR field is overwritten with the
+		 * next pointer each time that the command buffer segment is
+		 * exhausted. New commands will then be read from the newly
+		 * specified command buffer pointer.
+		 **/
+		uint64_t reserved_0_5          : 6;
+#else /* Word 0 - Little Endian */
+		uint64_t reserved_0_5          : 6;
+		uint64_t ptr                   : 43;
+		/**< [ 48:  6](R/W/H) Instruction buffer IOVA <48:6>
+		 * (64-byte aligned). When written, it is the initial buffer
+		 * starting address; when read, it is the next read pointer to
+		 * be requested from L2C. The PTR field is overwritten with the
+		 * next pointer each time that the command buffer segment is
+		 * exhausted. New commands will then be read from the newly
+		 * specified command buffer pointer.
+		 **/
+		uint64_t reserved_49_63        : 15;
+#endif /* Word 0 - End */
+	} s;
+	/* struct cptx_vqx_saddr_s cn; */
+} cptx_vqx_saddr_t;
+
+#endif /*__CPT_HW_TYPES_H*/
diff --git a/drivers/crypto/cpt/base/mcode_defines.h b/drivers/crypto/cpt/base/mcode_defines.h
new file mode 100644
index 0000000..15e7e60
--- /dev/null
+++ b/drivers/crypto/cpt/base/mcode_defines.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef _MCODE_DEFINES_H_
+#define _MCODE_DEFINES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*SE opcodes*/
+#define MAJOR_OP_FC         0x33
+#define MAJOR_OP_HASH       0x34
+#define MAJOR_OP_HMAC       0x35
+#define MAJOR_OP_ZUC_SNOW3G       0x37
+#define MAJOR_OP_KASUMI           0x38
+
+#define  BYTE_16 16
+#define  BYTE_24 24
+#define  BYTE_32 32
+#define  MAX_BUF_CNT 1024
+#define  MAX_SG_IN_OUT_CNT 16
+#define  MAX_SG_CNT (MAX_SG_IN_OUT_CNT/2)
+
+#define  ENCRYPT 1
+#define  DECRYPT 0
+#define  OFFSET_CONTROL_BYTES 8
+
+#define  DMA_MODE  (1 << 7)  /* Default support is with SG */
+
+#define FROM_CTX 0
+#define FROM_DPTR 1
+
+typedef enum {
+	MD5_TYPE        = 1,
+	SHA1_TYPE       = 2,
+	SHA2_SHA224     = 3,
+	SHA2_SHA256     = 4,
+	SHA2_SHA384     = 5,
+	SHA2_SHA512     = 6,
+	GMAC_TYPE       = 7,
+	XCBC_TYPE       = 8,
+	SHA3_SHA224     = 10,
+	SHA3_SHA256     = 11,
+	SHA3_SHA384     = 12,
+	SHA3_SHA512     = 13,
+	SHA3_SHAKE256   = 14,
+	SHA3_SHAKE512   = 15,
+
+	/* These are only for software use */
+	ZUC_EIA3        = 0x90,
+	SNOW3G_UIA2     = 0x91,
+	KASUMI_F9_CBC   = 0x92,
+	KASUMI_F9_ECB   = 0x93,
+} mc_hash_type_t;
+
+typedef enum {
+	/*
+	 * These are defined by MC for Flexi crypto
+	 * for field of 4 bits
+	 */
+	DES3_CBC    = 0x1,
+	DES3_ECB    = 0x2,
+	AES_CBC     = 0x3,
+	AES_ECB     = 0x4,
+	AES_CFB     = 0x5,
+	AES_CTR     = 0x6,
+	AES_GCM     = 0x7,
+	AES_XTS     = 0x8,
+
+	/* These are only for software use */
+	ZUC_EEA3        = 0x90,
+	SNOW3G_UEA2     = 0x91,
+	KASUMI_F8_CBC   = 0x92,
+	KASUMI_F8_ECB   = 0x93,
+} mc_cipher_type_t;
+
+typedef enum {
+	AES_128_BIT = 0x1,
+	AES_192_BIT = 0x2,
+	AES_256_BIT = 0x3
+} mc_aes_type_t;
+
+typedef enum {
+	/*Microcode errors*/
+	NO_ERR = 0x00,
+	ERR_OPCODE_UNSUPPORTED = 0x01,
+
+	/*SCATTER GATHER*/
+	ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,
+	ERR_SCATTER_GATHER_LIST = 0x03,
+	ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,
+
+	/*SE GC*/
+	ERR_GC_LENGTH_INVALID = 0x41,
+	ERR_GC_RANDOM_LEN_INVALID = 0x42,
+	ERR_GC_DATA_LEN_INVALID = 0x43,
+	ERR_GC_DRBG_TYPE_INVALID = 0x44,
+	ERR_GC_CTX_LEN_INVALID = 0x45,
+	ERR_GC_CIPHER_UNSUPPORTED = 0x46,
+	ERR_GC_AUTH_UNSUPPORTED = 0x47,
+	ERR_GC_OFFSET_INVALID = 0x48,
+	ERR_GC_HASH_MODE_UNSUPPORTED = 0x49,
+	ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,
+	ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,
+	ERR_GC_ICV_MISCOMPARE = 0x4c,
+	ERR_GC_DATA_UNALIGNED = 0x4d,
+
+	/* API Layer */
+	ERR_BAD_ALT_CCODE = 0xfd,
+	ERR_REQ_PENDING = 0xfe,
+	ERR_REQ_TIMEOUT = 0xff,
+
+	ERR_BAD_INPUT_LENGTH = (0x40000000 | 384),    /* 0x40000180 */
+	ERR_BAD_KEY_LENGTH,
+	ERR_BAD_KEY_HANDLE,
+	ERR_BAD_CONTEXT_HANDLE,
+	ERR_BAD_SCALAR_LENGTH,
+	ERR_BAD_DIGEST_LENGTH,
+	ERR_BAD_INPUT_ARG,
+	ERR_BAD_RECORD_PADDING,
+	ERR_NB_REQUEST_PENDING,
+	ERR_EIO,
+	ERR_ENODEV,
+} mc_error_code_t;
+
+/* FC offset_control at start of DPTR in bytes */
+#define OFF_CTRL_LEN  8 /* bytes */
+#define SHA1_BLOCK_SIZE 64
+
+typedef union {
+	uint64_t flags;
+	struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+		uint64_t enc_cipher   : 4;
+		uint64_t reserved1    : 1;
+		uint64_t aes_key      : 2;
+		uint64_t iv_source    : 1;
+		uint64_t hash_type    : 4;
+		uint64_t reserved2    : 3;
+		uint64_t auth_input_type : 1;
+		uint64_t mac_len      : 8;
+		uint64_t reserved3    : 8;
+		uint64_t encr_offset  : 16;
+		uint64_t iv_offset    : 8;
+		uint64_t auth_offset  : 8;
+#else
+		uint64_t auth_offset  : 8;
+		uint64_t iv_offset    : 8;
+		uint64_t encr_offset  : 16;
+		uint64_t reserved3    : 8;
+		uint64_t mac_len      : 8;
+		uint64_t auth_input_type : 1;
+		uint64_t reserved2    : 3;
+		uint64_t hash_type    : 4;
+		uint64_t iv_source    : 1;
+		uint64_t aes_key      : 2;
+		uint64_t reserved1    : 1;
+		uint64_t enc_cipher   : 4;
+#endif
+	} e;
+} encr_ctrl_t;
+
+typedef struct {
+	encr_ctrl_t enc_ctrl;
+	uint8_t  encr_key[32];
+	uint8_t  encr_iv[16];
+} mc_enc_context_t;
+
+typedef struct {
+	uint8_t  ipad[64];
+	uint8_t  opad[64];
+} mc_fc_hmac_context_t;
+
+typedef struct {
+	mc_enc_context_t     enc;
+	mc_fc_hmac_context_t hmac;
+} mc_fc_context_t;
+
+typedef struct {
+	uint8_t encr_auth_iv[16];
+	uint8_t ci_key[16];
+	uint8_t zuc_const[32];
+} mc_zuc_snow3g_ctx_t;
+
+typedef struct {
+	uint8_t reg_A[8];
+	uint8_t ci_key[16];
+} mc_kasumi_ctx_t;
+
+#define ENC_CTRL(fctx)  fctx.enc.enc_ctrl.e
+#define AUTH_CTRL(fctx) fctx.auth.auth_ctrl
+#define P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
+
+#define MAX_IVLEN 16
+#define MAX_KEYLEN 32
+
+/**
+ * Enumeration cpt_comp_e
+ *
+ * CPT Completion Enumeration
+ * Enumerates the values of CPT_RES_S[COMPCODE].
+ */
+typedef enum {
+	CPT_COMP_E_NOTDONE    = (0x00),
+	CPT_COMP_E_GOOD       = (0x01),
+	CPT_COMP_E_FAULT      = (0x02),
+	CPT_COMP_E_SWERR      = (0x03),
+	CPT_COMP_E_HWERR      = (0x04),
+	CPT_COMP_E_LAST_ENTRY = (0xFF)
+} cpt_comp_e_t;
+
+/** @endcond */
+
+#endif /* _MCODE_DEFINES_H_ */
-- 
1.9.3

Re: [dpdk-dev] [PATCH 02/16] crypto/cpt/base: add hardware definitions Cavium CPT

[Jerin Jacob]

-----Original Message-----
> Date: Fri,  8 Jun 2018 22:15:11 +0530
> From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> To: Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara
>  <pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>
> Cc: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>, Ankur Dwivedi
>  <ankur.dwivedi@cavium.com>, Jerin Jacob <jerin.jacob@caviumnetworks.com>,
>  Murthy NSSR <Nidadavolu.Murthy@cavium.com>, Narayana Prasad
>  <narayanaprasad.athreya@caviumnetworks.com>, Ragothaman Jayaraman
>  <Ragothaman.Jayaraman@cavium.com>, Srisivasubramanian Srinivasan
>  <Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org
> Subject: [PATCH 02/16] crypto/cpt/base: add hardware definitions Cavium CPT
> X-Mailer: git-send-email 2.7.4
> 
> From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> 
> Adds hardware specific definitions for Cavium CPT device.
> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
> ---
>  drivers/crypto/cpt/base/cpt_hw_types.h  | 836 ++++++++++++++++++++++++++++++++
>  drivers/crypto/cpt/base/mcode_defines.h | 215 ++++++++
>  2 files changed, 1051 insertions(+)
>  create mode 100644 drivers/crypto/cpt/base/cpt_hw_types.h
>  create mode 100644 drivers/crypto/cpt/base/mcode_defines.h
> 
> diff --git a/drivers/crypto/cpt/base/cpt_hw_types.h b/drivers/crypto/cpt/base/cpt_hw_types.h
> new file mode 100644
> index 0000000..b4b2af1
> --- /dev/null
> +++ b/drivers/crypto/cpt/base/cpt_hw_types.h
> @@ -0,0 +1,836 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2017 Cavium, Inc
> + */
> +
> +#ifndef __CPT_HW_TYPES_H
> +#define __CPT_HW_TYPES_H
> +
> +#include <stddef.h>
> +#include <stdint.h>
> +#include <stdbool.h>
> +#include <errno.h>
> +#include <string.h>

Use alphabetical order.

> +
> +#define CPT_INST_SIZE	            (64)
> +#define CPT_VQ_CHUNK_ALIGN	        (128) /**< 128 byte align */
> +#define CPT_NEXT_CHUNK_PTR_SIZE     (8)
> +#define CPT_INST_CHUNK_MAX_SIZE     (1023)
> +
> +#define CPT_PF_VF_MAILBOX_SIZE		(2)
> +
> +#define CPT_VF_INTR_MBOX_MASK   (1<<0)
> +#define CPT_VF_INTR_DOVF_MASK   (1<<1)
> +#define CPT_VF_INTR_IRDE_MASK   (1<<2)
> +#define CPT_VF_INTR_NWRP_MASK   (1<<3)
> +#define CPT_VF_INTR_SWERR_MASK  (1<<4)
> +#define CPT_VF_INTR_HWERR_MASK  (1<<5)
> +#define CPT_VF_INTR_FAULT_MASK  (1<<6)
> +
> +/*
> + * CPT_INST_S software command definitions
> + * Words EI (0-3)
> + */
> +typedef union {
> +	uint64_t u64;
> +	struct {
> +		uint16_t opcode;
> +		uint16_t param1;
> +		uint16_t param2;
> +		uint16_t dlen;
> +	} s;
> +} vq_cmd_word0_t;
> +
> +typedef union {
> +	uint64_t u64;
> +	struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__

Use DPDK primitives for endian checking.

> +		uint64_t grp	: 3;
> +		uint64_t cptr	: 61;
> +#else
> +		uint64_t cptr	: 61;
> +		uint64_t grp	: 3;
> +#endif
> +	} s;
> +	uint8_t reg_A[8];
> +	uint8_t ci_key[16];
> +} mc_kasumi_ctx_t;
> +
> +#define ENC_CTRL(fctx)  fctx.enc.enc_ctrl.e
> +#define AUTH_CTRL(fctx) fctx.auth.auth_ctrl
> +#define P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
> +
> +#define MAX_IVLEN 16
> +#define MAX_KEYLEN 32

If something specific to CPT, IMO, better to start with CPT_ to
avoid name collision.

[dpdk-dev] [PATCH 03/16] crypto/cpt/base: add hardware initialization API for CPT

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>

Adds hardware device initialization specific api for Cavium CPT device.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/base/cpt8xxx_device.c | 200 ++++++++++++++++
 drivers/crypto/cpt/base/cpt8xxx_device.h |  85 +++++++
 drivers/crypto/cpt/base/cpt_debug.h      | 231 +++++++++++++++++++
 drivers/crypto/cpt/base/cpt_device.c     | 383 +++++++++++++++++++++++++++++++
 drivers/crypto/cpt/base/cpt_device.h     | 162 +++++++++++++
 drivers/crypto/cpt/base/cpt_vf_mbox.c    | 176 ++++++++++++++
 drivers/crypto/cpt/base/cpt_vf_mbox.h    |  60 +++++
 7 files changed, 1297 insertions(+)
 create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.c
 create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.h
 create mode 100644 drivers/crypto/cpt/base/cpt_debug.h
 create mode 100644 drivers/crypto/cpt/base/cpt_device.c
 create mode 100644 drivers/crypto/cpt/base/cpt_device.h
 create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.c
 create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.h

diff --git a/drivers/crypto/cpt/base/cpt8xxx_device.c b/drivers/crypto/cpt/base/cpt8xxx_device.c
new file mode 100644
index 0000000..cdce96f
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt8xxx_device.c
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include "cpt8xxx_device.h"
+
+/*
+ * VF HAL functions
+ * Access its own BAR0/4 registers by passing VF number as 0.
+ * OS/PCI maps them accordingly.
+ */
+
+/* Send a mailbox message to PF
+ * @vf: vf from which this message to be sent
+ * @mbx: Message to be sent
+ */
+void cptvf_send_msg_to_pf(struct cpt_vf *cptvf, cpt_mbox_t *mbx)
+{
+	/* Writing mbox(1) causes interrupt */
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VFX_PF_MBOXX(0, 0, 0), mbx->msg);
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VFX_PF_MBOXX(0, 0, 1), mbx->data);
+}
+
+/* Read Interrupt status of the VF
+ * @vf: vf number
+ */
+uint64_t cptvf_read_vf_misc_intr_status(struct cpt_vf *cptvf)
+{
+	return CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0));
+}
+
+/* Clear mailbox interrupt of the VF
+ * @vf: vf number
+ */
+void cptvf_clear_mbox_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.mbox = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/* Clear swerr interrupt of the VF
+ * @vf: vf number
+ */
+void cptvf_clear_swerr_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.swerr = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/* Clear doorbell overflow interrupt of the VF
+ * @vf: vf number
+ */
+void cptvf_clear_dovf_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.dovf = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/* Clear instruction NCB read error interrupt of the VF
+ * @vf: vf number
+ */
+void cptvf_clear_irde_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.irde = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/* Clear NCB result write response error interrupt of the VF
+ * @vf: vf number
+ */
+void cptvf_clear_nwrp_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.nwrp = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/* Clear hwerr interrupt of the VF
+ * @vf: vf number
+ */
+void cptvf_clear_hwerr_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.hwerr = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/* Clear translation fault interrupt of the VF
+ * @vf: vf number
+ */
+void cptvf_clear_fault_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.fault = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/* Write to VQX_CTL register
+ */
+void cptvf_write_vq_ctl(struct cpt_vf *cptvf, bool val)
+{
+	cptx_vqx_ctl_t vqx_ctl;
+
+	vqx_ctl.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				 CPTX_VQX_CTL(0, 0));
+	vqx_ctl.s.ena = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_CTL(0, 0), vqx_ctl.u);
+}
+
+/* Write to VQX_INPROG register
+ */
+void cptvf_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val)
+{
+	cptx_vqx_inprog_t vqx_inprg;
+
+	vqx_inprg.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_INPROG(0, 0));
+	vqx_inprg.s.inflight = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_INPROG(0, 0), vqx_inprg.u);
+}
+
+/* Write to VQX_DONE_WAIT NUMWAIT register
+ */
+void cptvf_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val)
+{
+	cptx_vqx_done_wait_t vqx_dwait;
+
+	vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DONE_WAIT(0, 0));
+	vqx_dwait.s.num_wait = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
+}
+
+/* Write to VQX_DONE_WAIT NUM_WAIT register
+ */
+void cptvf_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val)
+{
+	cptx_vqx_done_wait_t vqx_dwait;
+
+	vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DONE_WAIT(0, 0));
+	vqx_dwait.s.time_wait = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
+}
+
+/* Write to VQX_SADDR register
+ */
+void cptvf_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val)
+{
+	cptx_vqx_saddr_t vqx_saddr;
+
+	vqx_saddr.u = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_SADDR(0, 0), vqx_saddr.u);
+}
diff --git a/drivers/crypto/cpt/base/cpt8xxx_device.h b/drivers/crypto/cpt/base/cpt8xxx_device.h
new file mode 100644
index 0000000..b7d7dcd
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt8xxx_device.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __CPT81XX_DEVICE_H
+#define __CPT81XX_DEVICE_H
+
+#include "cpt_device.h"
+#include "cpt_vf_mbox.h"
+/*
+ * CPT Registers map for 81xx
+ */
+
+/* VF registers */
+#define CPTX_VQX_CTL(a, b)               (0x0000100ll + 0x1000000000ll * \
+					  ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_SADDR(a, b)             (0x0000200ll + 0x1000000000ll * \
+					  ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_WAIT(a, b)         (0x0000400ll + 0x1000000000ll * \
+					  ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_INPROG(a, b)            (0x0000410ll + 0x1000000000ll * \
+					  ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE(a, b)              (0x0000420ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ACK(a, b)          (0x0000440ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1S(a, b)      (0x0000460ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1C(a, b)      (0x0000468ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1S(a, b)      (0x0000470ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1C(a, b)      (0x0000478ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT(a, b)          (0x0000500ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT_W1S(a, b)      (0x0000508ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1S(a, b)      (0x0000510ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1C(a, b)      (0x0000518ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DOORBELL(a, b)          (0x0000600ll + 0x1000000000ll * \
+					  ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VFX_PF_MBOXX(a, b, c)        (0x0001000ll + 0x1000000000ll * \
+					   ((a) & 0x1) + 0x100000ll * (b) + \
+					   8ll * ((c) & 0x1))
+/* VF HAL functions */
+void cptvf_send_msg_to_pf(struct cpt_vf *cptvf, cpt_mbox_t *mbx);
+void cptvf_clear_mbox_intr(struct cpt_vf *cptvf);
+void cptvf_clear_swerr_intr(struct cpt_vf *cptvf);
+void cptvf_clear_dovf_intr(struct cpt_vf *cptvf);
+void cptvf_clear_irde_intr(struct cpt_vf *cptvf);
+void cptvf_clear_nwrp_intr(struct cpt_vf *cptvf);
+void cptvf_clear_fault_intr(struct cpt_vf *cptvf);
+void cptvf_clear_hwerr_intr(struct cpt_vf *cptvf);
+void cptvf_write_vq_ctl(struct cpt_vf *cptvf, bool val);
+void cptvf_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val);
+void cptvf_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val);
+void cptvf_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val);
+void cptvf_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val);
+uint64_t cptvf_read_vf_misc_intr_status(struct cpt_vf *cptvf);
+
+/* Write to VQX_DOORBELL register
+ */
+static inline void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, uint32_t val)
+{
+	cptx_vqx_doorbell_t vqx_dbell;
+
+	vqx_dbell.u = 0;
+	vqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DOORBELL(0, 0), vqx_dbell.u);
+}
+
+static inline uint32_t cptvf_read_vq_doorbell(struct cpt_vf *cptvf)
+{
+	cptx_vqx_doorbell_t vqx_dbell;
+
+	vqx_dbell.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DOORBELL(0, 0));
+	return vqx_dbell.s.dbell_cnt;
+}
+
+#endif /* __CPT81XX_DEVICE_H */
diff --git a/drivers/crypto/cpt/base/cpt_debug.h b/drivers/crypto/cpt/base/cpt_debug.h
new file mode 100644
index 0000000..afa05df
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt_debug.h
@@ -0,0 +1,231 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __CPT_DEBUG_H
+#define __CPT_DEBUG_H
+#include <stdlib.h>
+#include <assert.h>
+#include "cpt_request_mgr.h"
+#include <rte_eal_memconfig.h>
+
+#ifdef CPT_DEBUG
+static inline void *
+os_iova2va(phys_addr_t physaddr)
+{
+	return rte_mem_iova2virt(physaddr);
+}
+
+static inline void __cpt_dump_buffer(const char *prefix_str,
+				     void *buf, size_t len, int rowsize)
+{
+	size_t i = 0;
+	unsigned char *ptr = (unsigned char *)buf;
+
+	PRINT("\n%s[%p]", prefix_str, buf);
+	PRINT("\n%.8lx: ", i);
+
+	if (buf == NULL) {
+		PRINT("\n!!!NULL ptr\n");
+		abort();
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i && !(i % rowsize))
+			PRINT("\n%.8lx: ", i);
+		PRINT("%02x ", ptr[i]);
+	}
+	PRINT("\n\n");
+}
+
+static inline void cpt_dump_buffer(const char *prefix_str,
+				   void *buf, size_t len)
+{
+	__cpt_dump_buffer(prefix_str, buf, len, 8);
+}
+
+#define cpt_fn_trace(fmt, ...)				\
+	do {						\
+		if (msg_req_trace(debug))		\
+			cpt_info(fmt, ##__VA_ARGS__);	\
+	} while (0)
+
+static inline void dump_cpt_request_info(struct cpt_request_info *req,
+					 cpt_inst_s_t *inst)
+{
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	uint16_t opcode, param1, param2, dlen;
+
+	vq_cmd_w0.u64 = be64toh(inst->s.ei0);
+	opcode = be16toh(vq_cmd_w0.s.opcode);
+	param1 = be16toh(vq_cmd_w0.s.param1);
+	param2 = be16toh(vq_cmd_w0.s.param2);
+	dlen = be16toh(vq_cmd_w0.s.dlen);
+	vq_cmd_w3.u64 = inst->s.ei3;
+
+	PRINT("\ncpt Request Info...\n");
+	PRINT("\tdma_mode: %u\n", req->dma_mode);
+	PRINT("\tis_se   : %u\n", req->se_req);
+	PRINT("\tgrp     : 0\n");
+
+	PRINT("\nRequest Info...\n");
+	PRINT("\topcode: 0x%0x\n", opcode);
+	PRINT("\tparam1: 0x%0x\n", param1);
+	PRINT("\tparam2: 0x%0x\n", param2);
+	PRINT("\tdlen: %u\n", dlen);
+	PRINT("\tctx_handle vaddr %p, dma 0x%lx\n",
+		     os_iova2va((uint64_t)vq_cmd_w3.s.cptr),
+		     (uint64_t)vq_cmd_w3.s.cptr);
+}
+
+static inline void
+dump_cpt_request_sglist(cpt_inst_s_t *inst,
+		       const char *header, bool data,
+		       bool glist)
+{
+	int i;
+	char suffix[64];
+	vq_cmd_word0_t vq_cmd_w0;
+	uint16_t opcode, dlen;
+	const char *list = glist ? "glist" : "slist";
+
+	vq_cmd_w0.u64 = be64toh(inst->s.ei0);
+	opcode = be16toh(vq_cmd_w0.s.opcode);
+	dlen = be16toh(vq_cmd_w0.s.dlen);
+
+	if (opcode & DMA_MODE) {
+		uint8_t *in_buffer = os_iova2va(inst->s.ei1);
+		uint16_t list_cnt, components;
+		struct sglist_comp *sg_ptr = NULL;
+		struct {
+			void *vaddr;
+			phys_addr_t dma_addr;
+			uint32_t size;
+		} list_ptr[MAX_SG_CNT];
+
+		PRINT("%s: DMA Mode\n", header);
+		snprintf(suffix, sizeof(suffix),
+			 "DPTR: vaddr %p, dma 0x%lx len %u: ",
+			 in_buffer, inst->s.ei1, dlen);
+
+		cpt_dump_buffer(suffix,
+				in_buffer,
+				dlen);
+
+		sg_ptr = (void *)(in_buffer + 8);
+		list_cnt = be16toh((((uint16_t *)in_buffer)[2]));
+		if (!glist) {
+			components = list_cnt / 4;
+			if (list_cnt % 4)
+				components++;
+			sg_ptr += components;
+			list_cnt = be16toh((((uint16_t *)in_buffer)[3]));
+		}
+		PRINT("current %s: %u\n", list, list_cnt);
+		if (!(list_cnt <= MAX_SG_CNT))
+			abort();
+
+		components = list_cnt / 4;
+
+		for (i = 0; i < components; i++) {
+			list_ptr[i*4+0].size = be16toh(sg_ptr->u.s.len[0]);
+			list_ptr[i*4+1].size = be16toh(sg_ptr->u.s.len[1]);
+			list_ptr[i*4+2].size = be16toh(sg_ptr->u.s.len[2]);
+			list_ptr[i*4+3].size = be16toh(sg_ptr->u.s.len[3]);
+			list_ptr[i*4+0].dma_addr = be64toh(sg_ptr->ptr[0]);
+			list_ptr[i*4+1].dma_addr = be64toh(sg_ptr->ptr[1]);
+			list_ptr[i*4+2].dma_addr = be64toh(sg_ptr->ptr[2]);
+			list_ptr[i*4+3].dma_addr = be64toh(sg_ptr->ptr[3]);
+
+			list_ptr[i*4+0].vaddr =
+				os_iova2va(list_ptr[i*4+0].dma_addr);
+			list_ptr[i*4+1].vaddr =
+				os_iova2va(list_ptr[i*4+1].dma_addr);
+			list_ptr[i*4+2].vaddr =
+				os_iova2va(list_ptr[i*4+2].dma_addr);
+			list_ptr[i*4+3].vaddr =
+				os_iova2va(list_ptr[i*4+3].dma_addr);
+			sg_ptr++;
+		}
+		components = list_cnt % 4;
+
+		switch (components) {
+		case 3:
+			list_ptr[i*4+2].size = be16toh(sg_ptr->u.s.len[2]);
+			list_ptr[i*4+2].dma_addr = be64toh(sg_ptr->ptr[2]);
+			list_ptr[i*4+2].vaddr =
+				os_iova2va(list_ptr[i*4+2].dma_addr);
+			/* fall through */
+		case 2:
+			list_ptr[i*4+1].size = be16toh(sg_ptr->u.s.len[1]);
+			list_ptr[i*4+1].dma_addr = be64toh(sg_ptr->ptr[1]);
+			list_ptr[i*4+1].vaddr =
+				os_iova2va(list_ptr[i*4+1].dma_addr);
+			/* fall through */
+		case 1:
+			list_ptr[i*4+0].size = be16toh(sg_ptr->u.s.len[0]);
+			list_ptr[i*4+0].dma_addr = be64toh(sg_ptr->ptr[0]);
+			list_ptr[i*4+0].vaddr =
+				os_iova2va(list_ptr[i*4+0].dma_addr);
+			break;
+		default:
+			break;
+		}
+
+		for (i = 0; i < list_cnt; i++) {
+			snprintf(suffix, sizeof(suffix),
+				 "%s[%d]: vaddr %p, dma 0x%lx len %u: ",
+				 list, i, list_ptr[i].vaddr,
+				 list_ptr[i].dma_addr,
+				 list_ptr[i].size);
+			if (data)
+				cpt_dump_buffer(suffix,
+						list_ptr[i].vaddr,
+						list_ptr[i].size);
+			else
+				PRINT("%s\n", suffix);
+		}
+	} else {
+		PRINT("%s: Direct Mode\n", header);
+
+		if (glist) {
+			snprintf(suffix, sizeof(suffix),
+				 "DPTR: vaddr %p, dma 0x%lx len %u: ",
+				 os_iova2va(inst->s.ei1),
+				 inst->s.ei1, dlen);
+			if (data)
+				cpt_dump_buffer(suffix,
+						os_iova2va(inst->s.ei1),
+						dlen);
+			else
+				PRINT("%s\n", suffix);
+		} else {
+			snprintf(suffix, sizeof(suffix),
+				 "RPTR: vaddr %p, dma 0x%lx len %u+..: ",
+				 os_iova2va(inst->s.ei2),
+				 inst->s.ei2, dlen);
+			/*
+			 * In direct mode, we don't have rlen
+			 * to dump exactly, so dump dlen + 32
+			 */
+			if (data)
+				cpt_dump_buffer(suffix,
+						os_iova2va(inst->s.ei2),
+						dlen + 32);
+			else
+				PRINT("%s\n", suffix);
+		}
+	}
+}
+
+
+#else
+
+#define cpt_dump_buffer(__str, __buf, __len)
+#define cpt_fn_trace(fmt, ...)
+#define dump_cpt_request_info(req, ist)
+#define dump_cpt_request_sglist(ist, header, data, flag)
+#endif /* CPT_DEBUG */
+
+#endif /* __CPT_DEBUG_H */
diff --git a/drivers/crypto/cpt/base/cpt_device.c b/drivers/crypto/cpt/base/cpt_device.c
new file mode 100644
index 0000000..b7cd5b5
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt_device.c
@@ -0,0 +1,383 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include "cpt_device.h"
+#include "cpt_debug.h"
+#include "cpt8xxx_device.h"
+#include "cpt_vf_mbox.h"
+#include "cpt_request_mgr.h"
+
+#include <rte_memzone.h>
+
+static void cptvf_vfvq_init(struct cpt_vf *cptvf)
+{
+	uint64_t base_addr = 0;
+
+	/* Disable the VQ */
+	cptvf_write_vq_ctl(cptvf, 0);
+
+	/* Reset the doorbell */
+	cptvf_write_vq_doorbell(cptvf, 0);
+	/* Clear inflight */
+	cptvf_write_vq_inprog(cptvf, 0);
+
+	/* Write VQ SADDR */
+	base_addr = (uint64_t)(cptvf->cqueue.chead[0].dma_addr);
+	cptvf_write_vq_saddr(cptvf, base_addr);
+
+	/* Configure timerhold / coalescence */
+	cptvf_write_vq_done_timewait(cptvf, CPT_TIMER_THOLD);
+	cptvf_write_vq_done_numwait(cptvf, CPT_COUNT_THOLD);
+
+	/* Enable the VQ */
+	cptvf_write_vq_ctl(cptvf, 1);
+
+	/* Flag the VF ready */
+	cptvf->flags |= CPT_FLAG_DEVICE_READY;
+}
+
+static int cpt_vf_init(struct cpt_vf *cptvf)
+{
+	int err = -1;
+
+	/* Mark as VF driver */
+	cptvf->flags |= CPT_FLAG_VF_DRIVER;
+
+	/* Check ready with PF */
+	/* Gets chip ID / device Id from PF if ready */
+	err = cptvf_check_pf_ready(cptvf);
+	if (err) {
+		PMD_DRV_LOG(ERR, "%s: PF not responding to READY msg\n",
+			    cptvf->dev_name);
+		err = -EBUSY;
+		goto cptvf_err;
+	}
+
+	PMD_DRV_LOG(DEBUG, "%s: cpt_vf_init() done\n", cptvf->dev_name);
+	return 0;
+
+cptvf_err:
+	return err;
+}
+
+static int cpt_vq_init(struct cpt_vf *cptvf, uint8_t group)
+{
+	int err;
+
+	/* Convey VQ LEN to PF */
+	err = cptvf_send_vq_size_msg(cptvf);
+	if (err) {
+		PMD_DRV_LOG(ERR, "%s: PF not responding to QLEN msg\n",
+			    cptvf->dev_name);
+		err = -EBUSY;
+		goto cleanup;
+	}
+
+	/* CPT VF device initialization */
+	cptvf_vfvq_init(cptvf);
+
+	/* Send msg to PF to assign currnet Q to required group */
+	cptvf->vfgrp = group;
+	err = cptvf_send_vf_to_grp_msg(cptvf, group);
+	if (err) {
+		PMD_DRV_LOG(ERR, "%s: PF not responding to VF_GRP msg\n",
+			    cptvf->dev_name);
+		err = -EBUSY;
+		goto cleanup;
+	}
+
+	PMD_DRV_LOG(DEBUG, "%s: cpt_vq_init() done\n", cptvf->dev_name);
+	return 0;
+
+cleanup:
+	return err;
+}
+
+void cptvf_poll_misc(void *dev)
+{
+	uint64_t intr;
+	struct cpt_vf *cptvf = dev;
+
+	intr = cptvf_read_vf_misc_intr_status(cptvf);
+
+	if (!intr)
+		return;
+
+	/*Check for MISC interrupt types*/
+	if (likely(intr & CPT_VF_INTR_MBOX_MASK)) {
+		PMD_DRV_LOG(DEBUG, "%s: Mailbox interrupt 0x%lx on CPT VF %d\n",
+			    cptvf->dev_name, intr, cptvf->vfid);
+		cptvf_handle_mbox_intr(cptvf);
+		cptvf_clear_mbox_intr(cptvf);
+	} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {
+		cptvf_clear_irde_intr(cptvf);
+		PMD_DRV_LOG(DEBUG, "%s: Instruction NCB read error interrupt"
+			    " 0x%lx on CPT VF %d\n", cptvf->dev_name, intr,
+			    cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) {
+		cptvf_clear_nwrp_intr(cptvf);
+		PMD_DRV_LOG(DEBUG, "%s: NCB response write error interrupt"
+		" 0x%lx on CPT VF %d\n", cptvf->dev_name, intr, cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) {
+		cptvf_clear_swerr_intr(cptvf);
+		PMD_DRV_LOG(DEBUG, "%s: Software error interrupt 0x%lx on"
+		" CPT VF %d\n", cptvf->dev_name, intr, cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) {
+		cptvf_clear_hwerr_intr(cptvf);
+		PMD_DRV_LOG(DEBUG, "%s: Hardware error interrupt 0x%lx on"
+		" CPT VF %d\n", cptvf->dev_name, intr, cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) {
+		cptvf_clear_fault_intr(cptvf);
+		PMD_DRV_LOG(DEBUG, "%s: Translation fault interrupt 0x%lx on"
+		" CPT VF %d\n", cptvf->dev_name, intr, cptvf->vfid);
+	} else
+		PMD_DRV_LOG(ERR, "%s: Unhandled interrupt 0x%lx in CPT VF %d\n",
+			    cptvf->dev_name, intr, cptvf->vfid);
+}
+
+int cptvf_deinit_device(struct cpt_vf *dev)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	/* Do misc work one last time */
+	cptvf_poll_misc(cptvf);
+
+	/* TODO anything else ?? */
+
+	return 0;
+}
+
+int cptvf_init_device(struct cpt_vf *cptvf,
+		      void *pdev,
+		      void *reg_base,
+		      char *name,
+		      uint32_t flags)
+{
+	(void) flags;
+
+	memset(cptvf, 0, sizeof(struct cpt_vf));
+
+	/* Bar0 base address */
+	cptvf->reg_base = reg_base;
+	strncpy(cptvf->dev_name, name, 32);
+
+	cptvf->nr_queues = 1;
+	cptvf->max_queues = 1;
+	cptvf->pdev = pdev;
+
+	/* To clear if there are any pending mbox msgs */
+	cptvf_poll_misc(cptvf);
+
+	if (cpt_vf_init(cptvf)) {
+		PMD_DRV_LOG(ERR, "Failed to initialize CPT VF device\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+
+int cptvf_get_resource(struct cpt_vf *dev,
+		       uint8_t group, cpt_instance_t **instance)
+{
+	int ret = -ENOENT, len, qlen, i;
+	int chunk_len, chunks, chunk_size;
+	struct cpt_vf *cptvf = dev;
+	cpt_instance_t *cpt_instance;
+	struct command_chunk *chunk_head = NULL, *chunk_prev = NULL;
+	struct command_chunk *chunk = NULL;
+	uint8_t *mem;
+	const struct rte_memzone *rz;
+	uint64_t dma_addr = 0, alloc_len, used_len;
+	uint64_t *next_ptr;
+	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
+
+	PMD_DRV_LOG(DEBUG, "Initializing csp resource %s\n", cptvf->dev_name);
+
+	cpt_instance = &cptvf->instance;
+
+	memset(&cptvf->cqueue, 0, sizeof(cptvf->cqueue));
+	memset(&cptvf->pqueue, 0, sizeof(cptvf->pqueue));
+
+	/* Chunks are of fixed size buffers */
+	chunks = DEFAULT_CMD_QCHUNKS;
+	chunk_len = DEFAULT_CMD_QCHUNK_SIZE;
+
+	qlen = chunks * chunk_len;
+	/* Chunk size includes 8 bytes of next chunk ptr */
+	chunk_size = chunk_len * CPT_INST_SIZE + CPT_NEXT_CHUNK_PTR_SIZE;
+
+	/* For command chunk structures */
+	len = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8);
+
+	/* For pending queue */
+	len += qlen * RTE_ALIGN(sizeof(rid_t), 8);
+
+	/* So that instruction queues start as pg size aligned */
+	len = RTE_ALIGN(len, pg_sz);
+
+	/* For Instruction queues */
+	len += chunks * RTE_ALIGN(chunk_size, 128);
+
+	/* Wastage after instruction queues */
+	len = RTE_ALIGN(len, pg_sz);
+
+	rz = rte_memzone_reserve_aligned(cptvf->dev_name, len, cptvf->node,
+					 RTE_MEMZONE_SIZE_HINT_ONLY |
+					 RTE_MEMZONE_256MB,
+					 RTE_CACHE_LINE_SIZE);
+	if (!rz) {
+		ret = rte_errno;
+		goto cleanup;
+	}
+
+	mem = rz->addr;
+	dma_addr = rz->phys_addr;
+	alloc_len = len;
+
+	memset(mem, 0, len);
+
+	cpt_instance->rsvd = (uint64_t)rz;
+
+	/* Pending queue setup */
+	cptvf->pqueue.rid_queue = (rid_t *)mem;
+	cptvf->pqueue.soft_qlen = qlen;
+	cptvf->pqueue.enq_tail = 0;
+	cptvf->pqueue.deq_head = 0;
+	cptvf->pqueue.pending_count = 0;
+
+	mem +=  qlen * RTE_ALIGN(sizeof(rid_t), 8);
+	len -=  qlen * RTE_ALIGN(sizeof(rid_t), 8);
+	dma_addr += qlen * RTE_ALIGN(sizeof(rid_t), 8);
+
+	/* Alignement wastage */
+	used_len = alloc_len - len;
+	mem += RTE_ALIGN(used_len, pg_sz) - used_len;
+	len -= RTE_ALIGN(used_len, pg_sz) - used_len;
+	dma_addr += RTE_ALIGN(used_len, pg_sz) - used_len;
+
+	/* Init instruction queues */
+	chunk_head = &cptvf->cqueue.chead[0];
+	i = qlen;
+
+	chunk_prev = NULL;
+	for (i = 0; i < DEFAULT_CMD_QCHUNKS; i++) {
+		int csize;
+
+		chunk = &cptvf->cqueue.chead[i];
+		chunk->head = mem;
+		chunk->dma_addr = dma_addr;
+
+		csize = RTE_ALIGN(chunk_size, 128);
+		mem += csize;
+		dma_addr += csize;
+		len -= csize;
+
+		if (chunk_prev) {
+			next_ptr = (uint64_t *)(chunk_prev->head +
+						chunk_size - 8);
+			*next_ptr = (uint64_t)chunk->dma_addr;
+		}
+		chunk_prev = chunk;
+	}
+	/* Circular loop */
+	next_ptr = (uint64_t *)(chunk_prev->head + chunk_size - 8);
+	*next_ptr = (uint64_t)chunk_head->dma_addr;
+
+	assert(!len);
+
+	cptvf->qlen = qlen;
+	/* This is used for CPT(0)_PF_Q(0..15)_CTL.size config */
+	cptvf->qsize = chunk_size / 8;
+	cptvf->cqueue.qhead = chunk_head->head;
+	cptvf->cqueue.idx = 0;
+	cptvf->cqueue.cchunk = 0;
+
+	if (cpt_vq_init(cptvf, group)) {
+		PMD_DRV_LOG(ERR, "Failed to initialize CPT VQ of device %s\n",
+			    cptvf->dev_name);
+		ret = -EBUSY;
+		goto cleanup;
+	}
+
+	*instance = cpt_instance;
+
+	PMD_DRV_LOG(DEBUG, "Crypto device (%s) initialized\n",
+		    cptvf->dev_name);
+
+	return 0;
+cleanup:
+	rte_memzone_free(rz);
+	*instance = NULL;
+	return ret;
+}
+
+int cptvf_put_resource(cpt_instance_t *instance)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct rte_memzone *rz;
+
+	if (!cptvf) {
+		PMD_DRV_LOG(ERR, "Invalid CPTVF handle\n");
+		return -EINVAL;
+	}
+
+	PMD_DRV_LOG(DEBUG, "Releasing csp device %s\n", cptvf->dev_name);
+
+	rz = (struct rte_memzone *)instance->rsvd;
+	rte_memzone_free(rz);
+	return 0;
+}
+
+int cptvf_start_device(struct cpt_vf *cptvf)
+{
+	int rc;
+
+	rc = cptvf_send_vf_up(cptvf);
+	if (rc) {
+		PMD_DRV_LOG(ERR, "Failed to mark CPT VF device %s UP, rc = %d\n"
+			    , cptvf->dev_name, rc);
+		return -EFAULT;
+	}
+
+	if ((cptvf->vftype != SE_TYPE) &&
+	    (cptvf->vftype != AE_TYPE)) {
+		PMD_DRV_LOG(ERR, "Fatal error, unexpected vf type %u, for CPT"
+		" VF device %s\n", cptvf->vftype, cptvf->dev_name);
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+void cptvf_stop_device(struct cpt_vf *cptvf)
+{
+	int rc;
+	uint32_t pending, retries = 5;
+
+	/* Wait for pending entries to complete */
+	pending = cptvf_read_vq_doorbell(cptvf);
+	while (pending) {
+		PRINT("%s: Waiting for pending %u cmds to complete\n",
+		      cptvf->dev_name, pending);
+		sleep(1);
+		pending = cptvf_read_vq_doorbell(cptvf);
+		retries--;
+		if (!retries)
+			break;
+	}
+
+	if (!retries && pending) {
+		PMD_DRV_LOG(ERR, "%s: Timeout waiting for commands(%u)\n",
+			    cptvf->dev_name, pending);
+		return;
+	}
+
+	rc = cptvf_send_vf_down(cptvf);
+	if (rc) {
+		PMD_DRV_LOG(ERR, "Failed to bring down vf %s, rc %d\n",
+			    cptvf->dev_name, rc);
+		return;
+	}
+}
diff --git a/drivers/crypto/cpt/base/cpt_device.h b/drivers/crypto/cpt/base/cpt_device.h
new file mode 100644
index 0000000..951c7ae
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt_device.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __CPT_DEVICE_H
+#define __CPT_DEVICE_H
+
+#include "cpt.h"
+#include "cpt_hw_types.h"
+#include <rte_io.h>
+#include <rte_atomic.h>
+#include <rte_cycles.h>
+#include <rte_pci.h>
+
+/* Device ID */
+#define PCI_VENDOR_ID_CAVIUM		    0x177d
+#define CPT_81XX_PCI_VF_DEVICE_ID	    0xa041
+
+#define CPT_NUM_QS_PER_VF           (1)
+
+#define CPT_MBOX_MSG_TIMEOUT    2000 /* In Milli Seconds */
+
+/**< flags to indicate the features supported */
+#define CPT_FLAG_VF_DRIVER		(uint16_t)(1 << 3)
+#define CPT_FLAG_DEVICE_READY	(uint16_t)(1 << 4)
+
+#ifndef ROUNDUP4
+#define ROUNDUP4(val)	(((val) + 3) & 0xfffffffc)
+#endif
+
+#ifndef ROUNDUP8
+#define ROUNDUP8(val)	(((val) + 7) & 0xfffffff8)
+#endif
+
+#ifndef ROUNDUP16
+#define ROUNDUP16(val)	(((val) + 15) & 0xfffffff0)
+#endif
+
+/* Default command queue length */
+#define DEFAULT_CMD_QCHUNKS	2
+#define DEFAULT_CMD_QCHUNK_SIZE 1023
+#define DEFAULT_CMD_QLEN (DEFAULT_CMD_QCHUNK_SIZE * DEFAULT_CMD_QCHUNKS)
+
+/* Default command timeout in seconds */
+#define DEFAULT_COMMAND_TIMEOUT	    4
+
+#define CPT_COUNT_THOLD		32
+#define CPT_TIMER_THOLD		0x3F
+
+
+#define AE_TYPE 1
+#define SE_TYPE 2
+
+typedef enum {
+	CPT_81XX = 1,
+	CPT_AE_83XX,
+	CPT_SE_83XX,
+	INVALID_CPT
+} cpt_pf_type_t;
+
+typedef struct rid {
+	uint64_t	rid;     /* Request id of a crypto operation */
+/*	void		*op; */    /* Opaque operation handle returned */
+} rid_t;                  /* Array of pending request's */
+
+typedef struct pending_queue {
+	uint16_t enq_tail;
+	uint16_t deq_head;
+	uint16_t soft_qlen;        /* Software expected queue length */
+	uint16_t p_doorbell;
+	rid_t      *rid_queue;     /* Array of pending request's */
+	uint64_t pending_count;           /* Pending requests count */
+} pending_queue_t;
+
+struct command_chunk {
+	uint8_t *head;		        /**< 128-byte aligned real_vaddr */
+	phys_addr_t dma_addr;		/**< 128-byte aligned real_dma_addr */
+};
+
+/**
+ * comamnd queue structure
+ */
+struct command_queue {
+	uint32_t idx;
+	/**< Command queue host write idx */
+	uint32_t cchunk;
+	uint8_t *qhead;
+	/**< Command queue head, instructions are inserted here */
+	struct command_chunk chead[DEFAULT_CMD_QCHUNKS];
+	/**< Command chunk list head */
+};
+
+/**
+ * CPT VF device structure
+ */
+struct cpt_vf {
+	cpt_instance_t instance;
+
+	/* base address where BAR is mapped */
+	uint8_t *reg_base;  /**< Register start address */
+
+	/* Command and Pending queues */
+	struct command_queue cqueue;/**< Command queue information */
+	struct pending_queue pqueue;/**< Pending queue information */
+
+	/* Below fields are accessed only in control path */
+
+	/*
+	 * This points to environment specific pdev that
+	 * represents the pci dev
+	 */
+	void *pdev;
+	uint32_t qlen;
+	/*
+	 * Qsize * CPT_INST_SIZE +
+	 * alignment size(CPT_INST_SIZE +
+	 * next chunk pointer size (8)
+	 */
+	uint32_t qsize;
+	/**< Calculated queue size */
+	uint32_t nr_queues;
+	uint32_t max_queues;
+
+	uint32_t chip_id;
+	/**< CPT Device ID */
+	uint16_t flags;
+	/**< Flags to hold device status bits */
+	uint8_t  vfid;
+	/**< Device Index (0...CPT_MAX_VQ_NUM */
+	uint8_t  vftype;
+	/**< VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
+	uint8_t  vfgrp;
+	/**< VF group (0 - 8) */
+	uint8_t  node;
+	/**< Operating node: Bits (46:44) in BAR0 address */
+
+	/* VF-PF mailbox communication */
+	bool pf_acked;
+	bool pf_nacked;
+	char dev_name[32];
+} ____cacheline_aligned_in_smp;
+
+#define CPT_CSR_REG_BASE(cpt)       ((cpt)->reg_base)
+
+#define CPT_READ_CSR(__hw_addr, __offset) \
+	rte_read64_relaxed((uint8_t *)__hw_addr + __offset)
+#define CPT_WRITE_CSR(__hw_addr, __offset, __val) \
+	rte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))
+
+void cptvf_poll_misc(void *dev);
+int cptvf_deinit_device(struct cpt_vf *dev);
+int cptvf_init_device(struct cpt_vf *cptvf,
+		      void *pdev,
+		      void *reg_base,
+		      char *name,
+		      uint32_t flags);
+int cptvf_get_resource(struct cpt_vf *dev,
+		       uint8_t group, cpt_instance_t **instance);
+int cptvf_put_resource(cpt_instance_t *instance);
+int cptvf_start_device(struct cpt_vf *cptvf);
+void cptvf_stop_device(struct cpt_vf *cptvf);
+#endif /* __CPT_DEVICE_H */
diff --git a/drivers/crypto/cpt/base/cpt_vf_mbox.c b/drivers/crypto/cpt/base/cpt_vf_mbox.c
new file mode 100644
index 0000000..00d98bb
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt_vf_mbox.c
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include "cpt8xxx_device.h"
+#include "cpt_vf_mbox.h"
+#include <unistd.h>
+
+/* Poll handler to handle mailbox messages from VFs */
+void cptvf_handle_mbox_intr(struct cpt_vf *cptvf)
+{
+	cpt_mbox_t mbx = {0, 0};
+
+	/*
+	 * MBOX[0] contains msg
+	 * MBOX[1] contains data
+	 */
+	mbx.msg  = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VFX_PF_MBOXX(0, 0, 0));
+	mbx.data = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VFX_PF_MBOXX(0, 0, 1));
+
+	PMD_DRV_LOG(DEBUG, "%s: Mailbox msg 0x%lx from PF\n",
+		    cptvf->dev_name, mbx.msg);
+	switch (mbx.msg) {
+	case CPT_MSG_READY:
+		{
+			cpt_chipid_vfid_t cid;
+
+			cid.u64 = mbx.data;
+			cptvf->pf_acked = true;
+			cptvf->vfid = cid.s.vfid;
+			cptvf->chip_id = cid.s.chip_id;
+			PMD_DRV_LOG(DEBUG, "%s: Received VFID %d chip_id %d\n",
+				    cptvf->dev_name,
+				    cptvf->vfid, cid.s.chip_id);
+		}
+		break;
+	case CPT_MSG_QBIND_GRP:
+		cptvf->pf_acked = true;
+		cptvf->vftype = mbx.data;
+		PMD_DRV_LOG(DEBUG, "%s: VF %d type %s group %d\n",
+			    cptvf->dev_name, cptvf->vfid,
+			    ((mbx.data == SE_TYPE) ? "SE" : "AE"),
+			    cptvf->vfgrp);
+		break;
+	case CPT_MBOX_MSG_TYPE_ACK:
+		cptvf->pf_acked = true;
+		break;
+	case CPT_MBOX_MSG_TYPE_NACK:
+		cptvf->pf_nacked = true;
+		break;
+	default:
+		PMD_DRV_LOG(DEBUG, "%s: Invalid msg from PF, msg 0x%lx\n",
+			    cptvf->dev_name, mbx.msg);
+		break;
+	}
+}
+
+static int32_t
+cptvf_send_msg_to_pf_timeout(struct cpt_vf *cptvf, cpt_mbox_t *mbx)
+{
+	int timeout = CPT_MBOX_MSG_TIMEOUT;
+	int sleep_ms = 10;
+
+	cptvf->pf_acked = false;
+	cptvf->pf_nacked = false;
+
+	cptvf_send_msg_to_pf(cptvf, mbx);
+
+	/* Wait for previous message to be acked, timeout 2sec */
+	while (!cptvf->pf_acked) {
+		if (cptvf->pf_nacked)
+			return -EINVAL;
+		usleep(sleep_ms * 1000);
+		cptvf_poll_misc(cptvf);
+		if (cptvf->pf_acked)
+			break;
+		timeout -= sleep_ms;
+		if (!timeout) {
+			PMD_DRV_LOG(ERR, "%s: PF didn't ack mbox msg %lx(vfid "
+				    "%u)\n",
+				    cptvf->dev_name,
+				    (mbx->msg & 0xFF), cptvf->vfid);
+			return -EBUSY;
+		}
+	}
+	return 0;
+}
+
+/*
+ * Checks if VF is able to comminicate with PF
+ * and also gets the CPT number this VF is associated to.
+ */
+int cptvf_check_pf_ready(struct cpt_vf *cptvf)
+{
+	cpt_mbox_t mbx = {0, 0};
+
+	mbx.msg = CPT_MSG_READY;
+	if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		PMD_DRV_LOG(ERR, "%s: PF didn't respond to READY msg\n",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+/*
+ * Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF.
+ * Must be ACKed.
+ */
+int cptvf_send_vq_size_msg(struct cpt_vf *cptvf)
+{
+	cpt_mbox_t mbx = {0, 0};
+
+	mbx.msg = CPT_MSG_QLEN;
+
+	mbx.data = cptvf->qsize;
+	if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		PMD_DRV_LOG(ERR, "%s: PF didn't respond to vq_size msg\n",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+/*
+ * Communicate VF group required to PF and get the VQ binded to that group
+ */
+int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf, uint32_t group)
+{
+	cpt_mbox_t mbx = {0, 0};
+
+	mbx.msg = CPT_MSG_QBIND_GRP;
+
+	/* Convey group of the VF */
+	mbx.data = group;
+	if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		PMD_DRV_LOG(ERR, "%s: PF didn't respond to vf_type msg\n",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+/*
+ * Communicate to PF that VF is UP and running
+ */
+int cptvf_send_vf_up(struct cpt_vf *cptvf)
+{
+	cpt_mbox_t mbx = {0, 0};
+
+	mbx.msg = CPT_MSG_VF_UP;
+	if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		PMD_DRV_LOG(ERR, "%s: PF didn't respond to UP msg\n",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+/*
+ * Communicate to PF that VF is DOWN and running
+ */
+int cptvf_send_vf_down(struct cpt_vf *cptvf)
+{
+	cpt_mbox_t mbx = {0, 0};
+
+	mbx.msg = CPT_MSG_VF_DOWN;
+	if (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		PMD_DRV_LOG(ERR, "%s: PF didn't respond to DOWN msg\n",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
diff --git a/drivers/crypto/cpt/base/cpt_vf_mbox.h b/drivers/crypto/cpt/base/cpt_vf_mbox.h
new file mode 100644
index 0000000..8e7a05f
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt_vf_mbox.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __CPTVF_MBOX_H
+#define __CPTVF_MBOX_H
+
+#include "cpt.h"
+#include "cpt_device.h"
+
+#define CPT_MBOX_MSG_TYPE_REQ	0
+#define CPT_MBOX_MSG_TYPE_ACK	1
+#define CPT_MBOX_MSG_TYPE_NACK	2
+#define CPT_MBOX_MSG_TYPE_NOP	3
+
+typedef enum {
+	CPT_MSG_VF_UP = 1,
+	CPT_MSG_VF_DOWN,
+	CPT_MSG_READY,
+	CPT_MSG_QLEN,
+	CPT_MSG_QBIND_GRP,
+	CPT_MSG_VQ_PRIORITY,
+	CPT_MSG_PF_TYPE,
+} cpt_mbox_opcode_t;
+
+/* CPT mailbox structure */
+typedef struct {
+	uint64_t msg; /* Message type MBOX[0] */
+	uint64_t data;/* Data         MBOX[1] */
+} cpt_mbox_t;
+
+typedef union {
+	uint64_t u64;
+	struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+		uint32_t chip_id;
+		uint8_t vfid;
+		uint8_t reserved[3];
+#else
+		uint8_t reserved[3];
+		uint8_t vfid;
+		uint32_t chip_id;
+#endif
+	} s;
+} cpt_chipid_vfid_t;
+
+
+void cptvf_mbox_send_ack(struct cpt_vf *cptvf, cpt_mbox_t *mbx);
+void cptvf_mbox_send_nack(struct cpt_vf *cptvf, cpt_mbox_t *mbx);
+int cptvf_check_pf_ready(struct cpt_vf *cptvf);
+int cptvf_send_vq_size_msg(struct cpt_vf *cptvf);
+int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf, uint32_t group);
+int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf, uint32_t priority);
+int cptvf_send_vf_down(struct cpt_vf *cptvf);
+int cptvf_send_vf_up(struct cpt_vf *cptvf);
+void cptvf_handle_mbox_intr(struct cpt_vf *cptvf);
+/* Synchronous raw operation to get vf cfg */
+int cptvf_get_pf_type_raw(char *dev_name, void *reg_base,
+			  cpt_pf_type_t *pf_type);
+#endif /* __CPTVF_MBOX_H */
-- 
1.9.3

Re: [dpdk-dev] [PATCH 03/16] crypto/cpt/base: add hardware initialization API for CPT

[Jerin Jacob]

-----Original Message-----
> Date: Fri,  8 Jun 2018 22:15:12 +0530
> From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> To: Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara
>  <pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>
> Cc: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>, Ankur Dwivedi
>  <ankur.dwivedi@cavium.com>, Jerin Jacob <jerin.jacob@caviumnetworks.com>,
>  Murthy NSSR <Nidadavolu.Murthy@cavium.com>, Narayana Prasad
>  <narayanaprasad.athreya@caviumnetworks.com>, Ragothaman Jayaraman
>  <Ragothaman.Jayaraman@cavium.com>, Srisivasubramanian Srinivasan
>  <Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org
> Subject: [PATCH 03/16] crypto/cpt/base: add hardware initialization API for
>  CPT
> X-Mailer: git-send-email 2.7.4
> 
> From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> 
> Adds hardware device initialization specific api for Cavium CPT device.
> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
> ---
>  drivers/crypto/cpt/base/cpt8xxx_device.c | 200 ++++++++++++++++
>  drivers/crypto/cpt/base/cpt8xxx_device.h |  85 +++++++
>  drivers/crypto/cpt/base/cpt_debug.h      | 231 +++++++++++++++++++
>  drivers/crypto/cpt/base/cpt_device.c     | 383 +++++++++++++++++++++++++++++++
>  drivers/crypto/cpt/base/cpt_device.h     | 162 +++++++++++++
>  drivers/crypto/cpt/base/cpt_vf_mbox.c    | 176 ++++++++++++++
>  drivers/crypto/cpt/base/cpt_vf_mbox.h    |  60 +++++
>  7 files changed, 1297 insertions(+)
>  create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.c
>  create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.h
>  create mode 100644 drivers/crypto/cpt/base/cpt_debug.h
>  create mode 100644 drivers/crypto/cpt/base/cpt_device.c
>  create mode 100644 drivers/crypto/cpt/base/cpt_device.h
>  create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.c
>  create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.h
> 
> +#include <assert.h>
> +#include "cpt_request_mgr.h"
> +#include <rte_eal_memconfig.h>
> +
> +#ifdef CPT_DEBUG

Remove CPT_DEBUG. No harming in compiling these definitions either case.
It will avoid the chance of build breakage.

> +static inline void *
> +os_iova2va(phys_addr_t physaddr)
> +{
> +	return rte_mem_iova2virt(physaddr);
> +}
> +
> +static inline void __cpt_dump_buffer(const char *prefix_str,
> +				     void *buf, size_t len, int rowsize)
> +{
> +	size_t i = 0;
> +	unsigned char *ptr = (unsigned char *)buf;
> +
> +	PRINT("\n%s[%p]", prefix_str, buf);


Something cpt_log() makes more sense than PRINT

> +	PRINT("\n%.8lx: ", i);
> +
> +	if (buf == NULL) {
> +		PRINT("\n!!!NULL ptr\n");
> +		abort();
> +	}
> +
> +	for (i = 0; i < len; i++) {
> +		if (i && !(i % rowsize))
> +			PRINT("\n%.8lx: ", i);
> +		PRINT("%02x ", ptr[i]);
> +	}
> +	PRINT("\n\n");
> +}
> +
> +static inline void cpt_dump_buffer(const char *prefix_str,
> +				   void *buf, size_t len)
> +{
> +	__cpt_dump_buffer(prefix_str, buf, len, 8);
> +}
> +
> +#define cpt_fn_trace(fmt, ...)				\
> +	do {						\
> +		if (msg_req_trace(debug))		\
> +			cpt_info(fmt, ##__VA_ARGS__);	\
> +	} while (0)
> +
> +static inline void dump_cpt_request_info(struct cpt_request_info *req,
> +					 cpt_inst_s_t *inst)
> +{
> +	vq_cmd_word0_t vq_cmd_w0;
> +	vq_cmd_word3_t vq_cmd_w3;
> +	uint16_t opcode, param1, param2, dlen;
> +
> +	vq_cmd_w0.u64 = be64toh(inst->s.ei0);
> +	opcode = be16toh(vq_cmd_w0.s.opcode);
> +	param1 = be16toh(vq_cmd_w0.s.param1);
> +	param2 = be16toh(vq_cmd_w0.s.param2);
> +	dlen = be16toh(vq_cmd_w0.s.dlen);
> +	vq_cmd_w3.u64 = inst->s.ei3;
> +
> +	PRINT("\ncpt Request Info...\n");
> +	PRINT("\tdma_mode: %u\n", req->dma_mode);
> +	PRINT("\tis_se   : %u\n", req->se_req);
> +	PRINT("\tgrp     : 0\n");
> +
> +	PRINT("\nRequest Info...\n");
> +	PRINT("\topcode: 0x%0x\n", opcode);
> +	PRINT("\tparam1: 0x%0x\n", param1);
> +	PRINT("\tparam2: 0x%0x\n", param2);
> +	PRINT("\tdlen: %u\n", dlen);
> +	PRINT("\tctx_handle vaddr %p, dma 0x%lx\n",
> +		     os_iova2va((uint64_t)vq_cmd_w3.s.cptr),
> +		     (uint64_t)vq_cmd_w3.s.cptr);
> +}
> +
> +			list_ptr[i*4+0].dma_addr = be64toh(sg_ptr->ptr[0]);
> +			list_ptr[i*4+1].dma_addr = be64toh(sg_ptr->ptr[1]);
> +			list_ptr[i*4+2].dma_addr = be64toh(sg_ptr->ptr[2]);
> +			list_ptr[i*4+3].dma_addr = be64toh(sg_ptr->ptr[3]);

use dpdk primitives for be64toh if possible.

> +
> +			list_ptr[i*4+0].vaddr =
> +				os_iova2va(list_ptr[i*4+0].dma_addr);
> +			list_ptr[i*4+1].vaddr =
> +				os_iova2va(list_ptr[i*4+1].dma_addr);
> +			list_ptr[i*4+2].vaddr =
> +				os_iova2va(list_ptr[i*4+2].dma_addr);
> +			list_ptr[i*4+3].vaddr =
> +				os_iova2va(list_ptr[i*4+3].dma_addr);
> +			sg_ptr++;
> +		}
> +		components = list_cnt % 4;
> +
> +		switch (components) {
> +		case 3:
> +			list_ptr[i*4+2].size = be16toh(sg_ptr->u.s.len[2]);
> +			list_ptr[i*4+2].dma_addr = be64toh(sg_ptr->ptr[2]);
> +			list_ptr[i*4+2].vaddr =
> +				os_iova2va(list_ptr[i*4+2].dma_addr);
> +			/* fall through */
> +		case 2:
> +			list_ptr[i*4+1].size = be16toh(sg_ptr->u.s.len[1]);
> +			list_ptr[i*4+1].dma_addr = be64toh(sg_ptr->ptr[1]);
> +			list_ptr[i*4+1].vaddr =
> +				os_iova2va(list_ptr[i*4+1].dma_addr);
> +			/* fall through */
> +		case 1:
> +			list_ptr[i*4+0].size = be16toh(sg_ptr->u.s.len[0]);
> +			list_ptr[i*4+0].dma_addr = be64toh(sg_ptr->ptr[0]);
> +			list_ptr[i*4+0].vaddr =
> +				os_iova2va(list_ptr[i*4+0].dma_addr);
> +			break;
> +		default:
> +			break;
> +		}
> +
> +		for (i = 0; i < list_cnt; i++) {
> +			snprintf(suffix, sizeof(suffix),
> +				 "%s[%d]: vaddr %p, dma 0x%lx len %u: ",
> +				 list, i, list_ptr[i].vaddr,
> +				 list_ptr[i].dma_addr,
> +				 list_ptr[i].size);
> +			if (data)
> +				cpt_dump_buffer(suffix,
> +						list_ptr[i].vaddr,
> +						list_ptr[i].size);
> +			else
> +				PRINT("%s\n", suffix);
> +		}
> +	} else {
> +		PRINT("%s: Direct Mode\n", header);
> +
> +		if (glist) {
> +			snprintf(suffix, sizeof(suffix),
> +				 "DPTR: vaddr %p, dma 0x%lx len %u: ",
> +				 os_iova2va(inst->s.ei1),
> +				 inst->s.ei1, dlen);
> +			if (data)
> +				cpt_dump_buffer(suffix,
> +						os_iova2va(inst->s.ei1),
> +						dlen);
> +			else
> +				PRINT("%s\n", suffix);
> +		} else {
> +			snprintf(suffix, sizeof(suffix),
> +				 "RPTR: vaddr %p, dma 0x%lx len %u+..: ",
> +				 os_iova2va(inst->s.ei2),
> +				 inst->s.ei2, dlen);
> +			/*
> +			 * In direct mode, we don't have rlen
> +			 * to dump exactly, so dump dlen + 32
> +			 */
> +			if (data)
> +				cpt_dump_buffer(suffix,
> +						os_iova2va(inst->s.ei2),
> +						dlen + 32);
> +			else
> +				PRINT("%s\n", suffix);
> +		}
> +	}
> +}
> +
> +
> +#else
> +
> +
> +int cptvf_deinit_device(struct cpt_vf *dev)
> +{
> +	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
> +
> +	/* Do misc work one last time */
> +	cptvf_poll_misc(cptvf);
> +
> +	/* TODO anything else ?? */

Remove unclear TODOs

> +
> +	return 0;
> +}
> +
> +int cptvf_init_device(struct cpt_vf *cptvf,
> +		      void *pdev,
> +		      void *reg_base,
> +		      char *name,
> +		      uint32_t flags)
> +{
> +	(void) flags;


RTE_SET_USED

> +
> +	memset(cptvf, 0, sizeof(struct cpt_vf));
> +
> +	/* Bar0 base address */
> +	cptvf->reg_base = reg_base;
> +	strncpy(cptvf->dev_name, name, 32);
> +
> +	cptvf->nr_queues = 1;
> +	cptvf->max_queues = 1;
> +	cptvf->pdev = pdev;
> +
> +	/* To clear if there are any pending mbox msgs */
> +	cptvf_poll_misc(cptvf);
> +
> +	if (cpt_vf_init(cptvf)) {
> +		PMD_DRV_LOG(ERR, "Failed to initialize CPT VF device\n");
> +		return -1;
> +	}
> +
> +	return 0;
> +}
> +
> +
> +	uint16_t flags;
> +	/**< Flags to hold device status bits */
> +	uint8_t  vfid;
> +	/**< Device Index (0...CPT_MAX_VQ_NUM */
> +	uint8_t  vftype;
> +	/**< VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
> +	uint8_t  vfgrp;
> +	/**< VF group (0 - 8) */
> +	uint8_t  node;
> +	/**< Operating node: Bits (46:44) in BAR0 address */
> +
> +	/* VF-PF mailbox communication */
> +	bool pf_acked;
> +	bool pf_nacked;
> +	char dev_name[32];
> +} ____cacheline_aligned_in_smp;


Use DPDK primitive if possible.

> +
> +#define CPT_CSR_REG_BASE(cpt)       ((cpt)->reg_base)
> +

Re: [dpdk-dev] [PATCH 03/16] crypto/cpt/base: add hardware initialization API for CPT

[De Lara Guarch, Pablo]

> -----Original Message-----
> From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com]
> Sent: Thursday, June 14, 2018 4:14 AM
> To: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> Cc: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Thomas Monjalon
> <thomas@monjalon.net>; Nithin Dabilpuram <nithin.dabilpuram@cavium.com>;
> Ankur Dwivedi <ankur.dwivedi@cavium.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> Subject: Re: [PATCH 03/16] crypto/cpt/base: add hardware initialization API for
> CPT
> 
> -----Original Message-----
> > Date: Fri,  8 Jun 2018 22:15:12 +0530
> > From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> > To: Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara
> > <pablo.de.lara.guarch@intel.com>, Thomas Monjalon
> > <thomas@monjalon.net>
> > Cc: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>, Ankur Dwivedi
> > <ankur.dwivedi@cavium.com>, Jerin Jacob
> > <jerin.jacob@caviumnetworks.com>,  Murthy NSSR
> > <Nidadavolu.Murthy@cavium.com>, Narayana Prasad
> > <narayanaprasad.athreya@caviumnetworks.com>, Ragothaman Jayaraman
> > <Ragothaman.Jayaraman@cavium.com>, Srisivasubramanian Srinivasan
> > <Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org
> > Subject: [PATCH 03/16] crypto/cpt/base: add hardware initialization
> > API for  CPT
> > X-Mailer: git-send-email 2.7.4
> >
> > From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> >
> > Adds hardware device initialization specific api for Cavium CPT device.
> >
> > Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> > Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> > Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> > Signed-off-by: Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>
> > Signed-off-by: Srisivasubramanian Srinivasan
> > <Srisivasubramanian.Srinivasan@cavium.com>
> > ---
> >  drivers/crypto/cpt/base/cpt8xxx_device.c | 200 ++++++++++++++++
> > drivers/crypto/cpt/base/cpt8xxx_device.h |  85 +++++++
> >  drivers/crypto/cpt/base/cpt_debug.h      | 231 +++++++++++++++++++
> >  drivers/crypto/cpt/base/cpt_device.c     | 383
> +++++++++++++++++++++++++++++++
> >  drivers/crypto/cpt/base/cpt_device.h     | 162 +++++++++++++
> >  drivers/crypto/cpt/base/cpt_vf_mbox.c    | 176 ++++++++++++++
> >  drivers/crypto/cpt/base/cpt_vf_mbox.h    |  60 +++++
> >  7 files changed, 1297 insertions(+)
> >  create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.c
> >  create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.h
> >  create mode 100644 drivers/crypto/cpt/base/cpt_debug.h
> >  create mode 100644 drivers/crypto/cpt/base/cpt_device.c
> >  create mode 100644 drivers/crypto/cpt/base/cpt_device.h
> >  create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.c
> >  create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.h
> >
> > +#include <assert.h>
> > +#include "cpt_request_mgr.h"
> > +#include <rte_eal_memconfig.h>

List the external to DPDK includes first, then internal to DPDK and then internal to this PMD,
separating these three blocks with a blank line.

> > +
> > +#ifdef CPT_DEBUG
> 
> Remove CPT_DEBUG. No harming in compiling these definitions either case.
> It will avoid the chance of build breakage.
> 

...

> > +int cptvf_deinit_device(struct cpt_vf *dev) {
> > +	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
> > +
> > +	/* Do misc work one last time */
> > +	cptvf_poll_misc(cptvf);
> > +
> > +	/* TODO anything else ?? */
> 
> Remove unclear TODOs
> 
> > +
> > +	return 0;
> > +}
> > +
> > +int cptvf_init_device(struct cpt_vf *cptvf,

Return type should be in the line above the function name,
as per DPDK coding style guidelines.

> > +		      void *pdev,
> > +		      void *reg_base,
> > +		      char *name,
> > +		      uint32_t flags)
> > +{
> > +	(void) flags;
> 
> 
> RTE_SET_USED

Actually, why don't you just remove the parameter?

Thanks,
Pablo

[dpdk-dev] [PATCH 04/16] crypto/cpt/base: add hardware enq/deq API for CPT

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@cavium.com>

Adds hardware enqueue/dequeue API of instructions to a queue pair
for Cavium CPT device.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/base/cpt.h             | 102 +++++++
 drivers/crypto/cpt/base/cpt_device.c      |   4 +-
 drivers/crypto/cpt/base/cpt_request_mgr.c | 424 ++++++++++++++++++++++++++++++
 drivers/crypto/cpt/base/cpt_request_mgr.h |  75 ++++++
 4 files changed, 603 insertions(+), 2 deletions(-)
 create mode 100644 drivers/crypto/cpt/base/cpt.h
 create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.c
 create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.h

diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h
new file mode 100644
index 0000000..11407ae
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __BASE_CPT_H__
+#define __BASE_CPT_H__
+
+/* Linux Includes */
+#include <endian.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <sys/cdefs.h>
+#include <unistd.h>
+#include <assert.h>
+
+/* DPDK includes */
+#include <rte_byteorder.h>
+#include <rte_common.h>
+#include <rte_errno.h>
+#include <rte_memory.h>
+#include <rte_prefetch.h>
+
+#include "../cpt_pmd_logs.h"
+#include "mcode_defines.h"
+
+/** @cond __INTERNAL_DOCUMENTATION__ */
+
+/* Declarations */
+typedef struct cpt_instance cpt_instance_t;
+
+/*
+ * Generic Defines
+ */
+
+/* Buffer pointer */
+typedef struct buf_ptr {
+	void *vaddr;
+	phys_addr_t dma_addr;
+	uint32_t size;
+	uint32_t resv;
+} buf_ptr_t;
+
+/* IOV Pointer */
+typedef struct{
+	int buf_cnt;
+	buf_ptr_t bufs[0];
+} iov_ptr_t;
+
+typedef struct app_data {
+	uint64_t pktout;
+	void *marker;
+} app_data_t;
+
+/* Instance operations */
+
+/* Enqueue an SE/AE request */
+int cpt_enqueue_req(cpt_instance_t *inst, void *req, uint8_t flags,
+	      void *event, uint64_t event_flags);
+
+/* Dequeue completed SE requests as burst */
+int32_t cpt_dequeue_burst(cpt_instance_t *instance, uint16_t cnt,
+			  void *resp[], uint8_t cc[]);
+
+/* Marks event as done in event driven mode */
+int32_t cpt_event_mark_done(void *marker, uint8_t *op_error);
+
+/* Checks queue full condition */
+uint16_t cpt_queue_full(cpt_instance_t *instance);
+
+/* Misc */
+uint32_t cpt_get_instance_count(void);
+
+#define ENQ_FLAG_SYNC		0x01
+#define ENQ_FLAG_EVENT		0x02
+#define ENQ_FLAG_NODOORBELL	0x04
+#define ENQ_FLAG_ONLY_DOORBELL	0x08
+
+
+#define OCTTX_EVENT_TAG(__flags) (__flags & 0xffffffff)
+#define OCTTX_EVENT_GRP(__flags) ((__flags >> 32) & 0xffff)
+#define OCTTX_EVENT_TT(__flags) ((__flags >> 48) & 0xff)
+
+#define OCTTX_EVENT_FLAGS(__tag, __grp, __tt)    \
+	(((uint64_t)__tag & 0xffffffff) |        \
+	 (((uint64_t)__grp & 0xffff) << 32) |    \
+	 (((uint64_t)__tt & 0xff) << 48))
+
+
+/* cpt instance */
+struct cpt_instance {
+	/* 0th cache line */
+	uint32_t queue_id;
+	uint64_t rsvd;
+};
+
+#define __hot __attribute__((hot))
+/** @endcond */
+
+#endif /* __BASE_CPT_H__ */
diff --git a/drivers/crypto/cpt/base/cpt_device.c b/drivers/crypto/cpt/base/cpt_device.c
index b7cd5b5..a50e5b8 100644
--- a/drivers/crypto/cpt/base/cpt_device.c
+++ b/drivers/crypto/cpt/base/cpt_device.c
@@ -193,7 +193,7 @@ int cptvf_get_resource(struct cpt_vf *dev,
 	uint64_t *next_ptr;
 	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
 
-	PMD_DRV_LOG(DEBUG, "Initializing csp resource %s\n", cptvf->dev_name);
+	PMD_DRV_LOG(DEBUG, "Initializing cpt resource %s\n", cptvf->dev_name);
 
 	cpt_instance = &cptvf->instance;
 
@@ -323,7 +323,7 @@ int cptvf_put_resource(cpt_instance_t *instance)
 		return -EINVAL;
 	}
 
-	PMD_DRV_LOG(DEBUG, "Releasing csp device %s\n", cptvf->dev_name);
+	PMD_DRV_LOG(DEBUG, "Releasing cpt device %s\n", cptvf->dev_name);
 
 	rz = (struct rte_memzone *)instance->rsvd;
 	rte_memzone_free(rz);
diff --git a/drivers/crypto/cpt/base/cpt_request_mgr.c b/drivers/crypto/cpt/base/cpt_request_mgr.c
new file mode 100644
index 0000000..8b9b1ff
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt_request_mgr.c
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include "cpt_request_mgr.h"
+#include "cpt_debug.h"
+#include <rte_atomic.h>
+
+#define MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
+
+#define __hot __attribute__((hot))
+
+static inline uint64_t cpu_cycles(void)
+{
+	return rte_get_timer_cycles();
+}
+
+static inline uint64_t cpu_cycles_freq(void)
+{
+	return rte_get_timer_hz();
+}
+
+static inline void *
+get_cpt_inst(struct command_queue *cqueue, void *req)
+{
+	(void)req;
+	PMD_TX_LOG(DEBUG, "CPT queue idx %u, req %p\n", cqueue->idx, req);
+	return &cqueue->qhead[cqueue->idx * CPT_INST_SIZE];
+}
+
+static inline void
+mark_cpt_inst(struct cpt_vf *cptvf,
+	      struct command_queue *queue,
+	      uint32_t ring_door_bell)
+{
+#ifdef CMD_DEBUG
+	/* DEBUG */
+	{
+		uint32_t i = queue->idx * CPT_INST_SIZE;
+		cpt_inst_s_t *cmd = (void *)&queue->qhead[i];
+		uint64_t *p = (void *)&queue->qhead[i];
+
+		PRINT("\nQUEUE parameters:");
+		PRINT("Queue index           = %u\n",
+		      queue->idx);
+		PRINT("Queue HEAD            = %p\n",
+		      queue->qhead);
+		PRINT("Command Entry         = %p\n",
+		      cmd);
+
+		PRINT("\nCPT_INST_S format:");
+		PRINT("cmd->s.doneint = %x\n", cmd->s.doneint);
+		PRINT("cmd->s.res_addr  = %lx\n", cmd->s.res_addr);
+		PRINT("cmd->s.grp       = %x\n", cmd->s.grp);
+		PRINT("cmd->s.tag       = %x\n", cmd->s.tag);
+		PRINT("cmd->s.tt        = %x\n", cmd->s.tt);
+		PRINT("cmd->s.wq_ptr    = %lx\n", cmd->s.wq_ptr);
+		PRINT("cmd->s.ei0       = %lx\n", cmd->s.ei0);
+		PRINT("cmd->s.ei1       = %lx\n", cmd->s.ei1);
+		PRINT("cmd->s.ei2       = %lx\n", cmd->s.ei2);
+		PRINT("cmd->s.ei3       = %lx\n", cmd->s.ei3);
+
+		PRINT("\nCommand dump from queue HEAD:");
+		for (i = 0; i < CPT_INST_SIZE / 8; i++)
+			PRINT("%lx\n", p[i]);
+	}
+#endif
+	if (unlikely(++queue->idx >= DEFAULT_CMD_QCHUNK_SIZE)) {
+		uint32_t cchunk = queue->cchunk;
+		MOD_INC(cchunk, DEFAULT_CMD_QCHUNKS);
+		queue->qhead = queue->chead[cchunk].head;
+		queue->idx = 0;
+		queue->cchunk = cchunk;
+	}
+
+	if (ring_door_bell) {
+		/* Memory barrier to flush pending writes */
+		rte_smp_wmb();
+		cptvf_write_vq_doorbell(cptvf, ring_door_bell);
+	}
+}
+
+static inline uint8_t
+check_nb_command_id(cpt_request_info_t *user_req, struct cpt_vf *cptvf)
+{
+	uint8_t ret = ERR_REQ_PENDING;
+	volatile cpt_res_s_t *cptres;
+
+	cptres = (volatile cpt_res_s_t *)user_req->completion_addr;
+
+	if (unlikely(cptres->s.compcode == CPT_COMP_E_NOTDONE)) {
+		/*
+		 * Wait for some time for this command to get completed
+		 * before timing out
+		 */
+		if (cpu_cycles() < user_req->time_out)
+			return ret;
+		/*
+		 * TODO: See if alternate caddr can be used to not loop
+		 * longer than needed.
+		 */
+		if ((cptres->s.compcode == CPT_COMP_E_NOTDONE) &&
+		    (user_req->extra_time < TIME_IN_RESET_COUNT)) {
+			user_req->extra_time++;
+			return ret;
+		}
+
+		if (cptres->s.compcode != CPT_COMP_E_NOTDONE)
+			goto complete;
+
+		ret = ERR_REQ_TIMEOUT;
+		PMD_DRV_LOG_RAW(ERR, "Request %p timedout\n", user_req);
+		cptvf_poll_misc(cptvf);
+		dump_cpt_request_sglist(&user_req->dbg_inst,
+					"Response Packet Gather in", 1, 1);
+		goto exit;
+	}
+
+complete:
+	if (likely(cptres->s.compcode == CPT_COMP_E_GOOD)) {
+		ret = 0; /* success */
+		PMD_RX_LOG(DEBUG, "MC status %.8x\n",
+			   *((volatile uint32_t *)user_req->alternate_caddr));
+		PMD_RX_LOG(DEBUG, "HW status %.8x\n",
+			   *((volatile uint32_t *)user_req->completion_addr));
+	} else if ((cptres->s.compcode == CPT_COMP_E_SWERR) ||
+		   (cptres->s.compcode == CPT_COMP_E_FAULT)) {
+		ret = (uint8_t)*user_req->alternate_caddr;
+		if (!ret)
+			ret = ERR_BAD_ALT_CCODE;
+		PMD_RX_LOG(DEBUG, "Request %p : failed with %s : err code :"
+			   "%x\n", user_req,
+			   (cptres->s.compcode == CPT_COMP_E_FAULT) ?
+			   "DMA Fault" : "Software error", ret);
+	} else {
+		PMD_DRV_LOG_RAW(ERR, "Request %p : unexpected completion code"
+			   " %d\n",
+			   user_req, cptres->s.compcode);
+		ret = (uint8_t)*user_req->alternate_caddr;
+	}
+
+exit:
+	dump_cpt_request_sglist(&user_req->dbg_inst,
+				"Response Packet Scatter Out", 1, 0);
+	return ret;
+}
+
+
+/*
+ * cpt_enqueue_req()
+ *
+ * SE & AE request enqueue function
+ */
+int32_t __hot
+cpt_enqueue_req(cpt_instance_t *instance, void *req, uint8_t flags,
+		void *event, uint64_t event_flags)
+{
+	struct pending_queue *pqueue;
+	struct cpt_vf *cptvf;
+	cpt_inst_s_t *cpt_ist_p = NULL;
+	cpt_request_info_t *user_req = (cpt_request_info_t *)req;
+	struct command_queue *cqueue;
+	int32_t ret = 0;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (unlikely(!instance)) {
+		PMD_DRV_LOG_RAW(ERR, "Invalid inputs (instance: %p, req: %p)\n",
+			   instance, req);
+		return -EINVAL;
+	}
+#endif
+
+	cptvf = (struct cpt_vf *)instance;
+	pqueue = &cptvf->pqueue;
+
+	if (unlikely(!req)) {
+		/* ring only pending doorbells */
+		if ((flags & ENQ_FLAG_ONLY_DOORBELL) && pqueue->p_doorbell) {
+			/* Memory barrier to flush pending writes */
+			rte_smp_wmb();
+			cptvf_write_vq_doorbell(cptvf, pqueue->p_doorbell);
+			pqueue->p_doorbell = 0;
+		}
+		return 0;
+	}
+
+#if defined(ATOMIC_THROTTLING_COUNTER)
+	/* Ask the application to try again later */
+	if (unlikely(cpt_pmd_pcount_load(&pqueue->pending_count) >=
+		     DEFAULT_CMD_QLEN)) {
+		return -EAGAIN;
+	}
+#else
+	if (unlikely(pqueue->pending_count >= DEFAULT_CMD_QLEN))
+		return -EAGAIN;
+#endif
+	cqueue = &cptvf->cqueue;
+	cpt_ist_p = get_cpt_inst(cqueue, req);
+	rte_prefetch_non_temporal(cpt_ist_p);
+
+	/* EI0, EI1, EI2, EI3 are already prepared */
+	/* HW W0 */
+	cpt_ist_p->u[0] = 0;
+	/* HW W1 */
+	cpt_ist_p->s.res_addr = user_req->comp_baddr;
+	/* HW W2 */
+	cpt_ist_p->u[2] = 0;
+	/* HW W3 */
+	cpt_ist_p->s.wq_ptr = 0;
+
+	/* MC EI0 */
+	cpt_ist_p->s.ei0 = user_req->ist.ei0;
+	/* MC EI1 */
+	cpt_ist_p->s.ei1 = user_req->ist.ei1;
+	/* MC EI2 */
+	cpt_ist_p->s.ei2 = user_req->ist.ei2;
+	/* MC EI3 */
+	cpt_ist_p->s.ei3 = user_req->ist.ei3;
+
+	PMD_TX_LOG(DEBUG, "req: %p op: %p dma_mode 0x%x se_req %u\n",
+		   req,
+		   user_req->op,
+		   user_req->dma_mode,
+		   user_req->se_req);
+
+#ifdef CPT_DEBUG
+	{
+		vq_cmd_word0_t vq_cmd_w0;
+		vq_cmd_word3_t vq_cmd_w3;
+
+		vq_cmd_w3.u64 = cpt_ist_p->s.ei3;
+		vq_cmd_w0.u64 = be64toh(cpt_ist_p->s.ei0);
+		user_req->dbg_inst = *cpt_ist_p;
+
+		if (vq_cmd_w3.s.cptr) {
+			PMD_TX_LOG(DEBUG, "Context Handle: 0x%016lx\n",
+				   (uint64_t)vq_cmd_w3.s.cptr);
+			/* Dump max context i.e 448 bytes */
+			cpt_dump_buffer("CONTEXT",
+					os_iova2va((uint64_t)vq_cmd_w3.s.cptr),
+					448);
+		}
+
+		dump_cpt_request_info(user_req, cpt_ist_p);
+		dump_cpt_request_sglist(cpt_ist_p, "Request (src)", 1, 1);
+		dump_cpt_request_sglist(cpt_ist_p, "Request (dst)", 0, 0);
+		cpt_dump_buffer("VQ command word0", &cpt_ist_p->u[4],
+				sizeof(vq_cmd_w0));
+		cpt_dump_buffer("VQ command word1", &cpt_ist_p->u[5],
+				sizeof(uint64_t));
+		cpt_dump_buffer("VQ command word2", &cpt_ist_p->u[6],
+				sizeof(uint64_t));
+		cpt_dump_buffer("VQ command word3", &cpt_ist_p->u[7],
+				sizeof(vq_cmd_w3));
+	}
+#endif
+
+	if (likely(!(flags & ENQ_FLAG_SYNC))) {
+		void *op = user_req->op;
+
+		if (unlikely(flags & ENQ_FLAG_EVENT)) {
+			app_data_t *app_data = op;
+
+			/* Event based completion */
+			cpt_ist_p->s.tag = OCTTX_EVENT_TAG(event_flags);
+			cpt_ist_p->s.grp = OCTTX_EVENT_GRP(event_flags);
+			cpt_ist_p->s.tt = OCTTX_EVENT_TT(event_flags);
+			cpt_ist_p->s.wq_ptr = (uint64_t)event;
+
+#if defined(ATOMIC_THROTTLING_COUNTER)
+			app_data->marker = user_req;
+			__atomic_fetch_add(&pqueue->pending_count,
+					   1, __ATOMIC_RELAXED);
+#else
+			rid_t *rid_e;
+			/*
+			 * Mark it as in progress in pending queue, software
+			 * will mark it when completion is received
+			 */
+			rid_e = &pqueue->rid_queue[pqueue->enq_tail];
+			rid_e->rid = (uint64_t)user_req;
+			/* rid_e->op = op; */
+			MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);
+			app_data->marker = rid_e;
+#endif
+
+			cpt_dump_buffer("CPT Instruction with wqe", cpt_ist_p,
+					sizeof(*cpt_ist_p));
+
+			mark_cpt_inst(cptvf, cqueue, 1);
+
+		} else {
+			uint32_t doorbell = 0;
+
+			if (likely(flags & ENQ_FLAG_NODOORBELL))
+				pqueue->p_doorbell++;
+			else
+				doorbell = ++pqueue->p_doorbell;
+
+			/* Fill time_out cycles */
+			user_req->time_out = cpu_cycles() +
+				DEFAULT_COMMAND_TIMEOUT * cpu_cycles_freq();
+			user_req->extra_time = 0;
+
+			cpt_dump_buffer("CPT Instruction", cpt_ist_p,
+					sizeof(*cpt_ist_p));
+
+			/* Default mode of software queue */
+			mark_cpt_inst(cptvf, cqueue, doorbell);
+
+			pqueue->p_doorbell -= doorbell;
+			pqueue->rid_queue[pqueue->enq_tail].rid =
+				(uint64_t)user_req;
+			/* pqueue->rid_queue[pqueue->enq_tail].op = op; */
+			/* We will use soft queue length here to limit
+			 * requests
+			 */
+			MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);
+			pqueue->pending_count += 1;
+		}
+
+		PMD_TX_LOG(DEBUG, "Submitted NB cmd with request: %p op: %p\n",
+			   user_req, op);
+	} else {
+		/*
+		 * Synchronous operation,
+		 * hold until completion / timeout
+		 */
+		/* Fill time_out cycles */
+		user_req->time_out = cpu_cycles() +
+			DEFAULT_COMMAND_TIMEOUT * cpu_cycles_freq();
+		user_req->extra_time = 0;
+
+		cpt_dump_buffer("CPT Instruction", cpt_ist_p,
+				sizeof(*cpt_ist_p));
+
+		/* Default mode of software queue */
+		mark_cpt_inst(cptvf, cqueue, 1);
+
+		do {
+			/* TODO: should we pause */
+			ret = check_nb_command_id(user_req, cptvf);
+			cptvf_poll_misc(cptvf);
+#if 0
+			PMD_TX_LOG(DEBUG, "Doorbell count for cptvf %s: %u\n",
+				   cptvf->dev_name,
+				   cptvf_read_vq_doorbell(cptvf));
+#endif
+		} while (ret == ERR_REQ_PENDING);
+
+		PMD_TX_LOG(DEBUG, "Completed blocking cmd req: 0x%016llx, rc "
+			   "0x%x\n", (unsigned long long)user_req, ret);
+	}
+
+	return ret;
+}
+
+
+int32_t __hot
+cpt_dequeue_burst(cpt_instance_t *instance, uint16_t cnt,
+		  void *resp[], uint8_t cc[])
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct pending_queue *pqueue = &cptvf->pqueue;
+	cpt_request_info_t *user_req;
+	rid_t *rid_e;
+	int i, count, pcount;
+	uint8_t ret;
+
+	pcount = pqueue->pending_count;
+	count = (cnt > pcount) ? pcount : cnt;
+
+	for (i = 0; i < count; i++) {
+		rid_e = &pqueue->rid_queue[pqueue->deq_head];
+		user_req = (cpt_request_info_t *)(rid_e->rid);
+
+		if (likely((i+1) < count))
+			rte_prefetch_non_temporal((void *)rid_e[1].rid);
+
+		ret = check_nb_command_id(user_req, cptvf);
+
+		if (unlikely(ret == ERR_REQ_PENDING)) {
+			/* Stop checking for completions */
+			break;
+		}
+
+		/* Return completion code and op handle */
+		cc[i] = (uint8_t)ret;
+		resp[i] = user_req->op;
+		PMD_RX_LOG(DEBUG, "Request %p Op %p completed with code %d",
+			   user_req, user_req->op, ret);
+
+		MOD_INC(pqueue->deq_head, DEFAULT_CMD_QLEN);
+		pqueue->pending_count -= 1;
+	}
+
+	return i;
+}
+
+uint16_t __hot
+cpt_queue_full(cpt_instance_t *instance)
+{
+	struct cpt_vf *cptvf;
+	struct pending_queue *pqueue;
+	uint16_t avail;
+
+	cptvf = (struct cpt_vf *)instance;
+	pqueue = &cptvf->pqueue;
+#if defined(ATOMIC_THROTTLING_COUNTER)
+	avail = DEFAULT_CMD_QLEN - cpt_pmd_pcount_load(&pqueue->pending_count);
+	/* Ask the application to try again later */
+	if (avail <= 0)
+		return 0;
+
+	return avail;
+#else
+	avail = DEFAULT_CMD_QLEN - pqueue->pending_count;
+	/*
+	 * This will be NULL if instruction
+	 * that was sent earlier which this entry was complete
+	 */
+	return avail;
+#endif
+}
diff --git a/drivers/crypto/cpt/base/cpt_request_mgr.h b/drivers/crypto/cpt/base/cpt_request_mgr.h
new file mode 100644
index 0000000..dfa4046
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt_request_mgr.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __REQUEST_MANGER_H
+#define __REQUEST_MANGER_H
+
+#include "cpt8xxx_device.h"
+
+#define TIME_IN_RESET_COUNT  5
+#define COMPLETION_CODE_SIZE 8
+#define COMPLETION_CODE_INIT 0
+
+#define SG_LIST_HDR_SIZE  (8u)
+#define SG_ENTRY_SIZE sizeof(sg_comp_t)
+
+#define AE_CORE_REQ 0
+#define SE_CORE_REQ 1
+
+#define CTRL_DMA_MODE_SGIO	2	/* DMA Mode but SGIO is already setup */
+
+#define MRS(reg) \
+	({ \
+	 uint64_t val; \
+	 __asm volatile("mrs %0, " #reg : "=r" (val)); \
+	 val; \
+	 })
+
+int calculate_pad(uint8_t *ipad, uint8_t *opad, auth_type_t hash_type,
+	      uint8_t *key, uint32_t keylen);
+
+typedef union opcode_info {
+	uint16_t flags;
+	struct {
+		uint8_t major;
+		uint8_t minor;
+	} s;
+} opcode_info_t;
+
+typedef struct sglist_comp {
+	union {
+		uint64_t len;
+		struct {
+			uint16_t len[4];
+		} s;
+	} u;
+	uint64_t ptr[4];
+} sg_comp_t;
+
+struct cpt_request_info {
+	/* fast path fields */
+	uint64_t dma_mode	: 2;	/**< DMA mode */
+	uint64_t se_req		: 1;	/**< To SE core */
+	uint64_t comp_baddr	: 61;
+	volatile uint64_t *completion_addr;
+	volatile uint64_t *alternate_caddr;
+	void *op; /** Reference to operation */
+	struct {
+		uint64_t ei0;
+		uint64_t ei1;
+		uint64_t ei2;
+		uint64_t ei3;
+	} ist;
+
+	/* slow path fields */
+	uint64_t time_out;
+	uint8_t extra_time;
+#ifdef CPT_DEBUG
+	cpt_inst_s_t dbg_inst;
+#endif
+
+};
+
+typedef struct cpt_request_info cpt_request_info_t;
+#endif
-- 
1.9.3

Re: [dpdk-dev] [PATCH 04/16] crypto/cpt/base: add hardware enq/deq API for CPT

[Jerin Jacob]

-----Original Message-----
> Date: Fri,  8 Jun 2018 22:15:13 +0530
> From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> To: Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara
>  <pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>
> Cc: Ankur Dwivedi <ankur.dwivedi@cavium.com>, Jerin Jacob
>  <jerin.jacob@caviumnetworks.com>, Murthy NSSR
>  <Nidadavolu.Murthy@cavium.com>, Narayana Prasad
>  <narayanaprasad.athreya@caviumnetworks.com>, Nithin Dabilpuram
>  <nithin.dabilpuram@cavium.com>, Ragothaman Jayaraman
>  <Ragothaman.Jayaraman@cavium.com>, Srisivasubramanian Srinivasan
>  <Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org
> Subject: [PATCH 04/16] crypto/cpt/base: add hardware enq/deq API for CPT
> X-Mailer: git-send-email 2.7.4
> 
> From: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> 
> Adds hardware enqueue/dequeue API of instructions to a queue pair
> for Cavium CPT device.
> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
> ---
>  drivers/crypto/cpt/base/cpt.h             | 102 +++++++
>  drivers/crypto/cpt/base/cpt_device.c      |   4 +-
>  drivers/crypto/cpt/base/cpt_request_mgr.c | 424 ++++++++++++++++++++++++++++++
>  drivers/crypto/cpt/base/cpt_request_mgr.h |  75 ++++++
>  4 files changed, 603 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/crypto/cpt/base/cpt.h
>  create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.c
>  create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.h
> 
> diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h
> new file mode 100644
> index 0000000..11407ae
> --- /dev/null
> +++ b/drivers/crypto/cpt/base/cpt.h
> @@ -0,0 +1,102 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2017 Cavium, Inc
> + */
> +
> +#ifndef __BASE_CPT_H__
> +#define __BASE_CPT_H__
> +
> +/* Linux Includes */
> +#include <endian.h>
> +#include <stdint.h>
> +#include <string.h>
> +#include <stdio.h>
> +#include <stdbool.h>
> +#include <errno.h>
> +#include <sys/cdefs.h>
> +#include <unistd.h>
> +#include <assert.h>

alphabetical order

> +
> +/* DPDK includes */
> +#include <rte_byteorder.h>
> +#include <rte_common.h>
> +#include <rte_errno.h>
> +#include <rte_memory.h>
> +#include <rte_prefetch.h>
> +
> +#include "../cpt_pmd_logs.h"
> +#include "mcode_defines.h"
> +
> +/** @cond __INTERNAL_DOCUMENTATION__ */
> +
> +/* Declarations */
> +typedef struct cpt_instance cpt_instance_t;
> +
> +/*
> + * Generic Defines
> + */
> +
> +/* Buffer pointer */
> +typedef struct buf_ptr {
> +	void *vaddr;
> +	phys_addr_t dma_addr;
> +	uint32_t size;
> +	uint32_t resv;
> +} buf_ptr_t;
> +
> +/* IOV Pointer */
> +typedef struct{
> +	int buf_cnt;
> +	buf_ptr_t bufs[0];
> +} iov_ptr_t;
> +
> +typedef struct app_data {
> +	uint64_t pktout;
> +	void *marker;
> +} app_data_t;
> +
> +/* Instance operations */
> +
> +/* Enqueue an SE/AE request */
> +int cpt_enqueue_req(cpt_instance_t *inst, void *req, uint8_t flags,
> +	      void *event, uint64_t event_flags);
> +
> +/* Dequeue completed SE requests as burst */
> +int32_t cpt_dequeue_burst(cpt_instance_t *instance, uint16_t cnt,
> +			  void *resp[], uint8_t cc[]);
> +
> +/* Marks event as done in event driven mode */
> +int32_t cpt_event_mark_done(void *marker, uint8_t *op_error);
> +
> +/* Checks queue full condition */
> +uint16_t cpt_queue_full(cpt_instance_t *instance);
> +
> +/* Misc */
> +uint32_t cpt_get_instance_count(void);
> +
> +#define ENQ_FLAG_SYNC		0x01
> +#define ENQ_FLAG_EVENT		0x02
> +#define ENQ_FLAG_NODOORBELL	0x04
> +#define ENQ_FLAG_ONLY_DOORBELL	0x08
> +
> +
> +#define OCTTX_EVENT_TAG(__flags) (__flags & 0xffffffff)
> +#define OCTTX_EVENT_GRP(__flags) ((__flags >> 32) & 0xffff)
> +#define OCTTX_EVENT_TT(__flags) ((__flags >> 48) & 0xff)
> +
> +#define OCTTX_EVENT_FLAGS(__tag, __grp, __tt)    \
> +	(((uint64_t)__tag & 0xffffffff) |        \
> +	 (((uint64_t)__grp & 0xffff) << 32) |    \
> +	 (((uint64_t)__tt & 0xff) << 48))
> +
> +
> +/* cpt instance */
> +struct cpt_instance {
> +	/* 0th cache line */
> +	uint32_t queue_id;
> +	uint64_t rsvd;
> +};
> +

#ifndef __hot
> +#define __hot __attribute__((hot))
#endif

> +/** @endcond */
> +
> +#endif /* __BASE_CPT_H__ */
> diff --git a/drivers/crypto/cpt/base/cpt_device.c b/drivers/crypto/cpt/base/cpt_device.c
> index b7cd5b5..a50e5b8 100644
> --- a/drivers/crypto/cpt/base/cpt_device.c
> +++ b/drivers/crypto/cpt/base/cpt_device.c
> @@ -193,7 +193,7 @@ int cptvf_get_resource(struct cpt_vf *dev,
>  	uint64_t *next_ptr;
>  	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
>  
> -	PMD_DRV_LOG(DEBUG, "Initializing csp resource %s\n", cptvf->dev_name);
> +	PMD_DRV_LOG(DEBUG, "Initializing cpt resource %s\n", cptvf->dev_name);
>  
>  	cpt_instance = &cptvf->instance;
>  
> @@ -323,7 +323,7 @@ int cptvf_put_resource(cpt_instance_t *instance)
>  		return -EINVAL;
>  	}
>  
> -	PMD_DRV_LOG(DEBUG, "Releasing csp device %s\n", cptvf->dev_name);
> +	PMD_DRV_LOG(DEBUG, "Releasing cpt device %s\n", cptvf->dev_name);
>  
>  	rz = (struct rte_memzone *)instance->rsvd;
>  	rte_memzone_free(rz);
> diff --git a/drivers/crypto/cpt/base/cpt_request_mgr.c b/drivers/crypto/cpt/base/cpt_request_mgr.c
> new file mode 100644
> index 0000000..8b9b1ff
> --- /dev/null
> +++ b/drivers/crypto/cpt/base/cpt_request_mgr.c
> @@ -0,0 +1,424 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2017 Cavium, Inc
> + */
> +
> +#include "cpt_request_mgr.h"
> +#include "cpt_debug.h"
> +#include <rte_atomic.h>
> +
> +#define MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
> +
> +#define __hot __attribute__((hot))

same as above

> +
> +static inline uint64_t cpu_cycles(void)
> +{
> +	return rte_get_timer_cycles();
> +}
> +
> +static inline uint64_t cpu_cycles_freq(void)
> +{
> +	return rte_get_timer_hz();
> +}
> +
> +static inline void *
> +get_cpt_inst(struct command_queue *cqueue, void *req)
> +{
> +	(void)req;
> +	PMD_TX_LOG(DEBUG, "CPT queue idx %u, req %p\n", cqueue->idx, req);
> +	return &cqueue->qhead[cqueue->idx * CPT_INST_SIZE];
> +}
> +
> +static inline void
> +mark_cpt_inst(struct cpt_vf *cptvf,
> +	      struct command_queue *queue,
> +	      uint32_t ring_door_bell)
> +{
> +#ifdef CMD_DEBUG
> +	/* DEBUG */
> +	{
> +		uint32_t i = queue->idx * CPT_INST_SIZE;
> +		cpt_inst_s_t *cmd = (void *)&queue->qhead[i];
> +		uint64_t *p = (void *)&queue->qhead[i];
> +
> +		PRINT("\nQUEUE parameters:");
> +		PRINT("Queue index           = %u\n",
> +		      queue->idx);
> +		PRINT("Queue HEAD            = %p\n",
> +		      queue->qhead);
> +		PRINT("Command Entry         = %p\n",
> +		      cmd);
> +
> +		PRINT("\nCPT_INST_S format:");
> +		PRINT("cmd->s.doneint = %x\n", cmd->s.doneint);
> +		PRINT("cmd->s.res_addr  = %lx\n", cmd->s.res_addr);
> +		PRINT("cmd->s.grp       = %x\n", cmd->s.grp);
> +		PRINT("cmd->s.tag       = %x\n", cmd->s.tag);
> +		PRINT("cmd->s.tt        = %x\n", cmd->s.tt);
> +		PRINT("cmd->s.wq_ptr    = %lx\n", cmd->s.wq_ptr);
> +		PRINT("cmd->s.ei0       = %lx\n", cmd->s.ei0);
> +		PRINT("cmd->s.ei1       = %lx\n", cmd->s.ei1);
> +		PRINT("cmd->s.ei2       = %lx\n", cmd->s.ei2);
> +		PRINT("cmd->s.ei3       = %lx\n", cmd->s.ei3);
> +
> +		PRINT("\nCommand dump from queue HEAD:");
> +		for (i = 0; i < CPT_INST_SIZE / 8; i++)
> +			PRINT("%lx\n", p[i]);
> +	}
> +#endif
> +	if (unlikely(++queue->idx >= DEFAULT_CMD_QCHUNK_SIZE)) {
> +		uint32_t cchunk = queue->cchunk;
> +		MOD_INC(cchunk, DEFAULT_CMD_QCHUNKS);
> +		queue->qhead = queue->chead[cchunk].head;
> +		queue->idx = 0;
> +		queue->cchunk = cchunk;
> +	}
> +
> +	if (ring_door_bell) {
> +		/* Memory barrier to flush pending writes */
> +		rte_smp_wmb();
> +		cptvf_write_vq_doorbell(cptvf, ring_door_bell);
> +	}
> +}
> +
> +static inline uint8_t
> +check_nb_command_id(cpt_request_info_t *user_req, struct cpt_vf *cptvf)
> +{
> +	uint8_t ret = ERR_REQ_PENDING;
> +	volatile cpt_res_s_t *cptres;
> +
> +	cptres = (volatile cpt_res_s_t *)user_req->completion_addr;
> +
> +	if (unlikely(cptres->s.compcode == CPT_COMP_E_NOTDONE)) {
> +		/*
> +		 * Wait for some time for this command to get completed
> +		 * before timing out
> +		 */
> +		if (cpu_cycles() < user_req->time_out)
> +			return ret;
> +		/*
> +		 * TODO: See if alternate caddr can be used to not loop
> +		 * longer than needed.
> +		 */
> +		if ((cptres->s.compcode == CPT_COMP_E_NOTDONE) &&
> +		    (user_req->extra_time < TIME_IN_RESET_COUNT)) {
> +			user_req->extra_time++;
> +			return ret;
> +		}
> +
> +		if (cptres->s.compcode != CPT_COMP_E_NOTDONE)
> +			goto complete;
> +
> +		ret = ERR_REQ_TIMEOUT;
> +		PMD_DRV_LOG_RAW(ERR, "Request %p timedout\n", user_req);
> +		cptvf_poll_misc(cptvf);
> +		dump_cpt_request_sglist(&user_req->dbg_inst,
> +					"Response Packet Gather in", 1, 1);
> +		goto exit;
> +	}
> +
> +complete:
> +	if (likely(cptres->s.compcode == CPT_COMP_E_GOOD)) {
> +		ret = 0; /* success */
> +		PMD_RX_LOG(DEBUG, "MC status %.8x\n",
> +			   *((volatile uint32_t *)user_req->alternate_caddr));
> +		PMD_RX_LOG(DEBUG, "HW status %.8x\n",
> +			   *((volatile uint32_t *)user_req->completion_addr));
> +	} else if ((cptres->s.compcode == CPT_COMP_E_SWERR) ||
> +		   (cptres->s.compcode == CPT_COMP_E_FAULT)) {
> +		ret = (uint8_t)*user_req->alternate_caddr;
> +		if (!ret)
> +			ret = ERR_BAD_ALT_CCODE;
> +		PMD_RX_LOG(DEBUG, "Request %p : failed with %s : err code :"
> +			   "%x\n", user_req,
> +			   (cptres->s.compcode == CPT_COMP_E_FAULT) ?
> +			   "DMA Fault" : "Software error", ret);
> +	} else {
> +		PMD_DRV_LOG_RAW(ERR, "Request %p : unexpected completion code"
> +			   " %d\n",
> +			   user_req, cptres->s.compcode);
> +		ret = (uint8_t)*user_req->alternate_caddr;
> +	}
> +
> +exit:
> +	dump_cpt_request_sglist(&user_req->dbg_inst,
> +				"Response Packet Scatter Out", 1, 0);
> +	return ret;
> +}
> +
> +
> +/*
> + * cpt_enqueue_req()
> + *
> + * SE & AE request enqueue function
> + */
> +int32_t __hot
> +cpt_enqueue_req(cpt_instance_t *instance, void *req, uint8_t flags,
> +		void *event, uint64_t event_flags)
> +{
> +	struct pending_queue *pqueue;
> +	struct cpt_vf *cptvf;
> +	cpt_inst_s_t *cpt_ist_p = NULL;
> +	cpt_request_info_t *user_req = (cpt_request_info_t *)req;
> +	struct command_queue *cqueue;
> +	int32_t ret = 0;
> +
> +#ifdef CPTVF_STRICT_PARAM_CHECK
> +	if (unlikely(!instance)) {
> +		PMD_DRV_LOG_RAW(ERR, "Invalid inputs (instance: %p, req: %p)\n",
> +			   instance, req);
> +		return -EINVAL;
> +	}
> +#endif
> +
> +	cptvf = (struct cpt_vf *)instance;
> +	pqueue = &cptvf->pqueue;
> +
> +	if (unlikely(!req)) {
> +		/* ring only pending doorbells */
> +		if ((flags & ENQ_FLAG_ONLY_DOORBELL) && pqueue->p_doorbell) {
> +			/* Memory barrier to flush pending writes */
> +			rte_smp_wmb();

Cross check it is rte_wmb() indented here as it barrier between device
and CPU

> +			cptvf_write_vq_doorbell(cptvf, pqueue->p_doorbell);
> +			pqueue->p_doorbell = 0;
> +		}
> +		return 0;
> +	}
> +
> +#if defined(ATOMIC_THROTTLING_COUNTER)

if this config useful for end user then expose it in config file and
explain the details in documentation.

> +	/* Ask the application to try again later */
> +	if (unlikely(cpt_pmd_pcount_load(&pqueue->pending_count) >=
> +		     DEFAULT_CMD_QLEN)) {
> +		return -EAGAIN;
> +	}
> +#else
> +	if (unlikely(pqueue->pending_count >= DEFAULT_CMD_QLEN))
> +		return -EAGAIN;
> +#endif
> +	cqueue = &cptvf->cqueue;
> +	cpt_ist_p = get_cpt_inst(cqueue, req);
> +	rte_prefetch_non_temporal(cpt_ist_p);
> +
> +	/* EI0, EI1, EI2, EI3 are already prepared */
> +	/* HW W0 */
> +	cpt_ist_p->u[0] = 0;
> +	/* HW W1 */
> +	cpt_ist_p->s.res_addr = user_req->comp_baddr;
> +	/* HW W2 */
> +	cpt_ist_p->u[2] = 0;
> +	/* HW W3 */
> +	cpt_ist_p->s.wq_ptr = 0;
> +
> +	/* MC EI0 */
> +	cpt_ist_p->s.ei0 = user_req->ist.ei0;
> +	/* MC EI1 */
> +	cpt_ist_p->s.ei1 = user_req->ist.ei1;
> +	/* MC EI2 */
> +	cpt_ist_p->s.ei2 = user_req->ist.ei2;
> +	/* MC EI3 */
> +	cpt_ist_p->s.ei3 = user_req->ist.ei3;
> +
> +	PMD_TX_LOG(DEBUG, "req: %p op: %p dma_mode 0x%x se_req %u\n",
> +		   req,
> +		   user_req->op,
> +		   user_req->dma_mode,
> +		   user_req->se_req);
> +
> +#ifdef CPT_DEBUG
> +	{
> +		vq_cmd_word0_t vq_cmd_w0;
> +		vq_cmd_word3_t vq_cmd_w3;
> +
> +		vq_cmd_w3.u64 = cpt_ist_p->s.ei3;
> +		vq_cmd_w0.u64 = be64toh(cpt_ist_p->s.ei0);
> +		user_req->dbg_inst = *cpt_ist_p;
> +
> +		if (vq_cmd_w3.s.cptr) {
> +			PMD_TX_LOG(DEBUG, "Context Handle: 0x%016lx\n",
> +				   (uint64_t)vq_cmd_w3.s.cptr);
> +			/* Dump max context i.e 448 bytes */
> +			cpt_dump_buffer("CONTEXT",
> +					os_iova2va((uint64_t)vq_cmd_w3.s.cptr),
> +					448);
> +		}
> +
> +		dump_cpt_request_info(user_req, cpt_ist_p);
> +		dump_cpt_request_sglist(cpt_ist_p, "Request (src)", 1, 1);
> +		dump_cpt_request_sglist(cpt_ist_p, "Request (dst)", 0, 0);
> +		cpt_dump_buffer("VQ command word0", &cpt_ist_p->u[4],
> +				sizeof(vq_cmd_w0));
> +		cpt_dump_buffer("VQ command word1", &cpt_ist_p->u[5],
> +				sizeof(uint64_t));
> +		cpt_dump_buffer("VQ command word2", &cpt_ist_p->u[6],
> +				sizeof(uint64_t));
> +		cpt_dump_buffer("VQ command word3", &cpt_ist_p->u[7],
> +				sizeof(vq_cmd_w3));
> +	}
> +#endif
> +
> +	if (likely(!(flags & ENQ_FLAG_SYNC))) {
> +		void *op = user_req->op;
> +
> +		if (unlikely(flags & ENQ_FLAG_EVENT)) {
> +			app_data_t *app_data = op;
> +
> +			/* Event based completion */
> +			cpt_ist_p->s.tag = OCTTX_EVENT_TAG(event_flags);
> +			cpt_ist_p->s.grp = OCTTX_EVENT_GRP(event_flags);
> +			cpt_ist_p->s.tt = OCTTX_EVENT_TT(event_flags);
> +			cpt_ist_p->s.wq_ptr = (uint64_t)event;
> +
> +#if defined(ATOMIC_THROTTLING_COUNTER)
> +			app_data->marker = user_req;
> +			__atomic_fetch_add(&pqueue->pending_count,
> +					   1, __ATOMIC_RELAXED);
> +#else
> +			rid_t *rid_e;
> +			/*
> +			 * Mark it as in progress in pending queue, software
> +			 * will mark it when completion is received
> +			 */
> +			rid_e = &pqueue->rid_queue[pqueue->enq_tail];
> +			rid_e->rid = (uint64_t)user_req;
> +			/* rid_e->op = op; */
> +			MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);
> +			app_data->marker = rid_e;
> +#endif
> +
> +			cpt_dump_buffer("CPT Instruction with wqe", cpt_ist_p,
> +					sizeof(*cpt_ist_p));
> +
> +			mark_cpt_inst(cptvf, cqueue, 1);
> +
> +		} else {
> +			uint32_t doorbell = 0;
> +
> +			if (likely(flags & ENQ_FLAG_NODOORBELL))
> +				pqueue->p_doorbell++;
> +			else
> +				doorbell = ++pqueue->p_doorbell;
> +
> +			/* Fill time_out cycles */
> +			user_req->time_out = cpu_cycles() +
> +				DEFAULT_COMMAND_TIMEOUT * cpu_cycles_freq();
> +			user_req->extra_time = 0;
> +
> +			cpt_dump_buffer("CPT Instruction", cpt_ist_p,
> +					sizeof(*cpt_ist_p));
> +
> +			/* Default mode of software queue */
> +			mark_cpt_inst(cptvf, cqueue, doorbell);
> +
> +			pqueue->p_doorbell -= doorbell;
> +			pqueue->rid_queue[pqueue->enq_tail].rid =
> +				(uint64_t)user_req;
> +			/* pqueue->rid_queue[pqueue->enq_tail].op = op; */
> +			/* We will use soft queue length here to limit
> +			 * requests
> +			 */
> +			MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);
> +			pqueue->pending_count += 1;
> +		}
> +
> +		PMD_TX_LOG(DEBUG, "Submitted NB cmd with request: %p op: %p\n",
> +			   user_req, op);
> +	} else {
> +		/*
> +		 * Synchronous operation,
> +		 * hold until completion / timeout
> +		 */
> +		/* Fill time_out cycles */
> +		user_req->time_out = cpu_cycles() +
> +			DEFAULT_COMMAND_TIMEOUT * cpu_cycles_freq();
> +		user_req->extra_time = 0;
> +
> +		cpt_dump_buffer("CPT Instruction", cpt_ist_p,
> +				sizeof(*cpt_ist_p));
> +
> +		/* Default mode of software queue */
> +		mark_cpt_inst(cptvf, cqueue, 1);
> +
> +		do {
> +			/* TODO: should we pause */
> +			ret = check_nb_command_id(user_req, cptvf);
> +			cptvf_poll_misc(cptvf);
> +#if 0

???

> +			PMD_TX_LOG(DEBUG, "Doorbell count for cptvf %s: %u\n",
> +				   cptvf->dev_name,
> +				   cptvf_read_vq_doorbell(cptvf));
> +#endif
> +		} while (ret == ERR_REQ_PENDING);
> +

Re: [dpdk-dev] [PATCH 04/16] crypto/cpt/base: add hardware enq/deq API for CPT

[De Lara Guarch, Pablo]

> -----Original Message-----
> From: Anoob Joseph [mailto:anoob.joseph@caviumnetworks.com]
> Sent: Friday, June 8, 2018 5:45 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Thomas Monjalon <thomas@monjalon.net>
> Cc: Ankur Dwivedi <ankur.dwivedi@cavium.com>; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> Subject: [PATCH 04/16] crypto/cpt/base: add hardware enq/deq API for CPT

No need to use "for CPT" here, as the "crypto/cpt/base" already states that.
Same applies in other patches.

> 
> From: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> 
> Adds hardware enqueue/dequeue API of instructions to a queue pair for Cavium
> CPT device.
> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>
> ---
>  drivers/crypto/cpt/base/cpt.h             | 102 +++++++
>  drivers/crypto/cpt/base/cpt_device.c      |   4 +-
>  drivers/crypto/cpt/base/cpt_request_mgr.c | 424
> ++++++++++++++++++++++++++++++
> drivers/crypto/cpt/base/cpt_request_mgr.h |  75 ++++++
>  4 files changed, 603 insertions(+), 2 deletions(-)  create mode 100644
> drivers/crypto/cpt/base/cpt.h  create mode 100644
> drivers/crypto/cpt/base/cpt_request_mgr.c
>  create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.h
> 
> diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h new
> file mode 100644 index 0000000..11407ae
> --- /dev/null
> +++ b/drivers/crypto/cpt/base/cpt.h

...
> +/* cpt instance */
> +struct cpt_instance {
> +	/* 0th cache line */

Is this comment useful for only 12 bytes of data?


...

> diff --git a/drivers/crypto/cpt/base/cpt_device.c
> b/drivers/crypto/cpt/base/cpt_device.c
> index b7cd5b5..a50e5b8 100644
> --- a/drivers/crypto/cpt/base/cpt_device.c
> +++ b/drivers/crypto/cpt/base/cpt_device.c
> @@ -193,7 +193,7 @@ int cptvf_get_resource(struct cpt_vf *dev,
>  	uint64_t *next_ptr;
>  	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
> 
> -	PMD_DRV_LOG(DEBUG, "Initializing csp resource %s\n", cptvf-
> >dev_name);
> +	PMD_DRV_LOG(DEBUG, "Initializing cpt resource %s\n", cptvf-
> >dev_name);

This should be "cpt resource" since the beginning, in the patch that introduced this line.
Same below.

> 
>  	cpt_instance = &cptvf->instance;
> 
> @@ -323,7 +323,7 @@ int cptvf_put_resource(cpt_instance_t *instance)
>  		return -EINVAL;
>  	}
> 
> -	PMD_DRV_LOG(DEBUG, "Releasing csp device %s\n", cptvf-
> >dev_name);
> +	PMD_DRV_LOG(DEBUG, "Releasing cpt device %s\n", cptvf-
> >dev_name);
> 
>  	rz = (struct rte_memzone *)instance->rsvd;
>  	rte_memzone_free(rz);
> diff --git a/drivers/crypto/cpt/base/cpt_request_mgr.c
> b/drivers/crypto/cpt/base/cpt_request_mgr.c
> new file mode 100644
> index 0000000..8b9b1ff
> --- /dev/null
> +++ b/drivers/crypto/cpt/base/cpt_request_mgr.c
> @@ -0,0 +1,424 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2017 Cavium, Inc
> + */
> +
> +#include "cpt_request_mgr.h"
> +#include "cpt_debug.h"
> +#include <rte_atomic.h>

Same comment about the includes applies here.
Separate them with blank lines, between external and internal to DPDK includes.

> +
> +#define MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
> +
> +#define __hot __attribute__((hot))
> +
> +static inline uint64_t cpu_cycles(void) {
> +	return rte_get_timer_cycles();
> +}
> +
> +static inline uint64_t cpu_cycles_freq(void) {
> +	return rte_get_timer_hz();
> +}
> +
> +static inline void *
> +get_cpt_inst(struct command_queue *cqueue, void *req) {
> +	(void)req;
> +	PMD_TX_LOG(DEBUG, "CPT queue idx %u, req %p\n", cqueue->idx, req);
> +	return &cqueue->qhead[cqueue->idx * CPT_INST_SIZE]; }
> +
> +static inline void
> +mark_cpt_inst(struct cpt_vf *cptvf,
> +	      struct command_queue *queue,
> +	      uint32_t ring_door_bell)
> +{
> +#ifdef CMD_DEBUG

Try to avoid this compile time checks, as Jerin suggested.

> +	/* DEBUG */
> +	{

Re: [dpdk-dev] [PATCH 04/16] crypto/cpt/base: add hardware enq/deq API for CPT

[De Lara Guarch, Pablo]

> -----Original Message-----
> From: Anoob Joseph [mailto:anoob.joseph@caviumnetworks.com]
> Sent: Friday, June 8, 2018 5:45 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Thomas Monjalon <thomas@monjalon.net>
> Cc: Ankur Dwivedi <ankur.dwivedi@cavium.com>; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> Subject: [PATCH 04/16] crypto/cpt/base: add hardware enq/deq API for CPT
> 
> From: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> 
> Adds hardware enqueue/dequeue API of instructions to a queue pair for Cavium
> CPT device.
> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>

...

> +
> +			/* Event based completion */
> +			cpt_ist_p->s.tag = OCTTX_EVENT_TAG(event_flags);
> +			cpt_ist_p->s.grp = OCTTX_EVENT_GRP(event_flags);
> +			cpt_ist_p->s.tt = OCTTX_EVENT_TT(event_flags);
> +			cpt_ist_p->s.wq_ptr = (uint64_t)event;

I am seeing an error when building with gcc 32 bits.

drivers/crypto/cpt/base/cpt_request_mgr.c:268:26: error:
cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
    cpt_ist_p->s.wq_ptr = (uint64_t)event;
                          ^
drivers/crypto/cpt/base/cpt_request_mgr.c:281:17: error:
cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
    rid_e->rid = (uint64_t)user_req;
                 ^
drivers/crypto/cpt/base/cpt_request_mgr.c:313:5: error:
cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
     (uint64_t)user_req;
     ^
drivers/crypto/cpt/base/cpt_request_mgr.c: In function 'cpt_dequeue_burst':
drivers/crypto/cpt/base/cpt_request_mgr.c:375:14:
error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
   user_req = (cpt_request_info_t *)(rid_e->rid);
              ^
drivers/crypto/cpt/base/cpt_request_mgr.c:378:30: error:
cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
    rte_prefetch_non_temporal((void *)rid_e[1].rid);
                              ^

[dpdk-dev] [PATCH 05/16] crypto/cpt/base: add sym crypto session init API for CPT

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@cavium.com>

Adds symmetric crypto session init API dependent on hardware/microcode.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/base/cpt_ops.c | 308 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 308 insertions(+)
 create mode 100644 drivers/crypto/cpt/base/cpt_ops.c

diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c
new file mode 100644
index 0000000..e340006
--- /dev/null
+++ b/drivers/crypto/cpt/base/cpt_ops.c
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include "cpt_request_mgr.h"
+
+#define __hot __attribute__((hot))
+
+#define FC_GEN		0x1
+#define ZUC_SNOW3G	0x2
+#define KASUMI		0x3
+#define HASH_HMAC	0x4
+
+struct cpt_ctx {
+	/* Below fields are accessed by sw */
+	uint64_t enc_cipher	:8;
+	uint64_t hash_type	:8;
+	uint64_t mac_len	:8;
+	uint64_t auth_key_len	:8;
+	uint64_t fc_type	:4;
+	uint64_t hmac		:1;
+	uint64_t zsk_flags	:3;
+	uint64_t k_ecb		:1;
+	uint64_t snow3g		:1; /* Set if it is snow3g and not ZUC */
+	uint64_t rsvd		:22;
+	/* Below fields are accessed by hardware */
+	union {
+		mc_fc_context_t fctx;
+		mc_zuc_snow3g_ctx_t zs_ctx;
+		mc_kasumi_ctx_t k_ctx;
+	};
+	uint8_t  auth_key[64];
+};
+
+static uint8_t zuc_d[32] = {
+	0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
+	0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
+	0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
+	0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC
+};
+
+static void gen_key_snow3g(uint8_t *ck, uint32_t *keyx)
+{
+	int i, base;
+
+	for (i = 0; i < 4; i++) {
+		base = 4 * i;
+		keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
+			(ck[base + 2] << 8) | (ck[base + 3]);
+		keyx[3 - i] = htobe32(keyx[3 - i]);
+	}
+}
+
+#define MAX_IV_LEN 16
+
+int cpt_fc_get_op_meta_len(void)
+{
+	uint32_t len = 0;
+
+	len += sizeof(cpt_request_info_t);
+	len += OFFSET_CONTROL_BYTES + MAX_IV_LEN;
+	len += ROUNDUP8(SG_LIST_HDR_SIZE +
+			(ROUNDUP4(MAX_SG_IN_OUT_CNT) >> 2) * SG_ENTRY_SIZE);
+	len += 2 * COMPLETION_CODE_SIZE;
+	len += 2 * sizeof(cpt_res_s_t);
+	return len;
+}
+
+/* Provides meta length required when it is
+ * direct mode i.e single buf inplace
+ */
+int32_t cpt_fc_get_op_sb_meta_len(void)
+{
+	uint32_t len = 0;
+
+	/* Request structure */
+	len = sizeof(cpt_request_info_t);
+	/* CPT HW result structure plus extra as it is aligned */
+	len += 2*sizeof(cpt_res_s_t);
+
+	return len;
+}
+
+int32_t cpt_fc_get_ctx_len(void)
+{
+	return sizeof(struct cpt_ctx);
+}
+
+int
+cpt_fc_ciph_set_key(cpt_instance_t *instance,
+		    void *ctx, cipher_type_t type, uint8_t *key,
+		    uint16_t key_len, uint8_t *salt)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	mc_fc_context_t *fctx = &cpt_ctx->fctx;
+	mc_aes_type_t aes_key_type = 0;
+	uint64_t *ctrl_flags;
+
+	(void) instance;
+
+	if (!type) {
+		/* to support passthrough case */
+
+		cpt_ctx->fc_type = FC_GEN;
+		ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags);
+		cpt_ctx->enc_cipher = 0;
+
+		*ctrl_flags = be64toh(*ctrl_flags);
+		P_ENC_CTRL(fctx).enc_cipher = 0;
+		*ctrl_flags = htobe64(*ctrl_flags);
+
+		return 0;
+	}
+
+	if ((type >= ZUC_EEA3) && (type <= KASUMI_F8_ECB)) {
+		uint32_t keyx[4];
+
+		if (key_len != 16)
+			return -1;
+
+		/* No support for AEAD yet */
+		if (cpt_ctx->hash_type)
+			return -1;
+
+		/* For ZUC/SNOW3G/Kasumi */
+		switch (type) {
+		case SNOW3G_UEA2:
+			cpt_ctx->snow3g = 1;
+			gen_key_snow3g(key, keyx);
+			memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0;
+			break;
+		case ZUC_EEA3:
+			cpt_ctx->snow3g = 0;
+			memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
+			memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0;
+			break;
+		case KASUMI_F8_ECB:
+			/* Kasumi ECB mode */
+			cpt_ctx->k_ecb = 1;
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->zsk_flags = 0;
+			cpt_ctx->fc_type = KASUMI;
+			break;
+		case KASUMI_F8_CBC:
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->zsk_flags = 0;
+			cpt_ctx->fc_type = KASUMI;
+			break;
+		default:
+			return -1;
+		}
+		cpt_ctx->enc_cipher = type;
+		return 0;
+	}
+
+	fctx = &cpt_ctx->fctx;
+	/* Even though iv source is from dptr,
+	 * aes_gcm salt is taken from ctx
+	 */
+	if (salt && (type == AES_GCM)) {
+		memcpy(fctx->enc.encr_iv, salt, 4);
+		/* Assuming it was just salt update
+		 * and nothing else
+		 */
+		if (!key)
+			return 0;
+	}
+
+	cpt_ctx->fc_type = FC_GEN;
+	ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags);
+	*ctrl_flags = be64toh(*ctrl_flags);
+
+	cpt_ctx->enc_cipher = type;
+	/* For GMAC auth, cipher must be NULL */
+	if (cpt_ctx->hash_type != GMAC_TYPE)
+		P_ENC_CTRL(fctx).enc_cipher = type;
+
+	if (type == AES_XTS)
+		key_len = key_len / 2;
+
+	/* key len only for AES */
+	if ((type != DES3_CBC) &&
+	    (type != DES3_ECB)) {
+		switch (key_len) {
+		case BYTE_16:
+			aes_key_type = AES_128_BIT;
+			break;
+		case BYTE_24:
+			aes_key_type = AES_192_BIT;
+			if (type == AES_XTS) {
+				PMD_DRV_LOG(ERR, "Invalid AES key len for"
+					    " XTS\n");
+				return -1;
+			}
+			break;
+		case BYTE_32:
+			aes_key_type = AES_256_BIT;
+			break;
+		default:
+			PMD_DRV_LOG(ERR, "Invalid AES key len\n");
+			return -1;
+		}
+
+		P_ENC_CTRL(fctx).aes_key = aes_key_type;
+	}
+	/*
+	 * We need to always say iv is from DPTR as user can
+	 * sometimes override IV per operation
+	 */
+	P_ENC_CTRL(fctx).iv_source = FROM_DPTR;
+
+	memcpy(fctx->enc.encr_key, key, key_len);
+	if (type == AES_XTS) {
+		/* Copy key2 for XTS into ipad */
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memcpy(fctx->hmac.ipad, &key[key_len], key_len);
+	}
+
+	*ctrl_flags = htobe64(*ctrl_flags);
+
+	return 0;
+}
+
+int
+cpt_fc_auth_set_key(cpt_instance_t *instance,
+		    void *ctx, auth_type_t type, uint8_t *key,
+		    uint16_t key_len, uint16_t mac_len)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	mc_fc_context_t *fctx = &cpt_ctx->fctx;
+	uint64_t *ctrl_flags = NULL;
+
+	(void) instance;
+
+	if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
+		uint32_t keyx[4];
+
+		if (key_len != 16)
+			return -1;
+		/* No support for AEAD yet */
+		if (cpt_ctx->enc_cipher)
+			return -1;
+		/* For ZUC/SNOW3G/Kasumi */
+		switch (type) {
+		case SNOW3G_UIA2:
+			cpt_ctx->snow3g = 1;
+			gen_key_snow3g(key, keyx);
+			memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case ZUC_EIA3:
+			cpt_ctx->snow3g = 0;
+			memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
+			memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case KASUMI_F9_ECB:
+			/* Kasumi ECB mode */
+			cpt_ctx->k_ecb = 1;
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->fc_type = KASUMI;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case KASUMI_F9_CBC:
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->fc_type = KASUMI;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		default:
+			return -1;
+		}
+		cpt_ctx->mac_len = 4;
+		cpt_ctx->hash_type = type;
+		return 0;
+	}
+
+	if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher)
+		cpt_ctx->fc_type = HASH_HMAC;
+
+	ctrl_flags = (uint64_t *)&fctx->enc.enc_ctrl.flags;
+	*ctrl_flags = be64toh(*ctrl_flags);
+
+	/* For GMAC auth, cipher must be NULL */
+	if (type == GMAC_TYPE)
+		P_ENC_CTRL(fctx).enc_cipher = 0;
+
+	P_ENC_CTRL(fctx).hash_type = cpt_ctx->hash_type = type;
+	P_ENC_CTRL(fctx).mac_len = cpt_ctx->mac_len = mac_len;
+
+	if (key_len) {
+		cpt_ctx->hmac = 1;
+		memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key));
+		memcpy(cpt_ctx->auth_key, key, key_len);
+		cpt_ctx->auth_key_len = key_len;
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
+		memcpy(fctx->hmac.opad, key, key_len);
+		P_ENC_CTRL(fctx).auth_input_type = 1;
+	}
+	*ctrl_flags = htobe64(*ctrl_flags);
+	return 0;
+}
-- 
1.9.3

[dpdk-dev] [PATCH 06/16] crypto/cpt/base: add sym crypto request prepare for CPT

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@cavium.com>

These functions help in preparing symmetric crypto requests
for the supported cipher/auth/aead. This includes all supported
algos except Kasumi, Snow3G, Zuc, HMAC_ONLY and HASH_ONLY cases.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/base/cpt.h     |  129 +++++
 drivers/crypto/cpt/base/cpt_ops.c | 1021 +++++++++++++++++++++++++++++++++++++
 2 files changed, 1150 insertions(+)

diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h
index 11407ae..54b1cb6 100644
--- a/drivers/crypto/cpt/base/cpt.h
+++ b/drivers/crypto/cpt/base/cpt.h
@@ -54,6 +54,135 @@
 	void *marker;
 } app_data_t;
 
+/*
+ * Parameters for Flexi Crypto
+ * requests
+ */
+#define VALID_AAD_BUF 0x01
+#define VALID_MAC_BUF 0x02
+#define VALID_IV_BUF 0x04
+#define SINGLE_BUF_INPLACE 0x08
+#define SINGLE_BUF_HEADTAILROOM 0x10
+
+#define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff)
+#define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff)
+#define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff)
+#define ENCR_DLEN(__d_lens) (__d_lens >> 32)
+#define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff)
+
+typedef struct fc_params {
+	/* 0th cache line */
+	union {
+		buf_ptr_t bufs[1];
+		struct {
+			iov_ptr_t *src_iov;
+			iov_ptr_t *dst_iov;
+		};
+	};
+	void *iv_buf;
+	void *auth_iv_buf;
+	buf_ptr_t meta_buf;
+	buf_ptr_t ctx_buf;
+	uint64_t rsvd2;
+
+	/* 1st cache line */
+	buf_ptr_t aad_buf;
+	buf_ptr_t mac_buf;
+
+} fc_params_t;
+
+/*
+ * Parameters for digest
+ * generate requests
+ * Only src_iov, op, ctx_buf, mac_buf, prep_req
+ * meta_buf, auth_data_len are used for digest gen.
+ */
+typedef struct fc_params digest_params_t;
+
+/* Cipher Algorithms */
+typedef mc_cipher_type_t cipher_type_t;
+
+/* Auth Algorithms */
+typedef mc_hash_type_t auth_type_t;
+
+/* Flexi Crypto Operations */
+/*
+ * Encr | Encr + Hmac | HASH-HMAC generation
+ */
+/*
+ * ZUC/SNOW3g enc cipher/cipher+auth/auth-gen operation
+ */
+/*
+ * kasumi enc cipher/cipher+auth/auth-gen operation
+ * F8 iv_buf: 64 bits Bigendian format
+ * COUNT[63-32] || BEARER[31-27] ||
+ * DIRECTION[26] || 0...0[25-0]
+ * F9 mac gen auth_iv_buf: 64 bits BE + 8 bits
+ * COUNT[63-32] || FRESH[31-0]
+ * 0...0[7-1] || DIRECTION[0]
+ */
+void *cpt_fc_enc_hmac_prep(uint32_t flags,
+			   uint64_t d_offs,
+			   uint64_t d_lens,
+			   fc_params_t *params,
+			   void *op,
+			   int *ret);
+/*
+ * Decr | Decr + Hmac
+ */
+/*
+ * ZUC/SNOW3g dec cipher/cipher+auth operation
+ */
+/*
+ * kasumi dec cipher/cipher+auth/ operation
+ * F8 iv_buf: 64 bits Bigendian format
+ * COUNT[63-32] || BEARER[31-27] ||
+ * DIRECTION[26] || 0...0[25-0]
+ */
+void *cpt_fc_dec_hmac_prep(uint32_t flags,
+			   uint64_t d_offs,
+			   uint64_t d_lens,
+			   fc_params_t *params,
+			   void *op,
+			   int *ret);
+
+/* Flexi Crypto Ctrl Operations */
+int32_t cpt_fc_ciph_set_key(cpt_instance_t *inst,
+			    void *ctx,
+			    cipher_type_t type,
+			    uint8_t *key,
+			    uint16_t key_len,
+			    uint8_t *salt);
+
+int32_t cpt_fc_ciph_set_iv(cpt_instance_t *inst,
+			   void *ctx,
+			   uint8_t *iv,
+			   uint16_t iv_len);
+
+int32_t cpt_fc_auth_set_key(cpt_instance_t *inst,
+			    void *ctx,
+			    auth_type_t type,
+			    uint8_t *key,
+			    uint16_t key_len,
+			    uint16_t mac_len);
+
+void
+cpt_fc_salt_update(void *ctx,
+		   uint8_t *salt);
+/*
+ * Get's size of contiguous meta buffer
+ * to be allocated per op
+ */
+int32_t  cpt_fc_get_op_meta_len(void);
+
+/* Get context length for a session */
+int32_t cpt_fc_get_ctx_len(void);
+
+/* Provides meta length required when it is
+ * direct mode i.e single buf inplace
+ */
+int32_t cpt_fc_get_op_sb_meta_len(void);
+
 /* Instance operations */
 
 /* Enqueue an SE/AE request */
diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c
index e340006..31f8064 100644
--- a/drivers/crypto/cpt/base/cpt_ops.c
+++ b/drivers/crypto/cpt/base/cpt_ops.c
@@ -86,6 +86,14 @@ int32_t cpt_fc_get_ctx_len(void)
 	return sizeof(struct cpt_ctx);
 }
 
+inline void
+cpt_fc_salt_update(void *ctx,
+		   uint8_t *salt)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	memcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);
+}
+
 int
 cpt_fc_ciph_set_key(cpt_instance_t *instance,
 		    void *ctx, cipher_type_t type, uint8_t *key,
@@ -306,3 +314,1016 @@ int32_t cpt_fc_get_ctx_len(void)
 	*ctrl_flags = htobe64(*ctrl_flags);
 	return 0;
 }
+
+static inline uint32_t
+fill_sg_comp(sg_comp_t *list,
+	     uint32_t i,
+	     phys_addr_t dma_addr,
+	     void *vaddr,
+	     uint32_t size)
+{
+	sg_comp_t *to = &list[i>>2];
+
+	to->u.s.len[i%4] = htobe16(size);
+	to->ptr[i%4] = htobe64(dma_addr);
+	(void) vaddr;
+	i++;
+	return i;
+}
+
+static inline uint32_t
+fill_sg_comp_from_buf(sg_comp_t *list,
+		      uint32_t i,
+		      buf_ptr_t *from)
+{
+	sg_comp_t *to = &list[i>>2];
+
+	to->u.s.len[i%4] = htobe16(from->size);
+	to->ptr[i%4] = htobe64(from->dma_addr);
+	i++;
+	return i;
+}
+
+static inline uint32_t
+fill_sg_comp_from_buf_min(sg_comp_t *list,
+			  uint32_t i,
+			  buf_ptr_t *from,
+			  uint32_t *psize)
+{
+	sg_comp_t *to = &list[i >> 2];
+	uint32_t size = *psize;
+	uint32_t e_len;
+
+	e_len = (size > from->size) ? from->size : size;
+	to->u.s.len[i % 4] = htobe16(e_len);
+	to->ptr[i % 4] = htobe64(from->dma_addr);
+	*psize -= e_len;
+	i++;
+	return i;
+}
+
+/*
+ * This fills the MC expected SGIO list
+ * from IOV given by user.
+ */
+static inline uint32_t
+fill_sg_comp_from_iov(sg_comp_t *list,
+		      uint32_t i,
+		      iov_ptr_t *from, uint32_t from_offset,
+		      uint32_t *psize, buf_ptr_t *extra_buf,
+		      uint32_t extra_offset)
+{
+	int32_t j;
+	uint32_t extra_len = extra_buf ? extra_buf->size : 0;
+	uint32_t size = *psize - extra_len;
+	buf_ptr_t *bufs;
+
+	bufs = from->bufs;
+	for (j = 0; (j < from->buf_cnt) && size; j++) {
+		phys_addr_t e_dma_addr;
+		uint32_t e_len;
+		sg_comp_t *to = &list[i >> 2];
+
+		if (!bufs[j].size)
+			continue;
+
+		if (unlikely(from_offset)) {
+			if (from_offset >= bufs[j].size) {
+				from_offset -= bufs[j].size;
+				continue;
+			}
+			e_dma_addr = bufs[j].dma_addr + from_offset;
+			e_len = (size > (bufs[j].size - from_offset)) ?
+				(bufs[j].size - from_offset) : size;
+			from_offset = 0;
+		} else {
+			e_dma_addr = bufs[j].dma_addr;
+			e_len = (size > bufs[j].size) ?
+				bufs[j].size : size;
+		}
+
+		to->u.s.len[i % 4] = htobe16(e_len);
+		to->ptr[i % 4] = htobe64(e_dma_addr);
+
+		if (extra_len && (e_len >= extra_offset)) {
+			/* Break the data at given offset */
+			uint32_t next_len = e_len - extra_offset;
+			phys_addr_t next_dma = e_dma_addr + extra_offset;
+
+			if (!extra_offset) {
+				i--;
+			} else {
+				e_len = extra_offset;
+				size -= e_len;
+				to->u.s.len[i % 4] = htobe16(e_len);
+			}
+
+			/* Insert extra data ptr */
+			if (extra_len) {
+				i++;
+				to = &list[i >> 2];
+				to->u.s.len[i % 4] = htobe16(extra_buf->size);
+				to->ptr[i % 4] = htobe64(extra_buf->dma_addr);
+
+				/* size already decremented by extra len */
+			}
+
+			/* insert the rest of the data */
+			if (next_len) {
+				i++;
+				to = &list[i >> 2];
+				to->u.s.len[i % 4] = htobe16(next_len);
+				to->ptr[i % 4] = htobe64(next_dma);
+				size -= next_len;
+			}
+			extra_len = 0;
+
+		} else {
+			size -= e_len;
+		}
+		if (extra_offset)
+			extra_offset -= size;
+		i++;
+	}
+
+	*psize = size;
+	return (uint32_t)i;
+}
+
+static inline int  __attribute__((always_inline))
+cpt_enc_hmac_prep(uint32_t flags,
+		  uint64_t d_offs,
+		  uint64_t d_lens,
+		  fc_params_t *fc_params,
+		  void *op,
+		  void **prep_req)
+{
+	uint32_t iv_offset = 0;
+	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t cipher_type, hash_type;
+	uint32_t mac_len, size;
+	uint8_t iv_len = 16;
+	cpt_request_info_t *req;
+	buf_ptr_t *meta_p, *aad_buf = NULL;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len, aad_len = 0;
+	uint32_t passthrough_len = 0;
+	void *m_vaddr, *offset_vaddr;
+	uint64_t m_dma, offset_dma, ctx_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr;
+	uint64_t c_dma;
+	int32_t m_size;
+	opcode_info_t opcode;
+
+	meta_p = &fc_params->meta_buf;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!fc_params || !meta_p->vaddr || !meta_p->size)
+		return ERR_BAD_INPUT_ARG;
+#endif
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs);
+	auth_offset = AUTH_OFFSET(d_offs);
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * We dont support both aad
+		 * and auth data separately
+		 */
+		auth_data_len = 0;
+		auth_offset = 0;
+		aad_len = fc_params->aad_buf.size;
+		aad_buf = &fc_params->aad_buf;
+	}
+	cpt_ctx = fc_params->ctx_buf.vaddr;
+	cipher_type = cpt_ctx->enc_cipher;
+	hash_type = cpt_ctx->hash_type;
+	mac_len = cpt_ctx->mac_len;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* start cpt request info struct at 8 byte boundary */
+	size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+		(uint8_t *)m_vaddr;
+
+	req = (cpt_request_info_t *)((uint8_t *)m_vaddr + size);
+
+	size += sizeof(cpt_request_info_t);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	if (hash_type == GMAC_TYPE)
+		encr_data_len = 0;
+
+	if (unlikely(!(flags & VALID_IV_BUF))) {
+		iv_len = 0;
+		iv_offset = ENCR_IV_OFFSET(d_offs);
+	}
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * When AAD is given, data above encr_offset is pass through
+		 * Since AAD is given as separate pointer and not as offset,
+		 * this is a special case as we need to fragment input data
+		 * into passthrough + encr_data and then insert AAD in between.
+		 */
+		if (hash_type != GMAC_TYPE) {
+			passthrough_len = encr_offset;
+			auth_offset = passthrough_len + iv_len;
+			encr_offset = passthrough_len + aad_len + iv_len;
+			auth_data_len = aad_len + encr_data_len;
+		} else {
+			passthrough_len = 16 + aad_len;
+			auth_offset = passthrough_len + iv_len;
+			auth_data_len = aad_len;
+		}
+	} else {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/* Initialising ctrl and opcode
+	 * fields in cpt request structure
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	/*
+	 * We are using DMA mode but indicate that
+	 * SGIO list is already populated.
+	 */
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	/* Encryption */
+	opcode.s.major = MAJOR_OP_FC;
+	opcode.s.minor = 0;
+
+	auth_dlen = auth_offset + auth_data_len;
+	enc_dlen = encr_data_len + encr_offset;
+	if (unlikely(encr_data_len & 0xf)) {
+		if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
+			enc_dlen = ROUNDUP8(encr_data_len) + encr_offset;
+		else if (likely((cipher_type == AES_CBC) ||
+				(cipher_type == AES_ECB)))
+			enc_dlen = ROUNDUP16(encr_data_len) + encr_offset;
+	}
+
+	/* TODO: MC issue */
+	if (unlikely(hash_type == GMAC_TYPE)) {
+		encr_offset = auth_dlen;
+		enc_dlen = 0;
+	}
+
+	if (unlikely(auth_dlen > enc_dlen)) {
+		inputlen = auth_dlen;
+		outputlen = auth_dlen + mac_len;
+	} else {
+		inputlen = enc_dlen;
+		outputlen = enc_dlen + mac_len;
+	}
+
+	/*GP op header */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = htobe16(encr_data_len);
+	vq_cmd_w0.s.param2 = htobe16(auth_data_len);
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((flags & SINGLE_BUF_INPLACE) &&
+		   (flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = fc_params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+		/* *req->alternate_caddr = ((uint64_t)0xdeadbeefdeadbeef) */
+
+		vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			htobe64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+
+		/* This falls under strict SG mode */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+		size = OFF_CTRL_LEN + iv_len;
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		opcode.s.major |= DMA_MODE;
+
+		vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			htobe64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+
+		i = 0;
+
+		/* Offset control word that includes iv */
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+		/* Add input data */
+		size = inputlen - iv_len;
+		if (likely(size)) {
+			uint32_t aad_offset = aad_len ? passthrough_len : 0;
+
+			if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+				i = fill_sg_comp_from_buf_min(gather_comp, i,
+							      fc_params->bufs,
+							      &size);
+			} else {
+
+				i = fill_sg_comp_from_iov(gather_comp, i,
+							  fc_params->src_iov,
+							  0, &size,
+							  aad_buf, aad_offset);
+			}
+
+			if (unlikely(size)) {
+				PMD_TX_LOG(ERR, "Insufficient buffer space,"
+					   " size %d need\n", size);
+				return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[2] = htobe16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter list
+		 */
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* Add IV */
+		if (likely(iv_len)) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* output data or output data + digest*/
+		if (unlikely(flags & VALID_MAC_BUF)) {
+			size = outputlen - iv_len - mac_len;
+			if (size) {
+				uint32_t aad_offset =
+					aad_len ? passthrough_len : 0;
+
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+								scatter_comp,
+								i,
+								fc_params->bufs,
+								&size);
+				} else {
+					i = fill_sg_comp_from_iov(scatter_comp,
+								i,
+							     fc_params->dst_iov,
+								0,
+								&size,
+								aad_buf,
+								aad_offset);
+				}
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+			/* mac_data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(scatter_comp, i,
+							  &fc_params->mac_buf);
+			}
+		} else {
+			/* Output including mac */
+			size = outputlen - iv_len;
+			if (likely(size)) {
+				uint32_t aad_offset =
+					aad_len ? passthrough_len : 0;
+
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+								scatter_comp,
+								i,
+								fc_params->bufs,
+								&size);
+				} else {
+					i = fill_sg_comp_from_iov(scatter_comp,
+								i,
+							     fc_params->dst_iov,
+								0,
+								&size,
+								aad_buf,
+								aad_offset);
+				}
+				if (unlikely(size)) {
+					PMD_TX_LOG(ERR, "Insufficient buffer"
+					" space, size %d need\n", size);
+					return ERR_BAD_INPUT_ARG;
+				}
+			}
+		}
+		((uint16_t *)in_buffer)[3] = htobe16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = htobe16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);
+
+	ctx_dma = fc_params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, fctx);
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = ctx_dma;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op  = op;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!(m_size >= 0)) {
+		PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n",
+			   m_size);
+		abort();
+	}
+#endif
+	*prep_req = req;
+	return 0;
+}
+
+static inline int
+cpt_dec_hmac_prep(uint32_t flags,
+		  uint64_t d_offs,
+		  uint64_t d_lens,
+		  fc_params_t *fc_params,
+		  void *op,
+		  void **prep_req)
+{
+	uint32_t iv_offset = 0, size;
+	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+	struct cpt_ctx *cpt_ctx;
+	int32_t hash_type, mac_len, m_size;
+	uint8_t iv_len = 16;
+	cpt_request_info_t *req;
+	buf_ptr_t *meta_p, *aad_buf = NULL;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len, aad_len = 0;
+	uint32_t passthrough_len = 0;
+	void *m_vaddr, *offset_vaddr;
+	uint64_t m_dma, offset_dma, ctx_dma;
+	opcode_info_t opcode;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr;
+	uint64_t c_dma;
+
+	meta_p = &fc_params->meta_buf;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!fc_params || !meta_p->vaddr || !meta_p->size)
+		return ERR_BAD_INPUT_ARG;
+#endif
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs);
+	auth_offset = AUTH_OFFSET(d_offs);
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * We dont support both aad
+		 * and auth data separately
+		 */
+		auth_data_len = 0;
+		auth_offset = 0;
+		aad_len = fc_params->aad_buf.size;
+		aad_buf = &fc_params->aad_buf;
+	}
+
+	cpt_ctx = fc_params->ctx_buf.vaddr;
+	hash_type = cpt_ctx->hash_type;
+	mac_len = cpt_ctx->mac_len;
+
+	if (hash_type == GMAC_TYPE)
+		encr_data_len = 0;
+
+	if (unlikely(!(flags & VALID_IV_BUF))) {
+		iv_len = 0;
+		iv_offset = ENCR_IV_OFFSET(d_offs);
+	}
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * When AAD is given, data above encr_offset is pass through
+		 * Since AAD is given as separate pointer and not as offset,
+		 * this is a special case as we need to fragment input data
+		 * into passthrough + encr_data and then insert AAD in between.
+		 */
+		if (hash_type != GMAC_TYPE) {
+			passthrough_len = encr_offset;
+			auth_offset = passthrough_len + iv_len;
+			encr_offset = passthrough_len + aad_len + iv_len;
+			auth_data_len = aad_len + encr_data_len;
+		} else {
+			passthrough_len = 16 + aad_len;
+			auth_offset = passthrough_len + iv_len;
+			auth_data_len = aad_len;
+		}
+	} else {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+	       (uint8_t *)m_vaddr;
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* start cpt request info structure at 8 byte alignment */
+	size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+		(uint8_t *)m_vaddr;
+
+	req = (cpt_request_info_t *)((uint8_t *)m_vaddr + size);
+
+	size += sizeof(cpt_request_info_t);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields in cpt request structure
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	/*
+	 * We are using DMA mode but indicate that
+	 * SGIO list is already populated.
+	 */
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	/* Decryption */
+	opcode.s.major = MAJOR_OP_FC;
+	opcode.s.minor = 1;
+
+	enc_dlen = encr_offset + encr_data_len;
+	auth_dlen = auth_offset + auth_data_len;
+
+	if (auth_dlen > enc_dlen) {
+		inputlen = auth_dlen + mac_len;
+		outputlen = auth_dlen;
+	} else {
+		inputlen = enc_dlen + mac_len;
+		outputlen = enc_dlen;
+	}
+
+	if (hash_type == GMAC_TYPE)
+		encr_offset = inputlen;
+
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = htobe16(encr_data_len);
+	vq_cmd_w0.s.param2 = htobe16(auth_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((flags & SINGLE_BUF_INPLACE) &&
+		   (flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = fc_params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+		req->ist.ei1 = offset_dma;
+
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+
+		/* In direct mode,changing the alternate completion code address
+		 * to start of rptr,the assumption is that most auth iv failure
+		 * are reported at first byte only.This will not give the
+		 * correct alternate completion code the auth iv fail is
+		 * reported  after some bytes.
+		 * FIXME
+		 */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					iv_len);
+		/* since this is decryption,
+		 * don't touch the content of
+		 * alternate ccode space as it contains
+		 * hmac.
+		 */
+
+		vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+						      OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			htobe64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+	} else {
+		uint64_t dptr_dma, rptr_dma;
+		uint32_t g_size_bytes, s_size_bytes;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint8_t i = 0;
+
+		/* This falls under strict SG mode */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+		size = OFF_CTRL_LEN + iv_len;
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		opcode.s.major |= DMA_MODE;
+
+		vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+						      OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			htobe64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word that includes iv */
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+		/* Add input data */
+		if (flags & VALID_MAC_BUF) {
+			size = inputlen - iv_len - mac_len;
+			if (size) {
+				/* input data only */
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+								gather_comp, i,
+								fc_params->bufs,
+								&size);
+				} else {
+					uint32_t aad_offset = aad_len ?
+						passthrough_len : 0;
+
+					i = fill_sg_comp_from_iov(gather_comp,
+							   i,
+							   fc_params->src_iov,
+							   0, &size,
+							   aad_buf,
+							   aad_offset);
+				}
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+
+			/* mac data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(gather_comp, i,
+							  &fc_params->mac_buf);
+			}
+		} else {
+			/* input data + mac */
+			size = inputlen - iv_len;
+			if (size) {
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+								gather_comp, i,
+								fc_params->bufs,
+								&size);
+				} else {
+					uint32_t aad_offset = aad_len ?
+						passthrough_len : 0;
+
+					if (!fc_params->src_iov)
+						return ERR_BAD_INPUT_ARG;
+
+				       i = fill_sg_comp_from_iov(gather_comp, i,
+							     fc_params->src_iov,
+							     0, &size,
+							     aad_buf,
+							     aad_offset);
+				}
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[2] = htobe16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* Add iv */
+		if (iv_len) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* Add output data */
+		size = outputlen - iv_len;
+		if (size) {
+			if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+				/* handle single buffer here */
+				i = fill_sg_comp_from_buf_min(scatter_comp, i,
+							      fc_params->bufs,
+							      &size);
+			} else {
+				uint32_t aad_offset = aad_len ?
+					passthrough_len : 0;
+
+				if (!fc_params->dst_iov)
+					return ERR_BAD_INPUT_ARG;
+
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  fc_params->dst_iov, 0,
+							  &size, aad_buf,
+							  aad_offset);
+			}
+
+			if (unlikely(size))
+				return ERR_BAD_INPUT_ARG;
+		}
+
+		((uint16_t *)in_buffer)[3] = htobe16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = htobe16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+		size += COMPLETION_CODE_SIZE;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);
+
+	ctx_dma = fc_params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, fctx);
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = ctx_dma;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!(m_size >= 0)) {
+		PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n",
+			   m_size);
+		abort();
+	}
+#endif
+	*prep_req = req;
+	return 0;
+}
+
+void *
+cpt_fc_dec_hmac_prep(uint32_t flags,
+		     uint64_t d_offs,
+		     uint64_t d_lens,
+		     fc_params_t *fc_params,
+		     void *op, int *ret_val)
+{
+	struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+	uint8_t fc_type;
+	void *prep_req = NULL;
+	int ret;
+
+	fc_type = ctx->fc_type;
+
+	if (likely(fc_type == FC_GEN)) {
+		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
+					fc_params, op, &prep_req);
+	} else {
+		/*
+		 * For AUTH_ONLY case,
+		 * MC only supports digest generation and verification
+		 * should be done in software by memcmp()
+		 */
+
+		ret = ERR_EIO;
+	}
+
+	if (unlikely(!prep_req))
+		*ret_val = ret;
+	return prep_req;
+}
+
+void *__hot
+cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
+		     fc_params_t *fc_params, void *op, int *ret_val)
+{
+	struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+	uint8_t fc_type;
+	void *prep_req = NULL;
+	int ret;
+
+	fc_type = ctx->fc_type;
+
+	/* Common api for rest of the ops */
+	if (likely(fc_type == FC_GEN)) {
+		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
+					fc_params, op, &prep_req);
+	} else {
+		ret = ERR_EIO;
+	}
+
+	if (unlikely(!prep_req))
+		*ret_val = ret;
+	return prep_req;
+}
-- 
1.9.3

Re: [dpdk-dev] [PATCH 06/16] crypto/cpt/base: add sym crypto request prepare for CPT

[Jerin Jacob]

-----Original Message-----
> Date: Fri,  8 Jun 2018 22:15:15 +0530
> From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> To: Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara
>  <pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>
> Cc: Ankur Dwivedi <ankur.dwivedi@cavium.com>, Jerin Jacob
>  <jerin.jacob@caviumnetworks.com>, Murthy NSSR
>  <Nidadavolu.Murthy@cavium.com>, Narayana Prasad
>  <narayanaprasad.athreya@caviumnetworks.com>, Nithin Dabilpuram
>  <nithin.dabilpuram@cavium.com>, Ragothaman Jayaraman
>  <Ragothaman.Jayaraman@cavium.com>, Srisivasubramanian Srinivasan
>  <Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org
> Subject: [PATCH 06/16] crypto/cpt/base: add sym crypto request prepare for
>  CPT
> X-Mailer: git-send-email 2.7.4
> 
> From: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> 
> These functions help in preparing symmetric crypto requests
> for the supported cipher/auth/aead. This includes all supported
> algos except Kasumi, Snow3G, Zuc, HMAC_ONLY and HASH_ONLY cases.
> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
> ---
>  drivers/crypto/cpt/base/cpt.h     |  129 +++++
>  drivers/crypto/cpt/base/cpt_ops.c | 1021 +++++++++++++++++++++++++++++++++++++
>  2 files changed, 1150 insertions(+)
> 
> diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h
> index 11407ae..54b1cb6 100644
> --- a/drivers/crypto/cpt/base/cpt.h
> +++ b/drivers/crypto/cpt/base/cpt.h
> @@ -54,6 +54,135 @@
>  	void *marker;
>  } app_data_t;
>  
> +/*
> + * Parameters for Flexi Crypto
> + * requests
> + */
> +#define VALID_AAD_BUF 0x01
> +#define VALID_MAC_BUF 0x02
> +#define VALID_IV_BUF 0x04
> +#define SINGLE_BUF_INPLACE 0x08
> +#define SINGLE_BUF_HEADTAILROOM 0x10
> +
> +#define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff)
> +#define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff)
> +#define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff)
> +#define ENCR_DLEN(__d_lens) (__d_lens >> 32)
> +#define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff)
> +
> +typedef struct fc_params {
> +	/* 0th cache line */

Does it used in fastpath, if so, make it cache aligned

> +	union {
> +		buf_ptr_t bufs[1];
> +		struct {
> +			iov_ptr_t *src_iov;
> +			iov_ptr_t *dst_iov;
> +		};
> +	};
> +	void *iv_buf;
> +	void *auth_iv_buf;
> +	buf_ptr_t meta_buf;
> +	buf_ptr_t ctx_buf;
> +	uint64_t rsvd2;
> +
> +	/* 1st cache line */
> +	buf_ptr_t aad_buf;
> +	buf_ptr_t mac_buf;
> +
> +} fc_params_t;
> +
> +/*
> + * Parameters for digest
> + * generate requests
> + * Only src_iov, op, ctx_buf, mac_buf, prep_req

[dpdk-dev] [PATCH 07/16] crypto/cpt/base: add request prepare API for ZUC and SNOW3G

[Anoob Joseph]

From: Murthy NSSR <Nidadavolu.Murthy@cavium.com>

These functions help in preparing symmetric crypto requests
for the ZUC, SNOW3G algorithms of both cipher and auth but
not cipher+auth in single xform.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/base/cpt_ops.c | 667 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 667 insertions(+)

diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c
index 31f8064..ff7522a 100644
--- a/drivers/crypto/cpt/base/cpt_ops.c
+++ b/drivers/crypto/cpt/base/cpt_ops.c
@@ -1272,6 +1272,667 @@ static inline int  __attribute__((always_inline))
 	return 0;
 }
 
+static int
+cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
+			uint64_t d_offs,
+			uint64_t d_lens,
+			fc_params_t *params,
+			void *op,
+			void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t mac_len = 0;
+	uint8_t snow3g, j;
+	cpt_request_info_t *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset = 0, auth_offset = 0;
+	uint32_t encr_data_len = 0, auth_data_len = 0;
+	int flags, iv_len = 16, m_size;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma, offset_ctrl;
+	uint64_t *offset_vaddr, offset_dma;
+	uint32_t *iv_s, iv[4];
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+
+	buf_p = &params->meta_buf;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!params || !buf_p->vaddr || !buf_p->size)
+		return ERR_BAD_INPUT_ARG;
+#endif
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	mac_len = cpt_ctx->mac_len;
+	snow3g = cpt_ctx->snow3g;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(cpt_request_info_t);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields for cpt request
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	opcode.s.major = MAJOR_OP_ZUC_SNOW3G;
+
+	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+	opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+			  (0 << 3) | (flags & 0x7));
+
+	if (flags == 0x1) {
+		/*
+		 * Microcode expects offsets in bytes
+		 * TODO: Rounding off
+		 */
+		auth_data_len = AUTH_DLEN(d_lens);
+
+		/* EIA3 or UIA2 */
+		auth_offset = AUTH_OFFSET(d_offs);
+		auth_offset = auth_offset / 8;
+
+		/* consider iv len */
+		auth_offset += iv_len;
+
+		inputlen = auth_offset +
+			(RTE_ALIGN(auth_data_len, 8) / 8);
+		outputlen = mac_len;
+
+		offset_ctrl = htobe64((uint64_t)auth_offset);
+
+	} else {
+		/* EEA3 or UEA2 */
+		/*
+		 * Microcode expects offsets in bytes
+		 * TODO: Rounding off
+		 */
+		encr_data_len = ENCR_DLEN(d_lens);
+
+
+		encr_offset = ENCR_OFFSET(d_offs);
+		encr_offset = encr_offset / 8;
+		/* consider iv len */
+		encr_offset += iv_len;
+
+		inputlen = encr_offset +
+			(RTE_ALIGN(encr_data_len, 8) / 8);
+		outputlen = inputlen;
+
+		/* iv offset is 0 */
+		offset_ctrl = htobe64((uint64_t)encr_offset << 16);
+	}
+
+	/* IV */
+	iv_s = (flags == 0x1) ? params->auth_iv_buf :
+		params->iv_buf;
+
+	if (snow3g) {
+		/*
+		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+		 */
+
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[3 - j];
+	} else {
+		/* ZUC doesn't need a swap */
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[j];
+	}
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = htobe16(encr_data_len);
+	vq_cmd_w0.s.param2 = htobe16(auth_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+		   (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					    OFF_CTRL_LEN - iv_len);
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			memcpy(iv_d, iv, 16);
+		}
+
+		*offset_vaddr = offset_ctrl;
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint32_t *iv_d;
+
+		/*save space for iv */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+
+		m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+		m_dma += OFF_CTRL_LEN + iv_len;
+		m_size -= OFF_CTRL_LEN + iv_len;
+
+		opcode.s.major |= DMA_MODE;
+
+		vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word followed by iv */
+
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+		/* iv offset is 0 */
+		*offset_vaddr = offset_ctrl;
+
+		iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+		memcpy(iv_d, iv, 16);
+
+		/* input data */
+		size = inputlen - iv_len;
+		if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+			if (!params->src_iov)
+				return ERR_BAD_INPUT_ARG;
+#endif
+
+			i = fill_sg_comp_from_iov(gather_comp, i,
+						  params->src_iov,
+						  0, &size, NULL, 0);
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[2] = htobe16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		if (flags == 0x1) {
+			/* IV in SLIST only for EEA3 & UEA2 */
+			iv_len = 0;
+		}
+
+		if (iv_len) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* Add output data */
+		if (req_flags & VALID_MAC_BUF) {
+			size = outputlen - iv_len - mac_len;
+			if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+				if (!params->dst_iov)
+					return ERR_BAD_INPUT_ARG;
+#endif
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  params->dst_iov, 0,
+							  &size, NULL, 0);
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+
+			/* mac data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(scatter_comp, i,
+							  &params->mac_buf);
+			}
+		} else {
+			/* Output including mac */
+			size = outputlen - iv_len;
+			if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+				if (!params->dst_iov)
+					return ERR_BAD_INPUT_ARG;
+#endif
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  params->dst_iov, 0,
+							  &size, NULL, 0);
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[3] = htobe16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = htobe16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, zs_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!(m_size >= 0)) {
+		PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n",
+			   m_size);
+		abort();
+	}
+#endif
+	*prep_req = req;
+	return 0;
+}
+
+static inline int
+cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
+			uint64_t d_offs,
+			uint64_t d_lens,
+			fc_params_t *params,
+			void *op,
+			void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint8_t snow3g, iv_len = 16;
+	cpt_request_info_t *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset;
+	uint32_t encr_data_len;
+	int flags, m_size;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	uint32_t *iv_s, iv[4], j;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+
+	(void)req_flags;
+	buf_p = &params->meta_buf;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!params || !buf_p->vaddr || !buf_p->size)
+		return ERR_BAD_INPUT_ARG;
+#endif
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	/*
+	 * Microcode expects offsets in bytes
+	 * TODO: Rounding off
+	 */
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	snow3g = cpt_ctx->snow3g;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (flags != 0) {
+		/* Dec not supported for EIA3 or UIA2 */
+		return ERR_BAD_INPUT_ARG;
+	}
+#endif
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(cpt_request_info_t);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields for cpt request
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	opcode.s.major = MAJOR_OP_ZUC_SNOW3G;
+
+	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+	opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+			  (0 << 3) | (flags & 0x7));
+
+	/* consider iv len */
+	encr_offset += iv_len;
+
+	inputlen = encr_offset +
+		(RTE_ALIGN(encr_data_len, 8) / 8);
+	outputlen = inputlen;
+
+	/* IV */
+	iv_s = params->iv_buf;
+	if (snow3g) {
+		/*
+		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+		 */
+
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[3 - j];
+	} else {
+		/* ZUC doesn't need a swap */
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[j];
+	}
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = htobe16(encr_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+		   (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					    OFF_CTRL_LEN - iv_len);
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+		/* *req->alternate_caddr = ((uint64_t)0xdeadbeefdeadbeef) */
+
+		vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			memcpy(iv_d, iv, 16);
+		}
+
+		/* iv offset is 0 */
+		*offset_vaddr = htobe64((uint64_t)encr_offset << 16);
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint32_t *iv_d;
+
+		/* save space for offset and iv... */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+
+		m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+		m_dma += OFF_CTRL_LEN + iv_len;
+		m_size -= OFF_CTRL_LEN + iv_len;
+
+		opcode.s.major |= DMA_MODE;
+
+		vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word */
+
+		/* iv offset is 0 */
+		*offset_vaddr = htobe64((uint64_t)encr_offset << 16);
+
+		i = fill_sg_comp(gather_comp, i, offset_dma, offset_vaddr,
+				 OFF_CTRL_LEN + iv_len);
+
+		iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+		memcpy(iv_d, iv, 16);
+
+		/* Add input data */
+		size = inputlen - iv_len;
+		if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+			if (!params->src_iov)
+				return ERR_BAD_INPUT_ARG;
+#endif
+			i = fill_sg_comp_from_iov(gather_comp, i,
+						  params->src_iov,
+						  0, &size, NULL, 0);
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[2] = htobe16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* IV */
+		i = fill_sg_comp(scatter_comp, i,
+				 offset_dma + OFF_CTRL_LEN,
+				 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+				 iv_len);
+
+		/* Add output data */
+		size = outputlen - iv_len;
+		if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+			if (!params->dst_iov)
+				return ERR_BAD_INPUT_ARG;
+#endif
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[3] = htobe16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = htobe16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, zs_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!(m_size >= 0)) {
+		PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n",
+			   m_size);
+		abort();
+	}
+#endif
+	*prep_req = req;
+	return 0;
+}
+
 void *
 cpt_fc_dec_hmac_prep(uint32_t flags,
 		     uint64_t d_offs,
@@ -1289,6 +1950,9 @@ static inline int  __attribute__((always_inline))
 	if (likely(fc_type == FC_GEN)) {
 		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
 					fc_params, op, &prep_req);
+	} else if (fc_type == ZUC_SNOW3G) {
+		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
+					      fc_params, op, &prep_req);
 	} else {
 		/*
 		 * For AUTH_ONLY case,
@@ -1319,6 +1983,9 @@ static inline int  __attribute__((always_inline))
 	if (likely(fc_type == FC_GEN)) {
 		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
 					fc_params, op, &prep_req);
+	} else if (fc_type == ZUC_SNOW3G) {
+		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
+					      fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
-- 
1.9.3

[dpdk-dev] [PATCH 08/16] crypto/cpt/base: add request prepare API for Kasumi

[Anoob Joseph]

From: Murthy NSSR <Nidadavolu.Murthy@cavium.com>

These functions help in preparing symmetric crypto request
for Kasumi of both cipher and auth but not cipher+auth in single
xform.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/base/cpt_ops.c | 545 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 545 insertions(+)

diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c
index ff7522a..15c3413 100644
--- a/drivers/crypto/cpt/base/cpt_ops.c
+++ b/drivers/crypto/cpt/base/cpt_ops.c
@@ -1933,6 +1933,545 @@ static inline int  __attribute__((always_inline))
 	return 0;
 }
 
+static int
+cpt_kasumi_enc_prep(uint32_t req_flags,
+		    uint64_t d_offs,
+		    uint64_t d_lens,
+		    fc_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen = 0;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t mac_len = 0;
+	uint8_t i = 0;
+	cpt_request_info_t *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len;
+	int flags, m_size;
+	uint8_t *iv_s, *iv_d, iv_len = 8;
+	uint8_t dir = 0;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+
+	buf_p = &params->meta_buf;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!params || !buf_p->vaddr || !buf_p->size)
+		return ERR_BAD_INPUT_ARG;
+#endif
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	auth_offset = AUTH_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	mac_len = cpt_ctx->mac_len;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (flags == 0x0) {
+		/* F8 Mode */
+		if (auth_offset || auth_data_len)
+			return ERR_BAD_INPUT_ARG;
+
+		if (!params->iv_buf)
+			return ERR_BAD_INPUT_ARG;
+	} else if (flags == 0x1) {
+		/* F9 mode */
+		if (encr_offset || encr_data_len)
+			return ERR_BAD_INPUT_ARG;
+
+		if (!params->auth_iv_buf)
+			return ERR_BAD_INPUT_ARG;
+	} else {
+		return ERR_EIO;
+	}
+#endif
+	if (flags == 0x0)
+		iv_s = params->iv_buf;
+	else
+		iv_s = params->auth_iv_buf;
+
+	dir = iv_s[8] & 0x1;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(cpt_request_info_t);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields for cpt request
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	opcode.s.major = MAJOR_OP_KASUMI | DMA_MODE;
+
+	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
+	opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
+			  (dir << 4) | (0 << 3) | (flags & 0x7));
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = htobe16(encr_data_len);
+	vq_cmd_w0.s.param2 = htobe16(auth_data_len);
+	vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+	/* consider iv len */
+	if (flags == 0x0) {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/* save space for offset ctrl and iv */
+	offset_vaddr = m_vaddr;
+	offset_dma = m_dma;
+
+	m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+	m_dma += OFF_CTRL_LEN + iv_len;
+	m_size -= OFF_CTRL_LEN + iv_len;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input Gather List
+	 */
+	i = 0;
+
+	/* Offset control word followed by iv */
+
+	if (flags == 0x0) {
+		inputlen = encr_offset +
+			(RTE_ALIGN(encr_data_len, 8) / 8);
+		outputlen = inputlen;
+		/* iv offset is 0 */
+		*offset_vaddr = htobe64((uint64_t)encr_offset << 16);
+	} else {
+		inputlen = auth_offset +
+			(RTE_ALIGN(auth_data_len, 8) / 8);
+		outputlen = mac_len;
+		/* iv offset is 0 */
+		*offset_vaddr = htobe64((uint64_t)auth_offset);
+	}
+
+	i = fill_sg_comp(gather_comp, i, offset_dma,
+			 offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+	/* IV */
+	iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;
+	memcpy(iv_d, iv_s, iv_len);
+
+	/* input data */
+	size = inputlen - iv_len;
+	if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+		if (!params->src_iov)
+			return ERR_BAD_INPUT_ARG;
+#endif
+		i = fill_sg_comp_from_iov(gather_comp, i,
+					  params->src_iov, 0,
+					  &size, NULL, 0);
+
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[2] = htobe16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp =
+		(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	if (flags == 0x1) {
+		/* IV in SLIST only for F8 */
+		iv_len = 0;
+	}
+
+	/* IV */
+	if (iv_len) {
+
+		i = fill_sg_comp(scatter_comp, i,
+				 offset_dma + OFF_CTRL_LEN,
+				 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+				 iv_len);
+	}
+
+	/* Add output data */
+	if (req_flags & VALID_MAC_BUF) {
+		size = outputlen - iv_len - mac_len;
+		if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+			if (!params->dst_iov)
+				return ERR_BAD_INPUT_ARG;
+#endif
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+
+		/* mac data */
+		if (mac_len) {
+			i = fill_sg_comp_from_buf(scatter_comp, i,
+						  &params->mac_buf);
+		}
+	} else {
+		/* Output including mac */
+		size = outputlen - iv_len;
+		if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+			if (!params->dst_iov)
+				return ERR_BAD_INPUT_ARG;
+#endif
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+	}
+	((uint16_t *)in_buffer)[3] = htobe16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = htobe16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, k_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!(m_size >= 0)) {
+		PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n",
+			   m_size);
+		abort();
+	}
+#endif
+	*prep_req = req;
+	return 0;
+}
+
+
+static inline int
+cpt_kasumi_dec_prep(uint32_t req_flags,
+		    uint64_t d_offs,
+		    uint64_t d_lens,
+		    fc_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint8_t i = 0, iv_len = 8;
+	cpt_request_info_t *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset;
+	uint32_t encr_data_len;
+	int flags, m_size;
+	uint8_t dir = 0;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+
+	(void)req_flags;
+	buf_p = &params->meta_buf;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!params || !buf_p->vaddr || !buf_p->size)
+		return ERR_BAD_INPUT_ARG;
+#endif
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!params->iv_buf)
+		return ERR_BAD_INPUT_ARG;
+#endif
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (flags != 0) {
+		/* Dec not supported for F9 */
+		return ERR_BAD_INPUT_ARG;
+	}
+#endif
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(cpt_request_info_t);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields for cpt req
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	opcode.s.major = MAJOR_OP_KASUMI | DMA_MODE;
+
+	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
+	opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
+			  (dir << 4) | (0 << 3) | (flags & 0x7));
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = htobe16(encr_data_len);
+	vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+	/* consider iv len */
+	encr_offset += iv_len;
+
+	inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);
+	outputlen = inputlen;
+
+	/* save space for offset ctrl & iv */
+	offset_vaddr = m_vaddr;
+	offset_dma = m_dma;
+
+	m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+	m_dma += OFF_CTRL_LEN + iv_len;
+	m_size -= OFF_CTRL_LEN + iv_len;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input Gather List
+	 */
+	i = 0;
+
+	/* Offset control word followed by iv */
+	*offset_vaddr = htobe64((uint64_t)encr_offset << 16);
+
+	i = fill_sg_comp(gather_comp, i, offset_dma, offset_vaddr,
+			 OFF_CTRL_LEN + iv_len);
+
+
+	/* IV */
+	memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+	       params->iv_buf, iv_len);
+
+	/* Add input data */
+	size = inputlen - iv_len;
+	if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+		if (!params->src_iov)
+			return ERR_BAD_INPUT_ARG;
+#endif
+		i = fill_sg_comp_from_iov(gather_comp, i,
+					  params->src_iov,
+					  0, &size, NULL, 0);
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[2] = htobe16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp =
+		(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	/* IV */
+	i = fill_sg_comp(scatter_comp, i,
+			 offset_dma + OFF_CTRL_LEN,
+			 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+			 iv_len);
+
+	/* Add output data */
+	size = outputlen - iv_len;
+	if (size) {
+#ifdef CPTVF_STRICT_PARAM_CHECK
+		if (!params->dst_iov)
+			return ERR_BAD_INPUT_ARG;
+#endif
+		i = fill_sg_comp_from_iov(scatter_comp, i,
+					  params->dst_iov, 0,
+					  &size, NULL, 0);
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[3] = htobe16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = htobe16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, k_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!(m_size >= 0))
+		abort();
+#endif
+	*prep_req = req;
+	return 0;
+}
+
 void *
 cpt_fc_dec_hmac_prep(uint32_t flags,
 		     uint64_t d_offs,
@@ -1953,6 +2492,9 @@ static inline int  __attribute__((always_inline))
 	} else if (fc_type == ZUC_SNOW3G) {
 		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
 					      fc_params, op, &prep_req);
+	} else if (fc_type == KASUMI) {
+		ret = cpt_kasumi_dec_prep(flags, d_offs, d_lens,
+					  fc_params, op, &prep_req);
 	} else {
 		/*
 		 * For AUTH_ONLY case,
@@ -1986,6 +2528,9 @@ static inline int  __attribute__((always_inline))
 	} else if (fc_type == ZUC_SNOW3G) {
 		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
 					      fc_params, op, &prep_req);
+	} else if (fc_type == KASUMI) {
+		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,
+					  fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
-- 
1.9.3

[dpdk-dev] [PATCH 09/16] crypto/cpt/base: add prepare request API for HASH and HMAC

[Anoob Joseph]

From: Murthy NSSR <Nidadavolu.Murthy@cavium.com>

These functions help in preparing symmetric crypto requests
for HMAC only or HMAC only cases.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/base/cpt_ops.c | 215 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 215 insertions(+)

diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c
index 15c3413..eb25607 100644
--- a/drivers/crypto/cpt/base/cpt_ops.c
+++ b/drivers/crypto/cpt/base/cpt_ops.c
@@ -450,6 +450,218 @@ int32_t cpt_fc_get_ctx_len(void)
 	return (uint32_t)i;
 }
 
+static int
+cpt_digest_gen_prep(uint32_t flags,
+		    uint64_t d_offs,
+		    uint64_t d_lens,
+		    digest_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	cpt_request_info_t *req;
+	uint32_t size, i;
+	int32_t m_size;
+	uint16_t data_len, mac_len, key_len;
+	auth_type_t hash_type;
+	buf_ptr_t *meta_p;
+	struct cpt_ctx *ctx;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr, *m_vaddr;
+	uint64_t c_dma, m_dma;
+	opcode_info_t opcode;
+
+	if (!params || !params->ctx_buf.vaddr)
+		return ERR_BAD_INPUT_ARG;
+
+	(void)d_offs;
+	ctx = params->ctx_buf.vaddr;
+	meta_p = &params->meta_buf;
+
+	if (!meta_p->vaddr || !meta_p->dma_addr)
+		return ERR_BAD_INPUT_ARG;
+
+	if (meta_p->size < sizeof(cpt_request_info_t))
+		return ERR_BAD_INPUT_ARG;
+
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	req = m_vaddr;
+
+	size = sizeof(cpt_request_info_t);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode fields */
+
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+	req->se_req = SE_CORE_REQ;
+
+	hash_type = ctx->hash_type;
+	mac_len = ctx->mac_len;
+	key_len = ctx->auth_key_len;
+	data_len = AUTH_DLEN(d_lens);
+
+	/*GP op header */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param2 = htobe16(((uint16_t)hash_type << 8));
+	if (ctx->hmac) {
+		opcode.s.major = MAJOR_OP_HMAC | DMA_MODE;
+		vq_cmd_w0.s.param1 = htobe16(key_len);
+		vq_cmd_w0.s.dlen = htobe16((data_len + ROUNDUP8(key_len)));
+	} else {
+		opcode.s.major = MAJOR_OP_HASH | DMA_MODE;
+		vq_cmd_w0.s.param1 = 0;
+		vq_cmd_w0.s.dlen = htobe16(data_len);
+	}
+
+	opcode.s.minor = 0;
+
+	vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input gather list
+	 */
+
+	i = 0;
+
+	if (ctx->hmac) {
+		uint64_t k_dma = params->ctx_buf.dma_addr +
+			offsetof(struct cpt_ctx, auth_key);
+		/* Key */
+		i = fill_sg_comp(gather_comp, i, k_dma,
+				 ctx->auth_key, ROUNDUP8(key_len));
+	}
+
+	/* input data */
+	size = data_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,
+					  0, &size, NULL, 0);
+		if (size) {
+			PMD_TX_LOG(DEBUG, "Insufficient dst IOV size, short by"
+				   " %dB\n", size);
+			return ERR_BAD_INPUT_ARG;
+		}
+	} else {
+		/*
+		 * Looks like we need to support zero data
+		 * gather ptr in case of hash & hmac
+		 */
+		i++;
+	}
+	((uint16_t *)in_buffer)[2] = htobe16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+
+	/*
+	 * Output Gather list
+	 */
+
+	i = 0;
+	scatter_comp =
+		(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	if (flags & VALID_MAC_BUF) {
+		if (params->mac_buf.size < mac_len)
+			return ERR_BAD_INPUT_ARG;
+
+		size = mac_len;
+		i = fill_sg_comp_from_buf_min(scatter_comp, i,
+					      &params->mac_buf, &size);
+	} else {
+		size = mac_len;
+		i = fill_sg_comp_from_iov(scatter_comp, i,
+					  params->src_iov, data_len,
+					  &size, NULL, 0);
+		if (size) {
+			PMD_TX_LOG(DEBUG, "Insufficient dst IOV size, short by"
+				   " %dB\n", size);
+			return ERR_BAD_INPUT_ARG;
+		}
+	}
+
+	((uint16_t *)in_buffer)[3] = htobe16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = htobe16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+	if (!(m_size >= 0))
+		abort();
+#endif
+	*prep_req = req;
+	return 0;
+}
+
 static inline int  __attribute__((always_inline))
 cpt_enc_hmac_prep(uint32_t flags,
 		  uint64_t d_offs,
@@ -2531,6 +2743,9 @@ static inline int  __attribute__((always_inline))
 	} else if (fc_type == KASUMI) {
 		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,
 					  fc_params, op, &prep_req);
+	} else if (fc_type == HASH_HMAC) {
+		ret = cpt_digest_gen_prep(flags, d_offs, d_lens,
+					  fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
-- 
1.9.3

[dpdk-dev] [PATCH 10/16] crypto/cpt: add driver initializations

[Anoob Joseph]

From: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>

Introduce driver initialization and enable build infrastructure.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/Makefile            |   9 +-
 drivers/crypto/cpt/cpt_pmd_cryptodev.c | 270 +++++++++++++++++++++++++++++++++
 drivers/crypto/cpt/cpt_pmd_logs.h      |  50 ++++++
 3 files changed, 328 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/cpt/cpt_pmd_cryptodev.c
 create mode 100644 drivers/crypto/cpt/cpt_pmd_logs.h

diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile
index b2d950d..40ec9e2 100644
--- a/drivers/crypto/cpt/Makefile
+++ b/drivers/crypto/cpt/Makefile
@@ -23,7 +23,14 @@ CFLAGS += -O3
 #CFLAGS += -DAUTH_SOFT_COMPUTE_IPAD_OPAD
 #CFLAGS += -DCPT_DEBUG
 
-SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) +=
+# PMD code
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_cryptodev.c
+
+# Base code
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_device.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_ops.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt8xxx_device.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_vf_mbox.c
 
 # export include files
 SYMLINK-y-include +=
diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
new file mode 100644
index 0000000..addddd8
--- /dev/null
+++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include <rte_common.h>
+#include <rte_dev.h>
+#include <rte_pci.h>
+#include <rte_crypto.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_alarm.h>
+#include <rte_bus_pci.h>
+
+#include "base/cpt_device.h"
+#include "cpt_pmd_logs.h"
+
+#define CSP_INTR_POLL_INTERVAL_MS 50
+
+static int global_init_done;
+uint8_t cryptodev_cpt_driver_id;
+struct rte_mempool *cpt_meta_pool;
+int cpt_op_mlen;
+int cpt_op_sb_mlen;
+
+static void
+cpt_pmd_alarm_cb(void *arg)
+{
+	struct cpt_vf *cptvf = arg;
+	cptvf_poll_misc(cptvf);
+	rte_eal_alarm_set(CSP_INTR_POLL_INTERVAL_MS * 1000,
+			  cpt_pmd_alarm_cb, cptvf);
+}
+
+static int
+cpt_pmd_periodic_alarm_start(void *arg)
+{
+	return rte_eal_alarm_set(CSP_INTR_POLL_INTERVAL_MS * 1000,
+				 cpt_pmd_alarm_cb, arg);
+}
+
+static int
+cpt_pmd_periodic_alarm_stop(void *arg)
+{
+	return rte_eal_alarm_cancel(cpt_pmd_alarm_cb, arg);
+}
+
+static struct rte_cryptodev_ops cptvf_ops = {
+	/* Device related operations */
+	.dev_configure = NULL,
+	.dev_start = NULL,
+	.dev_stop = NULL,
+	.dev_close = NULL,
+	.dev_infos_get = NULL,
+
+	.stats_get = NULL,
+	.stats_reset = NULL,
+	.queue_pair_setup = NULL,
+	.queue_pair_release = NULL,
+	.queue_pair_start = NULL,
+	.queue_pair_stop = NULL,
+	.queue_pair_count = NULL,
+
+	/* Crypto related operations */
+	.session_get_size = NULL,
+	.session_configure = NULL,
+	.session_clear = NULL
+};
+
+static int init_global_resources(void)
+{
+	/* In future consider rte_security and asym. 4B extra for app use */
+	cpt_op_mlen = cpt_fc_get_op_meta_len() + 4 * sizeof(uint64_t);
+	cpt_meta_pool = rte_mempool_create("cpt_metabuf-pool", 4096 * 16,
+					   cpt_op_mlen, 512, 0,
+					   NULL, NULL, NULL, NULL,
+					   SOCKET_ID_ANY, 0);
+	if (!cpt_meta_pool) {
+		PMD_DRV_LOG(ERR, "cpt metabuf pool not created\n");
+		return -ENOMEM;
+	}
+	cpt_op_sb_mlen = cpt_fc_get_op_sb_meta_len() + 4 * sizeof(uint64_t);
+
+	return 0;
+}
+
+static int
+cptvf_dev_init(struct rte_pci_driver *c_drv __rte_unused,
+		 struct rte_cryptodev *c_dev)
+{
+	struct rte_pci_device *pdev = RTE_DEV_TO_PCI(c_dev->device);
+	struct cpt_vf *cptvf = c_dev->data->dev_private;
+	void *reg_base;
+	char dev_name[32];
+	int ret;
+
+	PMD_DRV_LOG(DEBUG, ">>>");
+
+	if (pdev->mem_resource[0].phys_addr == 0ULL)
+		return -EIO;
+
+	/* for secondary processes, we don't initialise any further as primary
+	 * has already done this work.
+	 */
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	snprintf(dev_name, 32, "%02x:%02x.%x",
+			pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
+	PMD_DRV_LOG(DEBUG, "Found CPT device %s", dev_name);
+
+	reg_base = pdev->mem_resource[0].addr;
+	if (!reg_base) {
+		PMD_DRV_LOG(ERR, "Failed to map BAR0 of %s", dev_name);
+		ret = -ENODEV;
+		goto fail;
+	}
+
+	ret = cptvf_init_device(cptvf, pdev, reg_base, dev_name, 0);
+	if (ret) {
+		PMD_DRV_LOG(ERR, "Failed to init cptvf %s", dev_name);
+		return -EIO;
+	}
+
+	/* Start off timer for mailbox interrupts */
+	cpt_pmd_periodic_alarm_start(cptvf);
+	/* TODO Do we really need this to poll for mbox ?? */
+	/* cptvf_enable_mbox_interrupts(cptvf); */
+
+	if (!global_init_done) {
+		/* cpt_set_debug_level(debug); */
+		ret = init_global_resources();
+		if (ret)
+			goto init_fail;
+		global_init_done = 1;
+	}
+
+	c_dev->dev_ops = &cptvf_ops;
+
+	c_dev->enqueue_burst = NULL;
+	c_dev->dequeue_burst = NULL;
+
+	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+			RTE_CRYPTODEV_FF_HW_ACCELERATED |
+			RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING;
+
+	return 0;
+
+init_fail:
+	cpt_pmd_periodic_alarm_stop(cptvf);
+	cptvf_deinit_device(cptvf);
+	return ret;
+
+fail:
+	return ret;
+}
+
+static int
+rte_cptdev_pci_probe(struct rte_pci_driver *pci_drv,
+			struct rte_pci_device *pci_dev)
+{
+	struct rte_cryptodev *cryptodev;
+
+	char cryptodev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
+
+	int retval;
+
+	if (pci_drv == NULL)
+		return -ENODEV;
+
+	rte_pci_device_name(&pci_dev->addr, cryptodev_name,
+			sizeof(cryptodev_name));
+
+	cryptodev = rte_cryptodev_pmd_allocate(cryptodev_name, rte_socket_id());
+	if (cryptodev == NULL)
+		return -ENOMEM;
+
+	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
+		cryptodev->data->dev_private =
+				rte_zmalloc_socket(
+						"cryptodev private structure",
+						sizeof(struct cpt_vf),
+						RTE_CACHE_LINE_SIZE,
+						rte_socket_id());
+
+		if (cryptodev->data->dev_private == NULL)
+			rte_panic("Cannot allocate memzone for private "
+					"device data");
+	}
+
+	cryptodev->device = &pci_dev->device;
+	cryptodev->device->driver = &pci_drv->driver;
+	cryptodev->driver_id = cryptodev_cpt_driver_id;
+
+	/* init user callbacks */
+	TAILQ_INIT(&(cryptodev->link_intr_cbs));
+
+	/* Invoke PMD device initialization function */
+	retval = cptvf_dev_init(pci_drv, cryptodev);
+	if (retval == 0)
+		return 0;
+
+	PMD_DRV_LOG(ERR, "driver %s: crypto_dev_init(vendor_id=0x%x device_id="
+			"0x%x) failed", pci_drv->driver.name,
+			(unsigned int) pci_dev->id.vendor_id,
+			(unsigned int) pci_dev->id.device_id);
+
+	if (rte_eal_process_type() == RTE_PROC_PRIMARY)
+		rte_free(cryptodev->data->dev_private);
+
+	cryptodev->attached = RTE_CRYPTODEV_DETACHED;
+
+	return -ENXIO;
+}
+
+static int
+rte_cptdev_pci_remove(struct rte_pci_device *pci_dev)
+{
+	struct rte_cryptodev *cryptodev;
+	char cryptodev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
+
+	if (pci_dev == NULL)
+		return -EINVAL;
+
+	rte_pci_device_name(&pci_dev->addr, cryptodev_name,
+			sizeof(cryptodev_name));
+
+	cryptodev = rte_cryptodev_pmd_get_named_dev(cryptodev_name);
+	if (cryptodev == NULL)
+		return -ENODEV;
+
+	if (pci_dev->driver == NULL)
+		return -ENODEV;
+
+	/* free crypto device */
+	rte_cryptodev_pmd_release_device(cryptodev);
+
+	if (rte_eal_process_type() == RTE_PROC_PRIMARY)
+		rte_free(cryptodev->data->dev_private);
+
+	cryptodev->device = NULL;
+	cryptodev->device->driver = NULL;
+	cryptodev->data = NULL;
+
+	return 0;
+}
+static struct rte_pci_id pci_id_cpt_table[] = {
+	{
+		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_VF_DEVICE_ID),
+	},
+	/* sentinel */
+	{
+	.device_id = 0
+	},
+};
+
+static struct rte_pci_driver cptvf_pmd = {
+		.id_table = pci_id_cpt_table,
+		.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+		.probe = rte_cptdev_pci_probe,
+		.remove = rte_cptdev_pci_remove,
+};
+static struct cryptodev_driver cpt_crypto_drv;
+
+#define CRYPTODEV_NAME_CPT_SYM_PMD	crypto_cpt
+/* Cavium CPT Symmetric Crypto PMD device name */
+
+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_CPT_SYM_PMD, cptvf_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_CPT_SYM_PMD, pci_id_cpt_table);
+RTE_PMD_REGISTER_CRYPTO_DRIVER(cpt_crypto_drv, cptvf_pmd.driver,
+		cryptodev_cpt_driver_id);
diff --git a/drivers/crypto/cpt/cpt_pmd_logs.h b/drivers/crypto/cpt/cpt_pmd_logs.h
new file mode 100644
index 0000000..d245d62
--- /dev/null
+++ b/drivers/crypto/cpt/cpt_pmd_logs.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef _CPT_PMD_LOGS_H_
+#define _CPT_PMD_LOGS_H_
+
+#include <rte_log.h>
+
+#define PMD_DRV_LOG_RAW(level, fmt, args...) \
+		rte_log(RTE_LOG_ ## level, RTE_LOGTYPE_PMD, \
+			"PMD: %s(): " fmt "\n", __func__, ##args)
+
+#ifdef RTE_LIBRTE_PMD_CPT_DEBUG_INIT
+
+#define PMD_INIT_FUNC_TRACE() PMD_DRV_LOG_RAW(DEBUG, " >>")
+#define PMD_DRV_LOG(level, args...) \
+	PMD_DRV_LOG_RAW(level, ##args)
+#else
+
+#define PMD_DRV_LOG(...)  do { } while (0)
+#define PMD_INIT_FUNC_TRACE() do { } while (0)
+#endif
+
+#ifdef RTE_LIBRTE_PMD_CPT_DEBUG_RX
+
+#define CPT_DEBUG
+#define CPTVF_STRICT_PARAM_CHECK
+#define PMD_RX_LOG(level, args...) \
+	PMD_DRV_LOG_RAW(level, ##args)
+#else
+
+#define PMD_RX_LOG(...)  do { } while (0)
+#endif
+
+#ifdef RTE_LIBRTE_PMD_CPT_DEBUG_TX
+
+#define CPT_DEBUG
+#define CPTVF_STRICT_PARAM_CHECK
+
+#define PMD_TX_LOG(level, args...) \
+	PMD_DRV_LOG_RAW(level, ##args)
+#else
+
+#define PMD_TX_LOG(...)  do { } while (0)
+#endif
+
+#define PRINT printf
+
+#endif
-- 
1.9.3

Re: [dpdk-dev] [PATCH 10/16] crypto/cpt: add driver initializations

[De Lara Guarch, Pablo]

> -----Original Message-----
> From: Anoob Joseph [mailto:anoob.joseph@caviumnetworks.com]
> Sent: Friday, June 8, 2018 5:45 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Thomas Monjalon <thomas@monjalon.net>
> Cc: Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; Ankur Dwivedi
> <ankur.dwivedi@cavium.com>; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>; dev@dpdk.org
> Subject: [PATCH 10/16] crypto/cpt: add driver initializations
> 
> From: Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>
> 
> Introduce driver initialization and enable build infrastructure.
> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>
> ---
>  drivers/crypto/cpt/Makefile            |   9 +-
>  drivers/crypto/cpt/cpt_pmd_cryptodev.c | 270
> +++++++++++++++++++++++++++++++++
>  drivers/crypto/cpt/cpt_pmd_logs.h      |  50 ++++++
>  3 files changed, 328 insertions(+), 1 deletion(-)  create mode 100644
> drivers/crypto/cpt/cpt_pmd_cryptodev.c
>  create mode 100644 drivers/crypto/cpt/cpt_pmd_logs.h
> 

...


> +++ b/drivers/crypto/cpt/cpt_pmd_logs.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2017 Cavium, Inc
> + */
> +
> +#ifndef _CPT_PMD_LOGS_H_
> +#define _CPT_PMD_LOGS_H_
> +
> +#include <rte_log.h>
> +
> +#define PMD_DRV_LOG_RAW(level, fmt, args...) \
> +		rte_log(RTE_LOG_ ## level, RTE_LOGTYPE_PMD, \
> +			"PMD: %s(): " fmt "\n", __func__, ##args)
> +
> +#ifdef RTE_LIBRTE_PMD_CPT_DEBUG_INIT
> +
> +#define PMD_INIT_FUNC_TRACE() PMD_DRV_LOG_RAW(DEBUG, " >>")
> #define
> +PMD_DRV_LOG(level, args...) \
> +	PMD_DRV_LOG_RAW(level, ##args)
> +#else
> +
> +#define PMD_DRV_LOG(...)  do { } while (0) #define
> +PMD_INIT_FUNC_TRACE() do { } while (0) #endif
> +
> +#ifdef RTE_LIBRTE_PMD_CPT_DEBUG_RX
> +
> +#define CPT_DEBUG
> +#define CPTVF_STRICT_PARAM_CHECK
> +#define PMD_RX_LOG(level, args...) \
> +	PMD_DRV_LOG_RAW(level, ##args)
> +#else
> +
> +#define PMD_RX_LOG(...)  do { } while (0) #endif
> +
> +#ifdef RTE_LIBRTE_PMD_CPT_DEBUG_TX
> +
> +#define CPT_DEBUG
> +#define CPTVF_STRICT_PARAM_CHECK
> +
> +#define PMD_TX_LOG(level, args...) \
> +	PMD_DRV_LOG_RAW(level, ##args)
> +#else
> +
> +#define PMD_TX_LOG(...)  do { } while (0) #endif
> +
> +#define PRINT printf
> +
> +#endif
> --
> 1.9.3

As already said in another commit, use dynamic logging
and try to remove the compilation flags.

Thanks,
Pablo

[dpdk-dev] [PATCH 11/16] crypto/cpt: add the basic device callback functions

[Anoob Joseph]

From: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>

This patch addresses the following:
1. Adds the basic device operation functions for the cpt vf.
2. The probe/remove functions are staic so no need to declare in
the header file.
3. Removing extra declaration for cpt_dev_periodic_alarm_stop in the
header file.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/Makefile            |   1 +
 drivers/crypto/cpt/cpt_pmd_cryptodev.c |  13 +-
 drivers/crypto/cpt/cpt_pmd_ops.c       | 544 +++++++++++++++++++++++++++++++++
 drivers/crypto/cpt/cpt_pmd_ops.h       |  64 ++++
 4 files changed, 616 insertions(+), 6 deletions(-)
 create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.c
 create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.h

diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile
index 40ec9e2..bf22c2b 100644
--- a/drivers/crypto/cpt/Makefile
+++ b/drivers/crypto/cpt/Makefile
@@ -25,6 +25,7 @@ CFLAGS += -O3
 
 # PMD code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_ops.c
 
 # Base code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_device.c
diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
index addddd8..3939b5e 100644
--- a/drivers/crypto/cpt/cpt_pmd_cryptodev.c
+++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
@@ -13,6 +13,7 @@
 
 #include "base/cpt_device.h"
 #include "cpt_pmd_logs.h"
+#include "cpt_pmd_ops.h"
 
 #define CSP_INTR_POLL_INTERVAL_MS 50
 
@@ -38,7 +39,7 @@
 				 cpt_pmd_alarm_cb, arg);
 }
 
-static int
+int
 cpt_pmd_periodic_alarm_stop(void *arg)
 {
 	return rte_eal_alarm_cancel(cpt_pmd_alarm_cb, arg);
@@ -46,11 +47,11 @@
 
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
-	.dev_configure = NULL,
-	.dev_start = NULL,
-	.dev_stop = NULL,
-	.dev_close = NULL,
-	.dev_infos_get = NULL,
+	.dev_configure = cpt_pmd_dev_config,
+	.dev_start = cpt_pmd_dev_start,
+	.dev_stop = cpt_pmd_dev_stop,
+	.dev_close = cpt_pmd_dev_close,
+	.dev_infos_get = cptvf_dev_info_get,
 
 	.stats_get = NULL,
 	.stats_reset = NULL,
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.c b/drivers/crypto/cpt/cpt_pmd_ops.c
new file mode 100644
index 0000000..2f066cb
--- /dev/null
+++ b/drivers/crypto/cpt/cpt_pmd_ops.c
@@ -0,0 +1,544 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include <rte_cryptodev_pmd.h>
+#include <rte_crypto.h>
+#include <rte_bus_pci.h>
+
+#include "cpt_pmd_logs.h"
+#include "cpt_pmd_ops.h"
+#include "base/cpt.h"
+#include "base/cpt_device.h"
+
+struct cpt_sess_misc {
+	uint16_t cpt_op:4;
+	uint16_t zsk_flag:4;
+	uint16_t aes_gcm:1;
+	uint16_t aes_ctr:1;
+	uint16_t dir_dma_supp:1; /* Single frag DMA supported? */
+	uint16_t is_gmac:1;
+	uint16_t aad_length;
+	uint8_t mac_len;
+	uint8_t iv_length; /**< IV length in bytes */
+	uint8_t auth_iv_length; /**< Auth IV length in bytes */
+	uint8_t rsvd1;
+	uint16_t iv_offset; /**< IV offset in bytes */
+	uint16_t auth_iv_offset; /**< Auth IV offset in bytes */
+	uint32_t salt;
+	phys_addr_t ctx_dma_addr;
+};
+
+/* Helper macros */
+
+#define SRC_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * MAX_SG_CNT))
+#define DST_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * MAX_SG_CNT))
+
+#define SESS_PRIV(__sess) \
+	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
+
+#define BYTE_LEN 8
+
+/* #define CPT_ALWAYS_USE_SG_MODE */
+#define CPT_ALWAYS_USE_SEPARATE_BUF
+
+/* TODO: Add all other capabilities */
+static const struct rte_cryptodev_capabilities cpt_capabilities[] = {
+	{	/* SHA1 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 20,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* SHA224 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
+				.block_size = 64,
+					.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 28,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* SHA256 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 32,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* SHA384 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 48,
+					.increment = 1
+					},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* SHA512 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
+				.block_size = 128,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 64,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* MD5 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 8,
+					.max = 64,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 16,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* AES GCM */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+			{.aead = {
+				.algo = RTE_CRYPTO_AEAD_AES_GCM,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
+				},
+				.aad_size = {
+					.min = 0,
+					.max = 1024,
+					.increment = 1
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 12,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES GMAC (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_AES_GMAC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
+				},
+				.aad_size = {
+					.min = 1,
+					.max = 65535,
+					.increment = 1
+				}
+			}, }
+		}, }
+	},
+	{	/* SNOW 3G (UIA2) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.aad_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CBC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* SNOW 3G (UEA2) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES CTR */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CTR,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* NULL (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.aad_size = { 0 }
+			}, },
+		}, },
+	},
+	{	/* NULL (CIPHER) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				}
+			}, },
+		}, }
+	},
+	{       /* KASUMI (F8) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
+				.block_size = 8,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* ZUC (EIA3) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.aad_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* ZUC (EEA3) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{       /* KASUMI (F9) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_KASUMI_F9,
+				.block_size = 8,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.aad_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* 3DES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+				.block_size = 8,
+				.key_size = {
+					.min = 24,
+					.max = 24,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 8
+				}
+			}, }
+		}, }
+	},
+	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+int cpt_pmd_dev_config(struct rte_cryptodev *dev __rte_unused,
+		   struct rte_cryptodev_config *config __rte_unused)
+{
+	PMD_INIT_FUNC_TRACE();
+	return 0;
+}
+
+int cpt_pmd_dev_start(struct rte_cryptodev *c_dev __rte_unused)
+{
+	struct cpt_vf *cptvf = c_dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+
+	return cptvf_start_device(cptvf);
+}
+
+void cpt_pmd_dev_stop(struct rte_cryptodev *c_dev __rte_unused)
+{
+	struct cpt_vf *cptvf = c_dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+
+	cptvf_stop_device(cptvf);
+}
+
+int cpt_pmd_dev_close(struct rte_cryptodev *c_dev)
+{
+	struct cpt_vf *cptvf = c_dev->data->dev_private;
+	int i, ret;
+
+	PMD_INIT_FUNC_TRACE();
+
+	for (i = 0; i < c_dev->data->nb_queue_pairs; i++) {
+		ret = cpt_pmd_que_pair_release(c_dev, i);
+		if (ret)
+			return ret;
+	}
+	cpt_pmd_periodic_alarm_stop(cptvf);
+	cptvf_deinit_device(cptvf);
+
+	return 0;
+}
+
+void
+cptvf_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info)
+{
+	PMD_INIT_FUNC_TRACE();
+	if (info != NULL) {
+		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
+		info->feature_flags = dev->feature_flags;
+		info->capabilities = cpt_capabilities;
+		/* TODO: Hardcoding as of now */
+		info->sym.max_nb_sessions = 128;
+		info->driver_id = cryptodev_cpt_driver_id;
+	}
+}
+
+int
+cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)
+{
+	cpt_instance_t *instance = dev->data->queue_pairs[que_pair_id];
+	int ret;
+
+	PMD_INIT_FUNC_TRACE();
+
+	ret = cptvf_put_resource(instance);
+	if (ret != 0) {
+		PMD_DRV_LOG(ERR, "Error putting instance handle"
+			    " of device %s : ret = %d\n", dev->data->name, ret);
+		return ret;
+	}
+
+	dev->data->queue_pairs[que_pair_id] = NULL;
+
+	return 0;
+}
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.h b/drivers/crypto/cpt/cpt_pmd_ops.h
new file mode 100644
index 0000000..015b4a2
--- /dev/null
+++ b/drivers/crypto/cpt/cpt_pmd_ops.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __CPT_PMD_OPS_H_
+#define __CPT_PMD_OPS_H_
+
+#include "base/cpt.h"
+
+#define CAVIUM_VENDOR_ID       0x177d
+#define NITROXIII_DEV_ID       0x11
+
+#define CSP_OP_CIPHER_ENCRYPT	0x1
+#define CSP_OP_CIPHER_DECRYPT	0x2
+#define CSP_OP_CIPHER_MASK	0x3
+
+#define CSP_OP_AUTH_VERIFY	0x4
+#define CSP_OP_AUTH_GENERATE	0x8
+#define CSP_OP_AUTH_MASK	0xC
+
+#define CSP_OP_ENCODE	(CSP_OP_CIPHER_ENCRYPT | CSP_OP_AUTH_GENERATE)
+#define CSP_OP_DECODE	(CSP_OP_CIPHER_DECRYPT | CSP_OP_AUTH_VERIFY)
+
+#define MAX_CIPHER_KEY_LEN  32
+#define MAX_AUTH_KEY_LEN    32
+#define DEFAULT_BLOCK_SIZE      64
+
+#define CSP_DDMA_AUTH		(1 << 1)
+#define CSP_DDMA_ENC		(1 << 2)
+#define CSP_DDMA_SUPPORTED	(CSP_DDMA_AUTH | CSP_DDMA_ENC)
+
+/*
+ * Space needed in packet for direct-dma operation.
+ * UCODE result & padding - 16 bytes max
+ * Result -  16 bytes
+ * struct cb_info size
+ */
+#define CSP_DDMA_EXTRA_SPACE (32 + sizeof(struct cpt_cb_info))
+
+#define ZS_EA 0x1
+#define ZS_IA 0x2
+#define K_F8 0x4
+#define K_F9 0x8
+
+extern uint8_t cryptodev_cpt_driver_id;
+extern int cpt_pmd_periodic_alarm_stop(void *arg);
+extern struct rte_mempool *cpt_meta_pool;
+extern int cpt_op_mlen;
+extern int cpt_op_sb_mlen;
+
+int cpt_pmd_dev_config(struct rte_cryptodev *dev __rte_unused,
+		   struct rte_cryptodev_config *config __rte_unused);
+int cpt_pmd_dev_start(struct rte_cryptodev *dev);
+
+void cpt_pmd_dev_stop(struct rte_cryptodev *dev);
+
+int cpt_pmd_dev_close(struct rte_cryptodev *dev);
+
+void cptvf_dev_info_get(struct rte_cryptodev *dev,
+			  struct rte_cryptodev_info *inf);
+
+int cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id);
+
+#endif
-- 
1.9.3

Re: [dpdk-dev] [PATCH 11/16] crypto/cpt: add the basic device callback functions

[De Lara Guarch, Pablo]

> -----Original Message-----
> From: Anoob Joseph [mailto:anoob.joseph@caviumnetworks.com]
> Sent: Friday, June 8, 2018 5:45 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Thomas Monjalon <thomas@monjalon.net>
> Cc: Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; Ankur Dwivedi
> <ankur.dwivedi@cavium.com>; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>; dev@dpdk.org
> Subject: [PATCH 11/16] crypto/cpt: add the basic device callback functions
> 
> From: Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>
> 
> This patch addresses the following:
> 1. Adds the basic device operation functions for the cpt vf.
> 2. The probe/remove functions are staic so no need to declare in the header file.
> 3. Removing extra declaration for cpt_dev_periodic_alarm_stop in the header
> file.
> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>
> ---
>  drivers/crypto/cpt/Makefile            |   1 +
>  drivers/crypto/cpt/cpt_pmd_cryptodev.c |  13 +-
>  drivers/crypto/cpt/cpt_pmd_ops.c       | 544
> +++++++++++++++++++++++++++++++++
>  drivers/crypto/cpt/cpt_pmd_ops.h       |  64 ++++
>  4 files changed, 616 insertions(+), 6 deletions(-)  create mode 100644
> drivers/crypto/cpt/cpt_pmd_ops.c  create mode 100644
> drivers/crypto/cpt/cpt_pmd_ops.h
> 
> diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile index
> 40ec9e2..bf22c2b 100644

...

> +++ b/drivers/crypto/cpt/cpt_pmd_ops.c
> @@ -0,0 +1,544 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2017 Cavium, Inc
> + */
> +
> +#include <rte_cryptodev_pmd.h>
> +#include <rte_crypto.h>
> +#include <rte_bus_pci.h>
> +
> +#include "cpt_pmd_logs.h"
> +#include "cpt_pmd_ops.h"
> +#include "base/cpt.h"
> +#include "base/cpt_device.h"
> +
> +struct cpt_sess_misc {
> +	uint16_t cpt_op:4;
> +	uint16_t zsk_flag:4;
> +	uint16_t aes_gcm:1;
> +	uint16_t aes_ctr:1;
> +	uint16_t dir_dma_supp:1; /* Single frag DMA supported? */
> +	uint16_t is_gmac:1;
> +	uint16_t aad_length;
> +	uint8_t mac_len;
> +	uint8_t iv_length; /**< IV length in bytes */
> +	uint8_t auth_iv_length; /**< Auth IV length in bytes */
> +	uint8_t rsvd1;
> +	uint16_t iv_offset; /**< IV offset in bytes */
> +	uint16_t auth_iv_offset; /**< Auth IV offset in bytes */
> +	uint32_t salt;
> +	phys_addr_t ctx_dma_addr;
> +};
> +
> +/* Helper macros */
> +
> +#define SRC_IOV_SIZE \
> +	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * MAX_SG_CNT)) #define
> +DST_IOV_SIZE \
> +	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * MAX_SG_CNT))
> +
> +#define SESS_PRIV(__sess) \
> +	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
> +
> +#define BYTE_LEN 8
> +
> +/* #define CPT_ALWAYS_USE_SG_MODE */
> +#define CPT_ALWAYS_USE_SEPARATE_BUF
> +
> +/* TODO: Add all other capabilities */
> +static const struct rte_cryptodev_capabilities cpt_capabilities[] = {
> +	{	/* SHA1 HMAC */
> +		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> +		{.sym = {
> +			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> +			{.auth = {
> +				.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
> +				.block_size = 64,
> +				.key_size = {
> +					.min = 64,
> +					.max = 64,
> +					.increment = 0
> +				},
> +				.digest_size = {
> +					.min = 1,
> +					.max = 20,
> +					.increment = 1
> +				},
> +				.aad_size = { 0 }

Aad_size is not needed for authentication only algorithm, so it can be removed from these ones.
Unfortunately, it was left in the capabilities and to avoid breaking the API, it won't be removed
for the moment.

...

> +	{	/* AES GMAC (AUTH) */
> +		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> +		{.sym = {
> +			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> +			{.auth = {
> +				.algo = RTE_CRYPTO_AUTH_AES_GMAC,
> +				.block_size = 16,
> +				.key_size = {
> +					.min = 16,
> +					.max = 32,
> +					.increment = 8
> +				},
> +				.digest_size = {
> +					.min = 8,
> +					.max = 16,
> +					.increment = 4
> +				},
> +				.aad_size = {
> +					.min = 1,
> +					.max = 65535,
> +					.increment = 1
> +				}

GMAC does not use AAD. All the message is passing in m_src.

> +			}, }
> +		}, }
> +	},
> +	{	/* SNOW 3G (UIA2) */
> +		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> +		{.sym = {
> +			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> +			{.auth = {
> +				.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
> +				.block_size = 16,
> +				.key_size = {
> +					.min = 16,
> +					.max = 16,
> +					.increment = 0
> +				},
> +				.digest_size = {
> +					.min = 4,
> +					.max = 4,
> +					.increment = 0
> +				},
> +				.aad_size = {
> +					.min = 16,
> +					.max = 16,
> +					.increment = 0
> +				}

AAD is not used in SNOW3G/ZUC/KASUMI algorithms.

...

> +void
> +cptvf_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info
> +*info) {
> +	PMD_INIT_FUNC_TRACE();
> +	if (info != NULL) {
> +		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
> +		info->feature_flags = dev->feature_flags;
> +		info->capabilities = cpt_capabilities;
> +		/* TODO: Hardcoding as of now */
> +		info->sym.max_nb_sessions = 128;

Looks like "max_nb_sessions" will remain and if the PMD has no limitation, it should be set to 0.
Watch out for these series http://patches.dpdk.org/user/todo/dpdk/?series=70.

> +		info->driver_id = cryptodev_cpt_driver_id;

[dpdk-dev] [PATCH 12/16] crypto/cpt: adds some more callback functions for CPT

[Anoob Joseph]

From: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>

This patch does the following:
1. Adds the stats callback functions for the cpt vf.
2. Adds the queue pair setup and queue pair release callback
functions for cpt vf.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/cpt_pmd_cryptodev.c |  8 ++---
 drivers/crypto/cpt/cpt_pmd_ops.c       | 63 ++++++++++++++++++++++++++++++++++
 drivers/crypto/cpt/cpt_pmd_ops.h       | 11 ++++++
 3 files changed, 78 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
index 3939b5e..3961ec8 100644
--- a/drivers/crypto/cpt/cpt_pmd_cryptodev.c
+++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
@@ -53,10 +53,10 @@
 	.dev_close = cpt_pmd_dev_close,
 	.dev_infos_get = cptvf_dev_info_get,
 
-	.stats_get = NULL,
-	.stats_reset = NULL,
-	.queue_pair_setup = NULL,
-	.queue_pair_release = NULL,
+	.stats_get = cpt_pmd_stats_get,
+	.stats_reset = cpt_pmd_stats_reset,
+	.queue_pair_setup = cpt_pmd_que_pair_setup,
+	.queue_pair_release = cpt_pmd_que_pair_release,
 	.queue_pair_start = NULL,
 	.queue_pair_stop = NULL,
 	.queue_pair_count = NULL,
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.c b/drivers/crypto/cpt/cpt_pmd_ops.c
index 2f066cb..1c60191 100644
--- a/drivers/crypto/cpt/cpt_pmd_ops.c
+++ b/drivers/crypto/cpt/cpt_pmd_ops.c
@@ -523,6 +523,69 @@ int cpt_pmd_dev_close(struct rte_cryptodev *c_dev)
 	}
 }
 
+void
+cpt_pmd_stats_get(struct rte_cryptodev *dev __rte_unused,
+		  struct rte_cryptodev_stats *stats __rte_unused)
+{
+	PMD_INIT_FUNC_TRACE();
+}
+
+void cpt_pmd_stats_reset(struct rte_cryptodev *dev __rte_unused)
+{
+	PMD_INIT_FUNC_TRACE();
+}
+
+int
+cpt_pmd_que_pair_setup(struct rte_cryptodev *dev,
+		       uint16_t que_pair_id,
+		       const struct rte_cryptodev_qp_conf *qp_conf,
+		       int socket_id __rte_unused,
+		       struct rte_mempool *session_pool __rte_unused)
+{
+	struct cpt_vf *cptvf = dev->data->dev_private;
+	cpt_instance_t *instance = NULL;
+	struct rte_pci_device *pci_dev;
+	int ret = -1;
+
+	PMD_INIT_FUNC_TRACE();
+
+	if (dev->data->queue_pairs[que_pair_id] != NULL) {
+		ret = cpt_pmd_que_pair_release(dev, que_pair_id);
+		if (ret)
+			return ret;
+	}
+
+	if (qp_conf->nb_descriptors > DEFAULT_CMD_QLEN) {
+		PMD_DRV_LOG(INFO, "Number of descriptors too big %d,"
+			    " using default queue length of %d\n",
+			    qp_conf->nb_descriptors, DEFAULT_CMD_QLEN);
+	}
+
+	pci_dev = RTE_DEV_TO_PCI(dev->device);
+
+	if (pci_dev->mem_resource[0].addr == NULL) {
+		PMD_DRV_LOG(ERR, "PCI mem address null");
+		return -EIO;
+	}
+
+	/*
+	 * FIXME: We always setup a queue with DEFAULT_CMD_QLEN size
+	 * in get_hw_resource.
+	 */
+	ret = cptvf_get_resource(cptvf, 0, &instance);
+	if (ret != 0) {
+		PMD_DRV_LOG(ERR, "Error getting instance handle"
+				" from device %s : ret = %d\n",
+				dev->data->name, ret);
+		return ret;
+	}
+
+	instance->queue_id = que_pair_id;
+	dev->data->queue_pairs[que_pair_id] = instance;
+
+	return 0;
+}
+
 int
 cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)
 {
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.h b/drivers/crypto/cpt/cpt_pmd_ops.h
index 015b4a2..db2024b 100644
--- a/drivers/crypto/cpt/cpt_pmd_ops.h
+++ b/drivers/crypto/cpt/cpt_pmd_ops.h
@@ -58,7 +58,18 @@ int cpt_pmd_dev_config(struct rte_cryptodev *dev __rte_unused,
 
 void cptvf_dev_info_get(struct rte_cryptodev *dev,
 			  struct rte_cryptodev_info *inf);
+int
+cpt_pmd_que_pair_setup(struct rte_cryptodev *dev,
+		   uint16_t que_pair_id,
+		   const struct rte_cryptodev_qp_conf *qp_conf,
+		   int socket_id,
+		   struct rte_mempool *session_pool);
 
 int cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id);
 
+void cpt_pmd_stats_get(struct rte_cryptodev *dev,
+		   struct rte_cryptodev_stats *stats);
+
+void cpt_pmd_stats_reset(struct rte_cryptodev *dev);
+
 #endif
-- 
1.9.3

[dpdk-dev] [PATCH 13/16] crypto/cpt: adds the session related function callbacks

[Anoob Joseph]

From: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>

This patch adds the session callbacks functions. The cipher
keys, auth keys and aead keys are set during the session configure.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/cpt_pmd_cryptodev.c |   6 +-
 drivers/crypto/cpt/cpt_pmd_ops.c       | 470 +++++++++++++++++++++++++++++++++
 drivers/crypto/cpt/cpt_pmd_ops.h       |  11 +
 3 files changed, 484 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
index 3961ec8..939f31b 100644
--- a/drivers/crypto/cpt/cpt_pmd_cryptodev.c
+++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
@@ -62,9 +62,9 @@
 	.queue_pair_count = NULL,
 
 	/* Crypto related operations */
-	.session_get_size = NULL,
-	.session_configure = NULL,
-	.session_clear = NULL
+	.session_get_size = cpt_pmd_get_session_size,
+	.session_configure = cpt_pmd_session_cfg,
+	.session_clear = cpt_pmd_session_clear
 };
 
 static int init_global_resources(void)
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.c b/drivers/crypto/cpt/cpt_pmd_ops.c
index 1c60191..37808ce 100644
--- a/drivers/crypto/cpt/cpt_pmd_ops.c
+++ b/drivers/crypto/cpt/cpt_pmd_ops.c
@@ -605,3 +605,473 @@ void cpt_pmd_stats_reset(struct rte_cryptodev *dev __rte_unused)
 
 	return 0;
 }
+
+unsigned int
+cpt_pmd_get_session_size(struct rte_cryptodev *dev __rte_unused)
+{
+	return (sizeof(struct cpt_sess_misc) +
+		RTE_ALIGN_CEIL(cpt_fc_get_ctx_len(), 8));
+}
+
+static int
+fill_sess_aead(cpt_instance_t *instance, struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_aead_xform *aead_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint32_t cipher_key_len = 0;
+	uint8_t zsk_flag = 0, aes_gcm = 0;
+	aead_form = &xform->aead;
+	if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
+	   aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+		sess->cpt_op |= CSP_OP_CIPHER_ENCRYPT;
+		sess->cpt_op |= CSP_OP_AUTH_GENERATE;
+	} else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
+		aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+		sess->cpt_op |= CSP_OP_CIPHER_DECRYPT;
+		sess->cpt_op |= CSP_OP_AUTH_VERIFY;
+	} else {
+		PMD_DRV_LOG(ERR, "Unknown cipher operation\n");
+		return -1;
+	}
+	if (aead_form->key.length < cipher_key_len) {
+		PMD_DRV_LOG(ERR, "Invalid cipher params keylen %lu\n",
+		(unsigned int long)aead_form->key.length);
+		return -1;
+	}
+	switch (aead_form->algo) {
+	case RTE_CRYPTO_AEAD_AES_GCM:
+		enc_type = AES_GCM;
+		cipher_key_len = 16;
+		aes_gcm = 1;
+		break;
+	case RTE_CRYPTO_AEAD_AES_CCM:
+		PMD_DRV_LOG(ERR, "Crypto: Unsupported cipher alg %u",
+			    aead_form->algo);
+		return -1;
+	default:
+		PMD_DRV_LOG(ERR, "Crypto: Undefined cipher algo %u specified",
+			    aead_form->algo);
+		return -1;
+	}
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->mac_len = aead_form->digest_length;
+	sess->iv_offset = aead_form->iv.offset;
+	sess->iv_length = aead_form->iv.length;
+	sess->aad_length = aead_form->aad_length;
+	cpt_fc_ciph_set_key(instance,
+		(void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+			enc_type,
+			aead_form->key.data,
+			aead_form->key.length,
+			NULL);
+
+	cpt_fc_auth_set_key(instance,
+		(void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+		auth_type,
+		NULL,
+		0,
+		aead_form->digest_length);
+
+	return 0;
+}
+static int
+fill_sess_cipher(cpt_instance_t *instance, struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_cipher_xform *c_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	uint32_t cipher_key_len = 0;
+	uint8_t zsk_flag = 0, aes_gcm = 0, aes_ctr = 0;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER)
+		return -1;
+
+	c_form = &xform->cipher;
+
+	if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
+		sess->cpt_op |= CSP_OP_CIPHER_ENCRYPT;
+	else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
+		sess->cpt_op |= CSP_OP_CIPHER_DECRYPT;
+	else {
+		PMD_DRV_LOG(ERR, "Unknown cipher operation\n");
+		return -1;
+	}
+
+	switch (c_form->algo) {
+	case RTE_CRYPTO_CIPHER_AES_CBC:
+		enc_type = AES_CBC;
+		cipher_key_len = 16;
+		sess->dir_dma_supp |= CSP_DDMA_ENC;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CBC:
+		enc_type = DES3_CBC;
+		cipher_key_len = 24;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_CTR:
+		enc_type = AES_CTR;
+		cipher_key_len = 16;
+		aes_ctr = 1;
+		break;
+	case RTE_CRYPTO_CIPHER_NULL:
+		enc_type = 0;
+		break;
+	case RTE_CRYPTO_CIPHER_KASUMI_F8:
+		enc_type = KASUMI_F8_ECB;
+		cipher_key_len = 16;
+		zsk_flag = K_F8;
+		break;
+	case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
+		enc_type = SNOW3G_UEA2;
+		cipher_key_len = 16;
+		zsk_flag = ZS_EA;
+		break;
+	case RTE_CRYPTO_CIPHER_ZUC_EEA3:
+		enc_type = ZUC_EEA3;
+		cipher_key_len = 16;
+		zsk_flag = ZS_EA;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_XTS:
+		enc_type = AES_XTS;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_ECB:
+		enc_type = DES3_ECB;
+		cipher_key_len = 24;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_ECB:
+		enc_type = AES_ECB;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CTR:
+	case RTE_CRYPTO_CIPHER_AES_F8:
+	case RTE_CRYPTO_CIPHER_ARC4:
+		PMD_DRV_LOG(ERR, "Crypto: Unsupported cipher alg %u",
+			    c_form->algo);
+		return -1;
+	default:
+		PMD_DRV_LOG(ERR, "Crypto: Undefined cipher algo %u specified",
+			    c_form->algo);
+		return -1;
+	}
+
+	if (c_form->key.length < cipher_key_len) {
+		PMD_DRV_LOG(ERR, "Invalid cipher params keylen %lu\n",
+			    (unsigned long) c_form->key.length);
+		return -1;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->aes_ctr = aes_ctr;
+	sess->iv_offset = c_form->iv.offset;
+	sess->iv_length = c_form->iv.length;
+	cpt_fc_ciph_set_key(instance,
+			    SESS_PRIV(sess),
+			    enc_type,
+			    c_form->key.data,
+			    c_form->key.length,
+			    NULL);
+
+	return 0;
+}
+
+static int
+fill_sess_auth(cpt_instance_t *instance, struct rte_crypto_sym_xform *xform,
+	       struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_auth_xform *a_form;
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint8_t zsk_flag = 0, aes_gcm = 0;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
+		goto error_out;
+
+	a_form = &xform->auth;
+
+	if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
+		sess->cpt_op |= CSP_OP_AUTH_VERIFY;
+	else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
+		sess->cpt_op |= CSP_OP_AUTH_GENERATE;
+	else {
+		PMD_DRV_LOG(ERR, "Unknown auth operation\n");
+		return -1;
+	}
+
+	if (a_form->key.length > 64) {
+		PMD_DRV_LOG(ERR, "Auth key length is big\n");
+		return -1;
+	}
+
+	switch (a_form->algo) {
+	case RTE_CRYPTO_AUTH_SHA1_HMAC:
+		sess->dir_dma_supp |= CSP_DDMA_AUTH;
+		/* Fall through */
+	case RTE_CRYPTO_AUTH_SHA1:
+		auth_type = SHA1_TYPE;
+		break;
+	case RTE_CRYPTO_AUTH_SHA256_HMAC:
+	case RTE_CRYPTO_AUTH_SHA256:
+		auth_type = SHA2_SHA256;
+		break;
+	case RTE_CRYPTO_AUTH_SHA512_HMAC:
+	case RTE_CRYPTO_AUTH_SHA512:
+		auth_type = SHA2_SHA512;
+		break;
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		auth_type = GMAC_TYPE;
+		aes_gcm = 1;
+		break;
+	case RTE_CRYPTO_AUTH_SHA224_HMAC:
+	case RTE_CRYPTO_AUTH_SHA224:
+		auth_type = SHA2_SHA224;
+		break;
+	case RTE_CRYPTO_AUTH_SHA384_HMAC:
+	case RTE_CRYPTO_AUTH_SHA384:
+		auth_type = SHA2_SHA384;
+		break;
+	case RTE_CRYPTO_AUTH_MD5_HMAC:
+	case RTE_CRYPTO_AUTH_MD5:
+		auth_type = MD5_TYPE;
+		break;
+	case RTE_CRYPTO_AUTH_KASUMI_F9:
+		auth_type = KASUMI_F9_ECB;
+		/*
+		 * Indicate that direction needs to be taken out
+		 * from end of src
+		 */
+		zsk_flag = K_F9;
+		break;
+	case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
+		auth_type = SNOW3G_UIA2;
+		zsk_flag = ZS_IA;
+		break;
+	case RTE_CRYPTO_AUTH_ZUC_EIA3:
+		auth_type = ZUC_EIA3;
+		zsk_flag = ZS_IA;
+		break;
+	case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+	case RTE_CRYPTO_AUTH_AES_CMAC:
+	case RTE_CRYPTO_AUTH_AES_CBC_MAC:
+	case RTE_CRYPTO_AUTH_NULL:
+		PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
+			    a_form->algo);
+		goto error_out;
+	default:
+		PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
+			    a_form->algo);
+		goto error_out;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->mac_len = a_form->digest_length;
+	if (zsk_flag) {
+		sess->auth_iv_offset = a_form->iv.offset;
+		sess->auth_iv_length = a_form->iv.length;
+	}
+	cpt_fc_auth_set_key(instance,
+			    SESS_PRIV(sess),
+			    auth_type,
+			    a_form->key.data,
+			    a_form->key.length,
+			    a_form->digest_length);
+
+	return 0;
+
+error_out:
+	return -1;
+}
+static int
+fill_sess_gmac(cpt_instance_t *instance, struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_auth_xform *a_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint8_t zsk_flag = 0, aes_gcm = 0;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
+		return -1;
+
+	a_form = &xform->auth;
+
+	if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
+		sess->cpt_op |= CSP_OP_ENCODE;
+	else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
+		sess->cpt_op |= CSP_OP_DECODE;
+	else {
+		PMD_DRV_LOG(ERR, "Unknown auth operation\n");
+		return -1;
+	}
+
+	switch (a_form->algo) {
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		enc_type = AES_GCM;
+		auth_type = GMAC_TYPE;
+		break;
+	default:
+		PMD_DRV_LOG(ERR, "Crypto: Undefined cipher algo %u specified",
+			    a_form->algo);
+		return -1;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->is_gmac = 1;
+	sess->iv_offset = a_form->iv.offset;
+	sess->iv_length = a_form->iv.length;
+	sess->mac_len = a_form->digest_length;
+	cpt_fc_ciph_set_key(instance,
+		(void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+			enc_type,
+			a_form->key.data,
+			a_form->key.length,
+			NULL);
+	cpt_fc_auth_set_key(instance,
+		(void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+		auth_type,
+		NULL,
+		0,
+		a_form->digest_length);
+
+	return 0;
+}
+
+static void
+cpt_pmd_session_init(struct rte_mempool *mp __rte_unused, void *sym_sess,
+		 uint8_t driver_id)
+{
+	struct rte_cryptodev_sym_session *sess = sym_sess;
+	struct cpt_sess_misc *cpt_sess =
+	  (struct cpt_sess_misc *) get_session_private_data(sess, driver_id);
+
+	PMD_INIT_FUNC_TRACE();
+	cpt_sess->ctx_dma_addr = rte_mempool_virt2iova(cpt_sess) +
+			sizeof(struct cpt_sess_misc);
+}
+
+
+int cpt_pmd_session_cfg(struct rte_cryptodev *dev,
+		    struct rte_crypto_sym_xform *xform,
+		    struct rte_cryptodev_sym_session *sess,
+		    struct rte_mempool *mempool)
+{
+	struct rte_crypto_sym_xform *chain;
+	void *sess_private_data;
+
+	PMD_INIT_FUNC_TRACE();
+
+	/*
+	 * Microcode only supports the following combination.
+	 * Encryption followed by authentication
+	 * Authentication followed by decryption
+	 * Also zuc, kasumi and snow3g are not supported in
+	 * aead mode(ie. cipher+auth), but only cipher or auth.
+	 */
+	if (xform->next) {
+		if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
+			if ((xform->auth.algo == RTE_CRYPTO_AUTH_SNOW3G_UIA2) ||
+			    (xform->auth.algo == RTE_CRYPTO_AUTH_ZUC_EIA3) ||
+			    (xform->auth.algo == RTE_CRYPTO_AUTH_KASUMI_F9)) {
+				PMD_DRV_LOG(ERR, "Requested auth algorithm in "
+				 "combination with cipher unsupported\n");
+				goto err;
+			}
+			if ((xform->next->type ==
+			     RTE_CRYPTO_SYM_XFORM_CIPHER) &&
+			    (xform->next->cipher.op ==
+			     RTE_CRYPTO_CIPHER_OP_ENCRYPT)) {
+				PMD_DRV_LOG(ERR, "Unsupported combination by "
+				 "microcode\n");
+				goto err;
+				/* Unsupported as of now by microcode */
+			}
+		}
+		if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
+			if ((xform->cipher.algo ==
+			     RTE_CRYPTO_CIPHER_SNOW3G_UEA2) ||
+			    (xform->cipher.algo ==
+			     RTE_CRYPTO_CIPHER_ZUC_EEA3) ||
+			    (xform->cipher.algo ==
+			     RTE_CRYPTO_CIPHER_KASUMI_F8)) {
+				PMD_DRV_LOG(ERR, "Requested cipher algorithm "
+				 "in combination with auth unsupported\n");
+				goto err;
+			}
+			if ((xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
+			(xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)) {
+				/* For GMAC auth there is no cipher operation */
+				if ((xform->aead.algo !=
+				     RTE_CRYPTO_AEAD_AES_GCM) ||
+				    (xform->next->auth.algo !=
+				     RTE_CRYPTO_AUTH_AES_GMAC)) {
+					PMD_DRV_LOG(ERR, "Unsupported "
+					 "combination by microcode\n");
+					goto err;
+					/* Unsupported as of now by microcode */
+				}
+			}
+		}
+	}
+
+	if (unlikely(sess == NULL)) {
+		PMD_DRV_LOG(ERR, "invalid session struct");
+		return -EINVAL;
+	}
+
+	if (rte_mempool_get(mempool, &sess_private_data)) {
+		PMD_DRV_LOG(ERR, "Could not allocate sess_private_data\n");
+		return -ENOMEM;
+	}
+
+	chain = xform;
+	((struct cpt_sess_misc *) sess_private_data)->dir_dma_supp = 0;
+	/* TODO: Need to restrict this loop to 2 chain elements? */
+	while (chain) {
+		if (chain->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
+			if (fill_sess_aead(NULL, chain, sess_private_data))
+				goto err;
+		} else {
+		if (chain->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
+			if (fill_sess_cipher(NULL, chain, sess_private_data))
+				goto err;
+		} else if (chain->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
+			if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
+				if (fill_sess_gmac(NULL, chain,
+				    sess_private_data))
+					goto err;
+			} else {
+			if (fill_sess_auth(NULL, chain, sess_private_data))
+				goto err;
+			}
+		}
+		}
+		chain = chain->next;
+	}
+	set_session_private_data(sess, dev->driver_id, sess_private_data);
+	cpt_pmd_session_init(NULL, sess, dev->driver_id);
+	return 0;
+
+err:
+	/* TODO: rte_mempool_put(); */
+	return -EPERM;
+}
+
+void
+cpt_pmd_session_clear(struct rte_cryptodev *dev,
+		  struct rte_cryptodev_sym_session *sess)
+{
+	void *session_private = get_session_private_data(sess, dev->driver_id);
+
+	PMD_INIT_FUNC_TRACE();
+	if (session_private) {
+		memset(session_private, 0, cpt_pmd_get_session_size(dev));
+		struct rte_mempool *sess_mp =
+		   rte_mempool_from_obj(session_private);
+		set_session_private_data(sess, dev->driver_id, NULL);
+		rte_mempool_put(sess_mp, session_private);
+	}
+}
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.h b/drivers/crypto/cpt/cpt_pmd_ops.h
index db2024b..314b2b1 100644
--- a/drivers/crypto/cpt/cpt_pmd_ops.h
+++ b/drivers/crypto/cpt/cpt_pmd_ops.h
@@ -72,4 +72,15 @@ void cpt_pmd_stats_get(struct rte_cryptodev *dev,
 
 void cpt_pmd_stats_reset(struct rte_cryptodev *dev);
 
+unsigned int
+cpt_pmd_get_session_size(struct rte_cryptodev *dev);
+
+int cpt_pmd_session_cfg(struct rte_cryptodev *dev,
+		    struct rte_crypto_sym_xform *xform,
+		    struct rte_cryptodev_sym_session *sess,
+		    struct rte_mempool *mempool);
+
+void
+cpt_pmd_session_clear(struct rte_cryptodev *dev,
+		  struct rte_cryptodev_sym_session *sess);
 #endif
-- 
1.9.3

[dpdk-dev] [PATCH 14/16] crypto/cpt: adds the enqueue and dequeue callbacks

[Anoob Joseph]

From: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>

The functions present in cpt_request_mgr.c manages the work of
enqueing/dequeing the request/response to/from cpt hardware unit.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/Makefile            |   1 +
 drivers/crypto/cpt/cpt_pmd_cryptodev.c |   4 +-
 drivers/crypto/cpt/cpt_pmd_ops.c       | 859 +++++++++++++++++++++++++++++++++
 drivers/crypto/cpt/cpt_pmd_ops.h       |  10 +
 4 files changed, 872 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile
index bf22c2b..63553e0 100644
--- a/drivers/crypto/cpt/Makefile
+++ b/drivers/crypto/cpt/Makefile
@@ -29,6 +29,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_ops.c
 
 # Base code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_device.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_request_mgr.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_ops.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt8xxx_device.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_vf_mbox.c
diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
index 939f31b..45e052f 100644
--- a/drivers/crypto/cpt/cpt_pmd_cryptodev.c
+++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
@@ -137,8 +137,8 @@ static int init_global_resources(void)
 
 	c_dev->dev_ops = &cptvf_ops;
 
-	c_dev->enqueue_burst = NULL;
-	c_dev->dequeue_burst = NULL;
+	c_dev->enqueue_burst = cpt_pmd_pkt_enqueue;
+	c_dev->dequeue_burst = cpt_pmd_pkt_dequeue;
 
 	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
 			RTE_CRYPTODEV_FF_HW_ACCELERATED |
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.c b/drivers/crypto/cpt/cpt_pmd_ops.c
index 37808ce..d10caf5 100644
--- a/drivers/crypto/cpt/cpt_pmd_ops.c
+++ b/drivers/crypto/cpt/cpt_pmd_ops.c
@@ -1060,6 +1060,70 @@ int cpt_pmd_session_cfg(struct rte_cryptodev *dev,
 	return -EPERM;
 }
 
+static void *instance_session_cfg(cpt_instance_t *instance,
+			  struct rte_crypto_sym_xform *xform, void *sess)
+{
+	struct rte_crypto_sym_xform *chain;
+
+	PMD_INIT_FUNC_TRACE();
+
+	/*
+	 * Microcode only supports the following combination.
+	 * Encryption followed by authentication
+	 * Authentication followed by decryption
+	 */
+	if (xform->next) {
+		if ((xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
+		    (xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
+		    (xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)) {
+			PMD_DRV_LOG(ERR, "Unsupported combination by "
+					 "microcode\n");
+			goto err;
+			/* Unsupported as of now by microcode */
+		}
+		if ((xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
+		    (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
+		    (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)) {
+			/* For GMAC auth there is no cipher operation */
+			if (xform->aead.algo != RTE_CRYPTO_AEAD_AES_GCM ||
+			    xform->next->auth.algo !=
+			    RTE_CRYPTO_AUTH_AES_GMAC) {
+				PMD_DRV_LOG(ERR, "Unsupported combination by "
+					    "microcode\n");
+				goto err;
+				/* Unsupported as of now by microcode */
+			}
+		}
+	}
+
+	chain = xform;
+	while (chain) {
+		if (chain->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
+			if (fill_sess_aead(instance, chain, sess))
+				goto err;
+		} else {
+		if (chain->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
+			if (fill_sess_cipher(instance, chain, sess))
+				goto err;
+		} else if (chain->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
+			if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
+				if (fill_sess_gmac(NULL, chain, sess))
+					goto err;
+			} else {
+				if (fill_sess_auth(instance, chain, sess))
+					goto err;
+			}
+		}
+		}
+		chain = chain->next;
+	}
+
+	return sess;
+
+err:
+	return NULL;
+}
+
 void
 cpt_pmd_session_clear(struct rte_cryptodev *dev,
 		  struct rte_cryptodev_sym_session *sess)
@@ -1075,3 +1139,798 @@ int cpt_pmd_session_cfg(struct rte_cryptodev *dev,
 		rte_mempool_put(sess_mp, session_private);
 	}
 }
+
+static inline void *
+alloc_op_meta(struct rte_mbuf *m_src,
+	      buf_ptr_t *buf,
+	      int32_t len)
+{
+	uint8_t *mdata;
+
+#ifndef CPT_ALWAYS_USE_SEPARATE_BUF
+	if (likely(m_src && (m_src->nb_segs == 1))) {
+		int32_t tailroom;
+		phys_addr_t mphys;
+
+		/* Check if tailroom is sufficient to hold meta data */
+		tailroom = rte_pktmbuf_tailroom(m_src);
+		if (likely(tailroom > len + 8)) {
+			mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;
+			mphys = m_src->buf_physaddr + m_src->buf_len;
+			mdata -= len;
+			mphys -= len;
+			buf->vaddr = mdata;
+			buf->dma_addr = mphys;
+			buf->size = len;
+			/* Indicate that this is a mbuf allocated mdata */
+			mdata = (uint8_t *)((uint64_t)mdata | 1ull);
+			return mdata;
+		}
+	}
+#else
+	(void) m_src;
+#endif
+
+	if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))
+		return NULL;
+
+	buf->vaddr = mdata;
+	buf->dma_addr = rte_mempool_virt2iova(mdata);
+	buf->size = len;
+
+	return mdata;
+}
+
+/**
+ * cpt_free_metabuf - free metabuf to mempool.
+ * @param instance: pointer to instance.
+ * @param objp: pointer to the metabuf.
+ */
+static inline void free_op_meta(void *mdata)
+{
+	bool nofree = ((uint64_t)mdata & 1ull);
+
+	if (likely(nofree))
+		return;
+	rte_mempool_put(cpt_meta_pool, mdata);
+}
+
+static inline uint32_t
+prepare_iov_from_pkt(struct rte_mbuf *pkt,
+		     iov_ptr_t *iovec, uint32_t start_offset)
+{
+	uint16_t index = 0;
+	void *seg_data = NULL;
+	phys_addr_t seg_phys;
+	int32_t seg_size = 0;
+
+	if (!pkt) {
+		iovec->buf_cnt = 0;
+		return 0;
+	}
+
+	if (!start_offset) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+	} else {
+		while (start_offset >= pkt->data_len) {
+			start_offset -= pkt->data_len;
+			pkt = pkt->next;
+		}
+
+		seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);
+		seg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset);
+		seg_size = pkt->data_len - start_offset;
+		if (!seg_size)
+			return 1;
+	}
+
+	/* first seg */
+	iovec->bufs[index].vaddr = seg_data;
+	iovec->bufs[index].dma_addr = seg_phys;
+	iovec->bufs[index].size = seg_size;
+	index++;
+	pkt = pkt->next;
+
+	while (unlikely(pkt != NULL)) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+		if (!seg_size)
+			break;
+
+		iovec->bufs[index].vaddr = seg_data;
+		iovec->bufs[index].dma_addr = seg_phys;
+		iovec->bufs[index].size = seg_size;
+
+		index++;
+
+		/* FIXME: Not depending on wqe.w0.s.bufs to break */
+		pkt = pkt->next;
+	}
+
+	iovec->buf_cnt = index;
+	return 0;
+}
+
+static inline uint32_t
+prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,
+			     fc_params_t *param,
+			     uint32_t *flags)
+{
+	uint16_t index = 0;
+	void *seg_data = NULL;
+	phys_addr_t seg_phys;
+	uint32_t seg_size = 0;
+	iov_ptr_t *iovec;
+
+	seg_data = rte_pktmbuf_mtod(pkt, void *);
+	seg_phys = rte_pktmbuf_mtophys(pkt);
+	seg_size = pkt->data_len;
+
+	/* first seg */
+	if (likely(!pkt->next)) {
+		uint32_t headroom, tailroom;
+
+		*flags |= SINGLE_BUF_INPLACE;
+		headroom = rte_pktmbuf_headroom(pkt);
+		tailroom = rte_pktmbuf_tailroom(pkt);
+		if (likely((headroom >= 24) &&
+		    (tailroom >= 8))) {
+			/* In 83XX this is prerequivisit for Direct mode */
+			*flags |= SINGLE_BUF_HEADTAILROOM;
+		}
+		param->bufs[0].vaddr = seg_data;
+		param->bufs[0].dma_addr = seg_phys;
+		param->bufs[0].size = seg_size;
+		return 0;
+	}
+	iovec = param->src_iov;
+	iovec->bufs[index].vaddr = seg_data;
+	iovec->bufs[index].dma_addr = seg_phys;
+	iovec->bufs[index].size = seg_size;
+	index++;
+	pkt = pkt->next;
+
+	while (unlikely(pkt != NULL)) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+
+		if (!seg_size)
+			break;
+
+		iovec->bufs[index].vaddr = seg_data;
+		iovec->bufs[index].dma_addr = seg_phys;
+		iovec->bufs[index].size = seg_size;
+
+		index++;
+
+		pkt = pkt->next;
+	}
+
+	iovec->buf_cnt = index;
+	return 0;
+}
+
+static void
+find_kasumif9_direction_and_length(uint8_t *src,
+				   uint32_t counter_num_bytes,
+				   uint32_t *addr_length_in_bits,
+				   uint8_t *addr_direction)
+{
+	uint8_t found = 0;
+	while (!found && counter_num_bytes > 0) {
+		counter_num_bytes--;
+		if (src[counter_num_bytes] == 0x00)
+			continue;
+		if (src[counter_num_bytes] == 0x80) {
+			*addr_direction  =  src[counter_num_bytes - 1] & 0x1;
+			*addr_length_in_bits = counter_num_bytes * 8  - 1;
+			found = 1;
+		} else {
+			int i = 0;
+			uint8_t last_byte = src[counter_num_bytes];
+			for (i = 0; i < 8 && found == 0; i++) {
+				if (last_byte & (1 << i)) {
+					*addr_direction = (last_byte >> (i+1))
+							  & 0x1;
+					if (i != 6)
+						*addr_length_in_bits =
+							counter_num_bytes * 8
+							+ (8 - (i + 2));
+					else
+						*addr_length_in_bits =
+							counter_num_bytes * 8;
+
+					found = 1;
+					}
+				}
+			}
+	}
+}
+/*
+ * This handles all auth only except AES_GMAC
+ */
+static void *
+fill_digest_params(struct rte_crypto_op *cop,
+		   struct cpt_sess_misc *sess,
+		   void **mdata_ptr,
+		   int *op_ret)
+{
+	uint32_t space = 0;
+	struct rte_crypto_sym_op *sym_op = cop->sym;
+	void *mdata;
+	phys_addr_t mphys;
+	uint64_t *op;
+	uint32_t auth_range_off;
+	uint32_t flags = 0;
+	uint64_t d_offs = 0, d_lens;
+	void *prep_req = NULL;
+	struct rte_mbuf *m_src, *m_dst;
+	uint16_t auth_op = sess->cpt_op & CSP_OP_AUTH_MASK;
+	uint8_t zsk_flag = sess->zsk_flag;
+	uint16_t mac_len = sess->mac_len;
+	fc_params_t params;
+	char src[SRC_IOV_SIZE];
+	uint8_t iv_buf[16];
+
+	m_src = sym_op->m_src;
+
+	/* For just digest lets force mempool alloc */
+	mdata = alloc_op_meta(NULL, &params.meta_buf, cpt_op_mlen);
+	if (mdata == NULL) {
+		PMD_DRV_LOG(ERR, "Error allocating meta buffer for request\n");
+		*op_ret = -ENOMEM;
+		return NULL;
+	}
+
+	mphys = params.meta_buf.dma_addr;
+
+	op = mdata;
+	op[0] = (uint64_t)mdata;
+	op[1] = (uint64_t)cop;
+	op[2] = op[3] = 0; /* Used to indicate auth verify */
+	space += 4 * sizeof(uint64_t);
+
+	auth_range_off = sym_op->auth.data.offset;
+
+	flags = VALID_MAC_BUF;
+	params.src_iov = (void *)src;
+	if (unlikely(zsk_flag)) {
+		/*
+		 * Since for Zuc, Kasumi, Snow3g offsets are in bits
+		 * we will send pass through even for auth only case,
+		 * let MC handle it
+		 */
+		d_offs = auth_range_off;
+		auth_range_off = 0;
+		params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
+					uint8_t *, sess->auth_iv_offset);
+		if (zsk_flag == K_F9) {
+			uint32_t length_in_bits, num_bytes;
+			uint8_t *src, direction = 0;
+			uint32_t counter_num_bytes;
+
+			memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,
+							uint8_t *), 8);
+			/*
+			 * This is kasumi f9, take direction from
+			 * source buffer
+			 */
+			length_in_bits = cop->sym->auth.data.length;
+			num_bytes = (length_in_bits >> 3);
+			counter_num_bytes = num_bytes;
+			src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);
+			find_kasumif9_direction_and_length(src,
+						counter_num_bytes,
+						&length_in_bits,
+						&direction);
+			length_in_bits -= 64;
+			cop->sym->auth.data.offset += 64;
+			d_offs = cop->sym->auth.data.offset;
+			auth_range_off = d_offs / 8;
+			cop->sym->auth.data.length = length_in_bits;
+
+			/* Store it at end of auth iv */
+			iv_buf[8] = direction;
+			params.auth_iv_buf = iv_buf;
+		}
+	}
+
+	d_lens = sym_op->auth.data.length;
+
+	params.ctx_buf.vaddr = SESS_PRIV(sess);
+	params.ctx_buf.dma_addr = sess->ctx_dma_addr;
+
+	if (auth_op == CSP_OP_AUTH_GENERATE) {
+		if (sym_op->auth.digest.data) {
+			/*
+			 * Digest to be generated
+			 * in separate buffer
+			 */
+			params.mac_buf.size =
+				sess->mac_len;
+			params.mac_buf.vaddr =
+				sym_op->auth.digest.data;
+			params.mac_buf.dma_addr =
+				sym_op->auth.digest.phys_addr;
+		} else {
+			uint32_t off = sym_op->auth.data.offset +
+				sym_op->auth.data.length;
+			int32_t dlen, space;
+
+			m_dst = sym_op->m_dst ?
+				sym_op->m_dst : sym_op->m_src;
+			dlen = rte_pktmbuf_pkt_len(m_dst);
+
+			space = off + mac_len - dlen;
+			if (space > 0)
+				if (!rte_pktmbuf_append(m_dst, space)) {
+					PMD_DRV_LOG(ERR, "Failed to extend "
+					 "mbuf by %uB\n", space);
+					goto err;
+				}
+
+			params.mac_buf.vaddr =
+				rte_pktmbuf_mtod_offset(m_dst,
+							void *, off);
+			params.mac_buf.dma_addr =
+				rte_pktmbuf_mtophys_offset(m_dst, off);
+			params.mac_buf.size = mac_len;
+		}
+	} else {
+		/* Need space for storing generated mac */
+		params.mac_buf.vaddr =
+			(uint8_t *)mdata + space;
+		params.mac_buf.dma_addr = mphys + space;
+		params.mac_buf.size = mac_len;
+		space += RTE_ALIGN_CEIL(mac_len, 8);
+		op[2] = (uint64_t)params.mac_buf.vaddr;
+		op[3] = mac_len;
+
+	}
+
+	params.meta_buf.vaddr = (uint8_t *)mdata + space;
+	params.meta_buf.dma_addr = mphys + space;
+	params.meta_buf.size -= space;
+
+	/* Out of place processing */
+	params.src_iov = (void *)src;
+
+	/*Store SG I/O in the api for reuse */
+	if (prepare_iov_from_pkt(m_src, params.src_iov,
+				 auth_range_off)) {
+		PMD_DRV_LOG(ERR, "Prepare src iov failed\n");
+		*op_ret = -1;
+		goto err;
+	}
+
+	prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
+					&params, op, op_ret);
+	*mdata_ptr = mdata;
+	return prep_req;
+err:
+	if (unlikely(!prep_req))
+		free_op_meta(mdata);
+	return NULL;
+}
+
+static inline void *
+fill_fc_params(struct rte_crypto_op *cop,
+	       struct cpt_sess_misc *sess_misc,
+	       void **mdata_ptr,
+	       int *op_ret)
+{
+	uint32_t space = 0;
+	struct rte_crypto_sym_op *sym_op = cop->sym;
+	void *mdata;
+	uint64_t *op;
+	uint32_t mc_hash_off;
+	uint32_t flags = 0;
+	uint64_t d_offs, d_lens;
+	void *prep_req;
+	struct rte_mbuf *m_src, *m_dst;
+	uint8_t cpt_op = sess_misc->cpt_op;
+	uint8_t zsk_flag = sess_misc->zsk_flag;
+	uint8_t aes_gcm = sess_misc->aes_gcm;
+	uint16_t mac_len = sess_misc->mac_len;
+#ifdef CPT_ALWAYS_USE_SG_MODE
+	uint8_t inplace = 0;
+#else
+	uint8_t inplace = 1;
+#endif
+	fc_params_t fc_params;
+	char src[SRC_IOV_SIZE];
+	char dst[SRC_IOV_SIZE];
+	uint32_t iv_buf[4];
+
+	if (likely(sess_misc->iv_length)) {
+		flags |= VALID_IV_BUF;
+		fc_params.iv_buf = rte_crypto_op_ctod_offset(cop,
+				   uint8_t *, sess_misc->iv_offset);
+		if (sess_misc->aes_ctr &&
+		    unlikely(sess_misc->iv_length != 16)) {
+			memcpy((uint8_t *)iv_buf,
+				rte_crypto_op_ctod_offset(cop,
+				uint8_t *, sess_misc->iv_offset), 12);
+			iv_buf[3] = htobe32(0x1);
+			fc_params.iv_buf = iv_buf;
+		}
+	}
+
+	if (zsk_flag) {
+		fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
+					uint8_t *,
+					sess_misc->auth_iv_offset);
+		if (zsk_flag == K_F9) {
+			PMD_DRV_LOG(ERR, "Should not reach here for "
+			"kasumi F9\n");
+		}
+		if (zsk_flag != ZS_EA)
+			inplace = 0;
+	}
+	m_src = sym_op->m_src;
+	m_dst = sym_op->m_dst;
+
+	if (aes_gcm) {
+		uint8_t *salt;
+		uint8_t *aad_data;
+		uint16_t aad_len;
+
+		d_offs = sym_op->aead.data.offset;
+		d_lens = sym_op->aead.data.length;
+		mc_hash_off = sym_op->aead.data.offset +
+			      sym_op->aead.data.length;
+
+		aad_data = sym_op->aead.aad.data;
+		aad_len = sess_misc->aad_length;
+		if (likely((aad_data + aad_len) ==
+			   rte_pktmbuf_mtod_offset(m_src,
+				uint8_t *,
+				sym_op->aead.data.offset))) {
+			d_offs = (d_offs - aad_len) | (d_offs << 16);
+			d_lens = (d_lens + aad_len) | (d_lens << 32);
+		} else {
+			fc_params.aad_buf.vaddr = sym_op->aead.aad.data;
+			fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;
+			fc_params.aad_buf.size = aad_len;
+			flags |= VALID_AAD_BUF;
+			inplace = 0;
+			d_offs = d_offs << 16;
+			d_lens = d_lens << 32;
+		}
+
+		salt = fc_params.iv_buf;
+		if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
+			cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
+			sess_misc->salt = *(uint32_t *)salt;
+		}
+		fc_params.iv_buf = salt + 4;
+		if (likely(mac_len)) {
+			struct rte_mbuf *m = (cpt_op & CSP_OP_ENCODE) ? m_dst :
+					     m_src;
+
+			if (!m)
+				m = m_src;
+
+			/* hmac immediately following data is best case */
+			if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
+			    mc_hash_off !=
+			    (uint8_t *)sym_op->aead.digest.data)) {
+				flags |= VALID_MAC_BUF;
+				fc_params.mac_buf.size = sess_misc->mac_len;
+				fc_params.mac_buf.vaddr =
+				  sym_op->aead.digest.data;
+				fc_params.mac_buf.dma_addr =
+				 sym_op->aead.digest.phys_addr;
+				inplace = 0;
+			}
+		}
+	} else {
+		d_offs = sym_op->cipher.data.offset;
+		d_lens = sym_op->cipher.data.length;
+		mc_hash_off = sym_op->cipher.data.offset +
+			      sym_op->cipher.data.length;
+		d_offs = (d_offs << 16) | sym_op->auth.data.offset;
+		d_lens = (d_lens << 32) | sym_op->auth.data.length;
+
+		if (mc_hash_off < (sym_op->auth.data.offset +
+				   sym_op->auth.data.length)){
+			mc_hash_off = (sym_op->auth.data.offset +
+				       sym_op->auth.data.length);
+		}
+		/* for gmac, salt should be updated like in gcm */
+		if (unlikely(sess_misc->is_gmac)) {
+			uint8_t *salt;
+			salt = fc_params.iv_buf;
+			if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
+				cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
+				sess_misc->salt = *(uint32_t *)salt;
+			}
+			fc_params.iv_buf = salt + 4;
+		}
+			/* */
+		if (likely(mac_len)) {
+			struct rte_mbuf *m =
+			(cpt_op & CSP_OP_ENCODE) ? m_dst : m_src;
+
+			if (!m)
+				m = m_src;
+
+		/* hmac immediately following data is best case */
+			if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
+			    mc_hash_off !=
+			     (uint8_t *)sym_op->auth.digest.data)) {
+				flags |= VALID_MAC_BUF;
+				fc_params.mac_buf.size =
+					sess_misc->mac_len;
+				fc_params.mac_buf.vaddr =
+					sym_op->auth.digest.data;
+				fc_params.mac_buf.dma_addr =
+				sym_op->auth.digest.phys_addr;
+				inplace = 0;
+			}
+		}
+	}
+	fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);
+	fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;
+
+	if (likely(!m_dst && inplace)) {
+		/* Case of single buffer without AAD buf or
+		 * separate mac buf in place and
+		 * not air crypto
+		 */
+		fc_params.dst_iov = fc_params.src_iov = (void *)src;
+
+		if (unlikely(prepare_iov_from_pkt_inplace(m_src,
+							  &fc_params,
+							  &flags))) {
+			PMD_DRV_LOG(ERR, "Prepare inplace src iov failed\n");
+			*op_ret = -1;
+			return NULL;
+		}
+
+	} else {
+		/* Out of place processing */
+		fc_params.src_iov = (void *)src;
+		fc_params.dst_iov = (void *)dst;
+
+		/*Store SG I/O in the api for reuse */
+		if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {
+			PMD_DRV_LOG(ERR, "Prepare src iov failed\n");
+			*op_ret = -1;
+			return NULL;
+		}
+
+		if (unlikely(m_dst != NULL)) {
+			uint32_t pkt_len;
+
+			/* Try to make room as much as src has */
+			m_dst = sym_op->m_dst;
+			pkt_len = rte_pktmbuf_pkt_len(m_dst);
+
+			if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {
+				pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;
+				if (!rte_pktmbuf_append(m_dst, pkt_len)) {
+					PMD_DRV_LOG(ERR, "Not enough space in "
+					 "m_dst %p, need %u more\n",
+					 m_dst, pkt_len);
+					return NULL;
+				}
+			}
+
+			if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {
+				PMD_DRV_LOG(ERR, "Prepare dst iov failed for "
+				 "m_dst %p\n", m_dst);
+				return NULL;
+			}
+		} else {
+			fc_params.dst_iov = (void *)src;
+		}
+
+	}
+
+	if (likely(flags & SINGLE_BUF_HEADTAILROOM))
+		mdata = alloc_op_meta(m_src,
+				      &fc_params.meta_buf,
+				      cpt_op_sb_mlen);
+	else
+		mdata = alloc_op_meta(NULL,
+				      &fc_params.meta_buf,
+				      cpt_op_mlen);
+
+	if (unlikely(mdata == NULL)) {
+		PMD_DRV_LOG(ERR, "Error allocating meta buffer for request\n");
+		return NULL;
+	}
+
+	op = (uint64_t *)((uint64_t)mdata & ~1ull);
+	op[0] = (uint64_t)mdata;
+	op[1] = (uint64_t)cop;
+	op[2] = op[3] = 0; /* Used to indicate auth verify */
+	space += 4 * sizeof(uint64_t);
+
+	fc_params.meta_buf.vaddr = (uint8_t *)op + space;
+	fc_params.meta_buf.dma_addr += space;
+	fc_params.meta_buf.size -= space;
+
+	/* Finally prepare the instruction */
+	if (cpt_op & CSP_OP_ENCODE)
+		prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
+						&fc_params, op, op_ret);
+	else
+		prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,
+						&fc_params, op, op_ret);
+
+	if (unlikely(!prep_req))
+		free_op_meta(mdata);
+	*mdata_ptr = mdata;
+	return prep_req;
+}
+
+static inline void
+compl_auth_verify(struct rte_crypto_op *op,
+		      uint8_t *gen_mac,
+		      uint64_t mac_len)
+{
+	uint8_t *mac;
+	struct rte_crypto_sym_op *sym_op = op->sym;
+
+	if (sym_op->auth.digest.data)
+		mac = sym_op->auth.digest.data;
+	else
+		mac = rte_pktmbuf_mtod_offset(sym_op->m_src,
+					      uint8_t *,
+					      sym_op->auth.data.length +
+					      sym_op->auth.data.offset);
+	if (!mac) {
+		op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		return;
+	}
+
+	if (memcmp(mac, gen_mac, mac_len))
+		op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+	else
+		op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+}
+
+
+static inline int __hot
+cpt_pmd_crypto_operation(cpt_instance_t *instance,
+		     struct rte_crypto_op *op,
+		     bool last_op)
+{
+	struct cpt_sess_misc *sess = NULL;
+	struct rte_crypto_sym_op *sym_op = op->sym;
+	void *prep_req, *mdata = NULL;
+	int ret = 0;
+	uint64_t cpt_op;
+	uint8_t flags = last_op ? 0 : ENQ_FLAG_NODOORBELL;
+
+
+	if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
+		void *ptr = NULL;
+		int sess_len;
+
+		sess_len = cpt_pmd_get_session_size(NULL);
+
+		sess = rte_calloc(__func__, 1, sess_len, 8);
+		if (!sess)
+			return -ENOMEM;
+
+		sess->ctx_dma_addr =  rte_malloc_virt2iova(sess) +
+			sizeof(struct cpt_sess_misc);
+
+		ptr = instance_session_cfg(instance,
+					   sym_op->xform, (void *)sess);
+		if (ptr == NULL)
+			return -EINVAL;
+	} else {
+		sess = (struct cpt_sess_misc *)
+		get_session_private_data(sym_op->session,
+		cryptodev_cpt_driver_id);
+	}
+
+	cpt_op = sess->cpt_op;
+
+	if (likely(cpt_op & CSP_OP_CIPHER_MASK))
+		prep_req = fill_fc_params(op, sess, &mdata, &ret);
+	else
+		prep_req = fill_digest_params(op, sess, &mdata, &ret);
+
+	if (unlikely(!prep_req)) {
+		PMD_DRV_LOG_RAW(ERR, "prep cryto req : op %p, cpt_op 0x%x ret "
+		 "0x%x\n", op, (unsigned int)cpt_op, ret);
+		goto req_fail;
+	}
+
+	/* Enqueue prepared instruction to HW */
+	ret = cpt_enqueue_req(instance, prep_req,
+			      flags, NULL, 0);
+
+	if (unlikely(ret)) {
+		if (unlikely(ret == -EAGAIN))
+			goto req_fail;
+		PMD_DRV_LOG(ERR, "Error enqueing crypto request : error code "
+		 "%d\n", ret);
+		goto req_fail;
+	}
+
+	/* TODO: Stats here */
+
+	return 0;
+
+req_fail:
+	if (mdata)
+		free_op_meta(mdata);
+	return ret;
+}
+
+
+
+uint16_t
+cpt_pmd_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	cpt_instance_t *instance = (cpt_instance_t *)qptr;
+	uint16_t count = 0;
+	int ret;
+
+	count = cpt_queue_full(instance);
+	if (nb_ops > count)
+		nb_ops = count;
+
+	count = 0;
+	while (likely(count < nb_ops)) {
+		bool last_op = (count + 1 == nb_ops);
+		ret = cpt_pmd_crypto_operation(instance, ops[count], last_op);
+		if (unlikely(ret))
+			break;
+		count++;
+	}
+	return count;
+}
+
+uint16_t
+cpt_pmd_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	cpt_instance_t *instance = (cpt_instance_t *)qptr;
+	uint16_t nb_completed, i = 0;
+	uint8_t compcode[nb_ops];
+
+	nb_completed = cpt_dequeue_burst(instance, nb_ops,
+					 (void **)ops, compcode);
+	while (likely(i < nb_completed)) {
+		struct rte_crypto_op *cop;
+		void *metabuf;
+		uint64_t *rsp;
+		uint8_t status;
+
+		rsp = (void *)ops[i];
+		status = compcode[i];
+		if (likely((i + 1) < nb_completed))
+			rte_prefetch0(ops[i+1]);
+		metabuf = (void *)rsp[0];
+		cop = (void *)rsp[1];
+
+		ops[i] = cop;
+
+		if (likely(status == 0)) {
+			if (likely(!rsp[2]))
+				cop->status =
+					RTE_CRYPTO_OP_STATUS_SUCCESS;
+			else
+				compl_auth_verify(cop, (uint8_t *)rsp[2],
+						  rsp[3]);
+		} else if (status == ERR_GC_ICV_MISCOMPARE) {
+			/*auth data mismatch */
+			cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+		} else {
+			cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		}
+		free_op_meta(metabuf);
+		i++;
+	}
+	return nb_completed;
+}
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.h b/drivers/crypto/cpt/cpt_pmd_ops.h
index 314b2b1..17b3a09 100644
--- a/drivers/crypto/cpt/cpt_pmd_ops.h
+++ b/drivers/crypto/cpt/cpt_pmd_ops.h
@@ -83,4 +83,14 @@ int cpt_pmd_session_cfg(struct rte_cryptodev *dev,
 void
 cpt_pmd_session_clear(struct rte_cryptodev *dev,
 		  struct rte_cryptodev_sym_session *sess);
+
+uint16_t
+cpt_pmd_pkt_enqueue(void *qptr,
+		struct rte_crypto_op **ops,
+		uint16_t nb_ops);
+
+uint16_t
+cpt_pmd_pkt_dequeue(void *qptr,
+		struct rte_crypto_op **ops,
+		uint16_t nb_ops);
 #endif
-- 
1.9.3

[dpdk-dev] [PATCH 15/16] doc: add Cavium's CPT guide

[Anoob Joseph]

From: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>

The guide contains information about packages needed to compile
the CPT PMD. It also contains the compilation steps and how to
execute an examples application.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 doc/guides/cryptodevs/cpt.rst | 112 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 doc/guides/cryptodevs/cpt.rst

diff --git a/doc/guides/cryptodevs/cpt.rst b/doc/guides/cryptodevs/cpt.rst
new file mode 100644
index 0000000..262ce9e
--- /dev/null
+++ b/doc/guides/cryptodevs/cpt.rst
@@ -0,0 +1,112 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+   Copyright(c) 2017 Cavium, Inc
+
+*****************************
+Cavium's CPT Poll Mode Driver
+******************************
+
+The CPT poll mode driver provides support for offloading cryptographic
+operations on the Cavium's cryptographic accelerator unit(CPT) coprocessor
+hardware. This coprocessor is present on the Cavium's thunder boards(CN8xxx).
+The CPT poll mode driver enqueues the crypto request to this coprocessor and
+dequeues the response once the operation is completed.
+
+Supported Algorithms
+#####################
+
+Cipher Algorithms
+******************
+
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_CTR``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_NULL``
+
+Hash Algorithms
+****************
+
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+* ``RTE_CRYPTO_AUTH_AES_GMAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
+
+AEAD Algorithms
+****************
+
+* ``RTE_CRYPTO_AEAD_AES_GCM``
+
+Compilation
+############
+
+The thunder board must be running the linux kernel based on sdk-6.2.0 patch 2.
+In this the cpt pf driver is already built in. Also install the openssl package,
+because the cpt driver depends on the crypto library.
+
+For compiling the cpt poll mode driver, the CONFIG_RTE_LIBRTE_PMD_CPT setting
+should be made as `y` in config/common_base file. By default it is set to `n`.
+
+* ``CONFIG_RTE_LIBRTE_PMD_CPT=y``
+
+The following are the steps to compile the cpt poll mode driver:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        make config T=arm64-thunderx-linuxapp-gcc
+        make
+
+The example applications can be compiled using the following:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        export RTE_SDK=$PWD
+        export RTE_TARGET=build
+        cd examples/<application>
+        make
+
+Execution
+##########
+
+The sriov_numvfs should be assigned for the cpt pf driver using the following:
+
+.. code-block:: console
+
+        echo <num vfs> > /sys/bus/pci/devices/<device no>/sriov_numvfs
+
+The device number can be ascertained by running the dpdk-devbind.py scripts in
+the dpdk sources.
+
+Then the corresponding vf should be binded to the vfio-pci driver using the
+following:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        ./usertools/dpdk-devbind.py -u <vf device no>
+        ./usertools/dpdk-devbind.py -bvfio-pci <vf device no>
+
+Appropriate huge page need to be setup in order to run the examples dpdk
+application.
+
+.. code-block:: console
+
+        echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
+        mkdir /mnt/huge
+        mount -t hugetlbfs nodev /mnt/huge
+
+After that the example dpdk application can be executed on the hardware.
+
+.. code-block:: console
+        ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
+        "(0,0,0),(1,0,0)" -f ep0.cfg
-- 
1.9.3

Re: [dpdk-dev] [PATCH 15/16] doc: add Cavium's CPT guide

[De Lara Guarch, Pablo]

> -----Original Message-----
> From: Anoob Joseph [mailto:anoob.joseph@caviumnetworks.com]
> Sent: Friday, June 8, 2018 5:45 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Thomas Monjalon <thomas@monjalon.net>
> Cc: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>; Ankur
> Dwivedi <ankur.dwivedi@cavium.com>; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> <nithin.dabilpuram@cavium.com>; Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> Subject: [PATCH 15/16] doc: add Cavium's CPT guide
> 
> From: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
> 
> The guide contains information about packages needed to compile the CPT
> PMD. It also contains the compilation steps and how to execute an examples
> application.

You need to add the guide in index.rst.
Also, you should add cpt.ini under doc/guides/cryptodevs/features/.


> 
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
> Signed-off-by: Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>
> ---
>  doc/guides/cryptodevs/cpt.rst | 112
> ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 112 insertions(+)
>  create mode 100644 doc/guides/cryptodevs/cpt.rst
> 
> diff --git a/doc/guides/cryptodevs/cpt.rst b/doc/guides/cryptodevs/cpt.rst new
> file mode 100644 index 0000000..262ce9e
> --- /dev/null
> +++ b/doc/guides/cryptodevs/cpt.rst
> @@ -0,0 +1,112 @@
> +.. SPDX-License-Identifier: BSD-3-Clause
> +   Copyright(c) 2017 Cavium, Inc
> +
> +*****************************
> +Cavium's CPT Poll Mode Driver
> +******************************

Please, use the standard title underlines used in other guides
("=" for title, "-" for section, "~" for subsection).

> +
> +The CPT poll mode driver provides support for offloading cryptographic
> +operations on the Cavium's cryptographic accelerator unit(CPT)
> +coprocessor hardware. This coprocessor is present on the Cavium's thunder
> boards(CN8xxx).

...

> +Compilation
> +############
> +
> +The thunder board must be running the linux kernel based on sdk-6.2.0 patch 2.
> +In this the cpt pf driver is already built in. Also install the openssl
> +package, because the cpt driver depends on the crypto library.

Is this true? I could compile this without openssl.

> +
> +For compiling the cpt poll mode driver, the CONFIG_RTE_LIBRTE_PMD_CPT
> +setting should be made as `y` in config/common_base file. By default it is set to
> `n`.
> +

...

> +Then the corresponding vf should be binded to the vfio-pci driver using
> +the
> +following:
> +
> +.. code-block:: console
> +
> +        cd <dpdk directory>
> +        ./usertools/dpdk-devbind.py -u <vf device no>
> +        ./usertools/dpdk-devbind.py -bvfio-pci <vf device no>

Space between -b and vfio-pci?

[dpdk-dev] [PATCH 16/16] crypto/cpt: build with meson

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@cavium.com>

Adding the meson.build file for the CPT PMD.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/meson.build | 16 ++++++++++++++++
 drivers/crypto/meson.build     |  2 +-
 2 files changed, 17 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/cpt/meson.build

diff --git a/drivers/crypto/cpt/meson.build b/drivers/crypto/cpt/meson.build
new file mode 100644
index 0000000..d298587
--- /dev/null
+++ b/drivers/crypto/cpt/meson.build
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017 Cavium, Inc
+if host_machine.system() != 'linux'
+        build = false
+endif
+
+sources = files('cpt_pmd_cryptodev.c',
+		'cpt_pmd_ops.c',
+		'base/cpt_device.c',
+		'base/cpt_request_mgr.c',
+		'base/cpt_ops.c',
+		'base/cpt8xxx_device.c',
+		'base/cpt_vf_mbox.c')
+
+deps += ['bus_pci']
+pkgconfig_extra_libs += '-lcrypto'
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index d64ca41..6a7923f 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
-drivers = ['ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam',
+drivers = ['cpt', 'ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam',
 	'null', 'openssl', 'qat', 'virtio']
 
 std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
-- 
1.9.3

Re: [dpdk-dev] [PATCH 16/16] crypto/cpt: build with meson

[De Lara Guarch, Pablo]

Hi,

> -----Original Message-----
> From: Anoob Joseph [mailto:anoob.joseph@caviumnetworks.com]
> Sent: Friday, June 8, 2018 5:45 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Thomas Monjalon <thomas@monjalon.net>
> Cc: Ankur Dwivedi <ankur.dwivedi@cavium.com>; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> Subject: [PATCH 16/16] crypto/cpt: build with meson
> 
> From: Ankur Dwivedi <ankur.dwivedi@cavium.com>
> 
> Adding the meson.build file for the CPT PMD.

You should remove this patch and just add meson build in all the patches
where you are adding changes in the Makefiles.

Thanks,
Pablo

Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver

[Anoob Joseph]

Hi Akhil, Pablo,

Are there any top level comments on this?

Thanks,
Anoob
On 08/06/18 22:15, Anoob Joseph wrote:
> Ankur Dwivedi (4):
>    crypto/cpt/base: add hardware enq/deq API for CPT
>    crypto/cpt/base: add sym crypto session init API for CPT
>    crypto/cpt/base: add sym crypto request prepare for CPT
>    crypto/cpt: build with meson
>
> Murthy NSSR (3):
>    crypto/cpt/base: add request prepare API for ZUC and SNOW3G
>    crypto/cpt/base: add request prepare API for Kasumi
>    crypto/cpt/base: add prepare request API for HASH and HMAC
>
> Nithin Dabilpuram (3):
>    config: add Cavium CPT PMD skeleton
>    crypto/cpt/base: add hardware definitions Cavium CPT
>    crypto/cpt/base: add hardware initialization API for CPT
>
> Ragothaman Jayaraman (3):
>    crypto/cpt: adds the session related function callbacks
>    crypto/cpt: adds the enqueue and dequeue callbacks
>    doc: add Cavium's CPT guide
>
> Srisivasubramanian Srinivasan (3):
>    crypto/cpt: add driver initializations
>    crypto/cpt: add the basic device callback functions
>    crypto/cpt: adds some more callback functions for CPT
>
>   MAINTAINERS                                |    7 +
>   config/common_base                         |    8 +
>   doc/guides/cryptodevs/cpt.rst              |  112 ++
>   drivers/crypto/Makefile                    |    1 +
>   drivers/crypto/cpt/Makefile                |   49 +
>   drivers/crypto/cpt/base/cpt.h              |  231 +++
>   drivers/crypto/cpt/base/cpt8xxx_device.c   |  200 ++
>   drivers/crypto/cpt/base/cpt8xxx_device.h   |   85 +
>   drivers/crypto/cpt/base/cpt_debug.h        |  231 +++
>   drivers/crypto/cpt/base/cpt_device.c       |  383 ++++
>   drivers/crypto/cpt/base/cpt_device.h       |  162 ++
>   drivers/crypto/cpt/base/cpt_hw_types.h     |  836 +++++++++
>   drivers/crypto/cpt/base/cpt_ops.c          | 2756 ++++++++++++++++++++++++++++
>   drivers/crypto/cpt/base/cpt_request_mgr.c  |  424 +++++
>   drivers/crypto/cpt/base/cpt_request_mgr.h  |   75 +
>   drivers/crypto/cpt/base/cpt_vf_mbox.c      |  176 ++
>   drivers/crypto/cpt/base/cpt_vf_mbox.h      |   60 +
>   drivers/crypto/cpt/base/mcode_defines.h    |  215 +++
>   drivers/crypto/cpt/cpt_pmd_cryptodev.c     |  271 +++
>   drivers/crypto/cpt/cpt_pmd_logs.h          |   50 +
>   drivers/crypto/cpt/cpt_pmd_ops.c           | 1936 +++++++++++++++++++
>   drivers/crypto/cpt/cpt_pmd_ops.h           |   96 +
>   drivers/crypto/cpt/meson.build             |   16 +
>   drivers/crypto/cpt/rte_pmd_cpt_version.map |    4 +
>   drivers/crypto/meson.build                 |    2 +-
>   mk/rte.app.mk                              |    2 +-
>   26 files changed, 8386 insertions(+), 2 deletions(-)
>   create mode 100644 doc/guides/cryptodevs/cpt.rst
>   create mode 100644 drivers/crypto/cpt/Makefile
>   create mode 100644 drivers/crypto/cpt/base/cpt.h
>   create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.c
>   create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.h
>   create mode 100644 drivers/crypto/cpt/base/cpt_debug.h
>   create mode 100644 drivers/crypto/cpt/base/cpt_device.c
>   create mode 100644 drivers/crypto/cpt/base/cpt_device.h
>   create mode 100644 drivers/crypto/cpt/base/cpt_hw_types.h
>   create mode 100644 drivers/crypto/cpt/base/cpt_ops.c
>   create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.c
>   create mode 100644 drivers/crypto/cpt/base/cpt_request_mgr.h
>   create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.c
>   create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.h
>   create mode 100644 drivers/crypto/cpt/base/mcode_defines.h
>   create mode 100644 drivers/crypto/cpt/cpt_pmd_cryptodev.c
>   create mode 100644 drivers/crypto/cpt/cpt_pmd_logs.h
>   create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.c
>   create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.h
>   create mode 100644 drivers/crypto/cpt/meson.build
>   create mode 100644 drivers/crypto/cpt/rte_pmd_cpt_version.map
>

Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver

[De Lara Guarch, Pablo]

Hi Anoob,

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Anoob Joseph
> Sent: Monday, June 18, 2018 2:02 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>
> Cc: Thomas Monjalon <thomas@monjalon.net>; Ankur Dwivedi
> <ankur.dwivedi@cavium.com>; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT)
> driver
> 
> Hi Akhil, Pablo,
> 
> Are there any top level comments on this?

Sorry for the delay. I didn't have the time to review this yet.
Will do that asap.

Thanks,
Pablo

Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver

[De Lara Guarch, Pablo]

> -----Original Message-----
> From: De Lara Guarch, Pablo
> Sent: Monday, June 18, 2018 3:30 PM
> To: Anoob Joseph <Anoob.Joseph@caviumnetworks.com>; Akhil Goyal
> <akhil.goyal@nxp.com>
> Cc: Thomas Monjalon <thomas@monjalon.net>; Ankur Dwivedi
> <ankur.dwivedi@cavium.com>; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> Subject: RE: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT)
> driver
> 
> Hi Anoob,
> 
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Anoob Joseph
> > Sent: Monday, June 18, 2018 2:02 PM
> > To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> > <pablo.de.lara.guarch@intel.com>
> > Cc: Thomas Monjalon <thomas@monjalon.net>; Ankur Dwivedi
> > <ankur.dwivedi@cavium.com>; Jerin Jacob
> > <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> > <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> > <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> > <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> > <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> > <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> > Subject: Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto
> > device(CPT) driver
> >
> > Hi Akhil, Pablo,
> >
> > Are there any top level comments on this?
> 
> Sorry for the delay. I didn't have the time to review this yet.
> Will do that asap.

Hi Anoob,

I had some comments on this patchset.
Could you address these comments and send a v2?
Please, take into account the following patchset which will be applied tomorrow
(just waiting for a couple of acks):

http://patches.dpdk.org/user/todo/dpdk/?series=416


> 
> Thanks,
> Pablo

Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver

[Anoob Joseph]

Hi Pablo,

Thanks for the review. We had made some architectural modifications to 
the PMD while addressing your comments. This is taking longer than 
expected and so we might as well defer the v2 to the next release cycle. 
Is that fine?

Do you suggest submitting the patches as and when it is ready or should 
I wait till next release cycle?

> Please, take into account the following patchset which will be applied tomorrow
> (just waiting for a couple of acks):

> http://patches.dpdk.org/user/todo/dpdk/?series=416

This series is integrated.

Thanks,
Anoob

On 10-07-2018 04:25, De Lara Guarch, Pablo wrote:
> External Email
>
>> -----Original Message-----
>> From: De Lara Guarch, Pablo
>> Sent: Monday, June 18, 2018 3:30 PM
>> To: Anoob Joseph <Anoob.Joseph@caviumnetworks.com>; Akhil Goyal
>> <akhil.goyal@nxp.com>
>> Cc: Thomas Monjalon <thomas@monjalon.net>; Ankur Dwivedi
>> <ankur.dwivedi@cavium.com>; Jerin Jacob
>> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
>> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
>> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
>> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
>> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
>> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
>> Subject: RE: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT)
>> driver
>>
>> Hi Anoob,
>>
>>> -----Original Message-----
>>> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Anoob Joseph
>>> Sent: Monday, June 18, 2018 2:02 PM
>>> To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
>>> <pablo.de.lara.guarch@intel.com>
>>> Cc: Thomas Monjalon <thomas@monjalon.net>; Ankur Dwivedi
>>> <ankur.dwivedi@cavium.com>; Jerin Jacob
>>> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
>>> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
>>> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
>>> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
>>> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
>>> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
>>> Subject: Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto
>>> device(CPT) driver
>>>
>>> Hi Akhil, Pablo,
>>>
>>> Are there any top level comments on this?
>> Sorry for the delay. I didn't have the time to review this yet.
>> Will do that asap.
> Hi Anoob,
>
> I had some comments on this patchset.
> Could you address these comments and send a v2?
> Please, take into account the following patchset which will be applied tomorrow
> (just waiting for a couple of acks):
>
> http://patches.dpdk.org/user/todo/dpdk/?series=416
>
>
>> Thanks,
>> Pablo

Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver

[De Lara Guarch, Pablo]

Hi Anoob,

> -----Original Message-----
> From: Anoob Joseph [mailto:anoob.joseph@caviumnetworks.com]
> Sent: Tuesday, July 10, 2018 4:41 AM
> To: De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>; 'Akhil Goyal'
> <akhil.goyal@nxp.com>
> Cc: 'Thomas Monjalon' <thomas@monjalon.net>; 'Ankur Dwivedi'
> <ankur.dwivedi@cavium.com>; 'Jerin Jacob'
> <jerin.jacob@caviumnetworks.com>; 'Murthy NSSR'
> <Nidadavolu.Murthy@cavium.com>; 'Narayana Prasad'
> <narayanaprasad.athreya@caviumnetworks.com>; 'Nithin Dabilpuram'
> <nithin.dabilpuram@cavium.com>; 'Ragothaman Jayaraman'
> <Ragothaman.Jayaraman@cavium.com>; 'Srisivasubramanian Srinivasan'
> <Srisivasubramanian.Srinivasan@cavium.com>; 'dev@dpdk.org'
> <dev@dpdk.org>
> Subject: Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT)
> driver
> 
> Hi Pablo,
> 
> Thanks for the review. We had made some architectural modifications to the
> PMD while addressing your comments. This is taking longer than expected and
> so we might as well defer the v2 to the next release cycle.
> Is that fine?
> 
> Do you suggest submitting the patches as and when it is ready or should I wait
> till next release cycle?

It's ok to defer to next release, no problem. I suggest to wait until 18.08 is out, to make sure that people don't forget about it when they are focused on 18.08 last changes.


> 
> > Please, take into account the following patchset which will be applied
> > tomorrow (just waiting for a couple of acks):
> 
> > http://patches.dpdk.org/user/todo/dpdk/?series=416
> 
> This series is integrated.
> 
> Thanks,
> Anoob
> 
> On 10-07-2018 04:25, De Lara Guarch, Pablo wrote:
> > External Email
> >
> >> -----Original Message-----
> >> From: De Lara Guarch, Pablo
> >> Sent: Monday, June 18, 2018 3:30 PM
> >> To: Anoob Joseph <Anoob.Joseph@caviumnetworks.com>; Akhil Goyal
> >> <akhil.goyal@nxp.com>
> >> Cc: Thomas Monjalon <thomas@monjalon.net>; Ankur Dwivedi
> >> <ankur.dwivedi@cavium.com>; Jerin Jacob
> >> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> >> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> >> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> >> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> >> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> >> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> >> Subject: RE: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto
> >> device(CPT) driver
> >>
> >> Hi Anoob,
> >>
> >>> -----Original Message-----
> >>> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Anoob Joseph
> >>> Sent: Monday, June 18, 2018 2:02 PM
> >>> To: Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> >>> <pablo.de.lara.guarch@intel.com>
> >>> Cc: Thomas Monjalon <thomas@monjalon.net>; Ankur Dwivedi
> >>> <ankur.dwivedi@cavium.com>; Jerin Jacob
> >>> <jerin.jacob@caviumnetworks.com>; Murthy NSSR
> >>> <Nidadavolu.Murthy@cavium.com>; Narayana Prasad
> >>> <narayanaprasad.athreya@caviumnetworks.com>; Nithin Dabilpuram
> >>> <nithin.dabilpuram@cavium.com>; Ragothaman Jayaraman
> >>> <Ragothaman.Jayaraman@cavium.com>; Srisivasubramanian Srinivasan
> >>> <Srisivasubramanian.Srinivasan@cavium.com>; dev@dpdk.org
> >>> Subject: Re: [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto
> >>> device(CPT) driver
> >>>
> >>> Hi Akhil, Pablo,
> >>>
> >>> Are there any top level comments on this?
> >> Sorry for the delay. I didn't have the time to review this yet.
> >> Will do that asap.
> > Hi Anoob,
> >
> > I had some comments on this patchset.
> > Could you address these comments and send a v2?
> > Please, take into account the following patchset which will be applied
> > tomorrow (just waiting for a couple of acks):
> >
> > http://patches.dpdk.org/user/todo/dpdk/?series=416
> >
> >
> >> Thanks,
> >> Pablo

[dpdk-dev] [PATCH v2 00/33] Adding Cavium's OcteonTX crypto PMD

[Anoob Joseph]

Ankur Dwivedi (5):
  config: add Cavium OcteonTX crypto PMD skeleton
  common/cpt: add common logging support
  crypto/octeontx: add PCI probe and remove
  crypto/octeontx: add register addresses
  test: adds validation test

Anoob Joseph (5):
  common/cpt: add common code for init routine
  crypto/octeontx: add hardware init routine
  common/cpt: add hardware register defines
  crypto/octeontx: add hardware register access for misc poll
  doc: adds doc file

Murthy NSSR (5):
  crypto/octeontx: adds symmetric capabilities
  common/cpt: add PMD ops helper functions
  crypto/octeontx: add global resource init
  crypto/octeontx: add mailbox routines
  crypto/octeontx: add basic dev ops

Nithin Dabilpuram (5):
  common/cpt: add common macros for queue pair ops
  crypto/octeontx: add queue pair functions
  common/cpt: add common code required for session management
  crypto/octeontx: add session management ops
  common/cpt: add common code for fill session data

Ragothaman Jayaraman (5):
  crypto/octeontx: add supported sessions
  common/cpt: add common defines for microcode
  common/cpt: add microcode interface for encryption
  common/cpt: add microcode interface for decryption
  common/cpt: add crypo op enqueue request manager framework

Srisivasubramanian S (5):
  common/cpt: add support for zuc and snow3g
  common/cpt: add support for kasumi
  common/cpt: add support for hash
  crypto/octeontx: add routines to prepare instructions
  common/cpt: add common code for enqueuing cpt instruction

Tejasree Kondoj (3):
  crypto/octeontx: add enqueue burst op
  common/cpt: add common code for cpt dequeue
  crypto/octeontx: add dequeue burst op

 MAINTAINERS                                        |    7 +
 config/common_base                                 |    5 +
 doc/guides/cryptodevs/features/octeontx.ini        |   60 +
 doc/guides/cryptodevs/octeontx.rst                 |  121 +
 drivers/common/Makefile                            |    4 +
 drivers/common/cpt/Makefile                        |   25 +
 drivers/common/cpt/cpt_common.h                    |  103 +
 drivers/common/cpt/cpt_hw_types.h                  |  521 +++
 drivers/common/cpt/cpt_mcode_defines.h             |  378 ++
 drivers/common/cpt/cpt_pmd_logs.h                  |   52 +
 drivers/common/cpt/cpt_pmd_ops_helper.c            |   41 +
 drivers/common/cpt/cpt_pmd_ops_helper.h            |   34 +
 drivers/common/cpt/cpt_request_mgr.h               |  189 +
 drivers/common/cpt/cpt_ucode.h                     | 3646 ++++++++++++++++++++
 drivers/common/cpt/meson.build                     |    8 +
 drivers/common/cpt/rte_common_cpt_version.map      |    6 +
 drivers/common/meson.build                         |    2 +-
 drivers/crypto/Makefile                            |    1 +
 drivers/crypto/meson.build                         |    2 +-
 drivers/crypto/octeontx/Makefile                   |   45 +
 drivers/crypto/octeontx/meson.build                |   17 +
 drivers/crypto/octeontx/otx_cryptodev.c            |  135 +
 drivers/crypto/octeontx/otx_cryptodev.h            |   20 +
 .../crypto/octeontx/otx_cryptodev_capabilities.h   |  595 ++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  609 ++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h  |  320 ++
 drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  180 +
 drivers/crypto/octeontx/otx_cryptodev_mbox.h       |   92 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c        |  532 +++
 drivers/crypto/octeontx/otx_cryptodev_ops.h        |   18 +
 .../octeontx/rte_pmd_octeontx_crypto_version.map   |    4 +
 mk/rte.app.mk                                      |    5 +
 test/test/meson.build                              |    1 +
 test/test/test_cryptodev.c                         |  308 ++
 test/test/test_cryptodev.h                         |    1 +
 test/test/test_cryptodev_aes_test_vectors.h        |   96 +-
 test/test/test_cryptodev_blockcipher.c             |    9 +-
 test/test/test_cryptodev_blockcipher.h             |    1 +
 test/test/test_cryptodev_des_test_vectors.h        |   12 +-
 test/test/test_cryptodev_hash_test_vectors.h       |   72 +-
 40 files changed, 8214 insertions(+), 63 deletions(-)
 create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
 create mode 100644 doc/guides/cryptodevs/octeontx.rst
 create mode 100644 drivers/common/cpt/Makefile
 create mode 100644 drivers/common/cpt/cpt_common.h
 create mode 100644 drivers/common/cpt/cpt_hw_types.h
 create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
 create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
 create mode 100644 drivers/common/cpt/cpt_request_mgr.h
 create mode 100644 drivers/common/cpt/cpt_ucode.h
 create mode 100644 drivers/common/cpt/meson.build
 create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
 create mode 100644 drivers/crypto/octeontx/Makefile
 create mode 100644 drivers/crypto/octeontx/meson.build
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
 create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map

-- 
2.7.4

[dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

This adds Makefile, meson.build and config file options.
Also adds the version map files and maintainers
file to claim responsibility.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 MAINTAINERS                                        |  7 ++++
 config/common_base                                 |  5 +++
 drivers/crypto/Makefile                            |  1 +
 drivers/crypto/meson.build                         |  2 +-
 drivers/crypto/octeontx/Makefile                   | 37 ++++++++++++++++++++++
 drivers/crypto/octeontx/meson.build                | 12 +++++++
 .../octeontx/rte_pmd_octeontx_crypto_version.map   |  4 +++
 mk/rte.app.mk                                      |  1 +
 8 files changed, 68 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/octeontx/Makefile
 create mode 100644 drivers/crypto/octeontx/meson.build
 create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 9fd258f..09548fa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -771,6 +771,13 @@ F: drivers/crypto/armv8/
 F: doc/guides/cryptodevs/armv8.rst
 F: doc/guides/cryptodevs/features/armv8.ini
 
+Cavium OcteonTX
+M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
+F: drivers/common/cpt/
+F: drivers/crypto/octeontx/
+F: doc/guides/cryptodevs/octeontx.rst
+F: doc/guides/cryptodevs/features/octeontx.ini
+
 Crypto Scheduler
 M: Fan Zhang <roy.fan.zhang@intel.com>
 F: drivers/crypto/scheduler/
diff --git a/config/common_base b/config/common_base
index 4bcbaf9..4c6a951 100644
--- a/config/common_base
+++ b/config/common_base
@@ -635,6 +635,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
 CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
 
 #
+# Compile PMD for Cavium OcteonTX crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
+
+#
 # Compile raw device support
 # EXPERIMENTAL: API may change without prior notice
 #
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index c480cbd..c083e64 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -7,6 +7,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += aesni_gcm
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index d64ca41..2187870 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -2,7 +2,7 @@
 # Copyright(c) 2017 Intel Corporation
 
 drivers = ['ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam',
-	'null', 'openssl', 'qat', 'virtio']
+	'null', 'octeontx', 'openssl', 'qat', 'virtio']
 
 std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
 config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
new file mode 100644
index 0000000..65bd02f
--- /dev/null
+++ b/drivers/crypto/octeontx/Makefile
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_octeontx_crypto.a
+
+# library version
+LIBABIVER := 1
+
+# build flags
+CFLAGS += $(WERROR_FLAGS)
+
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_cryptodev
+LDLIBS += -lrte_pci -lrte_bus_pci
+
+VPATH += $(RTE_SDK)/drivers/crypto/octeontx
+
+CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX
+
+# export include files
+SYMLINK-y-include +=
+
+# versioning export map
+EXPORT_MAP := rte_pmd_octeontx_crypto_version.map
+
+# library dependencies
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_eal
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_cryptodev
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mempool
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mbuf
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_malloc
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
new file mode 100644
index 0000000..261bb77
--- /dev/null
+++ b/drivers/crypto/octeontx/meson.build
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+if host_machine.system() != 'linux'
+	build = false
+endif
+
+deps += ['bus_pci']
+name = 'octeontx_crypto'
+
+sources = files()
+
+cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
diff --git a/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
new file mode 100644
index 0000000..521e51f
--- /dev/null
+++ b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
@@ -0,0 +1,4 @@
+DPDK_18.11 {
+
+	local: *;
+};
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index de33883..b530337 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -211,6 +211,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC)         += -L$(LIBSSO_ZUC_PATH)/build -lsso
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -lrte_pmd_armv8
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler
 ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC)   += -lrte_pmd_dpaa2_sec
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Akhil Goyal]

Hi Anoob,

On 9/4/2018 9:28 AM, Anoob Joseph wrote:

> From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>
> This adds Makefile, meson.build and config file options.
> Also adds the version map files and maintainers
> file to claim responsibility.
>
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
> ---
>   MAINTAINERS                                        |  7 ++++
>   config/common_base                                 |  5 +++
>   drivers/crypto/Makefile                            |  1 +
>   drivers/crypto/meson.build                         |  2 +-
>   drivers/crypto/octeontx/Makefile                   | 37 ++++++++++++++++++++++
>   drivers/crypto/octeontx/meson.build                | 12 +++++++
>   .../octeontx/rte_pmd_octeontx_crypto_version.map   |  4 +++
>   mk/rte.app.mk                                      |  1 +
>   8 files changed, 68 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/crypto/octeontx/Makefile
>   create mode 100644 drivers/crypto/octeontx/meson.build
>   create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9fd258f..09548fa 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -771,6 +771,13 @@ F: drivers/crypto/armv8/
>   F: doc/guides/cryptodevs/armv8.rst
>   F: doc/guides/cryptodevs/features/armv8.ini
>   
> +Cavium OcteonTX
> +M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> +F: drivers/common/cpt/
> +F: drivers/crypto/octeontx/
> +F: doc/guides/cryptodevs/octeontx.rst
> +F: doc/guides/cryptodevs/features/octeontx.ini

octeontx.rst and octeontx.ini does not exist. Please update MAINTAINERS in
the patch which is adding this file.

> +
>   Crypto Scheduler
>   M: Fan Zhang <roy.fan.zhang@intel.com>
>   F: drivers/crypto/scheduler/
> diff --git a/config/common_base b/config/common_base
> index 4bcbaf9..4c6a951 100644
> --- a/config/common_base
> +++ b/config/common_base
> @@ -635,6 +635,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
>   CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
>   
>   #
> +# Compile PMD for Cavium OcteonTX crypto device
> +#
> +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
> +
> +#
>   # Compile raw device support
>   # EXPERIMENTAL: API may change without prior notice
>   #
> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
> index c480cbd..c083e64 100644
> --- a/drivers/crypto/Makefile
> +++ b/drivers/crypto/Makefile
> @@ -7,6 +7,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += aesni_gcm
>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb
>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8
>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp
> +DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx
>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl
>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
> diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
> index d64ca41..2187870 100644
> --- a/drivers/crypto/meson.build
> +++ b/drivers/crypto/meson.build
> @@ -2,7 +2,7 @@
>   # Copyright(c) 2017 Intel Corporation
>   
>   drivers = ['ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam',
> -	'null', 'openssl', 'qat', 'virtio']
> +	'null', 'octeontx', 'openssl', 'qat', 'virtio']
>   
>   std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
>   config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
> diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
> new file mode 100644
> index 0000000..65bd02f
> --- /dev/null
> +++ b/drivers/crypto/octeontx/Makefile
> @@ -0,0 +1,37 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Cavium, Inc
> +#
> +
> +include $(RTE_SDK)/mk/rte.vars.mk
> +
> +# library name
> +LIB = librte_pmd_octeontx_crypto.a
> +
> +# library version
> +LIBABIVER := 1
> +
> +# build flags
> +CFLAGS += $(WERROR_FLAGS)
> +
> +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
> +LDLIBS += -lrte_cryptodev
> +LDLIBS += -lrte_pci -lrte_bus_pci
> +
> +VPATH += $(RTE_SDK)/drivers/crypto/octeontx
> +
> +CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX
> +
> +# export include files
> +SYMLINK-y-include +=
> +
> +# versioning export map
> +EXPORT_MAP := rte_pmd_octeontx_crypto_version.map
> +
> +# library dependencies
> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_eal
> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_cryptodev
> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mempool
> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mbuf
> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_malloc
> +
> +include $(RTE_SDK)/mk/rte.lib.mk
> diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
> new file mode 100644
> index 0000000..261bb77
> --- /dev/null
> +++ b/drivers/crypto/octeontx/meson.build
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Cavium, Inc
> +if host_machine.system() != 'linux'
> +	build = false
> +endif
> +
> +deps += ['bus_pci']
> +name = 'octeontx_crypto'
> +
> +sources = files()
> +
> +cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
> diff --git a/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
> new file mode 100644
> index 0000000..521e51f
> --- /dev/null
> +++ b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
> @@ -0,0 +1,4 @@
> +DPDK_18.11 {
> +
> +	local: *;
> +};
> diff --git a/mk/rte.app.mk b/mk/rte.app.mk
> index de33883..b530337 100644
> --- a/mk/rte.app.mk
> +++ b/mk/rte.app.mk
> @@ -211,6 +211,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC)         += -L$(LIBSSO_ZUC_PATH)/build -lsso
>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -lrte_pmd_armv8
>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto
>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk
> +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto
>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler
>   ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)
>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC)   += -lrte_pmd_dpaa2_sec
>
I think it would be better to squash the makefile related changes in the 3/33 patch as the code

is actually added in that and here the code is not getting compiled here.

-Akhil

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Joseph, Anoob]

Hi Akhil,

Please see inline.

Thanks,
Anoob

On 14-09-2018 17:41, Akhil Goyal wrote:
> External Email
>
> Hi Anoob,
>
> On 9/4/2018 9:28 AM, Anoob Joseph wrote:
>
>> From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>>
>> This adds Makefile, meson.build and config file options.
>> Also adds the version map files and maintainers
>> file to claim responsibility.
>>
>> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
>> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
>> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
>> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
>> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
>> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
>> ---
>>   MAINTAINERS                                        |  7 ++++
>>   config/common_base                                 |  5 +++
>>   drivers/crypto/Makefile                            |  1 +
>>   drivers/crypto/meson.build                         |  2 +-
>>   drivers/crypto/octeontx/Makefile                   | 37 
>> ++++++++++++++++++++++
>>   drivers/crypto/octeontx/meson.build                | 12 +++++++
>>   .../octeontx/rte_pmd_octeontx_crypto_version.map   |  4 +++
>>   mk/rte.app.mk                                      |  1 +
>>   8 files changed, 68 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/crypto/octeontx/Makefile
>>   create mode 100644 drivers/crypto/octeontx/meson.build
>>   create mode 100644 
>> drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 9fd258f..09548fa 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -771,6 +771,13 @@ F: drivers/crypto/armv8/
>>   F: doc/guides/cryptodevs/armv8.rst
>>   F: doc/guides/cryptodevs/features/armv8.ini
>>
>> +Cavium OcteonTX
>> +M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
>> +F: drivers/common/cpt/
>> +F: drivers/crypto/octeontx/
>> +F: doc/guides/cryptodevs/octeontx.rst
>> +F: doc/guides/cryptodevs/features/octeontx.ini
>
> octeontx.rst and octeontx.ini does not exist. Please update 
> MAINTAINERS in
> the patch which is adding this file.
Will do so.
>
>> +
>>   Crypto Scheduler
>>   M: Fan Zhang <roy.fan.zhang@intel.com>
>>   F: drivers/crypto/scheduler/
>> diff --git a/config/common_base b/config/common_base
>> index 4bcbaf9..4c6a951 100644
>> --- a/config/common_base
>> +++ b/config/common_base
>> @@ -635,6 +635,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
>>   CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
>>
>>   #
>> +# Compile PMD for Cavium OcteonTX crypto device
>> +#
>> +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
>> +
>> +#
>>   # Compile raw device support
>>   # EXPERIMENTAL: API may change without prior notice
>>   #
>> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
>> index c480cbd..c083e64 100644
>> --- a/drivers/crypto/Makefile
>> +++ b/drivers/crypto/Makefile
>> @@ -7,6 +7,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += aesni_gcm
>>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb
>>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8
>>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp
>> +DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx
>>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl
>>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
>>   DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
>> diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
>> index d64ca41..2187870 100644
>> --- a/drivers/crypto/meson.build
>> +++ b/drivers/crypto/meson.build
>> @@ -2,7 +2,7 @@
>>   # Copyright(c) 2017 Intel Corporation
>>
>>   drivers = ['ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam',
>> -     'null', 'openssl', 'qat', 'virtio']
>> +     'null', 'octeontx', 'openssl', 'qat', 'virtio']
>>
>>   std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
>>   config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
>> diff --git a/drivers/crypto/octeontx/Makefile 
>> b/drivers/crypto/octeontx/Makefile
>> new file mode 100644
>> index 0000000..65bd02f
>> --- /dev/null
>> +++ b/drivers/crypto/octeontx/Makefile
>> @@ -0,0 +1,37 @@
>> +# SPDX-License-Identifier: BSD-3-Clause
>> +# Copyright(c) 2018 Cavium, Inc
>> +#
>> +
>> +include $(RTE_SDK)/mk/rte.vars.mk
>> +
>> +# library name
>> +LIB = librte_pmd_octeontx_crypto.a
>> +
>> +# library version
>> +LIBABIVER := 1
>> +
>> +# build flags
>> +CFLAGS += $(WERROR_FLAGS)
>> +
>> +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
>> +LDLIBS += -lrte_cryptodev
>> +LDLIBS += -lrte_pci -lrte_bus_pci
>> +
>> +VPATH += $(RTE_SDK)/drivers/crypto/octeontx
>> +
>> +CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX
>> +
>> +# export include files
>> +SYMLINK-y-include +=
>> +
>> +# versioning export map
>> +EXPORT_MAP := rte_pmd_octeontx_crypto_version.map
>> +
>> +# library dependencies
>> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_eal
>> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += 
>> lib/librte_cryptodev
>> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mempool
>> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mbuf
>> +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_malloc
>> +
>> +include $(RTE_SDK)/mk/rte.lib.mk
>> diff --git a/drivers/crypto/octeontx/meson.build 
>> b/drivers/crypto/octeontx/meson.build
>> new file mode 100644
>> index 0000000..261bb77
>> --- /dev/null
>> +++ b/drivers/crypto/octeontx/meson.build
>> @@ -0,0 +1,12 @@
>> +# SPDX-License-Identifier: BSD-3-Clause
>> +# Copyright(c) 2018 Cavium, Inc
>> +if host_machine.system() != 'linux'
>> +     build = false
>> +endif
>> +
>> +deps += ['bus_pci']
>> +name = 'octeontx_crypto'
>> +
>> +sources = files()
>> +
>> +cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
>> diff --git 
>> a/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map 
>> b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>> new file mode 100644
>> index 0000000..521e51f
>> --- /dev/null
>> +++ b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>> @@ -0,0 +1,4 @@
>> +DPDK_18.11 {
>> +
>> +     local: *;
>> +};
>> diff --git a/mk/rte.app.mk b/mk/rte.app.mk
>> index de33883..b530337 100644
>> --- a/mk/rte.app.mk
>> +++ b/mk/rte.app.mk
>> @@ -211,6 +211,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += 
>> -L$(LIBSSO_ZUC_PATH)/build -lsso
>>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -lrte_pmd_armv8
>>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += 
>> -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto
>>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += 
>> -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk
>> +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += 
>> -lrte_pmd_octeontx_crypto
>>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += 
>> -lrte_pmd_crypto_scheduler
>>   ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)
>>   _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC)   += -lrte_pmd_dpaa2_sec
>>
> I think it would be better to squash the makefile related changes in 
> the 3/33 patch as the code
>
> is actually added in that and here the code is not getting compiled here.
So the changes in the following files has to be moved to patch 3/33?
   drivers/crypto/Makefile
   drivers/crypto/meson.build
   drivers/crypto/octeontx/Makefile
   drivers/crypto/octeontx/meson.build
   mk/rte.app.mk

I think this patch will just have MAINTAINER edit (even that might be 
required to be moved to 3/33?) & changes to config/common_base, after 
that. Is that fine?
>
> -Akhil
>

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Akhil Goyal]

>>>
>> I think it would be better to squash the makefile related changes in 
>> the 3/33 patch as the code
>>
>> is actually added in that and here the code is not getting compiled 
>> here.
> So the changes in the following files has to be moved to patch 3/33?
>   drivers/crypto/Makefile
>   drivers/crypto/meson.build
>   drivers/crypto/octeontx/Makefile
>   drivers/crypto/octeontx/meson.build
>   mk/rte.app.mk
>
> I think this patch will just have MAINTAINER edit (even that might be 
> required to be moved to 3/33?) & changes to config/common_base, after 
> that. Is that fine?
In my opinion, you do not need this patch as separate one. 
config/common_base can also be added in the 3/33.
>>
>> -Akhil
>>
>

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Joseph, Anoob]

Hi Akhil,

On 17-09-2018 16:07, Akhil Goyal wrote:
> External Email
>
>>>>
>>> I think it would be better to squash the makefile related changes in
>>> the 3/33 patch as the code
>>>
>>> is actually added in that and here the code is not getting compiled
>>> here.
>> So the changes in the following files has to be moved to patch 3/33?
>>   drivers/crypto/Makefile
>>   drivers/crypto/meson.build
>>   drivers/crypto/octeontx/Makefile
>>   drivers/crypto/octeontx/meson.build
>>   mk/rte.app.mk
>>
>> I think this patch will just have MAINTAINER edit (even that might be
>> required to be moved to 3/33?) & changes to config/common_base, after
>> that. Is that fine?
> In my opinion, you do not need this patch as separate one.
> config/common_base can also be added in the 3/33.
In that case 02/33 patch would become the first patch right? The same 
problem would be there too, I guess. The macros added in that patch gets 
used only in 03/33 patch. Is that fine?

The first patch would be a shell patch for most PMD additions. That's 
the reason we started this way. If you want it changed, will do so. 
Please do let me know what will be the right approach.

Anoob

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Akhil Goyal]

On 9/17/2018 5:12 PM, Joseph, Anoob wrote:

> Hi Akhil,
> On 17-09-2018 16:07, Akhil Goyal wrote:
>> External Email
>>>> I think it would be better to squash the makefile related changes in
>>>> the 3/33 patch as the code
>>>> is actually added in that and here the code is not getting compiled
>>>> here.
>>> So the changes in the following files has to be moved to patch 3/33?
>>>    drivers/crypto/Makefile
>>>    drivers/crypto/meson.build
>>>    drivers/crypto/octeontx/Makefile
>>>    drivers/crypto/octeontx/meson.build
>>>    mk/rte.app.mk
>>> I think this patch will just have MAINTAINER edit (even that might be
>>> required to be moved to 3/33?) & changes to config/common_base, after
>>> that. Is that fine?
>> In my opinion, you do not need this patch as separate one.
>> config/common_base can also be added in the 3/33.
> In that case 02/33 patch would become the first patch right? The same
> problem would be there too, I guess. The macros added in that patch gets
> used only in 03/33 patch. Is that fine?

I think that would be fine. Better to have a 03/33 patch before 02/33 if it doesn't have dependencies.

> The first patch would be a shell patch for most PMD additions. That's
> the reason we started this way. If you want it changed, will do so.
> Please do let me know what will be the right approach.

For the makefiles, you would be compiling the empty files which does not have any code. That does not make any sense to me.

Normally, when we submit a new PMD, we add the basic PMD probe/remove in the first patch and add it into build system. Maintainers is also updated for the new PMD.

Further ops are added later in the patchset.

Hardware specific header files/ functions are added before they are used in the driver in a single/multiple logical patches.

In the end, documentation is added along with release note and MAINTAINERS update for documentation files.

- Akhil

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Joseph, Anoob]

Hi Akhil,


On 17-09-2018 17:50, Akhil Goyal wrote:
> External Email
>
> On 9/17/2018 5:12 PM, Joseph, Anoob wrote:
>
>> Hi Akhil,
>> On 17-09-2018 16:07, Akhil Goyal wrote:
>>> External Email
>>>>> I think it would be better to squash the makefile related changes in
>>>>> the 3/33 patch as the code
>>>>> is actually added in that and here the code is not getting compiled
>>>>> here.
>>>> So the changes in the following files has to be moved to patch 3/33?
>>>>    drivers/crypto/Makefile
>>>>    drivers/crypto/meson.build
>>>>    drivers/crypto/octeontx/Makefile
>>>>    drivers/crypto/octeontx/meson.build
>>>>    mk/rte.app.mk
>>>> I think this patch will just have MAINTAINER edit (even that might be
>>>> required to be moved to 3/33?) & changes to config/common_base, after
>>>> that. Is that fine?
>>> In my opinion, you do not need this patch as separate one.
>>> config/common_base can also be added in the 3/33.
>> In that case 02/33 patch would become the first patch right? The same
>> problem would be there too, I guess. The macros added in that patch gets
>> used only in 03/33 patch. Is that fine?
>
> I think that would be fine. Better to have a 03/33 patch before 02/33 
> if it doesn't have dependencies.
03/33 patch is dependent on 02/33 patch. Shall I proceed with merging 
01/33 to 03/33 and make 02/33 the first patch?
>
>> The first patch would be a shell patch for most PMD additions. That's
>> the reason we started this way. If you want it changed, will do so.
>> Please do let me know what will be the right approach.
>
> For the makefiles, you would be compiling the empty files which does 
> not have any code. That does not make any sense to me.
With 01/33 there won't be any files compiled. We are just adding the 
library (which would be empty)
>
> Normally, when we submit a new PMD, we add the basic PMD probe/remove 
> in the first patch and add it into build system. Maintainers is also 
> updated for the new PMD.
>
> Further ops are added later in the patchset.
>
> Hardware specific header files/ functions are added before they are 
> used in the driver in a single/multiple logical patches.
>
> In the end, documentation is added along with release note and 
> MAINTAINERS update for documentation files.
I shall proceed with merging 01/33 to 03/33, if you can confirm making 
02/33 the first patch is fine. Or please do let me know if you have any 
other suggestions.

Anoob

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Thomas Monjalon]

17/09/2018 16:13, Joseph, Anoob:
> On 17-09-2018 17:50, Akhil Goyal wrote:
> > On 9/17/2018 5:12 PM, Joseph, Anoob wrote:
> >> On 17-09-2018 16:07, Akhil Goyal wrote:
> >>>>> I think it would be better to squash the makefile related changes in
> >>>>> the 3/33 patch as the code
> >>>>> is actually added in that and here the code is not getting compiled
> >>>>> here.
> >>>> So the changes in the following files has to be moved to patch 3/33?
> >>>>    drivers/crypto/Makefile
> >>>>    drivers/crypto/meson.build
> >>>>    drivers/crypto/octeontx/Makefile
> >>>>    drivers/crypto/octeontx/meson.build
> >>>>    mk/rte.app.mk
> >>>> I think this patch will just have MAINTAINER edit (even that might be
> >>>> required to be moved to 3/33?) & changes to config/common_base, after
> >>>> that. Is that fine?
> >>> In my opinion, you do not need this patch as separate one.
> >>> config/common_base can also be added in the 3/33.
> >> In that case 02/33 patch would become the first patch right? The same
> >> problem would be there too, I guess. The macros added in that patch gets
> >> used only in 03/33 patch. Is that fine?
> >
> > I think that would be fine. Better to have a 03/33 patch before 02/33 
> > if it doesn't have dependencies.
> 03/33 patch is dependent on 02/33 patch. Shall I proceed with merging 
> 01/33 to 03/33 and make 02/33 the first patch?

You should start by introducing common code directory.
Then you introduce the PMD directory with minimal code in it.

Question: what means "cpt"?
Why it is not an "octeontx" common directory?

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Joseph, Anoob]

Hi Thomas,


On 17-09-2018 20:06, Thomas Monjalon wrote:
> External Email
>
> 17/09/2018 16:13, Joseph, Anoob:
>> On 17-09-2018 17:50, Akhil Goyal wrote:
>>> On 9/17/2018 5:12 PM, Joseph, Anoob wrote:
>>>> On 17-09-2018 16:07, Akhil Goyal wrote:
>>>>>>> I think it would be better to squash the makefile related changes in
>>>>>>> the 3/33 patch as the code
>>>>>>> is actually added in that and here the code is not getting compiled
>>>>>>> here.
>>>>>> So the changes in the following files has to be moved to patch 3/33?
>>>>>>     drivers/crypto/Makefile
>>>>>>     drivers/crypto/meson.build
>>>>>>     drivers/crypto/octeontx/Makefile
>>>>>>     drivers/crypto/octeontx/meson.build
>>>>>>     mk/rte.app.mk
>>>>>> I think this patch will just have MAINTAINER edit (even that might be
>>>>>> required to be moved to 3/33?) & changes to config/common_base, after
>>>>>> that. Is that fine?
>>>>> In my opinion, you do not need this patch as separate one.
>>>>> config/common_base can also be added in the 3/33.
>>>> In that case 02/33 patch would become the first patch right? The same
>>>> problem would be there too, I guess. The macros added in that patch gets
>>>> used only in 03/33 patch. Is that fine?
>>> I think that would be fine. Better to have a 03/33 patch before 02/33
>>> if it doesn't have dependencies.
>> 03/33 patch is dependent on 02/33 patch. Shall I proceed with merging
>> 01/33 to 03/33 and make 02/33 the first patch?
> You should start by introducing common code directory.
> Then you introduce the PMD directory with minimal code in it.
Understood.
> Question: what means "cpt"?
> Why it is not an "octeontx" common directory?
CPT is the cryptographic engine in OcteonTX family. This dir will have 
the common code that will be shared between octeontx and other 
processors with similar engine. The directory "common/octeontx" is for 
common code shared by different components of the same chip(octeontx). 
Here it's the code for same engine across multiple platforms.

Anoob

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Akhil Goyal]

Hi Anoob,

On 9/17/2018 7:43 PM, Joseph, Anoob wrote:
> Hi Akhil,
>
>
> On 17-09-2018 17:50, Akhil Goyal wrote:
>> External Email
>>
>> On 9/17/2018 5:12 PM, Joseph, Anoob wrote:
>>
>>> Hi Akhil,
>>> On 17-09-2018 16:07, Akhil Goyal wrote:
>>>> External Email
>>>>>> I think it would be better to squash the makefile related changes in
>>>>>> the 3/33 patch as the code
>>>>>> is actually added in that and here the code is not getting compiled
>>>>>> here.
>>>>> So the changes in the following files has to be moved to patch 3/33?
>>>>>    drivers/crypto/Makefile
>>>>>    drivers/crypto/meson.build
>>>>>    drivers/crypto/octeontx/Makefile
>>>>>    drivers/crypto/octeontx/meson.build
>>>>>    mk/rte.app.mk
>>>>> I think this patch will just have MAINTAINER edit (even that might be
>>>>> required to be moved to 3/33?) & changes to config/common_base, after
>>>>> that. Is that fine?
>>>> In my opinion, you do not need this patch as separate one.
>>>> config/common_base can also be added in the 3/33.
>>> In that case 02/33 patch would become the first patch right? The same
>>> problem would be there too, I guess. The macros added in that patch 
>>> gets
>>> used only in 03/33 patch. Is that fine?
>>
>> I think that would be fine. Better to have a 03/33 patch before 02/33 
>> if it doesn't have dependencies.
> 03/33 patch is dependent on 02/33 patch. Shall I proceed with merging 
> 01/33 to 03/33 and make 02/33 the first patch?
>>
>>> The first patch would be a shell patch for most PMD additions. That's
>>> the reason we started this way. If you want it changed, will do so.
>>> Please do let me know what will be the right approach.
>>
>> For the makefiles, you would be compiling the empty files which does 
>> not have any code. That does not make any sense to me.
> With 01/33 there won't be any files compiled. We are just adding the 
> library (which would be empty)
>>
>> Normally, when we submit a new PMD, we add the basic PMD probe/remove 
>> in the first patch and add it into build system. Maintainers is also 
>> updated for the new PMD.
>>
>> Further ops are added later in the patchset.
>>
>> Hardware specific header files/ functions are added before they are 
>> used in the driver in a single/multiple logical patches.
>>
>> In the end, documentation is added along with release note and 
>> MAINTAINERS update for documentation files.
> I shall proceed with merging 01/33 to 03/33, if you can confirm making 
> 02/33 the first patch is fine. Or please do let me know if you have 
> any other suggestions.
>
I see that the 2/33 is adding the logging macros. I believe that can 
also be merged in the 03/33.
Also I missed one comment on the documentation patch.. Please add your 
pmd doc entry in index.rst as well.
> Anoob
>

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Joseph]

Hi Akhil,

On 18-09-2018 18:01, Akhil Goyal wrote:
> External Email
>
> Hi Anoob,
>
> On 9/17/2018 7:43 PM, Joseph, Anoob wrote:
>> Hi Akhil,
>>
>>
>> On 17-09-2018 17:50, Akhil Goyal wrote:
>>> External Email
>>>
>>> On 9/17/2018 5:12 PM, Joseph, Anoob wrote:
>>>
>>>> Hi Akhil,
>>>> On 17-09-2018 16:07, Akhil Goyal wrote:
>>>>> External Email
>>>>>>> I think it would be better to squash the makefile related 
>>>>>>> changes in
>>>>>>> the 3/33 patch as the code
>>>>>>> is actually added in that and here the code is not getting compiled
>>>>>>> here.
>>>>>> So the changes in the following files has to be moved to patch 3/33?
>>>>>>    drivers/crypto/Makefile
>>>>>>    drivers/crypto/meson.build
>>>>>>    drivers/crypto/octeontx/Makefile
>>>>>>    drivers/crypto/octeontx/meson.build
>>>>>>    mk/rte.app.mk
>>>>>> I think this patch will just have MAINTAINER edit (even that 
>>>>>> might be
>>>>>> required to be moved to 3/33?) & changes to config/common_base, 
>>>>>> after
>>>>>> that. Is that fine?
>>>>> In my opinion, you do not need this patch as separate one.
>>>>> config/common_base can also be added in the 3/33.
>>>> In that case 02/33 patch would become the first patch right? The same
>>>> problem would be there too, I guess. The macros added in that patch
>>>> gets
>>>> used only in 03/33 patch. Is that fine?
>>>
>>> I think that would be fine. Better to have a 03/33 patch before 02/33
>>> if it doesn't have dependencies.
>> 03/33 patch is dependent on 02/33 patch. Shall I proceed with merging
>> 01/33 to 03/33 and make 02/33 the first patch?
>>>
>>>> The first patch would be a shell patch for most PMD additions. That's
>>>> the reason we started this way. If you want it changed, will do so.
>>>> Please do let me know what will be the right approach.
>>>
>>> For the makefiles, you would be compiling the empty files which does
>>> not have any code. That does not make any sense to me.
>> With 01/33 there won't be any files compiled. We are just adding the
>> library (which would be empty)
>>>
>>> Normally, when we submit a new PMD, we add the basic PMD probe/remove
>>> in the first patch and add it into build system. Maintainers is also
>>> updated for the new PMD.
>>>
>>> Further ops are added later in the patchset.
>>>
>>> Hardware specific header files/ functions are added before they are
>>> used in the driver in a single/multiple logical patches.
>>>
>>> In the end, documentation is added along with release note and
>>> MAINTAINERS update for documentation files.
>> I shall proceed with merging 01/33 to 03/33, if you can confirm making
>> 02/33 the first patch is fine. Or please do let me know if you have
>> any other suggestions.
>>
> I see that the 2/33 is adding the logging macros. I believe that can
> also be merged in the 03/33.
./devtools/check-git-log.sh was giving me issues when one patch was 
having edits in both drivers/common/cpt & drivers/crypto/octeontx. 
That's the reason it was separated out. Many patches had to be divided 
because of this.
> Also I missed one comment on the documentation patch.. Please add your
> pmd doc entry in index.rst as well.
Will fix this in v3.

Thanks,
Anoob

Re: [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton

[Akhil Goyal]

On 9/18/2018 6:10 PM, Joseph@dpdk.org wrote:
> Hi Akhil,
>
> On 18-09-2018 18:01, Akhil Goyal wrote:
>> External Email
>>
>> Hi Anoob,
>>
>> On 9/17/2018 7:43 PM, Joseph, Anoob wrote:
>>> Hi Akhil,
>>>
>>>
>>> On 17-09-2018 17:50, Akhil Goyal wrote:
>>>> External Email
>>>>
>>>> On 9/17/2018 5:12 PM, Joseph, Anoob wrote:
>>>>
>>>>> Hi Akhil,
>>>>> On 17-09-2018 16:07, Akhil Goyal wrote:
>>>>>> External Email
>>>>>>>> I think it would be better to squash the makefile related
>>>>>>>> changes in
>>>>>>>> the 3/33 patch as the code
>>>>>>>> is actually added in that and here the code is not getting compiled
>>>>>>>> here.
>>>>>>> So the changes in the following files has to be moved to patch 3/33?
>>>>>>>     drivers/crypto/Makefile
>>>>>>>     drivers/crypto/meson.build
>>>>>>>     drivers/crypto/octeontx/Makefile
>>>>>>>     drivers/crypto/octeontx/meson.build
>>>>>>>     mk/rte.app.mk
>>>>>>> I think this patch will just have MAINTAINER edit (even that
>>>>>>> might be
>>>>>>> required to be moved to 3/33?) & changes to config/common_base,
>>>>>>> after
>>>>>>> that. Is that fine?
>>>>>> In my opinion, you do not need this patch as separate one.
>>>>>> config/common_base can also be added in the 3/33.
>>>>> In that case 02/33 patch would become the first patch right? The same
>>>>> problem would be there too, I guess. The macros added in that patch
>>>>> gets
>>>>> used only in 03/33 patch. Is that fine?
>>>> I think that would be fine. Better to have a 03/33 patch before 02/33
>>>> if it doesn't have dependencies.
>>> 03/33 patch is dependent on 02/33 patch. Shall I proceed with merging
>>> 01/33 to 03/33 and make 02/33 the first patch?
>>>>> The first patch would be a shell patch for most PMD additions. That's
>>>>> the reason we started this way. If you want it changed, will do so.
>>>>> Please do let me know what will be the right approach.
>>>> For the makefiles, you would be compiling the empty files which does
>>>> not have any code. That does not make any sense to me.
>>> With 01/33 there won't be any files compiled. We are just adding the
>>> library (which would be empty)
>>>> Normally, when we submit a new PMD, we add the basic PMD probe/remove
>>>> in the first patch and add it into build system. Maintainers is also
>>>> updated for the new PMD.
>>>>
>>>> Further ops are added later in the patchset.
>>>>
>>>> Hardware specific header files/ functions are added before they are
>>>> used in the driver in a single/multiple logical patches.
>>>>
>>>> In the end, documentation is added along with release note and
>>>> MAINTAINERS update for documentation files.
>>> I shall proceed with merging 01/33 to 03/33, if you can confirm making
>>> 02/33 the first patch is fine. Or please do let me know if you have
>>> any other suggestions.
>>>
>> I see that the 2/33 is adding the logging macros. I believe that can
>> also be merged in the 03/33.
> ./devtools/check-git-log.sh was giving me issues when one patch was
> having edits in both drivers/common/cpt & drivers/crypto/octeontx.
> That's the reason it was separated out. Many patches had to be divided
> because of this.
Oh,  my bad... I missed that this is a separate driver. I thought it was 
for the same driver.
It would be fine to have 02/33 as your first patch as Thomas also suggested.
>> Also I missed one comment on the documentation patch.. Please add your
>> pmd doc entry in index.rst as well.
> Will fix this in v3.
>
> Thanks,
> Anoob

[dpdk-dev] [PATCH v2 02/33] common/cpt: add common logging support

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Add common logging macros

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_pmd_logs.h | 52 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 drivers/common/cpt/cpt_pmd_logs.h

diff --git a/drivers/common/cpt/cpt_pmd_logs.h b/drivers/common/cpt/cpt_pmd_logs.h
new file mode 100644
index 0000000..e1bfbb3
--- /dev/null
+++ b/drivers/common/cpt/cpt_pmd_logs.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_PMD_LOGS_H_
+#define _CPT_PMD_LOGS_H_
+
+#include <rte_log.h>
+
+/*
+ * This file defines log macros
+ */
+
+#define CPT_PMD_DRV_LOG_RAW(level, fmt, args...) \
+		rte_log(RTE_LOG_ ## level, cpt_logtype, \
+			"cpt: %s(): " fmt "\n", __func__, ##args)
+
+#define CPT_PMD_INIT_FUNC_TRACE() CPT_PMD_DRV_LOG_RAW(DEBUG, " >>")
+#define CPT_PMD_DRV_LOG(level, args...) \
+	CPT_PMD_DRV_LOG_RAW(level, ##args)
+
+#define CPT_LOG_INFO(fmt, args...) \
+	CPT_PMD_DRV_LOG_RAW(INFO, fmt, ## args)
+#define CPT_LOG_WARN(fmt, args...) \
+	CPT_PMD_DRV_LOG_RAW(WARNING, fmt, ## args)
+#define CPT_LOG_ERR(fmt, args...) \
+	CPT_PMD_DRV_LOG_RAW(ERR, fmt, ## args)
+
+/*
+ * DP logs, toggled out at compile time if level lower than current level.
+ * DP logs would be logged under 'PMD' type. So for dynamic logging, the
+ * level of 'pmd' has to be used.
+ */
+#define CPT_LOG_DP(level, fmt, args...) \
+	RTE_LOG_DP(level, PMD, fmt "\n", ## args)
+
+#define CPT_LOG_DP_DEBUG(fmt, args...) \
+	CPT_LOG_DP(DEBUG, fmt, ## args)
+#define CPT_LOG_DP_INFO(fmt, args...) \
+	CPT_LOG_DP(INFO, fmt, ## args)
+#define CPT_LOG_DP_WARN(fmt, args...) \
+	CPT_LOG_DP(WARNING, fmt, ## args)
+#define CPT_LOG_DP_ERR(fmt, args...) \
+	CPT_LOG_DP(ERR, fmt, ## args)
+
+/*
+ * cpt_logtype will be used for common logging. This field would be intiailized
+ * by otx_* driver routines during PCI probe.
+ */
+int cpt_logtype;
+
+#endif /* _CPT_PMD_LOGS_H_ */
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 02/33] common/cpt: add common logging support

[Akhil Goyal]

On 9/4/2018 9:28 AM, Anoob Joseph wrote:
> From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>
> Add common logging macros
>
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
> ---
>   drivers/common/cpt/cpt_pmd_logs.h | 52 +++++++++++++++++++++++++++++++++++++++
>   1 file changed, 52 insertions(+)
>   create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
>
> diff --git a/drivers/common/cpt/cpt_pmd_logs.h b/drivers/common/cpt/cpt_pmd_logs.h
> new file mode 100644
> index 0000000..e1bfbb3
> --- /dev/null
> +++ b/drivers/common/cpt/cpt_pmd_logs.h
> @@ -0,0 +1,52 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2018 Cavium, Inc
> + */
> +
> +#ifndef _CPT_PMD_LOGS_H_
> +#define _CPT_PMD_LOGS_H_
> +
> +#include <rte_log.h>
> +
> +/*
> + * This file defines log macros
> + */
> +
> +#define CPT_PMD_DRV_LOG_RAW(level, fmt, args...) \
> +		rte_log(RTE_LOG_ ## level, cpt_logtype, \
> +			"cpt: %s(): " fmt "\n", __func__, ##args)
> +
> +#define CPT_PMD_INIT_FUNC_TRACE() CPT_PMD_DRV_LOG_RAW(DEBUG, " >>")
> +#define CPT_PMD_DRV_LOG(level, args...) \
> +	CPT_PMD_DRV_LOG_RAW(level, ##args)
> +
> +#define CPT_LOG_INFO(fmt, args...) \
> +	CPT_PMD_DRV_LOG_RAW(INFO, fmt, ## args)
> +#define CPT_LOG_WARN(fmt, args...) \
> +	CPT_PMD_DRV_LOG_RAW(WARNING, fmt, ## args)
> +#define CPT_LOG_ERR(fmt, args...) \
> +	CPT_PMD_DRV_LOG_RAW(ERR, fmt, ## args)
> +
> +/*
> + * DP logs, toggled out at compile time if level lower than current level.
> + * DP logs would be logged under 'PMD' type. So for dynamic logging, the
> + * level of 'pmd' has to be used.
> + */
> +#define CPT_LOG_DP(level, fmt, args...) \
> +	RTE_LOG_DP(level, PMD, fmt "\n", ## args)
> +
> +#define CPT_LOG_DP_DEBUG(fmt, args...) \
> +	CPT_LOG_DP(DEBUG, fmt, ## args)
> +#define CPT_LOG_DP_INFO(fmt, args...) \
> +	CPT_LOG_DP(INFO, fmt, ## args)
> +#define CPT_LOG_DP_WARN(fmt, args...) \
> +	CPT_LOG_DP(WARNING, fmt, ## args)
> +#define CPT_LOG_DP_ERR(fmt, args...) \
> +	CPT_LOG_DP(ERR, fmt, ## args)
> +
> +/*
> + * cpt_logtype will be used for common logging. This field would be intiailized

typo intiailized

> + * by otx_* driver routines during PCI probe.
> + */
> +int cpt_logtype;
> +
> +#endif /* _CPT_PMD_LOGS_H_ */

[dpdk-dev] [PATCH v2 03/33] crypto/octeontx: add PCI probe and remove

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Adding basic PCI probe/remove functions for OcteonTX crypto device.
Initialization function for logging is also added.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile            |   5 ++
 drivers/crypto/octeontx/meson.build         |   4 +-
 drivers/crypto/octeontx/otx_cryptodev.c     | 132 ++++++++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev.h     |  20 +++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c |  15 ++++
 drivers/crypto/octeontx/otx_cryptodev_ops.h |  11 +++
 6 files changed, 186 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 65bd02f..12fec75 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -20,6 +20,11 @@ LDLIBS += -lrte_pci -lrte_bus_pci
 VPATH += $(RTE_SDK)/drivers/crypto/octeontx
 
 CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX
+CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
+
+# PMD code
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
 
 # export include files
 SYMLINK-y-include +=
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index 261bb77..6564090 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -7,6 +7,8 @@ endif
 deps += ['bus_pci']
 name = 'octeontx_crypto'
 
-sources = files()
+sources = files('otx_cryptodev.c',
+		'otx_cryptodev_ops.c')
 
 cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
+includes += include_directories('../../common/cpt')
diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c
new file mode 100644
index 0000000..df88a84
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev.c
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_log.h>
+#include <rte_pci.h>
+
+/* CPT common headers */
+#include "cpt_pmd_logs.h"
+
+#include "otx_cryptodev.h"
+#include "otx_cryptodev_ops.h"
+
+static int otx_cryptodev_logtype;
+
+static struct rte_pci_id pci_id_cpt_table[] = {
+	{
+		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_VF_DEVICE_ID),
+	},
+	/* sentinel */
+	{
+	.device_id = 0
+	},
+};
+
+static void
+otx_cpt_init_log(void)
+{
+	/* Bus level logs */
+	otx_cryptodev_logtype = rte_log_register("pmd.crypto.octeontx");
+	if (otx_cryptodev_logtype >= 0)
+		rte_log_set_level(otx_cryptodev_logtype, RTE_LOG_NOTICE);
+}
+
+static void
+otx_cpt_logtype_init(void)
+{
+	cpt_logtype = otx_cryptodev_logtype;
+}
+
+static int
+otx_cpt_pci_probe(struct rte_pci_driver *pci_drv,
+			struct rte_pci_device *pci_dev)
+{
+	struct rte_cryptodev *cryptodev;
+	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+	int retval;
+
+	if (pci_drv == NULL)
+		return -ENODEV;
+
+	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+	cryptodev = rte_cryptodev_pmd_allocate(name, rte_socket_id());
+	if (cryptodev == NULL)
+		return -ENOMEM;
+
+	cryptodev->device = &pci_dev->device;
+	cryptodev->device->driver = &pci_drv->driver;
+	cryptodev->driver_id = otx_cryptodev_driver_id;
+
+	/* init user callbacks */
+	TAILQ_INIT(&(cryptodev->link_intr_cbs));
+
+	/* init logtype used in common */
+	otx_cpt_logtype_init();
+
+	/* Invoke PMD device initialization function */
+	retval = otx_cpt_dev_create(cryptodev);
+	if (retval == 0)
+		return 0;
+
+	CPT_LOG_ERR("[DRV %s]: Failed to create device "
+			"(vendor_id: 0x%x device_id: 0x%x",
+			pci_drv->driver.name,
+			(unsigned int) pci_dev->id.vendor_id,
+			(unsigned int) pci_dev->id.device_id);
+
+	cryptodev->attached = RTE_CRYPTODEV_DETACHED;
+
+	return -ENXIO;
+}
+
+static int
+otx_cpt_pci_remove(struct rte_pci_device *pci_dev)
+{
+	struct rte_cryptodev *cryptodev;
+	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+
+	if (pci_dev == NULL)
+		return -EINVAL;
+
+	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+	cryptodev = rte_cryptodev_pmd_get_named_dev(name);
+	if (cryptodev == NULL)
+		return -ENODEV;
+
+	if (pci_dev->driver == NULL)
+		return -ENODEV;
+
+	/* free crypto device */
+	rte_cryptodev_pmd_release_device(cryptodev);
+
+	if (rte_eal_process_type() == RTE_PROC_PRIMARY)
+		rte_free(cryptodev->data->dev_private);
+
+	cryptodev->device = NULL;
+	cryptodev->device->driver = NULL;
+	cryptodev->data = NULL;
+
+	return 0;
+}
+
+static struct rte_pci_driver otx_cryptodev_pmd = {
+		.id_table = pci_id_cpt_table,
+		.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+		.probe = otx_cpt_pci_probe,
+		.remove = otx_cpt_pci_remove,
+};
+
+static struct cryptodev_driver otx_cryptodev_drv;
+
+RTE_INIT(otx_cpt_init_log);
+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX_PMD, otx_cryptodev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX_PMD, pci_id_cpt_table);
+RTE_PMD_REGISTER_CRYPTO_DRIVER(otx_cryptodev_drv, otx_cryptodev_pmd.driver,
+		otx_cryptodev_driver_id);
diff --git a/drivers/crypto/octeontx/otx_cryptodev.h b/drivers/crypto/octeontx/otx_cryptodev.h
new file mode 100644
index 0000000..99d3346
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_H_
+#define _OTX_CRYPTODEV_H_
+
+/* Cavium OcteonTX Crypto PMD device name */
+#define CRYPTODEV_NAME_OCTEONTX_PMD	crypto_octeontx
+
+/* Device ID */
+#define PCI_VENDOR_ID_CAVIUM		    0x177d
+#define CPT_81XX_PCI_VF_DEVICE_ID	    0xa041
+
+/*
+ * Crypto device driver ID
+ */
+uint8_t otx_cryptodev_driver_id;
+
+#endif /* _OTX_CRYPTODEV_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
new file mode 100644
index 0000000..1b5f108
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_cryptodev.h>
+
+#include "otx_cryptodev.h"
+#include "otx_cryptodev_ops.h"
+
+int
+otx_cpt_dev_create(struct rte_cryptodev *c_dev)
+{
+	RTE_SET_USED(c_dev);
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
new file mode 100644
index 0000000..3f2d829
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_OPS_H_
+#define _OTX_CRYPTODEV_OPS_H_
+
+int
+otx_cpt_dev_create(struct rte_cryptodev *c_dev);
+
+#endif /* _OTX_CRYPTODEV_OPS_H_ */
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 03/33] crypto/octeontx: add PCI probe and remove

[Akhil Goyal]

On 9/4/2018 9:28 AM, Anoob Joseph wrote:
> From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>
> Adding basic PCI probe/remove functions for OcteonTX crypto device.
> Initialization function for logging is also added.
>
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
> ---
>   drivers/crypto/octeontx/Makefile            |   5 ++
>   drivers/crypto/octeontx/meson.build         |   4 +-
>   drivers/crypto/octeontx/otx_cryptodev.c     | 132 ++++++++++++++++++++++++++++
>   drivers/crypto/octeontx/otx_cryptodev.h     |  20 +++++
>   drivers/crypto/octeontx/otx_cryptodev_ops.c |  15 ++++
>   drivers/crypto/octeontx/otx_cryptodev_ops.h |  11 +++
>   6 files changed, 186 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
>
> diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
> index 65bd02f..12fec75 100644
> --- a/drivers/crypto/octeontx/Makefile
> +++ b/drivers/crypto/octeontx/Makefile
> @@ -20,6 +20,11 @@ LDLIBS += -lrte_pci -lrte_bus_pci
>   VPATH += $(RTE_SDK)/drivers/crypto/octeontx
>   
>   CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX
> +CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
> +
> +# PMD code
> +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
> +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
>   
>   # export include files
>   SYMLINK-y-include +=
> diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
> index 261bb77..6564090 100644
> --- a/drivers/crypto/octeontx/meson.build
> +++ b/drivers/crypto/octeontx/meson.build
> @@ -7,6 +7,8 @@ endif
>   deps += ['bus_pci']
>   name = 'octeontx_crypto'
>   
> -sources = files()
> +sources = files('otx_cryptodev.c',
> +		'otx_cryptodev_ops.c')
>   
>   cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
> +includes += include_directories('../../common/cpt')
> diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c
> new file mode 100644
> index 0000000..df88a84
> --- /dev/null
> +++ b/drivers/crypto/octeontx/otx_cryptodev.c
> @@ -0,0 +1,132 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2018 Cavium, Inc
> + */
> +
> +#include <rte_bus_pci.h>
> +#include <rte_common.h>
> +#include <rte_cryptodev.h>
> +#include <rte_cryptodev_pmd.h>
> +#include <rte_log.h>
> +#include <rte_pci.h>
> +
> +/* CPT common headers */
> +#include "cpt_pmd_logs.h"
> +
> +#include "otx_cryptodev.h"
> +#include "otx_cryptodev_ops.h"
> +
> +static int otx_cryptodev_logtype;
> +
> +static struct rte_pci_id pci_id_cpt_table[] = {
> +	{
> +		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_VF_DEVICE_ID),
> +	},
> +	/* sentinel */
> +	{
> +	.device_id = 0
indentation
> +	},
> +};
> +
> +static void
> +otx_cpt_init_log(void)
> +{
> +	/* Bus level logs */
> +	otx_cryptodev_logtype = rte_log_register("pmd.crypto.octeontx");
> +	if (otx_cryptodev_logtype >= 0)
> +		rte_log_set_level(otx_cryptodev_logtype, RTE_LOG_NOTICE);
> +}
> +
> +static void
> +otx_cpt_logtype_init(void)
> +{
> +	cpt_logtype = otx_cryptodev_logtype;
> +}
> +
> +static int
> +otx_cpt_pci_probe(struct rte_pci_driver *pci_drv,
> +			struct rte_pci_device *pci_dev)
> +{
> +	struct rte_cryptodev *cryptodev;
> +	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
> +	int retval;
> +
> +	if (pci_drv == NULL)
> +		return -ENODEV;
> +
> +	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
> +
> +	cryptodev = rte_cryptodev_pmd_allocate(name, rte_socket_id());
> +	if (cryptodev == NULL)
> +		return -ENOMEM;
> +
> +	cryptodev->device = &pci_dev->device;
> +	cryptodev->device->driver = &pci_drv->driver;
> +	cryptodev->driver_id = otx_cryptodev_driver_id;
> +
> +	/* init user callbacks */
> +	TAILQ_INIT(&(cryptodev->link_intr_cbs));
> +
> +	/* init logtype used in common */
> +	otx_cpt_logtype_init();
> +
> +	/* Invoke PMD device initialization function */
> +	retval = otx_cpt_dev_create(cryptodev);
> +	if (retval == 0)
> +		return 0;
> +
> +	CPT_LOG_ERR("[DRV %s]: Failed to create device "
> +			"(vendor_id: 0x%x device_id: 0x%x",
> +			pci_drv->driver.name,
> +			(unsigned int) pci_dev->id.vendor_id,
> +			(unsigned int) pci_dev->id.device_id);
> +
> +	cryptodev->attached = RTE_CRYPTODEV_DETACHED;
> +
> +	return -ENXIO;
> +}
> +
> +static int
> +otx_cpt_pci_remove(struct rte_pci_device *pci_dev)
> +{
> +	struct rte_cryptodev *cryptodev;
> +	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
> +
> +	if (pci_dev == NULL)
> +		return -EINVAL;
> +
> +	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
> +
> +	cryptodev = rte_cryptodev_pmd_get_named_dev(name);
> +	if (cryptodev == NULL)
> +		return -ENODEV;
> +
> +	if (pci_dev->driver == NULL)
> +		return -ENODEV;
> +
> +	/* free crypto device */
> +	rte_cryptodev_pmd_release_device(cryptodev);
> +
> +	if (rte_eal_process_type() == RTE_PROC_PRIMARY)
> +		rte_free(cryptodev->data->dev_private);
> +
> +	cryptodev->device = NULL;
> +	cryptodev->device->driver = NULL;
> +	cryptodev->data = NULL;
> +
> +	return 0;
> +}
> +
> +static struct rte_pci_driver otx_cryptodev_pmd = {
> +		.id_table = pci_id_cpt_table,
> +		.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
> +		.probe = otx_cpt_pci_probe,
> +		.remove = otx_cpt_pci_remove,
> +};
remove extra spaces/
> +
> +static struct cryptodev_driver otx_cryptodev_drv;
> +
> +RTE_INIT(otx_cpt_init_log);
> +RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX_PMD, otx_cryptodev_pmd);
> +RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX_PMD, pci_id_cpt_table);
> +RTE_PMD_REGISTER_CRYPTO_DRIVER(otx_cryptodev_drv, otx_cryptodev_pmd.driver,
> +		otx_cryptodev_driver_id);
> diff --git a/drivers/crypto/octeontx/otx_cryptodev.h b/drivers/crypto/octeontx/otx_cryptodev.h
> new file mode 100644
> index 0000000..99d3346
> --- /dev/null
> +++ b/drivers/crypto/octeontx/otx_cryptodev.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2018 Cavium, Inc
> + */
> +
> +#ifndef _OTX_CRYPTODEV_H_
> +#define _OTX_CRYPTODEV_H_
> +
> +/* Cavium OcteonTX Crypto PMD device name */
> +#define CRYPTODEV_NAME_OCTEONTX_PMD	crypto_octeontx
> +
> +/* Device ID */
> +#define PCI_VENDOR_ID_CAVIUM		    0x177d
> +#define CPT_81XX_PCI_VF_DEVICE_ID	    0xa041
> +
> +/*
> + * Crypto device driver ID
> + */
> +uint8_t otx_cryptodev_driver_id;
> +
> +#endif /* _OTX_CRYPTODEV_H_ */
> diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> new file mode 100644
> index 0000000..1b5f108
> --- /dev/null
> +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2018 Cavium, Inc
> + */
> +
> +#include <rte_cryptodev.h>
> +
> +#include "otx_cryptodev.h"
> +#include "otx_cryptodev_ops.h"
> +
> +int
> +otx_cpt_dev_create(struct rte_cryptodev *c_dev)
> +{
> +	RTE_SET_USED(c_dev);
> +	return 0;
> +}
> diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
> new file mode 100644
> index 0000000..3f2d829
> --- /dev/null
> +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2018 Cavium, Inc
> + */
> +
> +#ifndef _OTX_CRYPTODEV_OPS_H_
> +#define _OTX_CRYPTODEV_OPS_H_
> +
> +int
> +otx_cpt_dev_create(struct rte_cryptodev *c_dev);
> +
> +#endif /* _OTX_CRYPTODEV_OPS_H_ */

Re: [dpdk-dev] [PATCH v2 03/33] crypto/octeontx: add PCI probe and remove

[Joseph, Anoob]

Hi Akhil,

See inline.

Thanks,

Anoob


On 14-09-2018 18:09, Akhil Goyal wrote:
> External Email
>
> On 9/4/2018 9:28 AM, Anoob Joseph wrote:
>> From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>>
>> Adding basic PCI probe/remove functions for OcteonTX crypto device.
>> Initialization function for logging is also added.
>>
>> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
>> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
>> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
>> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
>> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
>> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
>> ---
>>   drivers/crypto/octeontx/Makefile            |   5 ++
>>   drivers/crypto/octeontx/meson.build         |   4 +-
>>   drivers/crypto/octeontx/otx_cryptodev.c     | 132 
>> ++++++++++++++++++++++++++++
>>   drivers/crypto/octeontx/otx_cryptodev.h     |  20 +++++
>>   drivers/crypto/octeontx/otx_cryptodev_ops.c |  15 ++++
>>   drivers/crypto/octeontx/otx_cryptodev_ops.h |  11 +++
>>   6 files changed, 186 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
>>
>> diff --git a/drivers/crypto/octeontx/Makefile 
>> b/drivers/crypto/octeontx/Makefile
>> index 65bd02f..12fec75 100644
>> --- a/drivers/crypto/octeontx/Makefile
>> +++ b/drivers/crypto/octeontx/Makefile
>> @@ -20,6 +20,11 @@ LDLIBS += -lrte_pci -lrte_bus_pci
>>   VPATH += $(RTE_SDK)/drivers/crypto/octeontx
>>
>>   CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX
>> +CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
>> +
>> +# PMD code
>> +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
>> +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
>>
>>   # export include files
>>   SYMLINK-y-include +=
>> diff --git a/drivers/crypto/octeontx/meson.build 
>> b/drivers/crypto/octeontx/meson.build
>> index 261bb77..6564090 100644
>> --- a/drivers/crypto/octeontx/meson.build
>> +++ b/drivers/crypto/octeontx/meson.build
>> @@ -7,6 +7,8 @@ endif
>>   deps += ['bus_pci']
>>   name = 'octeontx_crypto'
>>
>> -sources = files()
>> +sources = files('otx_cryptodev.c',
>> +             'otx_cryptodev_ops.c')
>>
>>   cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
>> +includes += include_directories('../../common/cpt')
>> diff --git a/drivers/crypto/octeontx/otx_cryptodev.c 
>> b/drivers/crypto/octeontx/otx_cryptodev.c
>> new file mode 100644
>> index 0000000..df88a84
>> --- /dev/null
>> +++ b/drivers/crypto/octeontx/otx_cryptodev.c
>> @@ -0,0 +1,132 @@
>> +/* SPDX-License-Identifier: BSD-3-Clause
>> + * Copyright(c) 2018 Cavium, Inc
>> + */
>> +
>> +#include <rte_bus_pci.h>
>> +#include <rte_common.h>
>> +#include <rte_cryptodev.h>
>> +#include <rte_cryptodev_pmd.h>
>> +#include <rte_log.h>
>> +#include <rte_pci.h>
>> +
>> +/* CPT common headers */
>> +#include "cpt_pmd_logs.h"
>> +
>> +#include "otx_cryptodev.h"
>> +#include "otx_cryptodev_ops.h"
>> +
>> +static int otx_cryptodev_logtype;
>> +
>> +static struct rte_pci_id pci_id_cpt_table[] = {
>> +     {
>> +             RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 
>> CPT_81XX_PCI_VF_DEVICE_ID),
>> +     },
>> +     /* sentinel */
>> +     {
>> +     .device_id = 0
> indentation
Will fix it.
>> +     },
>> +};
>> +
>> +static void
>> +otx_cpt_init_log(void)
>> +{
>> +     /* Bus level logs */
>> +     otx_cryptodev_logtype = rte_log_register("pmd.crypto.octeontx");
>> +     if (otx_cryptodev_logtype >= 0)
>> +             rte_log_set_level(otx_cryptodev_logtype, RTE_LOG_NOTICE);
>> +}
>> +
>> +static void
>> +otx_cpt_logtype_init(void)
>> +{
>> +     cpt_logtype = otx_cryptodev_logtype;
>> +}
>> +
>> +static int
>> +otx_cpt_pci_probe(struct rte_pci_driver *pci_drv,
>> +                     struct rte_pci_device *pci_dev)
>> +{
>> +     struct rte_cryptodev *cryptodev;
>> +     char name[RTE_CRYPTODEV_NAME_MAX_LEN];
>> +     int retval;
>> +
>> +     if (pci_drv == NULL)
>> +             return -ENODEV;
>> +
>> +     rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
>> +
>> +     cryptodev = rte_cryptodev_pmd_allocate(name, rte_socket_id());
>> +     if (cryptodev == NULL)
>> +             return -ENOMEM;
>> +
>> +     cryptodev->device = &pci_dev->device;
>> +     cryptodev->device->driver = &pci_drv->driver;
>> +     cryptodev->driver_id = otx_cryptodev_driver_id;
>> +
>> +     /* init user callbacks */
>> +     TAILQ_INIT(&(cryptodev->link_intr_cbs));
>> +
>> +     /* init logtype used in common */
>> +     otx_cpt_logtype_init();
>> +
>> +     /* Invoke PMD device initialization function */
>> +     retval = otx_cpt_dev_create(cryptodev);
>> +     if (retval == 0)
>> +             return 0;
>> +
>> +     CPT_LOG_ERR("[DRV %s]: Failed to create device "
>> +                     "(vendor_id: 0x%x device_id: 0x%x",
>> +                     pci_drv->driver.name,
>> +                     (unsigned int) pci_dev->id.vendor_id,
>> +                     (unsigned int) pci_dev->id.device_id);
>> +
>> +     cryptodev->attached = RTE_CRYPTODEV_DETACHED;
>> +
>> +     return -ENXIO;
>> +}
>> +
>> +static int
>> +otx_cpt_pci_remove(struct rte_pci_device *pci_dev)
>> +{
>> +     struct rte_cryptodev *cryptodev;
>> +     char name[RTE_CRYPTODEV_NAME_MAX_LEN];
>> +
>> +     if (pci_dev == NULL)
>> +             return -EINVAL;
>> +
>> +     rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
>> +
>> +     cryptodev = rte_cryptodev_pmd_get_named_dev(name);
>> +     if (cryptodev == NULL)
>> +             return -ENODEV;
>> +
>> +     if (pci_dev->driver == NULL)
>> +             return -ENODEV;
>> +
>> +     /* free crypto device */
>> +     rte_cryptodev_pmd_release_device(cryptodev);
>> +
>> +     if (rte_eal_process_type() == RTE_PROC_PRIMARY)
>> +             rte_free(cryptodev->data->dev_private);
>> +
>> +     cryptodev->device = NULL;
>> +     cryptodev->device->driver = NULL;
>> +     cryptodev->data = NULL;
>> +
>> +     return 0;
>> +}
>> +
>> +static struct rte_pci_driver otx_cryptodev_pmd = {
>> +             .id_table = pci_id_cpt_table,
>> +             .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
>> +             .probe = otx_cpt_pci_probe,
>> +             .remove = otx_cpt_pci_remove,
>> +};
> remove extra spaces/
Between otx_cryptodev_pmd, otx_cryptodev_drv & 
RTE_INIT(otx_cpt_init_log)? Which all ones you want removed?
>> +
>> +static struct cryptodev_driver otx_cryptodev_drv;
>> +
>> +RTE_INIT(otx_cpt_init_log);
>> +RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX_PMD, otx_cryptodev_pmd);
>> +RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX_PMD, 
>> pci_id_cpt_table);
>> +RTE_PMD_REGISTER_CRYPTO_DRIVER(otx_cryptodev_drv, 
>> otx_cryptodev_pmd.driver,
>> +             otx_cryptodev_driver_id);
>> diff --git a/drivers/crypto/octeontx/otx_cryptodev.h 
>> b/drivers/crypto/octeontx/otx_cryptodev.h
>> new file mode 100644
>> index 0000000..99d3346
>> --- /dev/null
>> +++ b/drivers/crypto/octeontx/otx_cryptodev.h
>> @@ -0,0 +1,20 @@
>> +/* SPDX-License-Identifier: BSD-3-Clause
>> + * Copyright(c) 2018 Cavium, Inc
>> + */
>> +
>> +#ifndef _OTX_CRYPTODEV_H_
>> +#define _OTX_CRYPTODEV_H_
>> +
>> +/* Cavium OcteonTX Crypto PMD device name */
>> +#define CRYPTODEV_NAME_OCTEONTX_PMD  crypto_octeontx
>> +
>> +/* Device ID */
>> +#define PCI_VENDOR_ID_CAVIUM             0x177d
>> +#define CPT_81XX_PCI_VF_DEVICE_ID        0xa041
>> +
>> +/*
>> + * Crypto device driver ID
>> + */
>> +uint8_t otx_cryptodev_driver_id;
>> +
>> +#endif /* _OTX_CRYPTODEV_H_ */
>> diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c 
>> b/drivers/crypto/octeontx/otx_cryptodev_ops.c
>> new file mode 100644
>> index 0000000..1b5f108
>> --- /dev/null
>> +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
>> @@ -0,0 +1,15 @@
>> +/* SPDX-License-Identifier: BSD-3-Clause
>> + * Copyright(c) 2018 Cavium, Inc
>> + */
>> +
>> +#include <rte_cryptodev.h>
>> +
>> +#include "otx_cryptodev.h"
>> +#include "otx_cryptodev_ops.h"
>> +
>> +int
>> +otx_cpt_dev_create(struct rte_cryptodev *c_dev)
>> +{
>> +     RTE_SET_USED(c_dev);
>> +     return 0;
>> +}
>> diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h 
>> b/drivers/crypto/octeontx/otx_cryptodev_ops.h
>> new file mode 100644
>> index 0000000..3f2d829
>> --- /dev/null
>> +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
>> @@ -0,0 +1,11 @@
>> +/* SPDX-License-Identifier: BSD-3-Clause
>> + * Copyright(c) 2018 Cavium, Inc
>> + */
>> +
>> +#ifndef _OTX_CRYPTODEV_OPS_H_
>> +#define _OTX_CRYPTODEV_OPS_H_
>> +
>> +int
>> +otx_cpt_dev_create(struct rte_cryptodev *c_dev);
>> +
>> +#endif /* _OTX_CRYPTODEV_OPS_H_ */
>

Re: [dpdk-dev] [PATCH v2 03/33] crypto/octeontx: add PCI probe and remove

[Akhil Goyal]

>>> +static struct rte_pci_driver otx_cryptodev_pmd = {
>>> +             .id_table = pci_id_cpt_table,
>>> +             .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
>>> +             .probe = otx_cpt_pci_probe,
>>> +             .remove = otx_cpt_pci_remove,
>>> +};
>> remove extra spaces/
> Between otx_cryptodev_pmd, otx_cryptodev_drv & 
> RTE_INIT(otx_cpt_init_log)? Which all ones you want removed?
It looks there are 2 tabs for the elements of the above structure.. It 
should be a single tab.

Re: [dpdk-dev] [PATCH v2 03/33] crypto/octeontx: add PCI probe and remove

[Joseph, Anoob]

Hi Akhil,

On 17-09-2018 16:04, Akhil Goyal wrote:
> External Email
>
>>>> +static struct rte_pci_driver otx_cryptodev_pmd = {
>>>> +             .id_table = pci_id_cpt_table,
>>>> +             .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
>>>> +             .probe = otx_cpt_pci_probe,
>>>> +             .remove = otx_cpt_pci_remove,
>>>> +};
>>> remove extra spaces/
>> Between otx_cryptodev_pmd, otx_cryptodev_drv &
>> RTE_INIT(otx_cpt_init_log)? Which all ones you want removed?
> It looks there are 2 tabs for the elements of the above structure.. It
> should be a single tab.
Understood. Will fix it in v3.

Thanks,
Anoob

[dpdk-dev] [PATCH v2 04/33] crypto/octeontx: add register addresses

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 47 +++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
new file mode 100644
index 0000000..288ee41
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
+#define _OTX_CRYPTODEV_HW_ACCESS_H_
+
+/*
+ * CPT Registers map for 81xx
+ */
+
+/* VF registers */
+#define CPTX_VQX_CTL(a, b)		(0x0000100ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_SADDR(a, b)		(0x0000200ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_WAIT(a, b)	(0x0000400ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_INPROG(a, b)		(0x0000410ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE(a, b)		(0x0000420ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ACK(a, b)		(0x0000440ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1S(a, b)	(0x0000460ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1C(a, b)	(0x0000468ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1S(a, b)	(0x0000470ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1C(a, b)	(0x0000478ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT(a, b)		(0x0000500ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT_W1S(a, b)	(0x0000508ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1S(a, b)	(0x0000510ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1C(a, b)	(0x0000518ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DOORBELL(a, b)		(0x0000600ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VFX_PF_MBOXX(a, b, c)	(0x0001000ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b) + \
+					 8ll * ((c) & 0x1))
+
+#endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v2 05/33] common/cpt: add common code for init routine

[Anoob Joseph]

From: Anoob Joseph <anoob.joseph@caviumnetworks.com>

Adding code identified common for OcteonTX family crypto devices. This
patch is adding the code required by the structures and code path of
init routine.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h | 54 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 drivers/common/cpt/cpt_common.h

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
new file mode 100644
index 0000000..feca5fe
--- /dev/null
+++ b/drivers/common/cpt/cpt_common.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_COMMON_H_
+#define _CPT_COMMON_H_
+
+/*
+ * This file defines common macros and structs
+ */
+
+/*
+ * Macros to determine CPT model. Driver makefile will define CPT_MODEL
+ * accordingly
+ */
+#define CRYPTO_OCTEONTX		0x1
+
+#define AE_TYPE 1
+#define SE_TYPE 2
+
+/* cpt instance */
+struct cpt_instance {
+	uint32_t queue_id;
+	uintptr_t rsvd;
+};
+
+struct cptvf_meta_info {
+	void *cptvf_meta_pool;
+	int cptvf_op_mlen;
+	int cptvf_op_sb_mlen;
+};
+
+struct rid {
+	uintptr_t rid;
+		/**< Request id of a crypto operation */
+};
+
+/*
+ * Pending queue structure
+ *
+ */
+struct pending_queue {
+	uint16_t enq_tail;
+	uint16_t deq_head;
+	uint16_t soft_qlen;
+		/**< Software expected queue length */
+	uint16_t p_doorbell;
+	struct rid *rid_queue;
+		/**< Array of pending requests */
+	uint64_t pending_count;
+		/**< Pending requests count */
+};
+
+#endif /* _CPT_COMMON_H_ */
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 05/33] common/cpt: add common code for init routine

[Akhil Goyal]

On 9/4/2018 9:28 AM, Anoob Joseph wrote:
> From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
>
> Adding code identified common for OcteonTX family crypto devices. This
> patch is adding the code required by the structures and code path of
> init routine.
>
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
> ---
>   drivers/common/cpt/cpt_common.h | 54 +++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 54 insertions(+)
>   create mode 100644 drivers/common/cpt/cpt_common.h
>
> diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
> new file mode 100644
> index 0000000..feca5fe
> --- /dev/null
> +++ b/drivers/common/cpt/cpt_common.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2018 Cavium, Inc
> + */
> +
> +#ifndef _CPT_COMMON_H_
> +#define _CPT_COMMON_H_
> +
> +/*
> + * This file defines common macros and structs
> + */
> +
> +/*
> + * Macros to determine CPT model. Driver makefile will define CPT_MODEL
> + * accordingly
> + */
> +#define CRYPTO_OCTEONTX		0x1
> +
> +#define AE_TYPE 1
> +#define SE_TYPE 2
> +
> +/* cpt instance */
> +struct cpt_instance {
> +	uint32_t queue_id;
> +	uintptr_t rsvd;
> +};
> +
> +struct cptvf_meta_info {
> +	void *cptvf_meta_pool;
> +	int cptvf_op_mlen;
> +	int cptvf_op_sb_mlen;
> +};
> +
> +struct rid {
> +	uintptr_t rid;
> +		/**< Request id of a crypto operation */
no need for extra tab for comments.
> +};
> +
> +/*
> + * Pending queue structure
> + *
> + */
> +struct pending_queue {
> +	uint16_t enq_tail;
> +	uint16_t deq_head;
> +	uint16_t soft_qlen;
> +		/**< Software expected queue length */
> +	uint16_t p_doorbell;
> +	struct rid *rid_queue;
> +		/**< Array of pending requests */
> +	uint64_t pending_count;
> +		/**< Pending requests count */
> +};
better to add comment for each element of structure.
Also remove extra tab for comments(here and any other place if any.)
> +
> +#endif /* _CPT_COMMON_H_ */

Re: [dpdk-dev] [PATCH v2 05/33] common/cpt: add common code for init routine

[Thomas Monjalon]

17/09/2018 12:45, Akhil Goyal:
> On 9/4/2018 9:28 AM, Anoob Joseph wrote:
> > +struct pending_queue {
> > +	uint16_t enq_tail;
> > +	uint16_t deq_head;
> > +	uint16_t soft_qlen;
> > +		/**< Software expected queue length */
> > +	uint16_t p_doorbell;
> > +	struct rid *rid_queue;
> > +		/**< Array of pending requests */
> > +	uint64_t pending_count;
> > +		/**< Pending requests count */
> > +};
> better to add comment for each element of structure.
> Also remove extra tab for comments(here and any other place if any.)

I don't understand this trend in the community about doing comments
_after_ the item _and_ not on the same line.
The default style should be commenting _before_.
And if you feel it is better to have the comment on the same line,
then you can comment _after_, but on the same line.

Re: [dpdk-dev] [PATCH v2 05/33] common/cpt: add common code for init routine

[Joseph, Anoob]

Hi Thomas,

On 17-09-2018 17:16, Thomas Monjalon wrote:
> External Email
>
> 17/09/2018 12:45, Akhil Goyal:
>> On 9/4/2018 9:28 AM, Anoob Joseph wrote:
>>> +struct pending_queue {
>>> +   uint16_t enq_tail;
>>> +   uint16_t deq_head;
>>> +   uint16_t soft_qlen;
>>> +           /**< Software expected queue length */
>>> +   uint16_t p_doorbell;
>>> +   struct rid *rid_queue;
>>> +           /**< Array of pending requests */
>>> +   uint64_t pending_count;
>>> +           /**< Pending requests count */
>>> +};
>> better to add comment for each element of structure.
>> Also remove extra tab for comments(here and any other place if any.)
> I don't understand this trend in the community about doing comments
> _after_ the item _and_ not on the same line.
> The default style should be commenting _before_.
> And if you feel it is better to have the comment on the same line,
> then you can comment _after_, but on the same line.
Will fix it. Saw comments after the item being used frequently and 
thought that was the convention.

Thanks
Anoob

Re: [dpdk-dev] [PATCH v2 05/33] common/cpt: add common code for init routine

[Akhil Goyal]

Hi Thomas,

On 9/17/2018 5:16 PM, Thomas Monjalon wrote:

> 17/09/2018 12:45, Akhil Goyal:
>> On 9/4/2018 9:28 AM, Anoob Joseph wrote:
>>> +struct pending_queue {
>>> +	uint16_t enq_tail;
>>> +	uint16_t deq_head;
>>> +	uint16_t soft_qlen;
>>> +		/**< Software expected queue length */
>>> +	uint16_t p_doorbell;
>>> +	struct rid *rid_queue;
>>> +		/**< Array of pending requests */
>>> +	uint64_t pending_count;
>>> +		/**< Pending requests count */
>>> +};
>> better to add comment for each element of structure.
>> Also remove extra tab for comments(here and any other place if any.)
> I don't understand this trend in the community about doing comments
> _after_ the item _and_ not on the same line.
> The default style should be commenting _before_.
> And if you feel it is better to have the comment on the same line,
> then you can comment _after_, but on the same line.
>
I think this should not matter, whether the comment should be before or after,

it should be consistent across the code. I can see that both are being used equally.

Shall we change the complete code beyond this driver as well?

I think whatever we choose, it should be atleast consistent within the file.

-Akhil

>

Re: [dpdk-dev] [PATCH v2 05/33] common/cpt: add common code for init routine

[Thomas Monjalon]

17/09/2018 14:32, Akhil Goyal:
> 
> Hi Thomas,
> 
> On 9/17/2018 5:16 PM, Thomas Monjalon wrote:
> 
> > 17/09/2018 12:45, Akhil Goyal:
> >> On 9/4/2018 9:28 AM, Anoob Joseph wrote:
> >>> +struct pending_queue {
> >>> +	uint16_t enq_tail;
> >>> +	uint16_t deq_head;
> >>> +	uint16_t soft_qlen;
> >>> +		/**< Software expected queue length */
> >>> +	uint16_t p_doorbell;
> >>> +	struct rid *rid_queue;
> >>> +		/**< Array of pending requests */
> >>> +	uint64_t pending_count;
> >>> +		/**< Pending requests count */
> >>> +};
> >> better to add comment for each element of structure.
> >> Also remove extra tab for comments(here and any other place if any.)
> > I don't understand this trend in the community about doing comments
> > _after_ the item _and_ not on the same line.
> > The default style should be commenting _before_.
> > And if you feel it is better to have the comment on the same line,
> > then you can comment _after_, but on the same line.
> >
> I think this should not matter, whether the comment should be before or after,
> 
> it should be consistent across the code. I can see that both are being used equally.
> 
> Shall we change the complete code beyond this driver as well?
> 
> I think whatever we choose, it should be atleast consistent within the file.

Let me rephrase.

There are 3 styles:
	1/ comment on the previous line (before the item)
	2/ comment on the same line (just after the item)
	3/ comment on the next line (after the item)

I am fine with #1 and #2 but I really don't see the benefit of #3.

[dpdk-dev] [PATCH v2 06/33] crypto/octeontx: add hardware init routine

[Anoob Joseph]

From: Anoob Joseph <anoob.joseph@caviumnetworks.com>

Adding hardware init routine for OcteonTX crypto device. A place holder
is added for misc polling routine. That will be added in the further
patches.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                  |  1 +
 drivers/crypto/octeontx/meson.build               |  1 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 53 +++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 92 +++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 89 +++++++++++++++++++++-
 5 files changed, 235 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 12fec75..4582540 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -24,6 +24,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
 
 # PMD code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
 
 # export include files
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index 6564090..eca1cf1 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -8,6 +8,7 @@ deps += ['bus_pci']
 name = 'octeontx_crypto'
 
 sources = files('otx_cryptodev.c',
+		'otx_cryptodev_hw_access.c',
 		'otx_cryptodev_ops.c')
 
 cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
new file mode 100644
index 0000000..211b6ee
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+#include <string.h>
+
+#include <rte_common.h>
+
+#include "otx_cryptodev_hw_access.h"
+
+#include "cpt_pmd_logs.h"
+
+static int
+otx_cpt_vf_init(struct cpt_vf *cptvf)
+{
+	int ret = 0;
+
+	/* Mark as VF driver */
+	cptvf->flags |= CPT_FLAG_VF_DRIVER;
+
+	CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
+
+	return ret;
+}
+
+void
+otx_cpt_poll_misc(struct cpt_vf *cptvf)
+{
+	RTE_SET_USED(cptvf);
+}
+
+int
+otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
+{
+	memset(cptvf, 0, sizeof(struct cpt_vf));
+
+	/* Bar0 base address */
+	cptvf->reg_base = reg_base;
+	strncpy(cptvf->dev_name, name, 32);
+
+	cptvf->nr_queues = 1;
+	cptvf->max_queues = 1;
+	cptvf->pdev = pdev;
+
+	/* To clear if there are any pending mbox msgs */
+	otx_cpt_poll_misc(cptvf);
+
+	if (otx_cpt_vf_init(cptvf)) {
+		CPT_LOG_ERR("Failed to initialize CPT VF device");
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 288ee41..40db69c 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -5,6 +5,90 @@
 #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
 #define _OTX_CRYPTODEV_HW_ACCESS_H_
 
+#include <stdbool.h>
+
+#include <rte_memory.h>
+
+#include "cpt_common.h"
+
+/* Flags to indicate the features supported */
+#define CPT_FLAG_VF_DRIVER		(uint16_t)(1 << 3)
+
+#define CPT_INTR_POLL_INTERVAL_MS	(50)
+
+/* Default command queue length */
+#define DEFAULT_CMD_QCHUNKS	2
+
+struct command_chunk {
+	uint8_t *head;
+		/**< 128-byte aligned real_vaddr */
+	phys_addr_t dma_addr;
+		/**< 128-byte aligned real_dma_addr */
+};
+
+/**
+ * Command queue structure
+ */
+struct command_queue {
+	uint32_t idx;
+		/**< Command queue host write idx */
+	uint32_t cchunk;
+	uint8_t *qhead;
+		/**< Command queue head; instructions are inserted here */
+	struct command_chunk chead[DEFAULT_CMD_QCHUNKS];
+		/**< Command chunk list head */
+};
+
+/**
+ * CPT VF device structure
+ */
+struct cpt_vf {
+	struct cpt_instance instance;
+
+	uint8_t *reg_base;
+		/**< Register start address */
+	struct command_queue cqueue;
+		/**< Command queue information */
+	struct pending_queue pqueue;
+		/**< Pending queue information */
+	struct cptvf_meta_info meta_info;
+		/**< Meta information per vf */
+
+	/* Below fields are accessed only in control path */
+
+	void *pdev;
+		/**< Env specific pdev representing the pci dev */
+	uint32_t qlen;
+		/**< Qsize * CPT_INST_SIZE + alignment size(CPT_INST_SIZE +
+		 * next chunk pointer size (8)
+		 */
+	uint32_t qsize;
+		/**< Calculated queue size */
+	uint32_t nr_queues;
+	uint32_t max_queues;
+
+	uint32_t chip_id;
+		/**< CPT device ID */
+	uint16_t flags;
+		/**< Flags to hold device status bits */
+	uint8_t  vfid;
+		/**< Device index (0...CPT_MAX_VQ_NUM)*/
+	uint8_t  vftype;
+		/**< VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
+	uint8_t  vfgrp;
+		/**< VF group (0 - 8) */
+	uint8_t  node;
+		/**< Operating node: Bits (46:44) in BAR0 address */
+
+	/* VF-PF mailbox communication */
+
+	bool pf_acked;
+	bool pf_nacked;
+
+	char dev_name[32];
+		/**< Device name */
+} __rte_cache_aligned;
+
 /*
  * CPT Registers map for 81xx
  */
@@ -44,4 +128,12 @@
 					 ((a) & 0x1) + 0x100000ll * (b) + \
 					 8ll * ((c) & 0x1))
 
+/* VF HAL functions */
+
+void
+otx_cpt_poll_misc(struct cpt_vf *cptvf);
+
+int
+otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 1b5f108..d25f9c1 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -2,14 +2,101 @@
  * Copyright(c) 2018 Cavium, Inc
  */
 
+#include <rte_alarm.h>
+#include <rte_bus_pci.h>
 #include <rte_cryptodev.h>
+#include <rte_malloc.h>
+
+#include "cpt_pmd_logs.h"
 
 #include "otx_cryptodev.h"
+#include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_ops.h"
 
+/* Alarm routines */
+
+static void
+otx_cpt_alarm_cb(void *arg)
+{
+	struct cpt_vf *cptvf = arg;
+	otx_cpt_poll_misc(cptvf);
+	rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,
+			  otx_cpt_alarm_cb, cptvf);
+}
+
+static int
+otx_cpt_periodic_alarm_start(void *arg)
+{
+	return rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,
+				 otx_cpt_alarm_cb, arg);
+}
+
 int
 otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 {
-	RTE_SET_USED(c_dev);
+	struct rte_pci_device *pdev = RTE_DEV_TO_PCI(c_dev->device);
+	struct cpt_vf *cptvf = NULL;
+	void *reg_base;
+	char dev_name[32];
+	int ret;
+
+	if (pdev->mem_resource[0].phys_addr == 0ULL)
+		return -EIO;
+
+	/* for secondary processes, we don't initialise any further as primary
+	 * has already done this work.
+	 */
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	cptvf = rte_zmalloc_socket("otx_cryptodev_private_mem",
+			sizeof(struct cpt_vf), RTE_CACHE_LINE_SIZE,
+			rte_socket_id());
+
+	if (cptvf == NULL) {
+		CPT_LOG_ERR("Cannot allocate memory for device private data");
+		return -ENOMEM;
+	}
+
+	snprintf(dev_name, 32, "%02x:%02x.%x",
+			pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
+
+	reg_base = pdev->mem_resource[0].addr;
+	if (!reg_base) {
+		CPT_LOG_ERR("Failed to map BAR0 of %s", dev_name);
+		ret = -ENODEV;
+		goto fail;
+	}
+
+	ret = otx_cpt_hw_init(cptvf, pdev, reg_base, dev_name);
+	if (ret) {
+		CPT_LOG_ERR("Failed to init cptvf %s", dev_name);
+		ret = -EIO;
+		goto fail;
+	}
+
+	/* Start off timer for mailbox interrupts */
+	otx_cpt_periodic_alarm_start(cptvf);
+
+	c_dev->dev_ops = NULL;
+
+	c_dev->enqueue_burst = NULL;
+	c_dev->dequeue_burst = NULL;
+
+	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+			RTE_CRYPTODEV_FF_HW_ACCELERATED |
+			RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING;
+
+	/* Save dev private data */
+	c_dev->data->dev_private = cptvf;
+
 	return 0;
+
+fail:
+	if (cptvf) {
+		/* Free private data allocated */
+		rte_free(cptvf);
+	}
+
+	return ret;
 }
-- 
2.7.4

[dpdk-dev] [PATCH v2 07/33] common/cpt: add hardware register defines

[Anoob Joseph]

From: Anoob Joseph <anoob.joseph@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_hw_types.h | 517 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 517 insertions(+)
 create mode 100644 drivers/common/cpt/cpt_hw_types.h

diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h
new file mode 100644
index 0000000..8cd1bf8
--- /dev/null
+++ b/drivers/common/cpt/cpt_hw_types.h
@@ -0,0 +1,517 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_HW_TYPES_H_
+#define _CPT_HW_TYPES_H_
+
+#include <rte_byteorder.h>
+
+/*
+ * This file defines HRM specific structs.
+ *
+ */
+
+#define CPT_VF_INTR_MBOX_MASK   (1<<0)
+#define CPT_VF_INTR_DOVF_MASK   (1<<1)
+#define CPT_VF_INTR_IRDE_MASK   (1<<2)
+#define CPT_VF_INTR_NWRP_MASK   (1<<3)
+#define CPT_VF_INTR_SWERR_MASK  (1<<4)
+#define CPT_VF_INTR_HWERR_MASK  (1<<5)
+#define CPT_VF_INTR_FAULT_MASK  (1<<6)
+
+/*
+ * CPT_INST_S software command definitions
+ * Words EI (0-3)
+ */
+typedef union {
+	uint64_t u64;
+	struct {
+		uint16_t opcode;
+		uint16_t param1;
+		uint16_t param2;
+		uint16_t dlen;
+	} s;
+} vq_cmd_word0_t;
+
+typedef union {
+	uint64_t u64;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint64_t grp	: 3;
+		uint64_t cptr	: 61;
+#else
+		uint64_t cptr	: 61;
+		uint64_t grp	: 3;
+#endif
+	} s;
+} vq_cmd_word3_t;
+
+typedef struct cpt_vq_command {
+	vq_cmd_word0_t cmd;
+	uint64_t dptr;
+	uint64_t rptr;
+	vq_cmd_word3_t cptr;
+} cpt_vq_cmd_t;
+
+/**
+ * Structure cpt_inst_s
+ *
+ * CPT Instruction Structure
+ * This structure specifies the instruction layout.
+ * Instructions are stored in memory as little-endian unless
+ * CPT()_PF_Q()_CTL[INST_BE] is set.
+ */
+typedef union cpt_inst_s {
+	uint64_t u[8];
+	struct cpt_inst_s_8s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_17_63        : 47;
+		uint64_t doneint               : 1;
+		/*< [ 16: 16] Done interrupt.
+		 * 0 = No interrupts related to this instruction.
+		 * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]
+		 * will be incremented, and based on the rules described
+		 * there an interrupt may occur.
+		 */
+		uint64_t reserved_0_15         : 16;
+#else /* Word 0 - Little Endian */
+		uint64_t reserved_0_15         : 16;
+		uint64_t doneint               : 1;
+		uint64_t reserved_17_63        : 47;
+#endif /* Word 0 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
+		uint64_t res_addr              : 64;
+		/*< [127: 64] Result IOVA.
+		 * If nonzero, specifies where to write CPT_RES_S.
+		 * If zero, no result structure will be written.
+		 * Address must be 16-byte aligned.
+
+		 * Bits <63:49> are ignored by hardware; software should
+		 *use a sign-extended bit <48> for forward compatibility.
+		 */
+#else /* Word 1 - Little Endian */
+		uint64_t res_addr              : 64;
+#endif /* Word 1 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
+		uint64_t reserved_172_191      : 20;
+		uint64_t grp                   : 10;
+		/*< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
+		 * use when CPT submits work to SSO.
+		 * For the SSO to not discard the add-work request, FPA_PF_MAP()
+		 * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
+		 */
+		uint64_t tt                    : 2;
+		/*< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
+		 * when CPT submits work to SSO.
+		 */
+		uint64_t tag                   : 32;
+		/*< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when
+		 * CPT submits work to SSO.
+		 */
+#else /* Word 2 - Little Endian */
+		uint64_t tag                   : 32;
+		uint64_t tt                    : 2;
+		uint64_t grp                   : 10;
+		uint64_t reserved_172_191      : 20;
+#endif /* Word 2 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
+		uint64_t wq_ptr                : 64;
+		/**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
+		 * work-queue entry that CPT submits work to SSO after all
+		 * context, output data, and result write operations are
+		 * visible to other CNXXXX units and the cores.
+		 * Bits <2:0> must be zero.
+		 * Bits <63:49> are ignored by hardware; software should use a
+		 * sign-extended bit <48> for forward compatibility.
+		 * Internal:Bits <63:49>, <2:0> are ignored by hardware,
+		 * treated as always 0x0.
+		 **/
+#else /* Word 3 - Little Endian */
+		uint64_t wq_ptr                : 64;
+#endif /* Word 3 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 4 - Big Endian */
+		union {
+			uint64_t ei0                   : 64;
+			/**< [319:256] Engine instruction word 0. Passed to the
+			 * AE/SE.
+			 **/
+			vq_cmd_word0_t vq_cmd_w0;
+		};
+#else /* Word 4 - Little Endian */
+		union {
+			uint64_t ei0                   : 64;
+			vq_cmd_word0_t vq_cmd_w0;
+		};
+#endif /* Word 4 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 5 - Big Endian */
+		union {
+			uint64_t ei1                   : 64;
+			/**< [383:320] Engine instruction word 1. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t dptr;
+		};
+#else /* Word 5 - Little Endian */
+		union {
+			uint64_t ei1                   : 64;
+			uint64_t dptr;
+		};
+#endif /* Word 5 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 6 - Big Endian */
+		union {
+			uint64_t ei2                   : 64;
+			/**< [447:384] Engine instruction word 2. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t rptr;
+		};
+#else /* Word 6 - Little Endian */
+		union {
+			uint64_t ei2                   : 64;
+			uint64_t rptr;
+		};
+#endif /* Word 6 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 7 - Big Endian */
+		union {
+			uint64_t ei3                   : 64;
+			/**< [511:448] Engine instruction word 3. Passed to the
+			 * AE/SE.
+			 **/
+			vq_cmd_word3_t vq_cmd_w3;
+		};
+#else /* Word 7 - Little Endian */
+		union {
+			uint64_t ei3                   : 64;
+			vq_cmd_word3_t vq_cmd_w3;
+		};
+#endif /* Word 7 - End */
+	} s8x;
+} cpt_inst_s_t;
+
+/**
+ * Structure cpt_res_s
+ *
+ * CPT Result Structure
+ * The CPT coprocessor writes the result structure after it completes a
+ * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each
+ * instruction completion produces exactly one result structure.
+ *
+ * This structure is stored in memory as little-endian unless
+ * CPT()_PF_Q()_CTL[INST_BE] is set.
+ */
+typedef union cpt_res_s {
+	uint64_t u[2];
+	struct cpt_res_s_8s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_17_63        : 47;
+		uint64_t doneint               : 1;
+		/**< [ 16: 16] Done interrupt. This bit is copied from the
+		 * corresponding instruction's CPT_INST_S[DONEINT].
+		 **/
+		uint64_t reserved_8_15         : 8;
+		uint64_t compcode              : 8;
+		/**< [  7:  0] Indicates completion/error status of the CPT
+		 * coprocessor for the associated instruction, as enumerated by
+		 * CPT_COMP_E. Core software may write the memory location
+		 * containing [COMPCODE] to 0x0 before ringing the doorbell, and
+		 * then poll for completion by checking for a nonzero value.
+
+		 Once the core observes a nonzero [COMPCODE] value in this case,
+		 the CPT coprocessor will have also completed L2/DRAM write
+		 operations.
+		  */
+#else /* Word 0 - Little Endian */
+		uint64_t compcode              : 8;
+		uint64_t reserved_8_15         : 8;
+		uint64_t doneint               : 1;
+		uint64_t reserved_17_63        : 47;
+#endif /* Word 0 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
+		uint64_t reserved_64_127       : 64;
+#else /* Word 1 - Little Endian */
+		uint64_t reserved_64_127       : 64;
+#endif /* Word 1 - End */
+	} s8x;
+} cpt_res_s_t;
+
+/**
+ * Register (NCB) cpt#_vq#_ctl
+ *
+ * CPT VF Queue Control Registers
+ * This register configures queues. This register should be changed (other than
+ * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_ctl_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_1_63         : 63;
+		uint64_t ena                   : 1;
+		/**< [  0:  0](R/W/H) Enables the logical instruction queue.
+		 * See also CPT()_PF_Q()_CTL[CONT_ERR] and
+		 * CPT()_VQ()_INPROG[INFLIGHT].
+		 * 1 = Queue is enabled.
+		 * 0 = Queue is disabled.
+		 **/
+#else /* Word 0 - Little Endian */
+		uint64_t ena                   : 1;
+		uint64_t reserved_1_63         : 63;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_ctl_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done
+ *
+ * CPT Queue Done Count Registers
+ * These registers contain the per-queue instruction done count.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		uint64_t done                  : 20;
+		/**< [ 19:  0](R/W/H) Done count. When CPT_INST_S[DONEINT] set
+		 * and that instruction completes,CPT()_VQ()_DONE[DONE] is
+		 * incremented when the instruction finishes. Write to this
+		 * field are for diagnostic use only; instead software writes
+		 * CPT()_VQ()_DONE_ACK with the number of decrements for this
+		 * field.
+
+		Interrupts are sent as follows:
+
+		 * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,
+		 * the interrupt coalescing timer is held to zero, and an
+		 * interrupt is not sent.
+
+		 * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt
+		 * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE
+		 * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()
+		 * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough
+		 * results have arrived, then the interrupt is sent.  Otherwise,
+		 * it is not sent due to coalescing.
+
+		* When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is
+		* written but this is not typical), the interrupt coalescing
+		* timer restarts.  Note after decrementing this interrupt
+		* equation is recomputed, for example if CPT()_VQ()_DONE[DONE]
+		* >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is
+		* zero, the interrupt will be resent immediately.  (This covers
+		* the race case between software acknowledging an interrupt and
+		* a result returning.)
+
+		* When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not
+		* sent, but the counting described above still occurs.
+
+		Since CPT instructions complete out-of-order, if software is
+		using completion interrupts the suggested scheme is to request a
+		DONEINT on each request, and when an interrupt arrives perform a
+		"greedy" scan for completions; even if a later command is
+		acknowledged first this will not result in missing a completion.
+
+		Software is responsible for making sure [DONE] does not overflow
+		; for example by insuring there are not more than 2^20-1
+		instructions in flight that may request interrupts.
+		 */
+#else /* Word 0 - Little Endian */
+		uint64_t done                  : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_done_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done_ack
+ *
+ * CPT Queue Done Count Ack Registers
+ * This register is written by software to acknowledge interrupts.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_ack_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		uint64_t done_ack              : 20;
+		/**< [ 19:  0](R/W/H) Number of decrements to CPT()_VQ()_DONE
+		 * [DONE]. Reads CPT()_VQ()_DONE[DONE].
+
+		Written by software to acknowledge interrupts. If CPT()_VQ()_
+		DONE[DONE] is still nonzero the interrupt will be re-sent if the
+		conditions described in CPT()_VQ()_DONE[DONE] are satisfied.
+		 */
+#else /* Word 0 - Little Endian */
+		uint64_t done_ack              : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_done_ack_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done_wait
+ *
+ * CPT Queue Done Interrupt Coalescing Wait Registers
+ * Specifies the per queue interrupt coalescing settings.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_wait_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_48_63        : 16;
+		uint64_t time_wait             : 16;
+		/**< [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =
+		 * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When
+		 * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is
+		 * disabled.
+		 **/
+		uint64_t reserved_20_31        : 12;
+		uint64_t num_wait              : 20;
+		/**< [ 19:  0](R/W) Number of messages hold-off. When
+		 * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as
+		 * 0x1.
+		 **/
+#else /* Word 0 - Little Endian */
+		uint64_t num_wait              : 20;
+		uint64_t reserved_20_31        : 12;
+		uint64_t time_wait             : 16;
+		uint64_t reserved_48_63        : 16;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_done_wait_t;
+
+/**
+ * Register (NCB) cpt#_vq#_doorbell
+ *
+ * CPT Queue Doorbell Registers
+ * Doorbells for the CPT instruction queues.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_doorbell_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		uint64_t dbell_cnt             : 20;
+		/**< [ 19:  0](R/W/H) Number of instruction queue 64-bit words
+		 * to add to the CPT instruction doorbell count. Readback value
+		 * is the the current number of pending doorbell requests.
+
+		If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.
+
+		To reset the count back to zero, write one to clear
+		CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value of
+		2^20 minus the read [DBELL_CNT], then write one to
+		CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
+		CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].
+
+		Must be a multiple of 8.  All CPT instructions are 8 words and
+		require a doorbell count of multiple of 8.
+		 */
+#else /* Word 0 - Little Endian */
+		uint64_t dbell_cnt             : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_doorbell_t;
+
+/**
+ * Register (NCB) cpt#_vq#_inprog
+ *
+ * CPT Queue In Progress Count Registers
+ * These registers contain the per-queue instruction in flight registers.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_inprog_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_8_63         : 56;
+		uint64_t inflight              : 8;
+		/**< [  7:  0](RO/H) Inflight count. Counts the number of
+		 * instructions for the VF for which CPT is fetching, executing
+		 * or responding to instructions. However this does not include
+		 * any interrupts that are awaiting software handling
+		 * (CPT()_VQ()_DONE[DONE] != 0x0).
+
+		A queue may not be reconfigured until:
+		1. CPT()_VQ()_CTL[ENA] is cleared by software.
+		2. [INFLIGHT] is polled until equals to zero.
+		 */
+#else /* Word 0 - Little Endian */
+		uint64_t inflight              : 8;
+		uint64_t reserved_8_63         : 56;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_inprog_t;
+
+/**
+ * Register (NCB) cpt#_vq#_misc_int
+ *
+ * CPT Queue Misc Interrupt Register
+ * These registers contain the per-queue miscellaneous interrupts.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_misc_int_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_7_63         : 57;
+		uint64_t fault		       : 1;
+		/**< [  6:  6](R/W1C/H) Translation fault detected. */
+		uint64_t hwerr		       : 1;
+		/**< [  5:  5](R/W1C/H) Hardware error from engines. */
+		uint64_t swerr                 : 1;
+		/**< [  4:  4](R/W1C/H) Software error from engines. */
+		uint64_t nwrp                  : 1;
+		/**< [  3:  3](R/W1C/H) NCB result write response error. */
+		uint64_t irde                  : 1;
+		/**< [  2:  2](R/W1C/H) Instruction NCB read response error. */
+		uint64_t dovf                  : 1;
+		/**< [  1:  1](R/W1C/H) Doorbell overflow. */
+		uint64_t mbox                  : 1;
+		/**< [  0:  0](R/W1C/H) PF to VF mailbox interrupt. Set when
+		 * CPT()_VF()_PF_MBOX(0) is written.
+		 **/
+#else /* Word 0 - Little Endian */
+		uint64_t mbox                  : 1;
+		uint64_t dovf                  : 1;
+		uint64_t irde                  : 1;
+		uint64_t nwrp                  : 1;
+		uint64_t swerr                 : 1;
+		uint64_t hwerr		       : 1;
+		uint64_t fault		       : 1;
+		uint64_t reserved_5_63         : 59;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_misc_int_t;
+
+/**
+ * Register (NCB) cpt#_vq#_saddr
+ *
+ * CPT Queue Starting Buffer Address Registers
+ * These registers set the instruction buffer starting address.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_saddr_s	{
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_49_63        : 15;
+		uint64_t ptr                   : 43;
+		/**< [ 48:  6](R/W/H) Instruction buffer IOVA <48:6>
+		 * (64-byte aligned). When written, it is the initial buffer
+		 * starting address; when read, it is the next read pointer to
+		 * be requested from L2C. The PTR field is overwritten with the
+		 * next pointer each time that the command buffer segment is
+		 * exhausted. New commands will then be read from the newly
+		 * specified command buffer pointer.
+		 **/
+		uint64_t reserved_0_5          : 6;
+#else /* Word 0 - Little Endian */
+		uint64_t reserved_0_5          : 6;
+		uint64_t ptr                   : 43;
+		uint64_t reserved_49_63        : 15;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_saddr_t;
+
+#endif /*_CPT_HW_TYPES_H_ */
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 07/33] common/cpt: add hardware register defines

[Akhil Goyal]

> +typedef union cpt_res_s {
> +	uint64_t u[2];
> +	struct cpt_res_s_8s {
> +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
> +		uint64_t reserved_17_63        : 47;
> +		uint64_t doneint               : 1;
> +		/**< [ 16: 16] Done interrupt. This bit is copied from the
> +		 * corresponding instruction's CPT_INST_S[DONEINT].
> +		 **/
> +		uint64_t reserved_8_15         : 8;
> +		uint64_t compcode              : 8;
> +		/**< [  7:  0] Indicates completion/error status of the CPT
> +		 * coprocessor for the associated instruction, as enumerated by
> +		 * CPT_COMP_E. Core software may write the memory location
> +		 * containing [COMPCODE] to 0x0 before ringing the doorbell, and
> +		 * then poll for completion by checking for a nonzero value.
> +
> +		 Once the core observes a nonzero [COMPCODE] value in this case,
> +		 the CPT coprocessor will have also completed L2/DRAM write
> +		 operations.
> +		  */
commenting style shall be uniform in the file.
Half of the comments have * and half don't have. Please be consistent.

-Akhil

Re: [dpdk-dev] [PATCH v2 07/33] common/cpt: add hardware register defines

[Joseph, Anoob]

Hi Akhil,


On 17-09-2018 16:48, Akhil Goyal wrote:
> External Email
>
>> +typedef union cpt_res_s {
>> +     uint64_t u[2];
>> +     struct cpt_res_s_8s {
>> +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
>> +             uint64_t reserved_17_63        : 47;
>> +             uint64_t doneint               : 1;
>> +             /**< [ 16: 16] Done interrupt. This bit is copied from the
>> +              * corresponding instruction's CPT_INST_S[DONEINT].
>> +              **/
>> +             uint64_t reserved_8_15         : 8;
>> +             uint64_t compcode              : 8;
>> +             /**< [  7:  0] Indicates completion/error status of the 
>> CPT
>> +              * coprocessor for the associated instruction, as 
>> enumerated by
>> +              * CPT_COMP_E. Core software may write the memory location
>> +              * containing [COMPCODE] to 0x0 before ringing the 
>> doorbell, and
>> +              * then poll for completion by checking for a nonzero 
>> value.
>> +
>> +              Once the core observes a nonzero [COMPCODE] value in 
>> this case,
>> +              the CPT coprocessor will have also completed L2/DRAM 
>> write
>> +              operations.
>> +               */
> commenting style shall be uniform in the file.
> Half of the comments have * and half don't have. Please be consistent.
>
> -Akhil
Will fix this in v3.

Anoob

[dpdk-dev] [PATCH v2 08/33] crypto/octeontx: add hardware register access for misc poll

[Anoob Joseph]

From: Anoob Joseph <anoob.joseph@caviumnetworks.com>

Adding hardware register accesses required for misc poll

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 192 +++++++++++++++++++++-
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h |  11 ++
 2 files changed, 202 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index 211b6ee..02ec3ce 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -3,11 +3,19 @@
  */
 #include <string.h>
 
+#include <rte_branch_prediction.h>
 #include <rte_common.h>
 
 #include "otx_cryptodev_hw_access.h"
 
 #include "cpt_pmd_logs.h"
+#include "cpt_hw_types.h"
+
+/*
+ * VF HAL functions
+ * Access its own BAR0/4 registers by passing VF number as 0.
+ * OS/PCI maps them accordingly.
+ */
 
 static int
 otx_cpt_vf_init(struct cpt_vf *cptvf)
@@ -22,10 +30,192 @@ otx_cpt_vf_init(struct cpt_vf *cptvf)
 	return ret;
 }
 
+/*
+ * Read Interrupt status of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static uint64_t
+otx_cpt_read_vf_misc_intr_status(struct cpt_vf *cptvf)
+{
+	return CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0));
+}
+
+/*
+ * Clear mailbox interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_mbox_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.mbox = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear instruction NCB read error interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_irde_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.irde = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear NCB result write response error interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_nwrp_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.nwrp = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear swerr interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_swerr_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.swerr = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear hwerr interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_hwerr_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.hwerr = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear translation fault interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_fault_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.fault = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear doorbell overflow interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.dovf = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
 void
 otx_cpt_poll_misc(struct cpt_vf *cptvf)
 {
-	RTE_SET_USED(cptvf);
+	uint64_t intr;
+
+	intr = otx_cpt_read_vf_misc_intr_status(cptvf);
+
+	if (!intr)
+		return;
+
+	/* Check for MISC interrupt types */
+	if (likely(intr & CPT_VF_INTR_MBOX_MASK)) {
+		CPT_LOG_DP_DEBUG("%s: Mailbox interrupt 0x%lx on CPT VF %d",
+			cptvf->dev_name, (unsigned int long)intr, cptvf->vfid);
+		otx_cpt_clear_mbox_intr(cptvf);
+	} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {
+		otx_cpt_clear_irde_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Instruction NCB read error interrupt "
+				"0x%lx on CPT VF %d", cptvf->dev_name,
+				(unsigned int long)intr, cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) {
+		otx_cpt_clear_nwrp_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: NCB response write error interrupt 0x%lx"
+				" on CPT VF %d", cptvf->dev_name,
+				(unsigned int long)intr, cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) {
+		otx_cpt_clear_swerr_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Software error interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) {
+		otx_cpt_clear_hwerr_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Hardware error interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) {
+		otx_cpt_clear_fault_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Translation fault interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_DOVF_MASK)) {
+		otx_cpt_clear_dovf_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Doorbell overflow interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else
+		CPT_LOG_DP_ERR("%s: Unhandled interrupt 0x%lx in CPT VF %d",
+				cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
 }
 
 int
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 40db69c..f3c7a45 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -7,6 +7,7 @@
 
 #include <stdbool.h>
 
+#include <rte_io.h>
 #include <rte_memory.h>
 
 #include "cpt_common.h"
@@ -19,6 +20,16 @@
 /* Default command queue length */
 #define DEFAULT_CMD_QCHUNKS	2
 
+#define CPT_CSR_REG_BASE(cpt)		((cpt)->reg_base)
+
+/* Read hw register */
+#define CPT_READ_CSR(__hw_addr, __offset) \
+	rte_read64_relaxed((uint8_t *)__hw_addr + __offset)
+
+/* Write hw register */
+#define CPT_WRITE_CSR(__hw_addr, __offset, __val) \
+	rte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))
+
 struct command_chunk {
 	uint8_t *head;
 		/**< 128-byte aligned real_vaddr */
-- 
2.7.4

[dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

This patch adds the symmetric algorithms capabilities
supported by octeontx crypto hardware.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 .../crypto/octeontx/otx_cryptodev_capabilities.h   | 595 +++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c        |   6 +
 2 files changed, 601 insertions(+)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.h

diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
new file mode 100644
index 0000000..55ddb14
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
@@ -0,0 +1,595 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_CAPABILITIES_H_
+#define _OTX_CRYPTODEV_CAPABILITIES_H_
+
+#define OTX_SYM_CAPABILITIES						\
+	{	/* NULL (AUTH) */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_NULL,		\
+				.block_size = 1,			\
+				.key_size = {				\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				},					\
+			}, },						\
+		}, },							\
+	},								\
+	{	/* AES GMAC (AUTH) */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_AES_GMAC,	\
+				.block_size = 16,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 32,			\
+					.increment = 8			\
+				},					\
+				.digest_size = {			\
+					.min = 8,			\
+					.max = 16,			\
+					.increment = 4			\
+				},					\
+				.iv_size = {				\
+					.min = 12,			\
+					.max = 12,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* KASUMI (F9) */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_KASUMI_F9,	\
+				.block_size = 8,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 4,			\
+					.max = 4,			\
+					.increment = 0			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* MD5 */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_MD5,		\
+				.block_size = 64,			\
+				.key_size = {				\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 16,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* MD5 HMAC */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_MD5_HMAC,	\
+				.block_size = 64,			\
+				.key_size = {				\
+					.min = 8,			\
+					.max = 64,			\
+					.increment = 8			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 16,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA1 */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA1,		\
+				.block_size = 64,			\
+				.key_size = {				\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 20,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA1 HMAC */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,	\
+				.block_size = 64,			\
+				.key_size = {				\
+					.min = 64,			\
+					.max = 64,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 20,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA224 */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA224,		\
+				.block_size = 64,			\
+					.key_size = {			\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 28,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA224 HMAC */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,	\
+				.block_size = 64,			\
+					.key_size = {			\
+					.min = 64,			\
+					.max = 64,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 28,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA256 */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA256,		\
+				.block_size = 64,			\
+				.key_size = {				\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 32,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA256 HMAC */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,	\
+				.block_size = 64,			\
+				.key_size = {				\
+					.min = 64,			\
+					.max = 64,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 32,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA384 */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA384,		\
+				.block_size = 64,			\
+				.key_size = {				\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 48,			\
+					.increment = 1			\
+					},				\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA384 HMAC */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,	\
+				.block_size = 64,			\
+				.key_size = {				\
+					.min = 64,			\
+					.max = 64,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 48,			\
+					.increment = 1			\
+					},				\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA512 */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA512,		\
+				.block_size = 128,			\
+				.key_size = {				\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 64,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SHA512 HMAC */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,	\
+				.block_size = 128,			\
+				.key_size = {				\
+					.min = 64,			\
+					.max = 64,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 1,			\
+					.max = 64,			\
+					.increment = 1			\
+				},					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SNOW 3G (UIA2) */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,	\
+				.block_size = 16,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 4,			\
+					.max = 4,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* ZUC (EIA3) */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,	\
+			{.auth = {					\
+				.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,	\
+				.block_size = 16,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 4,			\
+					.max = 4,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* NULL (CIPHER) */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_NULL,		\
+				.block_size = 1,			\
+				.key_size = {				\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				}					\
+			}, },						\
+		}, }							\
+	},								\
+	{	/* 3DES CBC */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_3DES_CBC,	\
+				.block_size = 8,			\
+				.key_size = {				\
+					.min = 24,			\
+					.max = 24,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 8,			\
+					.max = 16,			\
+					.increment = 8			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* 3DES ECB */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_3DES_ECB,	\
+				.block_size = 8,			\
+				.key_size = {				\
+					.min = 24,			\
+					.max = 24,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 0,			\
+					.max = 0,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* AES CBC */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_AES_CBC,	\
+				.block_size = 16,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 32,			\
+					.increment = 8			\
+				},					\
+				.iv_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* AES CTR */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_AES_CTR,	\
+				.block_size = 16,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 32,			\
+					.increment = 8			\
+				},					\
+				.iv_size = {				\
+					.min = 12,			\
+					.max = 16,			\
+					.increment = 4			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* AES XTS */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_AES_XTS,	\
+				.block_size = 16,			\
+				.key_size = {				\
+					.min = 32,			\
+					.max = 64,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* DES CBC */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_DES_CBC,	\
+				.block_size = 8,			\
+				.key_size = {				\
+					.min = 8,			\
+					.max = 8,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 8,			\
+					.max = 8,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* KASUMI (F8) */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_KASUMI_F8,	\
+				.block_size = 8,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 8,			\
+					.max = 8,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* SNOW 3G (UEA2) */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,	\
+				.block_size = 16,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* ZUC (EEA3) */					\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,	\
+			{.cipher = {					\
+				.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,	\
+				.block_size = 16,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				},					\
+				.iv_size = {				\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	},								\
+	{	/* AES GCM */						\
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,	\
+			{.aead = {					\
+				.algo = RTE_CRYPTO_AEAD_AES_GCM,	\
+				.block_size = 16,			\
+				.key_size = {				\
+					.min = 16,			\
+					.max = 32,			\
+					.increment = 8			\
+				},					\
+				.digest_size = {			\
+					.min = 8,			\
+					.max = 16,			\
+					.increment = 4			\
+				},					\
+				.aad_size = {				\
+					.min = 0,			\
+					.max = 1024,			\
+					.increment = 1			\
+				},					\
+				.iv_size = {				\
+					.min = 12,			\
+					.max = 12,			\
+					.increment = 0			\
+				}					\
+			}, }						\
+		}, }							\
+	}
+
+#endif /* _OTX_CRYPTODEV_CAPABILITIES_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index d25f9c1..cc0030e 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -10,9 +10,15 @@
 #include "cpt_pmd_logs.h"
 
 #include "otx_cryptodev.h"
+#include "otx_cryptodev_capabilities.h"
 #include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_ops.h"
 
+static const struct rte_cryptodev_capabilities otx_capabilities[] = {
+	OTX_SYM_CAPABILITIES,
+	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
 /* Alarm routines */
 
 static void
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Akhil Goyal]

> diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> index d25f9c1..cc0030e 100644
> --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
> +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
> @@ -10,9 +10,15 @@
>   #include "cpt_pmd_logs.h"
>   
>   #include "otx_cryptodev.h"
> +#include "otx_cryptodev_capabilities.h"
>   #include "otx_cryptodev_hw_access.h"
>   #include "otx_cryptodev_ops.h"
>   
> +static const struct rte_cryptodev_capabilities otx_capabilities[] = {
> +	OTX_SYM_CAPABILITIES,
> +	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
> +};
> +

better to have otx_capabilities structure defined in the otx_cryptodev_capabilities.h

I don't see any value addition of creating a macro in one file using in a separate structure in another file

which doesn't have anything new in that structure. It would also give checkpatch error.

You can directly have a capability structure without the #define.

>   /* Alarm routines */
>   
>   static void
>

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Joseph, Anoob]

Hi Akhil,

On 17-09-2018 17:31, Akhil Goyal wrote:
> External Email
>
>> diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c 
>> b/drivers/crypto/octeontx/otx_cryptodev_ops.c
>> index d25f9c1..cc0030e 100644
>> --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
>> +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
>> @@ -10,9 +10,15 @@
>>   #include "cpt_pmd_logs.h"
>>
>>   #include "otx_cryptodev.h"
>> +#include "otx_cryptodev_capabilities.h"
>>   #include "otx_cryptodev_hw_access.h"
>>   #include "otx_cryptodev_ops.h"
>>
>> +static const struct rte_cryptodev_capabilities otx_capabilities[] = {
>> +     OTX_SYM_CAPABILITIES,
>> +     RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
>> +};
>> +
>
> better to have otx_capabilities structure defined in the 
> otx_cryptodev_capabilities.h
>
> I don't see any value addition of creating a macro in one file using 
> in a separate structure in another file
>
> which doesn't have anything new in that structure. It would also give 
> checkpatch error.
>
> You can directly have a capability structure without the #define.
This was the convention followed in qat driver.

https://git.dpdk.org/dpdk/tree/drivers/crypto/qat/qat_sym_capabilities.h

I guess it was to avoid variable definition in header. May be Pablo too 
can comment on this. I'll make the change accordingly.

Thanks,
Anoob

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Joseph, Anoob]

Hi Fiona,

Can you please comment on this?

We are adding all capabilities of octeontx-crypto PMD as a macro in 
otx_cryptodev_capabilites.h file and then we are using it from 
otx_cryptodev_ops.c. This is the approach followed by QAT crypto PMD. As 
per my understanding, this is to ensure that cryptodev_ops file remains 
simple. For other PMDs with fewer number of capabilities, the structure 
can be populated in the .c file itself without the size of the file 
coming into the picture.

But this would cause checkpatch to report error. Akhil's suggestion is 
to move the entire definition to a header and include it from the .c 
file. I believe, the QAT approach was to avoid variable definition in 
the header. What do you think would be a better approach here?

Thanks,
Anoob
On 17-09-2018 18:05, Joseph, Anoob wrote:
> Hi Akhil,
>
> On 17-09-2018 17:31, Akhil Goyal wrote:
>> External Email
>>
>>> diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c 
>>> b/drivers/crypto/octeontx/otx_cryptodev_ops.c
>>> index d25f9c1..cc0030e 100644
>>> --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
>>> +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
>>> @@ -10,9 +10,15 @@
>>>   #include "cpt_pmd_logs.h"
>>>
>>>   #include "otx_cryptodev.h"
>>> +#include "otx_cryptodev_capabilities.h"
>>>   #include "otx_cryptodev_hw_access.h"
>>>   #include "otx_cryptodev_ops.h"
>>>
>>> +static const struct rte_cryptodev_capabilities otx_capabilities[] = {
>>> +     OTX_SYM_CAPABILITIES,
>>> +     RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
>>> +};
>>> +
>>
>> better to have otx_capabilities structure defined in the 
>> otx_cryptodev_capabilities.h
>>
>> I don't see any value addition of creating a macro in one file using 
>> in a separate structure in another file
>>
>> which doesn't have anything new in that structure. It would also give 
>> checkpatch error.
>>
>> You can directly have a capability structure without the #define.
> This was the convention followed in qat driver.
>
> https://git.dpdk.org/dpdk/tree/drivers/crypto/qat/qat_sym_capabilities.h
>
> I guess it was to avoid variable definition in header. May be Pablo 
> too can comment on this. I'll make the change accordingly.
>
> Thanks,
> Anoob
>

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Joseph, Anoob]

Hi Fiona,

Did you get a chance to look at this?

Thanks,
Anoob
On 24-09-2018 17:06, Joseph, Anoob wrote:
> Hi Fiona,
>
> Can you please comment on this?
>
> We are adding all capabilities of octeontx-crypto PMD as a macro in 
> otx_cryptodev_capabilites.h file and then we are using it from 
> otx_cryptodev_ops.c. This is the approach followed by QAT crypto PMD. 
> As per my understanding, this is to ensure that cryptodev_ops file 
> remains simple. For other PMDs with fewer number of capabilities, the 
> structure can be populated in the .c file itself without the size of 
> the file coming into the picture.
>
> But this would cause checkpatch to report error. Akhil's suggestion is 
> to move the entire definition to a header and include it from the .c 
> file. I believe, the QAT approach was to avoid variable definition in 
> the header. What do you think would be a better approach here?
>
> Thanks,
> Anoob
> On 17-09-2018 18:05, Joseph, Anoob wrote:
>> Hi Akhil,
>>
>> On 17-09-2018 17:31, Akhil Goyal wrote:
>>> External Email
>>>
>>>> diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c 
>>>> b/drivers/crypto/octeontx/otx_cryptodev_ops.c
>>>> index d25f9c1..cc0030e 100644
>>>> --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
>>>> +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
>>>> @@ -10,9 +10,15 @@
>>>>   #include "cpt_pmd_logs.h"
>>>>
>>>>   #include "otx_cryptodev.h"
>>>> +#include "otx_cryptodev_capabilities.h"
>>>>   #include "otx_cryptodev_hw_access.h"
>>>>   #include "otx_cryptodev_ops.h"
>>>>
>>>> +static const struct rte_cryptodev_capabilities otx_capabilities[] = {
>>>> +     OTX_SYM_CAPABILITIES,
>>>> +     RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
>>>> +};
>>>> +
>>>
>>> better to have otx_capabilities structure defined in the 
>>> otx_cryptodev_capabilities.h
>>>
>>> I don't see any value addition of creating a macro in one file using 
>>> in a separate structure in another file
>>>
>>> which doesn't have anything new in that structure. It would also 
>>> give checkpatch error.
>>>
>>> You can directly have a capability structure without the #define.
>> This was the convention followed in qat driver.
>>
>> https://git.dpdk.org/dpdk/tree/drivers/crypto/qat/qat_sym_capabilities.h
>>
>> I guess it was to avoid variable definition in header. May be Pablo 
>> too can comment on this. I'll make the change accordingly.
>>
>> Thanks,
>> Anoob
>>
>

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Thomas Monjalon]

24/09/2018 13:36, Joseph, Anoob:
> Hi Fiona,
> 
> Can you please comment on this?
> 
> We are adding all capabilities of octeontx-crypto PMD as a macro in 
> otx_cryptodev_capabilites.h file and then we are using it from 
> otx_cryptodev_ops.c. This is the approach followed by QAT crypto PMD. As 
> per my understanding, this is to ensure that cryptodev_ops file remains 
> simple. For other PMDs with fewer number of capabilities, the structure 
> can be populated in the .c file itself without the size of the file 
> coming into the picture.
> 
> But this would cause checkpatch to report error. Akhil's suggestion is 
> to move the entire definition to a header and include it from the .c 
> file. I believe, the QAT approach was to avoid variable definition in 
> the header. What do you think would be a better approach here?

I think we should avoid adding some code in a .h file.
And it is even worst when using macros.

I suggest defining the capabilities in a .c file.
If you don't want to bloat the main .c file, you can create a function
defined in another .c file.

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Trahe, Fiona]

Hi Akhil, Joseph, Thomas,
Just spotted this now.
See below.

> -----Original Message-----
> From: Thomas Monjalon [mailto:thomas@monjalon.net]
> Sent: Monday, October 1, 2018 11:05 AM
> To: Joseph, Anoob <Anoob.Joseph@caviumnetworks.com>
> Cc: dev@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; Akhil Goyal <akhil.goyal@nxp.com>; Anoob
> Joseph <ajoseph@caviumnetworks.com>; De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>;
> Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>; Narayana Prasad
> <narayanaprasad.athreya@caviumnetworks.com>; Ankur Dwivedi
> <ankur.dwivedi@caviumnetworks.com>; Nithin Dabilpuram
> <nithin.dabilpuram@caviumnetworks.com>; Ragothaman Jayaraman
> <rjayaraman@caviumnetworks.com>; Srisivasubramanian S <ssrinivasan@caviumnetworks.com>;
> Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
> Subject: Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities
> 
> 24/09/2018 13:36, Joseph, Anoob:
> > Hi Fiona,
> >
> > Can you please comment on this?
> >
> > We are adding all capabilities of octeontx-crypto PMD as a macro in
> > otx_cryptodev_capabilites.h file and then we are using it from
> > otx_cryptodev_ops.c. This is the approach followed by QAT crypto PMD. As
> > per my understanding, this is to ensure that cryptodev_ops file remains
> > simple. For other PMDs with fewer number of capabilities, the structure
> > can be populated in the .c file itself without the size of the file
> > coming into the picture.
> >
> > But this would cause checkpatch to report error. Akhil's suggestion is
> > to move the entire definition to a header and include it from the .c
> > file. I believe, the QAT approach was to avoid variable definition in
> > the header. What do you think would be a better approach here?
> 
> I think we should avoid adding some code in a .h file.
> And it is even worst when using macros.
> 
> I suggest defining the capabilities in a .c file.
> If you don't want to bloat the main .c file, you can create a function
> defined in another .c file.
> 
I can't remember all the variations we tried, but there were a few.
I think the macro works well in this case. 
What is the issue we need to solve?

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Thomas Monjalon]

08/10/2018 17:59, Trahe, Fiona:
> Hi Akhil, Joseph, Thomas,
> Just spotted this now.
> See below.
> 
> From: Thomas Monjalon [mailto:thomas@monjalon.net]
> > 24/09/2018 13:36, Joseph, Anoob:
> > > Hi Fiona,
> > >
> > > Can you please comment on this?
> > >
> > > We are adding all capabilities of octeontx-crypto PMD as a macro in
> > > otx_cryptodev_capabilites.h file and then we are using it from
> > > otx_cryptodev_ops.c. This is the approach followed by QAT crypto PMD. As
> > > per my understanding, this is to ensure that cryptodev_ops file remains
> > > simple. For other PMDs with fewer number of capabilities, the structure
> > > can be populated in the .c file itself without the size of the file
> > > coming into the picture.
> > >
> > > But this would cause checkpatch to report error. Akhil's suggestion is
> > > to move the entire definition to a header and include it from the .c
> > > file. I believe, the QAT approach was to avoid variable definition in
> > > the header. What do you think would be a better approach here?
> > 
> > I think we should avoid adding some code in a .h file.
> > And it is even worst when using macros.
> > 
> > I suggest defining the capabilities in a .c file.
> > If you don't want to bloat the main .c file, you can create a function
> > defined in another .c file.
> > 
> I can't remember all the variations we tried, but there were a few.
> I think the macro works well in this case. 
> What is the issue we need to solve?

It is a discussion about best practice.
My answer is: avoid long macros and avoid instructions in .h file.

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Joseph, Anoob]

Hi Fiona,

We were following the QAT approach for defining the capabilities. OCTEON 
TX crypto PMD has similar number of capabilities and QAT was the close 
model that we could follow. I can see the advantages of the macro 
approach, but that would give a checkpatch warning. Also, Thomas didn't 
really like the idea of having long macros. So we have fixed it in the 
upstream code.

I would like to understand what would be your approach when you add 
asymmetric support. We are also adding asymmetric support and would like 
to understand how you would be adding, while supporting devices with 
varying capability.

Thanks,
Anoob
On 09-10-2018 01:57, Thomas Monjalon wrote:
> External Email
>
> 08/10/2018 17:59, Trahe, Fiona:
>> Hi Akhil, Joseph, Thomas,
>> Just spotted this now.
>> See below.
>>
>> From: Thomas Monjalon [mailto:thomas@monjalon.net]
>>> 24/09/2018 13:36, Joseph, Anoob:
>>>> Hi Fiona,
>>>>
>>>> Can you please comment on this?
>>>>
>>>> We are adding all capabilities of octeontx-crypto PMD as a macro in
>>>> otx_cryptodev_capabilites.h file and then we are using it from
>>>> otx_cryptodev_ops.c. This is the approach followed by QAT crypto PMD. As
>>>> per my understanding, this is to ensure that cryptodev_ops file remains
>>>> simple. For other PMDs with fewer number of capabilities, the structure
>>>> can be populated in the .c file itself without the size of the file
>>>> coming into the picture.
>>>>
>>>> But this would cause checkpatch to report error. Akhil's suggestion is
>>>> to move the entire definition to a header and include it from the .c
>>>> file. I believe, the QAT approach was to avoid variable definition in
>>>> the header. What do you think would be a better approach here?
>>> I think we should avoid adding some code in a .h file.
>>> And it is even worst when using macros.
>>>
>>> I suggest defining the capabilities in a .c file.
>>> If you don't want to bloat the main .c file, you can create a function
>>> defined in another .c file.
>>>
>> I can't remember all the variations we tried, but there were a few.
>> I think the macro works well in this case.
>> What is the issue we need to solve?
> It is a discussion about best practice.
> My answer is: avoid long macros and avoid instructions in .h file.
>
>
>

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Joseph, Anoob]

Hi Fiona,

Reminder!!

Thanks,
Anoob

> -----Original Message-----
> From: Joseph, Anoob
> Sent: 10 October 2018 11:10
> To: Thomas Monjalon <thomas@monjalon.net>; Trahe, Fiona
> <fiona.trahe@intel.com>
> Cc: dev@dpdk.org; Akhil Goyal <akhil.goyal@nxp.com>; Joseph, Anoob
> <Anoob.Joseph@cavium.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Murthy, Nidadavolu
> <Nidadavolu.Murthy@cavium.com>; Jacob, Jerin
> <Jerin.JacobKollanukkaran@cavium.com>; Athreya, Narayana Prasad
> <NarayanaPrasad.Athreya@cavium.com>; Dwivedi, Ankur
> <Ankur.Dwivedi@cavium.com>; Dabilpuram, Nithin
> <Nithin.Dabilpuram@cavium.com>; Jayaraman, Ragothaman
> <Ragothaman.Jayaraman@cavium.com>; Srinivasan, Srisivasubramanian
> <Srisivasubramanian.Srinivasan@cavium.com>; Tejasree, Kondoj
> <Kondoj.Tejasree@cavium.com>
> Subject: Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric
> capabilities
> 
> Hi Fiona,
> 
> We were following the QAT approach for defining the capabilities. OCTEON
> TX crypto PMD has similar number of capabilities and QAT was the close
> model that we could follow. I can see the advantages of the macro approach,
> but that would give a checkpatch warning. Also, Thomas didn't really like the
> idea of having long macros. So we have fixed it in the upstream code.
> 
> I would like to understand what would be your approach when you add
> asymmetric support. We are also adding asymmetric support and would like
> to understand how you would be adding, while supporting devices with
> varying capability.
> 
> Thanks,
> Anoob
> On 09-10-2018 01:57, Thomas Monjalon wrote:
> > External Email
> >
> > 08/10/2018 17:59, Trahe, Fiona:
> >> Hi Akhil, Joseph, Thomas,
> >> Just spotted this now.
> >> See below.
> >>
> >> From: Thomas Monjalon [mailto:thomas@monjalon.net]
> >>> 24/09/2018 13:36, Joseph, Anoob:
> >>>> Hi Fiona,
> >>>>
> >>>> Can you please comment on this?
> >>>>
> >>>> We are adding all capabilities of octeontx-crypto PMD as a macro in
> >>>> otx_cryptodev_capabilites.h file and then we are using it from
> >>>> otx_cryptodev_ops.c. This is the approach followed by QAT crypto
> >>>> PMD. As per my understanding, this is to ensure that cryptodev_ops
> >>>> file remains simple. For other PMDs with fewer number of
> >>>> capabilities, the structure can be populated in the .c file itself
> >>>> without the size of the file coming into the picture.
> >>>>
> >>>> But this would cause checkpatch to report error. Akhil's suggestion
> >>>> is to move the entire definition to a header and include it from
> >>>> the .c file. I believe, the QAT approach was to avoid variable
> >>>> definition in the header. What do you think would be a better approach
> here?
> >>> I think we should avoid adding some code in a .h file.
> >>> And it is even worst when using macros.
> >>>
> >>> I suggest defining the capabilities in a .c file.
> >>> If you don't want to bloat the main .c file, you can create a
> >>> function defined in another .c file.
> >>>
> >> I can't remember all the variations we tried, but there were a few.
> >> I think the macro works well in this case.
> >> What is the issue we need to solve?
> > It is a discussion about best practice.
> > My answer is: avoid long macros and avoid instructions in .h file.
> >
> >
> >

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Trahe, Fiona]

Hi Anoob,

Sorry for the delay, I've been travelling a lot lately.
We don't have an alternative solution - will have to explore options
when we get to that stage of the asym PMD development.
I think the macro works well for this specific case, however we'll 
look for an alternative. At the moment we don't have 
bandwidth to investigate further. If you come up with a 
neat solution we'll be happy to follow it.

Fiona

> -----Original Message-----
> From: Joseph, Anoob [mailto:Anoob.Joseph@cavium.com]
> Sent: Tuesday, October 16, 2018 10:41 PM
> To: Thomas Monjalon <thomas@monjalon.net>; Trahe, Fiona <fiona.trahe@intel.com>
> Cc: dev@dpdk.org; Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Murthy, Nidadavolu <Nidadavolu.Murthy@cavium.com>; Jacob, Jerin
> <Jerin.JacobKollanukkaran@cavium.com>; Athreya, Narayana Prasad
> <NarayanaPrasad.Athreya@cavium.com>; Dwivedi, Ankur <Ankur.Dwivedi@cavium.com>; Dabilpuram,
> Nithin <Nithin.Dabilpuram@cavium.com>; Jayaraman, Ragothaman
> <Ragothaman.Jayaraman@cavium.com>; Srinivasan, Srisivasubramanian
> <Srisivasubramanian.Srinivasan@cavium.com>; Tejasree, Kondoj <Kondoj.Tejasree@cavium.com>
> Subject: RE: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities
> 
> Hi Fiona,
> 
> Reminder!!
> 
> Thanks,
> Anoob
> 
> > -----Original Message-----
> > From: Joseph, Anoob
> > Sent: 10 October 2018 11:10
> > To: Thomas Monjalon <thomas@monjalon.net>; Trahe, Fiona
> > <fiona.trahe@intel.com>
> > Cc: dev@dpdk.org; Akhil Goyal <akhil.goyal@nxp.com>; Joseph, Anoob
> > <Anoob.Joseph@cavium.com>; De Lara Guarch, Pablo
> > <pablo.de.lara.guarch@intel.com>; Murthy, Nidadavolu
> > <Nidadavolu.Murthy@cavium.com>; Jacob, Jerin
> > <Jerin.JacobKollanukkaran@cavium.com>; Athreya, Narayana Prasad
> > <NarayanaPrasad.Athreya@cavium.com>; Dwivedi, Ankur
> > <Ankur.Dwivedi@cavium.com>; Dabilpuram, Nithin
> > <Nithin.Dabilpuram@cavium.com>; Jayaraman, Ragothaman
> > <Ragothaman.Jayaraman@cavium.com>; Srinivasan, Srisivasubramanian
> > <Srisivasubramanian.Srinivasan@cavium.com>; Tejasree, Kondoj
> > <Kondoj.Tejasree@cavium.com>
> > Subject: Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric
> > capabilities
> >
> > Hi Fiona,
> >
> > We were following the QAT approach for defining the capabilities. OCTEON
> > TX crypto PMD has similar number of capabilities and QAT was the close
> > model that we could follow. I can see the advantages of the macro approach,
> > but that would give a checkpatch warning. Also, Thomas didn't really like the
> > idea of having long macros. So we have fixed it in the upstream code.
> >
> > I would like to understand what would be your approach when you add
> > asymmetric support. We are also adding asymmetric support and would like
> > to understand how you would be adding, while supporting devices with
> > varying capability.
> >
> > Thanks,
> > Anoob
> > On 09-10-2018 01:57, Thomas Monjalon wrote:
> > > External Email
> > >
> > > 08/10/2018 17:59, Trahe, Fiona:
> > >> Hi Akhil, Joseph, Thomas,
> > >> Just spotted this now.
> > >> See below.
> > >>
> > >> From: Thomas Monjalon [mailto:thomas@monjalon.net]
> > >>> 24/09/2018 13:36, Joseph, Anoob:
> > >>>> Hi Fiona,
> > >>>>
> > >>>> Can you please comment on this?
> > >>>>
> > >>>> We are adding all capabilities of octeontx-crypto PMD as a macro in
> > >>>> otx_cryptodev_capabilites.h file and then we are using it from
> > >>>> otx_cryptodev_ops.c. This is the approach followed by QAT crypto
> > >>>> PMD. As per my understanding, this is to ensure that cryptodev_ops
> > >>>> file remains simple. For other PMDs with fewer number of
> > >>>> capabilities, the structure can be populated in the .c file itself
> > >>>> without the size of the file coming into the picture.
> > >>>>
> > >>>> But this would cause checkpatch to report error. Akhil's suggestion
> > >>>> is to move the entire definition to a header and include it from
> > >>>> the .c file. I believe, the QAT approach was to avoid variable
> > >>>> definition in the header. What do you think would be a better approach
> > here?
> > >>> I think we should avoid adding some code in a .h file.
> > >>> And it is even worst when using macros.
> > >>>
> > >>> I suggest defining the capabilities in a .c file.
> > >>> If you don't want to bloat the main .c file, you can create a
> > >>> function defined in another .c file.
> > >>>
> > >> I can't remember all the variations we tried, but there were a few.
> > >> I think the macro works well in this case.
> > >> What is the issue we need to solve?
> > > It is a discussion about best practice.
> > > My answer is: avoid long macros and avoid instructions in .h file.
> > >
> > >
> > >

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Joseph, Anoob]

Hi Fiona,

I do agree that your solution seems to be a neat way for organizing capabilities. But Akhil & Thomas were against that idea and we had to come up with one array with all capabilities. This would not scale well when we start supporting devices with varying capabilities.

If your plan is to follow the same approach for asym support, maybe we will also follow suit and submit the required patches.

@Akhil, Thomas, thoughts?

Thanks,
Anoob

> -----Original Message-----
> From: Trahe, Fiona <fiona.trahe@intel.com>
> Sent: 20 October 2018 02:40
> To: Joseph, Anoob <Anoob.Joseph@cavium.com>; Thomas Monjalon
> <thomas@monjalon.net>
> Cc: dev@dpdk.org; Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch,
> Pablo <pablo.de.lara.guarch@intel.com>; Murthy, Nidadavolu
> <Nidadavolu.Murthy@cavium.com>; Jacob, Jerin
> <Jerin.JacobKollanukkaran@cavium.com>; Athreya, Narayana Prasad
> <NarayanaPrasad.Athreya@cavium.com>; Dwivedi, Ankur
> <Ankur.Dwivedi@cavium.com>; Dabilpuram, Nithin
> <Nithin.Dabilpuram@cavium.com>; Jayaraman, Ragothaman
> <Ragothaman.Jayaraman@cavium.com>; Srinivasan, Srisivasubramanian
> <Srisivasubramanian.Srinivasan@cavium.com>; Tejasree, Kondoj
> <Kondoj.Tejasree@cavium.com>; Trahe, Fiona <fiona.trahe@intel.com>
> Subject: RE: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric
> capabilities
> 
> External Email
> 
> Hi Anoob,
> 
> Sorry for the delay, I've been travelling a lot lately.
> We don't have an alternative solution - will have to explore options when we
> get to that stage of the asym PMD development.
> I think the macro works well for this specific case, however we'll look for an
> alternative. At the moment we don't have bandwidth to investigate further.
> If you come up with a neat solution we'll be happy to follow it.
> 
> Fiona
> 
> > -----Original Message-----
> > From: Joseph, Anoob [mailto:Anoob.Joseph@cavium.com]
> > Sent: Tuesday, October 16, 2018 10:41 PM
> > To: Thomas Monjalon <thomas@monjalon.net>; Trahe, Fiona
> > <fiona.trahe@intel.com>
> > Cc: dev@dpdk.org; Akhil Goyal <akhil.goyal@nxp.com>; De Lara Guarch,
> > Pablo <pablo.de.lara.guarch@intel.com>; Murthy, Nidadavolu
> > <Nidadavolu.Murthy@cavium.com>; Jacob, Jerin
> > <Jerin.JacobKollanukkaran@cavium.com>; Athreya, Narayana Prasad
> > <NarayanaPrasad.Athreya@cavium.com>; Dwivedi, Ankur
> > <Ankur.Dwivedi@cavium.com>; Dabilpuram, Nithin
> > <Nithin.Dabilpuram@cavium.com>; Jayaraman, Ragothaman
> > <Ragothaman.Jayaraman@cavium.com>; Srinivasan, Srisivasubramanian
> > <Srisivasubramanian.Srinivasan@cavium.com>; Tejasree, Kondoj
> > <Kondoj.Tejasree@cavium.com>
> > Subject: RE: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds
> > symmetric capabilities
> >
> > Hi Fiona,
> >
> > Reminder!!
> >
> > Thanks,
> > Anoob
> >
> > > -----Original Message-----
> > > From: Joseph, Anoob
> > > Sent: 10 October 2018 11:10
> > > To: Thomas Monjalon <thomas@monjalon.net>; Trahe, Fiona
> > > <fiona.trahe@intel.com>
> > > Cc: dev@dpdk.org; Akhil Goyal <akhil.goyal@nxp.com>; Joseph, Anoob
> > > <Anoob.Joseph@cavium.com>; De Lara Guarch, Pablo
> > > <pablo.de.lara.guarch@intel.com>; Murthy, Nidadavolu
> > > <Nidadavolu.Murthy@cavium.com>; Jacob, Jerin
> > > <Jerin.JacobKollanukkaran@cavium.com>; Athreya, Narayana Prasad
> > > <NarayanaPrasad.Athreya@cavium.com>; Dwivedi, Ankur
> > > <Ankur.Dwivedi@cavium.com>; Dabilpuram, Nithin
> > > <Nithin.Dabilpuram@cavium.com>; Jayaraman, Ragothaman
> > > <Ragothaman.Jayaraman@cavium.com>; Srinivasan, Srisivasubramanian
> > > <Srisivasubramanian.Srinivasan@cavium.com>; Tejasree, Kondoj
> > > <Kondoj.Tejasree@cavium.com>
> > > Subject: Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds
> > > symmetric capabilities
> > >
> > > Hi Fiona,
> > >
> > > We were following the QAT approach for defining the capabilities.
> > > OCTEON TX crypto PMD has similar number of capabilities and QAT was
> > > the close model that we could follow. I can see the advantages of
> > > the macro approach, but that would give a checkpatch warning. Also,
> > > Thomas didn't really like the idea of having long macros. So we have fixed
> it in the upstream code.
> > >
> > > I would like to understand what would be your approach when you add
> > > asymmetric support. We are also adding asymmetric support and would
> > > like to understand how you would be adding, while supporting devices
> > > with varying capability.
> > >
> > > Thanks,
> > > Anoob
> > > On 09-10-2018 01:57, Thomas Monjalon wrote:
> > > > External Email
> > > >
> > > > 08/10/2018 17:59, Trahe, Fiona:
> > > >> Hi Akhil, Joseph, Thomas,
> > > >> Just spotted this now.
> > > >> See below.
> > > >>
> > > >> From: Thomas Monjalon [mailto:thomas@monjalon.net]
> > > >>> 24/09/2018 13:36, Joseph, Anoob:
> > > >>>> Hi Fiona,
> > > >>>>
> > > >>>> Can you please comment on this?
> > > >>>>
> > > >>>> We are adding all capabilities of octeontx-crypto PMD as a
> > > >>>> macro in otx_cryptodev_capabilites.h file and then we are using
> > > >>>> it from otx_cryptodev_ops.c. This is the approach followed by
> > > >>>> QAT crypto PMD. As per my understanding, this is to ensure that
> > > >>>> cryptodev_ops file remains simple. For other PMDs with fewer
> > > >>>> number of capabilities, the structure can be populated in the
> > > >>>> .c file itself without the size of the file coming into the picture.
> > > >>>>
> > > >>>> But this would cause checkpatch to report error. Akhil's
> > > >>>> suggestion is to move the entire definition to a header and
> > > >>>> include it from the .c file. I believe, the QAT approach was to
> > > >>>> avoid variable definition in the header. What do you think
> > > >>>> would be a better approach
> > > here?
> > > >>> I think we should avoid adding some code in a .h file.
> > > >>> And it is even worst when using macros.
> > > >>>
> > > >>> I suggest defining the capabilities in a .c file.
> > > >>> If you don't want to bloat the main .c file, you can create a
> > > >>> function defined in another .c file.
> > > >>>
> > > >> I can't remember all the variations we tried, but there were a few.
> > > >> I think the macro works well in this case.
> > > >> What is the issue we need to solve?
> > > > It is a discussion about best practice.
> > > > My answer is: avoid long macros and avoid instructions in .h file.
> > > >
> > > >
> > > >

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Thomas Monjalon]

22/10/2018 05:49, Joseph, Anoob:
> Hi Fiona,
> 
> I do agree that your solution seems to be a neat way for organizing capabilities. But Akhil & Thomas were against that idea and we had to come up with one array with all capabilities. This would not scale well when we start supporting devices with varying capabilities.
> 
> If your plan is to follow the same approach for asym support, maybe we will also follow suit and submit the required patches.
> 
> @Akhil, Thomas, thoughts?

Generally speaking, macros are bad.

Why cannot you just write functions?
I don't understand your issue.

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Joseph, Anoob]

Hi Thomas,

I had replaced macro with functions when I revised the patch. But when more devices (with varying capabilities) need to be supported, this can get complicated. Macro approach would be simpler in that case. Right now QAT has macros and we would like to stick to what is being followed in the community.

Following would be the use case for macros,

#define QAT_BASE_GEN1_SYM_CAPABILITIES, 	\
{	CAPABILITES,				\
	...					\
}

#define QAT_EXTRA_GEN2_SYM_CAPABILITIES  	\
{	CAPABILITES,				\
	...					\
}

static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities[] = {
	QAT_BASE_GEN1_SYM_CAPABILITIES,
	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};

static const struct rte_cryptodev_capabilities qat_gen2_sym_capabilities[] = {
	QAT_BASE_GEN1_SYM_CAPABILITIES,
	QAT_EXTRA_GEN2_SYM_CAPABILITIES,
	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};

Without the macros, we will be required to populate the array there itself and would mean repetition of GEN1 capabilities. Either approach is fine for us, but this could complicate things when we add support for ASYM. Since QAT is already doing this, is it fine to move to that approach as we add support for ASYM? Or if QAT is to follow any other scheme, I'm fine with adopting that as well. Whatever is simple and uniform would work. 

Thanks,
Anoob

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: 22 October 2018 12:22
> To: Joseph, Anoob <Anoob.Joseph@cavium.com>
> Cc: Trahe, Fiona <fiona.trahe@intel.com>; dev@dpdk.org; Akhil Goyal
> <akhil.goyal@nxp.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Murthy, Nidadavolu
> <Nidadavolu.Murthy@cavium.com>; Jacob, Jerin
> <Jerin.JacobKollanukkaran@cavium.com>; Athreya, Narayana Prasad
> <NarayanaPrasad.Athreya@cavium.com>; Dwivedi, Ankur
> <Ankur.Dwivedi@cavium.com>; Dabilpuram, Nithin
> <Nithin.Dabilpuram@cavium.com>; Jayaraman, Ragothaman
> <Ragothaman.Jayaraman@cavium.com>; Srinivasan, Srisivasubramanian
> <Srisivasubramanian.Srinivasan@cavium.com>; Tejasree, Kondoj
> <Kondoj.Tejasree@cavium.com>
> Subject: Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric
> capabilities
> 
> External Email
> 
> 22/10/2018 05:49, Joseph, Anoob:
> > Hi Fiona,
> >
> > I do agree that your solution seems to be a neat way for organizing
> capabilities. But Akhil & Thomas were against that idea and we had to come up
> with one array with all capabilities. This would not scale well when we start
> supporting devices with varying capabilities.
> >
> > If your plan is to follow the same approach for asym support, maybe we will
> also follow suit and submit the required patches.
> >
> > @Akhil, Thomas, thoughts?
> 
> Generally speaking, macros are bad.
> 
> Why cannot you just write functions?
> I don't understand your issue.
> 

Re: [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities

[Thomas Monjalon]

23/10/2018 10:48, Joseph, Anoob:
> From: Thomas Monjalon <thomas@monjalon.net>
> > 22/10/2018 05:49, Joseph, Anoob:
> > > Hi Fiona,
> > >
> > > I do agree that your solution seems to be a neat way for organizing
> > capabilities. But Akhil & Thomas were against that idea and we had to come up
> > with one array with all capabilities. This would not scale well when we start
> > supporting devices with varying capabilities.
> > >
> > > If your plan is to follow the same approach for asym support, maybe we will
> > also follow suit and submit the required patches.
> > >
> > > @Akhil, Thomas, thoughts?
> > 
> > Generally speaking, macros are bad.
> > 
> > Why cannot you just write functions?
> > I don't understand your issue.
> 
> I had replaced macro with functions when I revised the patch. But when more devices (with varying capabilities) need to be supported, this can get complicated. Macro approach would be simpler in that case. Right now QAT has macros and we would like to stick to what is being followed in the community.
> 
> Following would be the use case for macros,
> 
> #define QAT_BASE_GEN1_SYM_CAPABILITIES, 	\
> {	CAPABILITES,				\
> 	...					\
> }
> 
> #define QAT_EXTRA_GEN2_SYM_CAPABILITIES  	\
> {	CAPABILITES,				\
> 	...					\
> }
> 
> static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities[] = {
> 	QAT_BASE_GEN1_SYM_CAPABILITIES,
> 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
> };
> 
> static const struct rte_cryptodev_capabilities qat_gen2_sym_capabilities[] = {
> 	QAT_BASE_GEN1_SYM_CAPABILITIES,
> 	QAT_EXTRA_GEN2_SYM_CAPABILITIES,
> 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
> };
> 
> Without the macros, we will be required to populate the array there itself and would mean repetition of GEN1 capabilities. Either approach is fine for us, but this could complicate things when we add support for ASYM. Since QAT is already doing this, is it fine to move to that approach as we add support for ASYM? Or if QAT is to follow any other scheme, I'm fine with adopting that as well. Whatever is simple and uniform would work.

You can use simple assignments in functions and avoid repetition.

There is a warning in checkpatch about macros.
I think we should be more strict with this warning.

[dpdk-dev] [PATCH v2 10/33] common/cpt: add PMD ops helper functions

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding pmd ops helper functions. Control path accessed APIs would be
added as helper functions. Adding microcode defined macros etc as
dependencies to the helper functions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/Makefile                       |  4 +++
 drivers/common/cpt/Makefile                   | 25 ++++++++++++++++
 drivers/common/cpt/cpt_common.h               | 41 +++++++++++++++++++++++++++
 drivers/common/cpt/cpt_mcode_defines.h        | 38 +++++++++++++++++++++++++
 drivers/common/cpt/cpt_pmd_ops_helper.c       | 41 +++++++++++++++++++++++++++
 drivers/common/cpt/cpt_pmd_ops_helper.h       | 34 ++++++++++++++++++++++
 drivers/common/cpt/meson.build                |  8 ++++++
 drivers/common/cpt/rte_common_cpt_version.map |  6 ++++
 drivers/common/meson.build                    |  2 +-
 mk/rte.app.mk                                 |  4 +++
 10 files changed, 202 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cpt/Makefile
 create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
 create mode 100644 drivers/common/cpt/meson.build
 create mode 100644 drivers/common/cpt/rte_common_cpt_version.map

diff --git a/drivers/common/Makefile b/drivers/common/Makefile
index 0fd2237..ca4e854 100644
--- a/drivers/common/Makefile
+++ b/drivers/common/Makefile
@@ -8,4 +8,8 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
 DIRS-y += octeontx
 endif
 
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+DIRS-y += cpt
+endif
+
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/common/cpt/Makefile b/drivers/common/cpt/Makefile
new file mode 100644
index 0000000..2340aa9
--- /dev/null
+++ b/drivers/common/cpt/Makefile
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_common_cpt.a
+
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
+EXPORT_MAP := rte_common_cpt_version.map
+
+LIBABIVER := 1
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-y += cpt_pmd_ops_helper.c
+
+LDLIBS += -lrte_eal
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index feca5fe..1f78d42 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -18,6 +18,24 @@
 #define AE_TYPE 1
 #define SE_TYPE 2
 
+#ifndef ROUNDUP4
+#define ROUNDUP4(val)	(((val) + 3) & 0xfffffffc)
+#endif
+
+#ifndef ROUNDUP8
+#define ROUNDUP8(val)	(((val) + 7) & 0xfffffff8)
+#endif
+
+#ifndef ROUNDUP16
+#define ROUNDUP16(val)	(((val) + 15) & 0xfffffff0)
+#endif
+
+#ifndef __hot
+#define __hot __attribute__((hot))
+#endif
+
+#define MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
+
 /* cpt instance */
 struct cpt_instance {
 	uint32_t queue_id;
@@ -51,4 +69,27 @@ struct pending_queue {
 		/**< Pending requests count */
 };
 
+struct cpt_request_info {
+	/* fast path fields */
+	uint64_t dma_mode	: 2;
+		/**< DMA mode */
+	uint64_t se_req		: 1;
+		/**< To SE core */
+	uint64_t comp_baddr	: 61;
+	volatile uint64_t *completion_addr;
+	volatile uint64_t *alternate_caddr;
+	void *op;
+		/**< Reference to operation */
+	struct {
+		uint64_t ei0;
+		uint64_t ei1;
+		uint64_t ei2;
+		uint64_t ei3;
+	} ist;
+
+	/* slow path fields */
+	uint64_t time_out;
+	uint8_t extra_time;
+};
+
 #endif /* _CPT_COMMON_H_ */
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
new file mode 100644
index 0000000..1bbe8c4
--- /dev/null
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_MCODE_DEFINES_H_
+#define _CPT_MCODE_DEFINES_H_
+
+/*
+ * This file defines macros and structures according to microcode spec
+ *
+ */
+
+#define CPT_BYTE_16		16
+#define CPT_BYTE_24		24
+#define CPT_BYTE_32		32
+#define CPT_MAX_SG_IN_OUT_CNT	16
+#define CPT_MAX_SG_CNT		(CPT_MAX_SG_IN_OUT_CNT/2)
+
+#define COMPLETION_CODE_SIZE	8
+#define COMPLETION_CODE_INIT	0
+
+#define SG_LIST_HDR_SIZE	(8u)
+#define SG_ENTRY_SIZE		sizeof(sg_comp_t)
+
+/* #define CPT_ALWAYS_USE_SG_MODE */
+#define CPT_ALWAYS_USE_SEPARATE_BUF
+
+typedef struct sglist_comp {
+	union {
+		uint64_t len;
+		struct {
+			uint16_t len[4];
+		} s;
+	} u;
+	uint64_t ptr[4];
+} sg_comp_t;
+
+#endif /* _CPT_MCODE_DEFINES_H_ */
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.c b/drivers/common/cpt/cpt_pmd_ops_helper.c
new file mode 100644
index 0000000..1c18180
--- /dev/null
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_common.h>
+
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
+#include "cpt_mcode_defines.h"
+#include "cpt_pmd_ops_helper.h"
+
+#define CPT_MAX_IV_LEN 16
+#define CPT_OFFSET_CONTROL_BYTES 8
+
+int32_t
+cpt_pmd_ops_helper_get_mlen_direct_mode(void)
+{
+	uint32_t len = 0;
+
+	/* Request structure */
+	len = sizeof(struct cpt_request_info);
+
+	/* CPT HW result structure plus extra as it is aligned */
+	len += 2*sizeof(cpt_res_s_t);
+
+	return len;
+}
+
+int
+cpt_pmd_ops_helper_get_mlen_sg_mode(void)
+{
+	uint32_t len = 0;
+
+	len += sizeof(struct cpt_request_info);
+	len += CPT_OFFSET_CONTROL_BYTES + CPT_MAX_IV_LEN;
+	len += ROUNDUP8(SG_LIST_HDR_SIZE +
+			(ROUNDUP4(CPT_MAX_SG_IN_OUT_CNT) >> 2) * SG_ENTRY_SIZE);
+	len += 2 * COMPLETION_CODE_SIZE;
+	len += 2 * sizeof(cpt_res_s_t);
+	return len;
+}
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.h b/drivers/common/cpt/cpt_pmd_ops_helper.h
new file mode 100644
index 0000000..a9358ae
--- /dev/null
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_PMD_OPS_HELPER_H_
+#define _CPT_PMD_OPS_HELPER_H_
+
+/*
+ * This file defines the agreement between the common layer and the individual
+ * crypto drivers for OcteonTX series. Control path in otx* directory can
+ * directly call functions declared here.
+ */
+
+/*
+ * Get meta length required when operating in direct mode (single buffer
+ * in-place)
+ *
+ * @return
+ *   - length
+ */
+
+int32_t
+cpt_pmd_ops_helper_get_mlen_direct_mode(void);
+
+/*
+ * Get size of contiguous meta buffer to be allocated when working in scatter
+ * gather mode.
+ *
+ * @return
+ *   - length
+ */
+int
+cpt_pmd_ops_helper_get_mlen_sg_mode(void);
+#endif /* _CPT_PMD_OPS_HELPER_H_ */
diff --git a/drivers/common/cpt/meson.build b/drivers/common/cpt/meson.build
new file mode 100644
index 0000000..0a905aa
--- /dev/null
+++ b/drivers/common/cpt/meson.build
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+
+sources = files('cpt_pmd_ops_helper.c')
+
+deps = ['kvargs', 'pci', 'cryptodev']
+includes += include_directories('../../crypto/octeontx')
+allow_experimental_apis = true
diff --git a/drivers/common/cpt/rte_common_cpt_version.map b/drivers/common/cpt/rte_common_cpt_version.map
new file mode 100644
index 0000000..dec614f
--- /dev/null
+++ b/drivers/common/cpt/rte_common_cpt_version.map
@@ -0,0 +1,6 @@
+DPDK_18.11 {
+	global:
+
+	cpt_pmd_ops_helper_get_mlen_direct_mode;
+	cpt_pmd_ops_helper_get_mlen_sg_mode;
+};
diff --git a/drivers/common/meson.build b/drivers/common/meson.build
index d7b7d8c..aa88934 100644
--- a/drivers/common/meson.build
+++ b/drivers/common/meson.build
@@ -2,6 +2,6 @@
 # Copyright(c) 2018 Cavium, Inc
 
 std_deps = ['eal']
-drivers = ['octeontx', 'qat']
+drivers = ['cpt', 'octeontx', 'qat']
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 driver_name_fmt = 'rte_common_@0@'
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index b530337..08f76c7 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -98,6 +98,10 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
 _LDLIBS-y += -lrte_common_octeontx
 endif
 
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+_LDLIBS-y += -lrte_common_cpt
+endif
+
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PCI_BUS)        += -lrte_bus_pci
 _LDLIBS-$(CONFIG_RTE_LIBRTE_VDEV_BUS)       += -lrte_bus_vdev
 _LDLIBS-$(CONFIG_RTE_LIBRTE_DPAA_BUS)       += -lrte_bus_dpaa
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 10/33] common/cpt: add PMD ops helper functions

[Akhil Goyal]

On 9/4/2018 9:28 AM, Anoob Joseph wrote:
> From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
>
> Adding pmd ops helper functions. Control path accessed APIs would be
> added as helper functions. Adding microcode defined macros etc as
> dependencies to the helper functions.
>
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
> ---
>   drivers/common/Makefile                       |  4 +++
>   drivers/common/cpt/Makefile                   | 25 ++++++++++++++++
>   drivers/common/cpt/cpt_common.h               | 41 +++++++++++++++++++++++++++
>   drivers/common/cpt/cpt_mcode_defines.h        | 38 +++++++++++++++++++++++++
>   drivers/common/cpt/cpt_pmd_ops_helper.c       | 41 +++++++++++++++++++++++++++
>   drivers/common/cpt/cpt_pmd_ops_helper.h       | 34 ++++++++++++++++++++++
>   drivers/common/cpt/meson.build                |  8 ++++++
>   drivers/common/cpt/rte_common_cpt_version.map |  6 ++++
>   drivers/common/meson.build                    |  2 +-
>   mk/rte.app.mk                                 |  4 +++
>   10 files changed, 202 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/common/cpt/Makefile
>   create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
>   create mode 100644 drivers/common/cpt/meson.build
>   create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
>
> diff --git a/drivers/common/Makefile b/drivers/common/Makefile
> index 0fd2237..ca4e854 100644
> --- a/drivers/common/Makefile
> +++ b/drivers/common/Makefile
> @@ -8,4 +8,8 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
>   DIRS-y += octeontx
>   endif
>   
> +ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
> +DIRS-y += cpt
> +endif
> +
>   include $(RTE_SDK)/mk/rte.subdir.mk
> diff --git a/drivers/common/cpt/Makefile b/drivers/common/cpt/Makefile
> new file mode 100644
> index 0000000..2340aa9
> --- /dev/null
> +++ b/drivers/common/cpt/Makefile
> @@ -0,0 +1,25 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Cavium, Inc
> +#
> +
> +include $(RTE_SDK)/mk/rte.vars.mk
> +
> +#
> +# library name
> +#
> +LIB = librte_common_cpt.a
> +
> +CFLAGS += $(WERROR_FLAGS)
> +CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
> +EXPORT_MAP := rte_common_cpt_version.map
> +
> +LIBABIVER := 1
> +
> +#
> +# all source are stored in SRCS-y
> +#
> +SRCS-y += cpt_pmd_ops_helper.c
> +
> +LDLIBS += -lrte_eal
> +
> +include $(RTE_SDK)/mk/rte.lib.mk
> diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
> index feca5fe..1f78d42 100644
> --- a/drivers/common/cpt/cpt_common.h
> +++ b/drivers/common/cpt/cpt_common.h
> @@ -18,6 +18,24 @@
>   #define AE_TYPE 1
>   #define SE_TYPE 2
>   
> +#ifndef ROUNDUP4
> +#define ROUNDUP4(val)	(((val) + 3) & 0xfffffffc)
> +#endif
> +
> +#ifndef ROUNDUP8
> +#define ROUNDUP8(val)	(((val) + 7) & 0xfffffff8)
> +#endif
> +
> +#ifndef ROUNDUP16
> +#define ROUNDUP16(val)	(((val) + 15) & 0xfffffff0)
> +#endif
> +
> +#ifndef __hot
> +#define __hot __attribute__((hot))
> +#endif
> +
> +#define MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
> +
>   /* cpt instance */
>   struct cpt_instance {
>   	uint32_t queue_id;
> @@ -51,4 +69,27 @@ struct pending_queue {
>   		/**< Pending requests count */
>   };
>   
> +struct cpt_request_info {
> +	/* fast path fields */
> +	uint64_t dma_mode	: 2;
> +		/**< DMA mode */
> +	uint64_t se_req		: 1;
> +		/**< To SE core */
> +	uint64_t comp_baddr	: 61;
> +	volatile uint64_t *completion_addr;
> +	volatile uint64_t *alternate_caddr;
> +	void *op;
> +		/**< Reference to operation */
better to have comments in the same line wherever possible and if not, 
please check indentation.
Please check other patches as well.

Re: [dpdk-dev] [PATCH v2 10/33] common/cpt: add PMD ops helper functions

[Joseph, Anoob]

HI Akhil,


On 17-09-2018 18:17, Akhil Goyal wrote:
> External Email
>
> On 9/4/2018 9:28 AM, Anoob Joseph wrote:
>> From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
>>
>> Adding pmd ops helper functions. Control path accessed APIs would be
>> added as helper functions. Adding microcode defined macros etc as
>> dependencies to the helper functions.
>>
>> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
>> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
>> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
>> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
>> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
>> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
>> ---
>>   drivers/common/Makefile                       |  4 +++
>>   drivers/common/cpt/Makefile                   | 25 ++++++++++++++++
>>   drivers/common/cpt/cpt_common.h               | 41 
>> +++++++++++++++++++++++++++
>>   drivers/common/cpt/cpt_mcode_defines.h        | 38 
>> +++++++++++++++++++++++++
>>   drivers/common/cpt/cpt_pmd_ops_helper.c       | 41 
>> +++++++++++++++++++++++++++
>>   drivers/common/cpt/cpt_pmd_ops_helper.h       | 34 
>> ++++++++++++++++++++++
>>   drivers/common/cpt/meson.build                |  8 ++++++
>>   drivers/common/cpt/rte_common_cpt_version.map |  6 ++++
>>   drivers/common/meson.build                    |  2 +-
>>   mk/rte.app.mk                                 |  4 +++
>>   10 files changed, 202 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/common/cpt/Makefile
>>   create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
>>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
>>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
>>   create mode 100644 drivers/common/cpt/meson.build
>>   create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
>>
>> diff --git a/drivers/common/Makefile b/drivers/common/Makefile
>> index 0fd2237..ca4e854 100644
>> --- a/drivers/common/Makefile
>> +++ b/drivers/common/Makefile
>> @@ -8,4 +8,8 @@ ifeq 
>> ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
>>   DIRS-y += octeontx
>>   endif
>>
>> +ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
>> +DIRS-y += cpt
>> +endif
>> +
>>   include $(RTE_SDK)/mk/rte.subdir.mk
>> diff --git a/drivers/common/cpt/Makefile b/drivers/common/cpt/Makefile
>> new file mode 100644
>> index 0000000..2340aa9
>> --- /dev/null
>> +++ b/drivers/common/cpt/Makefile
>> @@ -0,0 +1,25 @@
>> +# SPDX-License-Identifier: BSD-3-Clause
>> +# Copyright(c) 2018 Cavium, Inc
>> +#
>> +
>> +include $(RTE_SDK)/mk/rte.vars.mk
>> +
>> +#
>> +# library name
>> +#
>> +LIB = librte_common_cpt.a
>> +
>> +CFLAGS += $(WERROR_FLAGS)
>> +CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
>> +EXPORT_MAP := rte_common_cpt_version.map
>> +
>> +LIBABIVER := 1
>> +
>> +#
>> +# all source are stored in SRCS-y
>> +#
>> +SRCS-y += cpt_pmd_ops_helper.c
>> +
>> +LDLIBS += -lrte_eal
>> +
>> +include $(RTE_SDK)/mk/rte.lib.mk
>> diff --git a/drivers/common/cpt/cpt_common.h 
>> b/drivers/common/cpt/cpt_common.h
>> index feca5fe..1f78d42 100644
>> --- a/drivers/common/cpt/cpt_common.h
>> +++ b/drivers/common/cpt/cpt_common.h
>> @@ -18,6 +18,24 @@
>>   #define AE_TYPE 1
>>   #define SE_TYPE 2
>>
>> +#ifndef ROUNDUP4
>> +#define ROUNDUP4(val)        (((val) + 3) & 0xfffffffc)
>> +#endif
>> +
>> +#ifndef ROUNDUP8
>> +#define ROUNDUP8(val)        (((val) + 7) & 0xfffffff8)
>> +#endif
>> +
>> +#ifndef ROUNDUP16
>> +#define ROUNDUP16(val)       (((val) + 15) & 0xfffffff0)
>> +#endif
>> +
>> +#ifndef __hot
>> +#define __hot __attribute__((hot))
>> +#endif
>> +
>> +#define MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
>> +
>>   /* cpt instance */
>>   struct cpt_instance {
>>       uint32_t queue_id;
>> @@ -51,4 +69,27 @@ struct pending_queue {
>>               /**< Pending requests count */
>>   };
>>
>> +struct cpt_request_info {
>> +     /* fast path fields */
>> +     uint64_t dma_mode       : 2;
>> +             /**< DMA mode */
>> +     uint64_t se_req         : 1;
>> +             /**< To SE core */
>> +     uint64_t comp_baddr     : 61;
>> +     volatile uint64_t *completion_addr;
>> +     volatile uint64_t *alternate_caddr;
>> +     void *op;
>> +             /**< Reference to operation */
> better to have comments in the same line wherever possible and if not,
> please check indentation.
> Please check other patches as well.
>
Will fix this in v3. I'll try to make all comments on the line before 
the thing.

Anoob

[dpdk-dev] [PATCH v2 11/33] crypto/octeontx: add global resource init

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding initialization of global resources. This will be saved as
metadata in cptvf and would be used by common code. Exit path for
failure case is also added along with the new routines.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                  |  1 +
 drivers/crypto/octeontx/meson.build               |  3 +-
 drivers/crypto/octeontx/otx_cryptodev.c           |  3 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 11 +++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h |  3 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 90 +++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.h       |  3 +
 7 files changed, 113 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 4582540..064c9b0 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -16,6 +16,7 @@ CFLAGS += $(WERROR_FLAGS)
 LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
 LDLIBS += -lrte_cryptodev
 LDLIBS += -lrte_pci -lrte_bus_pci
+LDLIBS += -lrte_common_cpt
 
 VPATH += $(RTE_SDK)/drivers/crypto/octeontx
 
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index eca1cf1..60ffc97 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -5,11 +5,12 @@ if host_machine.system() != 'linux'
 endif
 
 deps += ['bus_pci']
+deps += ['common_cpt']
 name = 'octeontx_crypto'
 
 sources = files('otx_cryptodev.c',
 		'otx_cryptodev_hw_access.c',
 		'otx_cryptodev_ops.c')
 
-cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
 includes += include_directories('../../common/cpt')
+cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c
index df88a84..ed1a3a1 100644
--- a/drivers/crypto/octeontx/otx_cryptodev.c
+++ b/drivers/crypto/octeontx/otx_cryptodev.c
@@ -113,6 +113,9 @@ otx_cpt_pci_remove(struct rte_pci_device *pci_dev)
 	cryptodev->device->driver = NULL;
 	cryptodev->data = NULL;
 
+	/* free metapool memory */
+	cleanup_global_resources();
+
 	return 0;
 }
 
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index 02ec3ce..f8b6005 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -241,3 +241,14 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
 
 	return 0;
 }
+
+int
+otx_cpt_deinit_device(void *dev)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	/* Do misc work one last time */
+	otx_cpt_poll_misc(cptvf);
+
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index f3c7a45..82d8255 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -147,4 +147,7 @@ otx_cpt_poll_misc(struct cpt_vf *cptvf);
 int
 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
 
+int
+otx_cpt_deinit_device(void *dev);
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index cc0030e..d109159 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -8,6 +8,7 @@
 #include <rte_malloc.h>
 
 #include "cpt_pmd_logs.h"
+#include "cpt_pmd_ops_helper.h"
 
 #include "otx_cryptodev.h"
 #include "otx_cryptodev_capabilities.h"
@@ -19,6 +20,63 @@ static const struct rte_cryptodev_capabilities otx_capabilities[] = {
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
+static int otx_cryptodev_probe_count;
+static rte_spinlock_t otx_probe_count_lock = RTE_SPINLOCK_INITIALIZER;
+
+static struct rte_mempool *otx_cpt_meta_pool;
+static int otx_cpt_op_mlen;
+static int otx_cpt_op_sb_mlen;
+
+/*
+ * Initializes global variables used by fast-path code
+ *
+ * @return
+ *   - 0 on success, errcode on error
+ */
+static int
+init_global_resources(void)
+{
+	/* Get meta len for scatter gather mode */
+	otx_cpt_op_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+
+	/* Extra 4B saved for future considerations */
+	otx_cpt_op_mlen += 4 * sizeof(uint64_t);
+
+	otx_cpt_meta_pool = rte_mempool_create("cpt_metabuf-pool", 4096 * 16,
+					       otx_cpt_op_mlen, 512, 0,
+					       NULL, NULL, NULL, NULL,
+					       SOCKET_ID_ANY, 0);
+	if (!otx_cpt_meta_pool) {
+		CPT_LOG_ERR("cpt metabuf pool not created");
+		return -ENOMEM;
+	}
+
+	/* Get meta len for direct mode */
+	otx_cpt_op_sb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+	/* Extra 4B saved for future considerations */
+	otx_cpt_op_sb_mlen += 4 * sizeof(uint64_t);
+
+	return 0;
+}
+
+void
+cleanup_global_resources(void)
+{
+	/* Take lock */
+	rte_spinlock_lock(&otx_probe_count_lock);
+
+	/* Decrement the cryptodev count */
+	otx_cryptodev_probe_count--;
+
+	/* Free buffers */
+	if (otx_cpt_meta_pool && otx_cryptodev_probe_count == 0)
+		rte_mempool_free(otx_cpt_meta_pool);
+
+	/* Free lock */
+	rte_spinlock_unlock(&otx_probe_count_lock);
+}
+
 /* Alarm routines */
 
 static void
@@ -37,6 +95,20 @@ otx_cpt_periodic_alarm_start(void *arg)
 				 otx_cpt_alarm_cb, arg);
 }
 
+static int
+otx_cpt_periodic_alarm_stop(void *arg)
+{
+	return rte_eal_alarm_cancel(otx_cpt_alarm_cb, arg);
+}
+
+static void
+otx_cpt_common_vars_init(struct cpt_vf *cptvf)
+{
+	cptvf->meta_info.cptvf_meta_pool = otx_cpt_meta_pool;
+	cptvf->meta_info.cptvf_op_mlen = otx_cpt_op_mlen;
+	cptvf->meta_info.cptvf_op_sb_mlen = otx_cpt_op_sb_mlen;
+}
+
 int
 otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 {
@@ -84,6 +156,20 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	/* Start off timer for mailbox interrupts */
 	otx_cpt_periodic_alarm_start(cptvf);
 
+	rte_spinlock_lock(&otx_probe_count_lock);
+	if (!otx_cryptodev_probe_count) {
+		ret = init_global_resources();
+		if (ret) {
+			rte_spinlock_unlock(&otx_probe_count_lock);
+			goto init_fail;
+		}
+	}
+	otx_cryptodev_probe_count++;
+	rte_spinlock_unlock(&otx_probe_count_lock);
+
+	/* Initialize data path variables used by common code */
+	otx_cpt_common_vars_init(cptvf);
+
 	c_dev->dev_ops = NULL;
 
 	c_dev->enqueue_burst = NULL;
@@ -98,6 +184,10 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 
 	return 0;
 
+init_fail:
+	otx_cpt_periodic_alarm_stop(cptvf);
+	otx_cpt_deinit_device(cptvf);
+
 fail:
 	if (cptvf) {
 		/* Free private data allocated */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
index 3f2d829..ac88fa5 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -5,6 +5,9 @@
 #ifndef _OTX_CRYPTODEV_OPS_H_
 #define _OTX_CRYPTODEV_OPS_H_
 
+void
+cleanup_global_resources(void);
+
 int
 otx_cpt_dev_create(struct rte_cryptodev *c_dev);
 
-- 
2.7.4

[dpdk-dev] [PATCH v2 12/33] crypto/octeontx: add mailbox routines

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding mailbox routines to interact with the pf driver

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                  |   1 +
 drivers/crypto/octeontx/meson.build               |   1 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c |  13 ++
 drivers/crypto/octeontx/otx_cryptodev_mbox.c      | 180 ++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_mbox.h      |  92 +++++++++++
 5 files changed, 287 insertions(+)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 064c9b0..949e983 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -26,6 +26,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
 # PMD code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_mbox.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
 
 # export include files
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index 60ffc97..54e775c 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -10,6 +10,7 @@ name = 'octeontx_crypto'
 
 sources = files('otx_cryptodev.c',
 		'otx_cryptodev_hw_access.c',
+		'otx_cryptodev_mbox.c',
 		'otx_cryptodev_ops.c')
 
 includes += include_directories('../../common/cpt')
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index f8b6005..a6b5bc6 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -7,6 +7,7 @@
 #include <rte_common.h>
 
 #include "otx_cryptodev_hw_access.h"
+#include "otx_cryptodev_mbox.h"
 
 #include "cpt_pmd_logs.h"
 #include "cpt_hw_types.h"
@@ -25,8 +26,19 @@ otx_cpt_vf_init(struct cpt_vf *cptvf)
 	/* Mark as VF driver */
 	cptvf->flags |= CPT_FLAG_VF_DRIVER;
 
+	/* Check ready with PF */
+	/* Gets chip ID / device Id from PF if ready */
+	ret = otx_cpt_check_pf_ready(cptvf);
+	if (ret) {
+		CPT_LOG_ERR("%s: PF not responding to READY msg",
+				cptvf->dev_name);
+		ret = -EBUSY;
+		goto exit;
+	}
+
 	CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
 
+exit:
 	return ret;
 }
 
@@ -181,6 +193,7 @@ otx_cpt_poll_misc(struct cpt_vf *cptvf)
 	if (likely(intr & CPT_VF_INTR_MBOX_MASK)) {
 		CPT_LOG_DP_DEBUG("%s: Mailbox interrupt 0x%lx on CPT VF %d",
 			cptvf->dev_name, (unsigned int long)intr, cptvf->vfid);
+		otx_cpt_handle_mbox_intr(cptvf);
 		otx_cpt_clear_mbox_intr(cptvf);
 	} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {
 		otx_cpt_clear_irde_intr(cptvf);
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.c b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
new file mode 100644
index 0000000..d85f0d1
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <unistd.h>
+
+#include "otx_cryptodev_hw_access.h"
+#include "otx_cryptodev_mbox.h"
+
+void
+otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	/*
+	 * MBOX[0] contains msg
+	 * MBOX[1] contains data
+	 */
+	mbx.msg  = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VFX_PF_MBOXX(0, 0, 0));
+	mbx.data = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VFX_PF_MBOXX(0, 0, 1));
+
+	CPT_LOG_DP_DEBUG("%s: Mailbox msg 0x%lx from PF",
+		    cptvf->dev_name, (unsigned int long)mbx.msg);
+	switch (mbx.msg) {
+	case OTX_CPT_MSG_READY:
+		{
+			otx_cpt_chipid_vfid_t cid;
+
+			cid.u64 = mbx.data;
+			cptvf->pf_acked = true;
+			cptvf->vfid = cid.s.vfid;
+			cptvf->chip_id = cid.s.chip_id;
+			CPT_LOG_DP_DEBUG("%s: Received VFID %d chip_id %d",
+				    cptvf->dev_name,
+				    cptvf->vfid, cid.s.chip_id);
+		}
+		break;
+	case OTX_CPT_MSG_QBIND_GRP:
+		cptvf->pf_acked = true;
+		cptvf->vftype = mbx.data;
+		CPT_LOG_DP_DEBUG("%s: VF %d type %s group %d",
+			    cptvf->dev_name, cptvf->vfid,
+			    ((mbx.data == SE_TYPE) ? "SE" : "AE"),
+			    cptvf->vfgrp);
+		break;
+	case OTX_CPT_MBOX_MSG_TYPE_ACK:
+		cptvf->pf_acked = true;
+		break;
+	case OTX_CPT_MBOX_MSG_TYPE_NACK:
+		cptvf->pf_nacked = true;
+		break;
+	default:
+		CPT_LOG_DP_DEBUG("%s: Invalid msg from PF, msg 0x%lx",
+			    cptvf->dev_name, (unsigned int long)mbx.msg);
+		break;
+	}
+}
+
+/* Send a mailbox message to PF
+ * @vf: vf from which this message to be sent
+ * @mbx: Message to be sent
+ */
+static void
+otx_cpt_send_msg_to_pf(struct cpt_vf *cptvf, struct cpt_mbox *mbx)
+{
+	/* Writing mbox(1) causes interrupt */
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VFX_PF_MBOXX(0, 0, 0), mbx->msg);
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VFX_PF_MBOXX(0, 0, 1), mbx->data);
+}
+
+static int32_t
+otx_cpt_send_msg_to_pf_timeout(struct cpt_vf *cptvf, struct cpt_mbox *mbx)
+{
+	int timeout = OTX_CPT_MBOX_MSG_TIMEOUT;
+	int sleep_ms = 10;
+
+	cptvf->pf_acked = false;
+	cptvf->pf_nacked = false;
+
+	otx_cpt_send_msg_to_pf(cptvf, mbx);
+
+	/* Wait for previous message to be acked, timeout 2sec */
+	while (!cptvf->pf_acked) {
+		if (cptvf->pf_nacked)
+			return -EINVAL;
+		usleep(sleep_ms * 1000);
+		otx_cpt_poll_misc(cptvf);
+		if (cptvf->pf_acked)
+			break;
+		timeout -= sleep_ms;
+		if (!timeout) {
+			CPT_PMD_DRV_LOG(ERR,
+				    "%s: PF didn't ack mbox msg %lx(vfid %u)",
+				    cptvf->dev_name,
+				    (unsigned int long)(mbx->msg & 0xFF),
+				    cptvf->vfid);
+			return -EBUSY;
+		}
+	}
+	return 0;
+}
+
+int
+otx_cpt_check_pf_ready(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_READY;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to READY msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_QLEN;
+
+	mbx.data = cptvf->qsize;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to vq_size msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vf_grp_msg(struct cpt_vf *cptvf, uint32_t group)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_QBIND_GRP;
+
+	/* Convey group of the VF */
+	mbx.data = group;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to vf_type msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vf_up(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_VF_UP;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to UP msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vf_down(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_VF_DOWN;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to DOWN msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.h b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
new file mode 100644
index 0000000..2c51c4f
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_MBOX_H_
+#define _OTX_CRYPTODEV_MBOX_H_
+
+#include <rte_byteorder.h>
+#include <rte_common.h>
+
+#include "cpt_common.h"
+#include "cpt_pmd_logs.h"
+
+#include "otx_cryptodev_hw_access.h"
+
+#define OTX_CPT_MBOX_MSG_TIMEOUT    2000 /* In Milli Seconds */
+
+#define OTX_CPT_MBOX_MSG_TYPE_REQ	0
+#define OTX_CPT_MBOX_MSG_TYPE_ACK	1
+#define OTX_CPT_MBOX_MSG_TYPE_NACK	2
+#define OTX_CPT_MBOX_MSG_TYPE_NOP	3
+
+/* CPT mailbox structure */
+struct cpt_mbox {
+	uint64_t msg;
+		/**< Message type MBOX[0] */
+	uint64_t data;
+		/**< Data         MBOX[1] */
+};
+
+typedef enum {
+	OTX_CPT_MSG_VF_UP = 1,
+	OTX_CPT_MSG_VF_DOWN,
+	OTX_CPT_MSG_READY,
+	OTX_CPT_MSG_QLEN,
+	OTX_CPT_MSG_QBIND_GRP,
+	OTX_CPT_MSG_VQ_PRIORITY,
+	OTX_CPT_MSG_PF_TYPE,
+} otx_cpt_mbox_opcode_t;
+
+typedef union {
+	uint64_t u64;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint32_t chip_id;
+		uint8_t vfid;
+		uint8_t reserved[3];
+#else
+		uint8_t reserved[3];
+		uint8_t vfid;
+		uint32_t chip_id;
+#endif
+	} s;
+} otx_cpt_chipid_vfid_t;
+
+/* Poll handler to handle mailbox messages from VFs */
+void
+otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf);
+
+/*
+ * Checks if VF is able to comminicate with PF
+ * and also gets the CPT number this VF is associated to.
+ */
+int
+otx_cpt_check_pf_ready(struct cpt_vf *cptvf);
+
+/*
+ * Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF.
+ * Must be ACKed.
+ */
+int
+otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf);
+
+/*
+ * Communicate VF group required to PF and get the VQ binded to that group
+ */
+int
+otx_cpt_send_vf_grp_msg(struct cpt_vf *cptvf, uint32_t group);
+
+/*
+ * Communicate to PF that VF is UP and running
+ */
+int
+otx_cpt_send_vf_up(struct cpt_vf *cptvf);
+
+/*
+ * Communicate to PF that VF is DOWN and running
+ */
+int
+otx_cpt_send_vf_down(struct cpt_vf *cptvf);
+
+#endif /* _OTX_CRYPTODEV_MBOX_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v2 13/33] crypto/octeontx: add basic dev ops

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding the following dev ops,
- dev_configure
- dev_start
- dev_stop
- dev_close
- dev_infos_get
- stats_get
- stats_reset

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 57 ++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 30 ++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 94 ++++++++++++++++++++++-
 drivers/crypto/octeontx/otx_cryptodev_ops.h       |  4 +
 4 files changed, 184 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index a6b5bc6..d8b8872 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2018 Cavium, Inc
  */
 #include <string.h>
+#include <unistd.h>
 
 #include <rte_branch_prediction.h>
 #include <rte_common.h>
@@ -265,3 +266,59 @@ otx_cpt_deinit_device(void *dev)
 
 	return 0;
 }
+
+int
+otx_cpt_start_device(void *dev)
+{
+	int rc;
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	rc = otx_cpt_send_vf_up(cptvf);
+	if (rc) {
+		CPT_LOG_ERR("Failed to mark CPT VF device %s UP, rc = %d",
+			    cptvf->dev_name, rc);
+		return -EFAULT;
+	}
+
+	if ((cptvf->vftype != SE_TYPE) &&
+	    (cptvf->vftype != AE_TYPE)) {
+		CPT_LOG_ERR("Fatal error, unexpected vf type %u, for CPT VF "
+			    "device %s\n", cptvf->vftype, cptvf->dev_name);
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+void
+otx_cpt_stop_device(void *dev)
+{
+	int rc;
+	uint32_t pending, retries = 5;
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	/* Wait for pending entries to complete */
+	pending = otx_cpt_read_vq_doorbell(cptvf);
+	while (pending) {
+		CPT_LOG_DP_DEBUG("%s: Waiting for pending %u cmds to complete",
+				 cptvf->dev_name, pending);
+		sleep(1);
+		pending = otx_cpt_read_vq_doorbell(cptvf);
+		retries--;
+		if (!retries)
+			break;
+	}
+
+	if (!retries && pending) {
+		CPT_LOG_ERR("%s: Timeout waiting for commands(%u)",
+			    cptvf->dev_name, pending);
+		return;
+	}
+
+	rc = otx_cpt_send_vf_down(cptvf);
+	if (rc) {
+		CPT_LOG_ERR("Failed to bring down vf %s, rc %d",
+			    cptvf->dev_name, rc);
+		return;
+	}
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 82d8255..7dbc41e 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -11,6 +11,7 @@
 #include <rte_memory.h>
 
 #include "cpt_common.h"
+#include "cpt_hw_types.h"
 
 /* Flags to indicate the features supported */
 #define CPT_FLAG_VF_DRIVER		(uint16_t)(1 << 3)
@@ -150,4 +151,33 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
 int
 otx_cpt_deinit_device(void *dev);
 
+int
+otx_cpt_start_device(void *cptvf);
+
+void
+otx_cpt_stop_device(void *cptvf);
+
+/* Write to VQX_DOORBELL register
+ */
+static __rte_always_inline void
+otx_cpt_write_vq_doorbell(struct cpt_vf *cptvf, uint32_t val)
+{
+	cptx_vqx_doorbell_t vqx_dbell;
+
+	vqx_dbell.u = 0;
+	vqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DOORBELL(0, 0), vqx_dbell.u);
+}
+
+static __rte_always_inline uint32_t
+otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
+{
+	cptx_vqx_doorbell_t vqx_dbell;
+
+	vqx_dbell.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DOORBELL(0, 0));
+	return vqx_dbell.s.dbell_cnt;
+}
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index d109159..2bbf82f 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -5,6 +5,7 @@
 #include <rte_alarm.h>
 #include <rte_bus_pci.h>
 #include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
 #include <rte_malloc.h>
 
 #include "cpt_pmd_logs.h"
@@ -101,6 +102,97 @@ otx_cpt_periodic_alarm_stop(void *arg)
 	return rte_eal_alarm_cancel(otx_cpt_alarm_cb, arg);
 }
 
+/* PMD ops */
+
+static int
+otx_cpt_dev_config(struct rte_cryptodev *dev __rte_unused,
+		   struct rte_cryptodev_config *config __rte_unused)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+	return 0;
+}
+
+static int
+otx_cpt_dev_start(struct rte_cryptodev *c_dev)
+{
+	void *cptvf = c_dev->data->dev_private;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	return otx_cpt_start_device(cptvf);
+}
+
+static void
+otx_cpt_dev_stop(struct rte_cryptodev *c_dev)
+{
+	void *cptvf = c_dev->data->dev_private;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	otx_cpt_stop_device(cptvf);
+}
+
+static int
+otx_cpt_dev_close(struct rte_cryptodev *c_dev)
+{
+	void *cptvf = c_dev->data->dev_private;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	otx_cpt_periodic_alarm_stop(cptvf);
+	otx_cpt_deinit_device(cptvf);
+
+	return 0;
+}
+
+static void
+otx_cpt_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+	if (info != NULL) {
+		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
+		info->feature_flags = dev->feature_flags;
+		info->capabilities = otx_capabilities;
+		info->sym.max_nb_sessions = 0;
+		info->driver_id = otx_cryptodev_driver_id;
+		info->min_mbuf_headroom_req = OTX_CPT_MIN_HEADROOM_REQ;
+		info->min_mbuf_tailroom_req = OTX_CPT_MIN_TAILROOM_REQ;
+	}
+}
+
+static void
+otx_cpt_stats_get(struct rte_cryptodev *dev __rte_unused,
+		  struct rte_cryptodev_stats *stats __rte_unused)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+}
+
+static void
+otx_cpt_stats_reset(struct rte_cryptodev *dev __rte_unused)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+}
+
+static struct rte_cryptodev_ops cptvf_ops = {
+	/* Device related operations */
+	.dev_configure = otx_cpt_dev_config,
+	.dev_start = otx_cpt_dev_start,
+	.dev_stop = otx_cpt_dev_stop,
+	.dev_close = otx_cpt_dev_close,
+	.dev_infos_get = otx_cpt_dev_info_get,
+
+	.stats_get = otx_cpt_stats_get,
+	.stats_reset = otx_cpt_stats_reset,
+	.queue_pair_setup = NULL,
+	.queue_pair_release = NULL,
+	.queue_pair_count = NULL,
+
+	/* Crypto related operations */
+	.sym_session_get_size = NULL,
+	.sym_session_configure = NULL,
+	.sym_session_clear = NULL
+};
+
 static void
 otx_cpt_common_vars_init(struct cpt_vf *cptvf)
 {
@@ -170,7 +262,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	/* Initialize data path variables used by common code */
 	otx_cpt_common_vars_init(cptvf);
 
-	c_dev->dev_ops = NULL;
+	c_dev->dev_ops = &cptvf_ops;
 
 	c_dev->enqueue_burst = NULL;
 	c_dev->dequeue_burst = NULL;
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
index ac88fa5..b3efecf 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -5,6 +5,10 @@
 #ifndef _OTX_CRYPTODEV_OPS_H_
 #define _OTX_CRYPTODEV_OPS_H_
 
+#define OTX_CPT_MIN_HEADROOM_REQ	(24)
+#define OTX_CPT_MIN_TAILROOM_REQ	(8)
+#define CPT_NUM_QS_PER_VF		(1)
+
 void
 cleanup_global_resources(void);
 
-- 
2.7.4

[dpdk-dev] [PATCH v2 14/33] common/cpt: add common macros for queue pair ops

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding common macros required by queue pair op functions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h   | 3 +++
 drivers/common/cpt/cpt_hw_types.h | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 1f78d42..61621dc 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -15,6 +15,9 @@
  */
 #define CRYPTO_OCTEONTX		0x1
 
+#define CPT_COUNT_THOLD		32
+#define CPT_TIMER_THOLD		0x3F
+
 #define AE_TYPE 1
 #define SE_TYPE 2
 
diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h
index 8cd1bf8..4b70dde 100644
--- a/drivers/common/cpt/cpt_hw_types.h
+++ b/drivers/common/cpt/cpt_hw_types.h
@@ -20,6 +20,10 @@
 #define CPT_VF_INTR_HWERR_MASK  (1<<5)
 #define CPT_VF_INTR_FAULT_MASK  (1<<6)
 
+#define CPT_INST_SIZE           (64)
+#define CPT_NEXT_CHUNK_PTR_SIZE (8)
+#define DEFAULT_CMD_QLEN        (DEFAULT_CMD_QCHUNK_SIZE * DEFAULT_CMD_QCHUNKS)
+
 /*
  * CPT_INST_S software command definitions
  * Words EI (0-3)
-- 
2.7.4

[dpdk-dev] [PATCH v2 15/33] crypto/octeontx: add queue pair functions

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding queue pair setup and release functions

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 285 ++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h |   8 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c       |  82 ++++++-
 3 files changed, 373 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index d8b8872..fe054e6 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -1,11 +1,14 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2018 Cavium, Inc
  */
+#include <assert.h>
 #include <string.h>
 #include <unistd.h>
 
 #include <rte_branch_prediction.h>
 #include <rte_common.h>
+#include <rte_errno.h>
+#include <rte_memzone.h>
 
 #include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_mbox.h"
@@ -180,6 +183,136 @@ otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)
 		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
 }
 
+/* Write to VQX_CTL register
+ */
+static void
+otx_cpt_write_vq_ctl(struct cpt_vf *cptvf, bool val)
+{
+	cptx_vqx_ctl_t vqx_ctl;
+
+	vqx_ctl.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				 CPTX_VQX_CTL(0, 0));
+	vqx_ctl.s.ena = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_CTL(0, 0), vqx_ctl.u);
+}
+
+/* Write to VQX_INPROG register
+ */
+static void
+otx_cpt_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val)
+{
+	cptx_vqx_inprog_t vqx_inprg;
+
+	vqx_inprg.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_INPROG(0, 0));
+	vqx_inprg.s.inflight = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_INPROG(0, 0), vqx_inprg.u);
+}
+
+/* Write to VQX_DONE_WAIT NUMWAIT register
+ */
+static void
+otx_cpt_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val)
+{
+	cptx_vqx_done_wait_t vqx_dwait;
+
+	vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DONE_WAIT(0, 0));
+	vqx_dwait.s.num_wait = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
+}
+
+/* Write to VQX_DONE_WAIT NUM_WAIT register
+ */
+static void
+otx_cpt_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val)
+{
+	cptx_vqx_done_wait_t vqx_dwait;
+
+	vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DONE_WAIT(0, 0));
+	vqx_dwait.s.time_wait = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
+}
+
+/* Write to VQX_SADDR register
+ */
+static void
+otx_cpt_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val)
+{
+	cptx_vqx_saddr_t vqx_saddr;
+
+	vqx_saddr.u = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_SADDR(0, 0), vqx_saddr.u);
+}
+
+static void
+otx_cpt_vfvq_init(struct cpt_vf *cptvf)
+{
+	uint64_t base_addr = 0;
+
+	/* Disable the VQ */
+	otx_cpt_write_vq_ctl(cptvf, 0);
+
+	/* Reset the doorbell */
+	otx_cpt_write_vq_doorbell(cptvf, 0);
+	/* Clear inflight */
+	otx_cpt_write_vq_inprog(cptvf, 0);
+
+	/* Write VQ SADDR */
+	base_addr = (uint64_t)(cptvf->cqueue.chead[0].dma_addr);
+	otx_cpt_write_vq_saddr(cptvf, base_addr);
+
+	/* Configure timerhold / coalescence */
+	otx_cpt_write_vq_done_timewait(cptvf, CPT_TIMER_THOLD);
+	otx_cpt_write_vq_done_numwait(cptvf, CPT_COUNT_THOLD);
+
+	/* Enable the VQ */
+	otx_cpt_write_vq_ctl(cptvf, 1);
+
+	/* Flag the VF ready */
+	cptvf->flags |= CPT_FLAG_DEVICE_READY;
+}
+
+static int
+cpt_vq_init(struct cpt_vf *cptvf, uint8_t group)
+{
+	int err;
+
+	/* Convey VQ LEN to PF */
+	err = otx_cpt_send_vq_size_msg(cptvf);
+	if (err) {
+		CPT_LOG_ERR("%s: PF not responding to QLEN msg",
+			    cptvf->dev_name);
+		err = -EBUSY;
+		goto cleanup;
+	}
+
+	/* CPT VF device initialization */
+	otx_cpt_vfvq_init(cptvf);
+
+	/* Send msg to PF to assign currnet Q to required group */
+	cptvf->vfgrp = group;
+	err = otx_cpt_send_vf_grp_msg(cptvf, group);
+	if (err) {
+		CPT_LOG_ERR("%s: PF not responding to VF_GRP msg",
+			    cptvf->dev_name);
+		err = -EBUSY;
+		goto cleanup;
+	}
+
+	CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
+	return 0;
+
+cleanup:
+	return err;
+}
+
 void
 otx_cpt_poll_misc(struct cpt_vf *cptvf)
 {
@@ -268,6 +401,158 @@ otx_cpt_deinit_device(void *dev)
 }
 
 int
+otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance)
+{
+	int ret = -ENOENT, len, qlen, i;
+	int chunk_len, chunks, chunk_size;
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+	struct cpt_instance *cpt_instance;
+	struct command_chunk *chunk_head = NULL, *chunk_prev = NULL;
+	struct command_chunk *chunk = NULL;
+	uint8_t *mem;
+	const struct rte_memzone *rz;
+	uint64_t dma_addr = 0, alloc_len, used_len;
+	uint64_t *next_ptr;
+	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
+
+	CPT_LOG_DP_DEBUG("Initializing cpt resource %s", cptvf->dev_name);
+
+	cpt_instance = &cptvf->instance;
+
+	memset(&cptvf->cqueue, 0, sizeof(cptvf->cqueue));
+	memset(&cptvf->pqueue, 0, sizeof(cptvf->pqueue));
+
+	/* Chunks are of fixed size buffers */
+	chunks = DEFAULT_CMD_QCHUNKS;
+	chunk_len = DEFAULT_CMD_QCHUNK_SIZE;
+
+	qlen = chunks * chunk_len;
+	/* Chunk size includes 8 bytes of next chunk ptr */
+	chunk_size = chunk_len * CPT_INST_SIZE + CPT_NEXT_CHUNK_PTR_SIZE;
+
+	/* For command chunk structures */
+	len = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8);
+
+	/* For pending queue */
+	len += qlen * RTE_ALIGN(sizeof(struct rid), 8);
+
+	/* So that instruction queues start as pg size aligned */
+	len = RTE_ALIGN(len, pg_sz);
+
+	/* For Instruction queues */
+	len += chunks * RTE_ALIGN(chunk_size, 128);
+
+	/* Wastage after instruction queues */
+	len = RTE_ALIGN(len, pg_sz);
+
+	rz = rte_memzone_reserve_aligned(cptvf->dev_name, len, cptvf->node,
+					 RTE_MEMZONE_SIZE_HINT_ONLY |
+					 RTE_MEMZONE_256MB,
+					 RTE_CACHE_LINE_SIZE);
+	if (!rz) {
+		ret = rte_errno;
+		goto cleanup;
+	}
+
+	mem = rz->addr;
+	dma_addr = rz->phys_addr;
+	alloc_len = len;
+
+	memset(mem, 0, len);
+
+	cpt_instance->rsvd = (uintptr_t)rz;
+
+	/* Pending queue setup */
+	cptvf->pqueue.rid_queue = (struct rid *)mem;
+	cptvf->pqueue.soft_qlen = qlen;
+	cptvf->pqueue.enq_tail = 0;
+	cptvf->pqueue.deq_head = 0;
+	cptvf->pqueue.pending_count = 0;
+
+	mem +=  qlen * RTE_ALIGN(sizeof(struct rid), 8);
+	len -=  qlen * RTE_ALIGN(sizeof(struct rid), 8);
+	dma_addr += qlen * RTE_ALIGN(sizeof(struct rid), 8);
+
+	/* Alignment wastage */
+	used_len = alloc_len - len;
+	mem += RTE_ALIGN(used_len, pg_sz) - used_len;
+	len -= RTE_ALIGN(used_len, pg_sz) - used_len;
+	dma_addr += RTE_ALIGN(used_len, pg_sz) - used_len;
+
+	/* Init instruction queues */
+	chunk_head = &cptvf->cqueue.chead[0];
+	i = qlen;
+
+	chunk_prev = NULL;
+	for (i = 0; i < DEFAULT_CMD_QCHUNKS; i++) {
+		int csize;
+
+		chunk = &cptvf->cqueue.chead[i];
+		chunk->head = mem;
+		chunk->dma_addr = dma_addr;
+
+		csize = RTE_ALIGN(chunk_size, 128);
+		mem += csize;
+		dma_addr += csize;
+		len -= csize;
+
+		if (chunk_prev) {
+			next_ptr = (uint64_t *)(chunk_prev->head +
+						chunk_size - 8);
+			*next_ptr = (uint64_t)chunk->dma_addr;
+		}
+		chunk_prev = chunk;
+	}
+	/* Circular loop */
+	next_ptr = (uint64_t *)(chunk_prev->head + chunk_size - 8);
+	*next_ptr = (uint64_t)chunk_head->dma_addr;
+
+	assert(!len);
+
+	cptvf->qlen = qlen;
+	/* This is used for CPT(0)_PF_Q(0..15)_CTL.size config */
+	cptvf->qsize = chunk_size / 8;
+	cptvf->cqueue.qhead = chunk_head->head;
+	cptvf->cqueue.idx = 0;
+	cptvf->cqueue.cchunk = 0;
+
+	if (cpt_vq_init(cptvf, group)) {
+		CPT_LOG_ERR("Failed to initialize CPT VQ of device %s",
+			    cptvf->dev_name);
+		ret = -EBUSY;
+		goto cleanup;
+	}
+
+	*instance = cpt_instance;
+
+	CPT_LOG_DP_DEBUG("Crypto device (%s) initialized", cptvf->dev_name);
+
+	return 0;
+cleanup:
+	rte_memzone_free(rz);
+	*instance = NULL;
+	return ret;
+}
+
+int
+otx_cpt_put_resource(struct cpt_instance *instance)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct rte_memzone *rz;
+
+	if (!cptvf) {
+		CPT_LOG_ERR("Invalid CPTVF handle");
+		return -EINVAL;
+	}
+
+	CPT_LOG_DP_DEBUG("Releasing cpt device %s", cptvf->dev_name);
+
+	rz = (struct rte_memzone *)instance->rsvd;
+	rte_memzone_free(rz);
+	return 0;
+}
+
+int
 otx_cpt_start_device(void *dev)
 {
 	int rc;
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 7dbc41e..b9a634b 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -15,11 +15,13 @@
 
 /* Flags to indicate the features supported */
 #define CPT_FLAG_VF_DRIVER		(uint16_t)(1 << 3)
+#define CPT_FLAG_DEVICE_READY		(uint16_t)(1 << 4)
 
 #define CPT_INTR_POLL_INTERVAL_MS	(50)
 
 /* Default command queue length */
 #define DEFAULT_CMD_QCHUNKS	2
+#define DEFAULT_CMD_QCHUNK_SIZE		1023
 
 #define CPT_CSR_REG_BASE(cpt)		((cpt)->reg_base)
 
@@ -152,6 +154,12 @@ int
 otx_cpt_deinit_device(void *dev);
 
 int
+otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance);
+
+int
+otx_cpt_put_resource(struct cpt_instance *instance);
+
+int
 otx_cpt_start_device(void *cptvf);
 
 void
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 2bbf82f..e6b2ed9 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -28,6 +28,11 @@ static struct rte_mempool *otx_cpt_meta_pool;
 static int otx_cpt_op_mlen;
 static int otx_cpt_op_sb_mlen;
 
+/* Forward declarations */
+
+static int
+otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id);
+
 /*
  * Initializes global variables used by fast-path code
  *
@@ -136,9 +141,16 @@ static int
 otx_cpt_dev_close(struct rte_cryptodev *c_dev)
 {
 	void *cptvf = c_dev->data->dev_private;
+	int i, ret;
 
 	CPT_PMD_INIT_FUNC_TRACE();
 
+	for (i = 0; i < c_dev->data->nb_queue_pairs; i++) {
+		ret = otx_cpt_que_pair_release(c_dev, i);
+		if (ret)
+			return ret;
+	}
+
 	otx_cpt_periodic_alarm_stop(cptvf);
 	otx_cpt_deinit_device(cptvf);
 
@@ -173,6 +185,72 @@ otx_cpt_stats_reset(struct rte_cryptodev *dev __rte_unused)
 	CPT_PMD_INIT_FUNC_TRACE();
 }
 
+static int
+otx_cpt_que_pair_setup(struct rte_cryptodev *dev,
+		       uint16_t que_pair_id,
+		       const struct rte_cryptodev_qp_conf *qp_conf,
+		       int socket_id __rte_unused,
+		       struct rte_mempool *session_pool __rte_unused)
+{
+	void *cptvf = dev->data->dev_private;
+	struct cpt_instance *instance = NULL;
+	struct rte_pci_device *pci_dev;
+	int ret = -1;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (dev->data->queue_pairs[que_pair_id] != NULL) {
+		ret = otx_cpt_que_pair_release(dev, que_pair_id);
+		if (ret)
+			return ret;
+	}
+
+	if (qp_conf->nb_descriptors > DEFAULT_CMD_QLEN) {
+		CPT_LOG_INFO("Number of descriptors too big %d, using default "
+			     "queue length of %d", qp_conf->nb_descriptors,
+			     DEFAULT_CMD_QLEN);
+	}
+
+	pci_dev = RTE_DEV_TO_PCI(dev->device);
+
+	if (pci_dev->mem_resource[0].addr == NULL) {
+		CPT_PMD_DRV_LOG(ERR, "PCI mem address null");
+		return -EIO;
+	}
+
+	ret = otx_cpt_get_resource(cptvf, 0, &instance);
+	if (ret != 0) {
+		CPT_LOG_ERR("Error getting instance handle from device %s : "
+			    "ret = %d", dev->data->name, ret);
+		return ret;
+	}
+
+	instance->queue_id = que_pair_id;
+	dev->data->queue_pairs[que_pair_id] = instance;
+
+	return 0;
+}
+
+static int
+otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)
+{
+	struct cpt_instance *instance = dev->data->queue_pairs[que_pair_id];
+	int ret;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	ret = otx_cpt_put_resource(instance);
+	if (ret != 0) {
+		CPT_PMD_DRV_LOG(ERR, "Error putting instance handle"
+			    " of device %s : ret = %d\n", dev->data->name, ret);
+		return ret;
+	}
+
+	dev->data->queue_pairs[que_pair_id] = NULL;
+
+	return 0;
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -183,8 +261,8 @@ static struct rte_cryptodev_ops cptvf_ops = {
 
 	.stats_get = otx_cpt_stats_get,
 	.stats_reset = otx_cpt_stats_reset,
-	.queue_pair_setup = NULL,
-	.queue_pair_release = NULL,
+	.queue_pair_setup = otx_cpt_que_pair_setup,
+	.queue_pair_release = otx_cpt_que_pair_release,
 	.queue_pair_count = NULL,
 
 	/* Crypto related operations */
-- 
2.7.4

[dpdk-dev] [PATCH v2 16/33] common/cpt: add common code required for session management

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding common code required for session configure, session clear and get
session size ops routines

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h | 110 +++++++++++++++++++++++++++++++++
 drivers/common/cpt/cpt_request_mgr.h   |  32 ++++++++++
 drivers/common/cpt/cpt_ucode.h         |  47 ++++++++++++++
 3 files changed, 189 insertions(+)
 create mode 100644 drivers/common/cpt/cpt_request_mgr.h
 create mode 100644 drivers/common/cpt/cpt_ucode.h

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 1bbe8c4..5b1566e 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -5,6 +5,9 @@
 #ifndef _CPT_MCODE_DEFINES_H_
 #define _CPT_MCODE_DEFINES_H_
 
+#include <rte_byteorder.h>
+#include <rte_memory.h>
+
 /*
  * This file defines macros and structures according to microcode spec
  *
@@ -35,4 +38,111 @@ typedef struct sglist_comp {
 	uint64_t ptr[4];
 } sg_comp_t;
 
+struct cpt_sess_misc {
+	uint16_t cpt_op:4;
+	uint16_t zsk_flag:4;
+	uint16_t aes_gcm:1;
+	uint16_t aes_ctr:1;
+	uint16_t is_null:1;
+		/**< To check if NULL cipher/auth */
+	uint16_t is_gmac:1;
+	uint16_t aad_length;
+	uint8_t mac_len;
+	uint8_t iv_length;
+		/**< IV length in bytes */
+	uint8_t auth_iv_length;
+		/**< Auth IV length in bytes */
+	uint8_t rsvd1;
+	uint16_t iv_offset;
+		/**< IV offset in bytes */
+	uint16_t auth_iv_offset;
+		/**< Auth IV offset in bytes */
+	uint32_t salt;
+	phys_addr_t ctx_dma_addr;
+};
+
+typedef union {
+	uint64_t flags;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint64_t enc_cipher   : 4;
+		uint64_t reserved1    : 1;
+		uint64_t aes_key      : 2;
+		uint64_t iv_source    : 1;
+		uint64_t hash_type    : 4;
+		uint64_t reserved2    : 3;
+		uint64_t auth_input_type : 1;
+		uint64_t mac_len      : 8;
+		uint64_t reserved3    : 8;
+		uint64_t encr_offset  : 16;
+		uint64_t iv_offset    : 8;
+		uint64_t auth_offset  : 8;
+#else
+		uint64_t auth_offset  : 8;
+		uint64_t iv_offset    : 8;
+		uint64_t encr_offset  : 16;
+		uint64_t reserved3    : 8;
+		uint64_t mac_len      : 8;
+		uint64_t auth_input_type : 1;
+		uint64_t reserved2    : 3;
+		uint64_t hash_type    : 4;
+		uint64_t iv_source    : 1;
+		uint64_t aes_key      : 2;
+		uint64_t reserved1    : 1;
+		uint64_t enc_cipher   : 4;
+#endif
+	} e;
+} encr_ctrl_t;
+
+typedef struct {
+	encr_ctrl_t enc_ctrl;
+	uint8_t  encr_key[32];
+	uint8_t  encr_iv[16];
+} mc_enc_context_t;
+
+typedef struct {
+	uint8_t  ipad[64];
+	uint8_t  opad[64];
+} mc_fc_hmac_context_t;
+
+typedef struct {
+	mc_enc_context_t     enc;
+	mc_fc_hmac_context_t hmac;
+} mc_fc_context_t;
+
+typedef struct {
+	uint8_t encr_auth_iv[16];
+	uint8_t ci_key[16];
+	uint8_t zuc_const[32];
+} mc_zuc_snow3g_ctx_t;
+
+typedef struct {
+	uint8_t reg_A[8];
+	uint8_t ci_key[16];
+} mc_kasumi_ctx_t;
+
+struct cpt_ctx {
+	/* Below fields are accessed by sw */
+	uint64_t enc_cipher	:8;
+	uint64_t hash_type	:8;
+	uint64_t mac_len	:8;
+	uint64_t auth_key_len	:8;
+	uint64_t fc_type	:4;
+	uint64_t hmac		:1;
+	uint64_t zsk_flags	:3;
+	uint64_t k_ecb		:1;
+	uint64_t snow3g		:1;
+		/**< Set if it is snow3g and not ZUC */
+	uint64_t rsvd		:22;
+	/* Below fields are accessed by hardware */
+	union {
+		mc_fc_context_t fctx;
+		mc_zuc_snow3g_ctx_t zs_ctx;
+		mc_kasumi_ctx_t k_ctx;
+	};
+	uint8_t  auth_key[64];
+};
+
+#define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
+
 #endif /* _CPT_MCODE_DEFINES_H_ */
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
new file mode 100644
index 0000000..733c402
--- /dev/null
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_REQUEST_MGR_H_
+#define _CPT_REQUEST_MGR_H_
+
+#include "cpt_mcode_defines.h"
+
+/*
+ * This file defines the agreement between the common layer and the individual
+ * crypto drivers for OcteonTX series. Datapath in otx* directory include this
+ * file and all these functions are static inlined for better performance.
+ *
+ */
+
+/*
+ * Get the session size
+ *
+ * This function is used in the data path.
+ *
+ * @return
+ *   - session size
+ */
+static __rte_always_inline unsigned int
+cpt_get_session_size(void)
+{
+	unsigned int ctx_len = sizeof(struct cpt_ctx);
+	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
+}
+
+#endif /* _CPT_REQUEST_MGR_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
new file mode 100644
index 0000000..e4f16fe
--- /dev/null
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_UCODE_H_
+#define _CPT_UCODE_H_
+
+#include "cpt_mcode_defines.h"
+
+/*
+ * This file defines functions that are interfaces to microcode spec.
+ *
+ */
+
+static __rte_always_inline int
+cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
+{
+	/*
+	 * Microcode only supports the following combination.
+	 * Encryption followed by authentication
+	 * Authentication followed by decryption
+	 */
+	if (xform->next) {
+		if ((xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
+		    (xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
+		    (xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)) {
+			/* Unsupported as of now by microcode */
+			CPT_LOG_DP_ERR("Unsupported combination");
+			return -1;
+		}
+		if ((xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
+		    (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
+		    (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)) {
+			/* For GMAC auth there is no cipher operation */
+			if (xform->aead.algo != RTE_CRYPTO_AEAD_AES_GCM ||
+			    xform->next->auth.algo !=
+			    RTE_CRYPTO_AUTH_AES_GMAC) {
+				/* Unsupported as of now by microcode */
+				CPT_LOG_DP_ERR("Unsupported combination");
+				return -1;
+			}
+		}
+	}
+	return 0;
+}
+
+#endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v2 17/33] crypto/octeontx: add session management ops

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding routines for session configure, session clear and get session
size ops.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_ops.c | 83 +++++++++++++++++++++++++++--
 1 file changed, 80 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index e6b2ed9..51f374d 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -10,6 +10,8 @@
 
 #include "cpt_pmd_logs.h"
 #include "cpt_pmd_ops_helper.h"
+#include "cpt_ucode.h"
+#include "cpt_request_mgr.h"
 
 #include "otx_cryptodev.h"
 #include "otx_cryptodev_capabilities.h"
@@ -251,6 +253,81 @@ otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)
 	return 0;
 }
 
+static unsigned int
+otx_cpt_get_session_size(struct rte_cryptodev *dev __rte_unused)
+{
+	return cpt_get_session_size();
+}
+
+static void
+otx_cpt_session_init(void *sym_sess, uint8_t driver_id)
+{
+	struct rte_cryptodev_sym_session *sess = sym_sess;
+	struct cpt_sess_misc *cpt_sess =
+	 (struct cpt_sess_misc *) get_sym_session_private_data(sess, driver_id);
+
+	CPT_PMD_INIT_FUNC_TRACE();
+	cpt_sess->ctx_dma_addr = rte_mempool_virt2iova(cpt_sess) +
+			sizeof(struct cpt_sess_misc);
+}
+
+static int
+otx_cpt_session_cfg(struct rte_cryptodev *dev,
+		    struct rte_crypto_sym_xform *xform,
+		    struct rte_cryptodev_sym_session *sess,
+		    struct rte_mempool *mempool)
+{
+	struct rte_crypto_sym_xform *chain;
+	void *sess_private_data;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (cpt_is_algo_supported(xform))
+		goto err;
+
+	if (unlikely(sess == NULL)) {
+		CPT_LOG_ERR("invalid session struct");
+		return -EINVAL;
+	}
+
+	if (rte_mempool_get(mempool, &sess_private_data)) {
+		CPT_LOG_ERR("Could not allocate sess_private_data");
+		return -ENOMEM;
+	}
+
+	chain = xform;
+	while (chain) {
+		switch (chain->type) {
+		default:
+			CPT_LOG_ERR("Invalid crypto xform type");
+			break;
+		}
+		chain = chain->next;
+	}
+	set_sym_session_private_data(sess, dev->driver_id, sess_private_data);
+	otx_cpt_session_init(sess, dev->driver_id);
+	return 0;
+
+err:
+	rte_mempool_put(mempool, sess_private_data);
+	return -EPERM;
+}
+
+static void
+otx_cpt_session_clear(struct rte_cryptodev *dev,
+		  struct rte_cryptodev_sym_session *sess)
+{
+	void *sess_priv = get_sym_session_private_data(sess, dev->driver_id);
+
+	CPT_PMD_INIT_FUNC_TRACE();
+	if (sess_priv) {
+		memset(sess_priv, 0, otx_cpt_get_session_size(dev));
+		struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
+		set_sym_session_private_data(sess, dev->driver_id, NULL);
+		rte_mempool_put(sess_mp, sess_priv);
+	}
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -266,9 +343,9 @@ static struct rte_cryptodev_ops cptvf_ops = {
 	.queue_pair_count = NULL,
 
 	/* Crypto related operations */
-	.sym_session_get_size = NULL,
-	.sym_session_configure = NULL,
-	.sym_session_clear = NULL
+	.sym_session_get_size = otx_cpt_get_session_size,
+	.sym_session_configure = otx_cpt_session_cfg,
+	.sym_session_clear = otx_cpt_session_clear
 };
 
 static void
-- 
2.7.4

[dpdk-dev] [PATCH v2 18/33] common/cpt: add common code for fill session data

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding common code required for filling session data for AEAD, cipher &
auth sessions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h |  88 +++++
 drivers/common/cpt/cpt_ucode.h         | 574 +++++++++++++++++++++++++++++++++
 2 files changed, 662 insertions(+)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 5b1566e..0d2d0db 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -25,9 +25,86 @@
 #define SG_LIST_HDR_SIZE	(8u)
 #define SG_ENTRY_SIZE		sizeof(sg_comp_t)
 
+#define CPT_DMA_MODE		(1 << 7)  /* Default support is with SG */
+
+#define CPT_FROM_CTX		0
+#define CPT_FROM_DPTR		1
+
+#define FC_GEN			0x1
+#define ZUC_SNOW3G		0x2
+#define KASUMI			0x3
+#define HASH_HMAC		0x4
+
+#define ZS_EA			0x1
+#define ZS_IA			0x2
+#define K_F8			0x4
+#define K_F9			0x8
+
+#define CPT_OP_CIPHER_ENCRYPT	0x1
+#define CPT_OP_CIPHER_DECRYPT	0x2
+#define CPT_OP_CIPHER_MASK	0x3
+
+#define CPT_OP_AUTH_VERIFY	0x4
+#define CPT_OP_AUTH_GENERATE	0x8
+#define CPT_OP_AUTH_MASK	0xC
+
+#define CPT_OP_ENCODE	(CPT_OP_CIPHER_ENCRYPT | CPT_OP_AUTH_GENERATE)
+#define CPT_OP_DECODE	(CPT_OP_CIPHER_DECRYPT | CPT_OP_AUTH_VERIFY)
+
 /* #define CPT_ALWAYS_USE_SG_MODE */
 #define CPT_ALWAYS_USE_SEPARATE_BUF
 
+typedef enum {
+	MD5_TYPE        = 1,
+	SHA1_TYPE       = 2,
+	SHA2_SHA224     = 3,
+	SHA2_SHA256     = 4,
+	SHA2_SHA384     = 5,
+	SHA2_SHA512     = 6,
+	GMAC_TYPE       = 7,
+	XCBC_TYPE       = 8,
+	SHA3_SHA224     = 10,
+	SHA3_SHA256     = 11,
+	SHA3_SHA384     = 12,
+	SHA3_SHA512     = 13,
+	SHA3_SHAKE256   = 14,
+	SHA3_SHAKE512   = 15,
+
+	/* These are only for software use */
+	ZUC_EIA3        = 0x90,
+	SNOW3G_UIA2     = 0x91,
+	KASUMI_F9_CBC   = 0x92,
+	KASUMI_F9_ECB   = 0x93,
+} mc_hash_type_t;
+
+typedef enum {
+	/*
+	 * These are defined by MC for Flexi crypto
+	 * for field of 4 bits
+	 */
+	DES3_CBC    = 0x1,
+	DES3_ECB    = 0x2,
+	AES_CBC     = 0x3,
+	AES_ECB     = 0x4,
+	AES_CFB     = 0x5,
+	AES_CTR     = 0x6,
+	AES_GCM     = 0x7,
+	AES_XTS     = 0x8,
+
+	/* These are only for software use */
+	ZUC_EEA3        = 0x90,
+	SNOW3G_UEA2     = 0x91,
+	KASUMI_F8_CBC   = 0x92,
+	KASUMI_F8_ECB   = 0x93,
+} mc_cipher_type_t;
+
+typedef enum {
+	AES_128_BIT = 0x1,
+	AES_192_BIT = 0x2,
+	AES_256_BIT = 0x3
+} mc_aes_type_t;
+
+
 typedef struct sglist_comp {
 	union {
 		uint64_t len;
@@ -143,6 +220,17 @@ struct cpt_ctx {
 	uint8_t  auth_key[64];
 };
 
+typedef struct fc_params digest_params_t;
+
+/* Cipher Algorithms */
+typedef mc_cipher_type_t cipher_type_t;
+
+/* Auth Algorithms */
+typedef mc_hash_type_t auth_type_t;
+
 #define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
 
+#define SESS_PRIV(__sess) \
+	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
+
 #endif /* _CPT_MCODE_DEFINES_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index e4f16fe..a9aef68 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -12,6 +12,13 @@
  *
  */
 
+static uint8_t zuc_d[32] = {
+	0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
+	0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
+	0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
+	0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC
+};
+
 static __rte_always_inline int
 cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
 {
@@ -44,4 +51,571 @@ cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
 	return 0;
 }
 
+static __rte_always_inline void
+gen_key_snow3g(uint8_t *ck, uint32_t *keyx)
+{
+	int i, base;
+
+	for (i = 0; i < 4; i++) {
+		base = 4 * i;
+		keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
+			(ck[base + 2] << 8) | (ck[base + 3]);
+		keyx[3 - i] = rte_cpu_to_be_32(keyx[3 - i]);
+	}
+}
+
+static __rte_always_inline int
+cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,
+		    uint16_t key_len, uint8_t *salt)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	mc_fc_context_t *fctx = &cpt_ctx->fctx;
+	mc_aes_type_t aes_key_type = 0;
+	uint64_t *ctrl_flags;
+
+	if (!type) {
+		/* to support passthrough case */
+
+		cpt_ctx->fc_type = FC_GEN;
+		ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags);
+		cpt_ctx->enc_cipher = 0;
+
+		*ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
+		CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
+		*ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
+
+		return 0;
+	}
+
+	if ((type >= ZUC_EEA3) && (type <= KASUMI_F8_ECB)) {
+		uint32_t keyx[4];
+
+		if (key_len != 16)
+			return -1;
+
+		/* No support for AEAD yet */
+		if (cpt_ctx->hash_type)
+			return -1;
+
+		/* For ZUC/SNOW3G/Kasumi */
+		switch (type) {
+		case SNOW3G_UEA2:
+			cpt_ctx->snow3g = 1;
+			gen_key_snow3g(key, keyx);
+			memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0;
+			break;
+		case ZUC_EEA3:
+			cpt_ctx->snow3g = 0;
+			memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
+			memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0;
+			break;
+		case KASUMI_F8_ECB:
+			/* Kasumi ECB mode */
+			cpt_ctx->k_ecb = 1;
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->zsk_flags = 0;
+			cpt_ctx->fc_type = KASUMI;
+			break;
+		case KASUMI_F8_CBC:
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->zsk_flags = 0;
+			cpt_ctx->fc_type = KASUMI;
+			break;
+		default:
+			return -1;
+		}
+		cpt_ctx->enc_cipher = type;
+		return 0;
+	}
+
+	fctx = &cpt_ctx->fctx;
+	/* Even though iv source is from dptr,
+	 * aes_gcm salt is taken from ctx
+	 */
+	if (salt && (type == AES_GCM)) {
+		memcpy(fctx->enc.encr_iv, salt, 4);
+		/* Assuming it was just salt update
+		 * and nothing else
+		 */
+		if (!key)
+			return 0;
+	}
+
+	cpt_ctx->fc_type = FC_GEN;
+	ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags);
+	*ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
+
+	cpt_ctx->enc_cipher = type;
+
+	/* For GMAC auth, cipher must be NULL */
+	if (cpt_ctx->hash_type != GMAC_TYPE)
+		CPT_P_ENC_CTRL(fctx).enc_cipher = type;
+
+	if (type == AES_XTS)
+		key_len = key_len / 2;
+
+	/* key len only for AES */
+	if ((type != DES3_CBC) &&
+	    (type != DES3_ECB)) {
+		switch (key_len) {
+		case CPT_BYTE_16:
+			aes_key_type = AES_128_BIT;
+			break;
+		case CPT_BYTE_24:
+			aes_key_type = AES_192_BIT;
+			if (type == AES_XTS) {
+				CPT_LOG_DP_ERR("Invalid AES key len for"
+					    " XTS\n");
+				return -1;
+			}
+			break;
+		case CPT_BYTE_32:
+			aes_key_type = AES_256_BIT;
+			break;
+		default:
+			CPT_LOG_DP_ERR("Invalid AES key len\n");
+			return -1;
+		}
+
+		CPT_P_ENC_CTRL(fctx).aes_key = aes_key_type;
+	}
+
+	/*
+	 * We need to always say iv is from DPTR as user can
+	 * sometimes override IV per operation.
+	 * For DES3_ECB IV need to be from CTX.
+	 */
+	if (type == DES3_ECB)
+		CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_CTX;
+	else
+		CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_DPTR;
+
+	memcpy(fctx->enc.encr_key, key, key_len);
+
+	if ((type == DES3_CBC) && (key_len == 8)) {
+		/* CPT performs DES using 3DES with the 8B DES-key
+		 * replicated 2 more times to match the 24B 3DES-key.
+		 * Eg. If org. key is "0x0a 0x0b", then new key is
+		 * "0x0a 0x0b 0x0a 0x0b 0x0a 0x0b"
+		 */
+		memcpy(fctx->enc.encr_key+key_len, key, key_len);
+		memcpy(fctx->enc.encr_key+2*key_len, key, key_len);
+	}
+
+	if (type == AES_XTS) {
+		/* Copy key2 for XTS into ipad */
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memcpy(fctx->hmac.ipad, &key[key_len], key_len);
+	}
+
+	*ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
+
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_fc_auth_set_key(void *ctx, auth_type_t type, uint8_t *key,
+		    uint16_t key_len, uint16_t mac_len)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	mc_fc_context_t *fctx = &cpt_ctx->fctx;
+	uint64_t *ctrl_flags = NULL;
+
+	if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
+		uint32_t keyx[4];
+
+		if (key_len != 16)
+			return -1;
+		/* No support for AEAD yet */
+		if (cpt_ctx->enc_cipher)
+			return -1;
+		/* For ZUC/SNOW3G/Kasumi */
+		switch (type) {
+		case SNOW3G_UIA2:
+			cpt_ctx->snow3g = 1;
+			gen_key_snow3g(key, keyx);
+			memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case ZUC_EIA3:
+			cpt_ctx->snow3g = 0;
+			memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
+			memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case KASUMI_F9_ECB:
+			/* Kasumi ECB mode */
+			cpt_ctx->k_ecb = 1;
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->fc_type = KASUMI;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case KASUMI_F9_CBC:
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->fc_type = KASUMI;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		default:
+			return -1;
+		}
+		cpt_ctx->mac_len = 4;
+		cpt_ctx->hash_type = type;
+		return 0;
+	}
+
+	if (!(cpt_ctx->fc_type == FC_GEN && !type)) {
+		if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher)
+			cpt_ctx->fc_type = HASH_HMAC;
+	}
+
+	ctrl_flags = (uint64_t *)&fctx->enc.enc_ctrl.flags;
+	*ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
+
+	/* For GMAC auth, cipher must be NULL */
+	if (type == GMAC_TYPE)
+		CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
+
+	CPT_P_ENC_CTRL(fctx).hash_type = cpt_ctx->hash_type = type;
+	CPT_P_ENC_CTRL(fctx).mac_len = cpt_ctx->mac_len = mac_len;
+
+	if (key_len) {
+		cpt_ctx->hmac = 1;
+		memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key));
+		memcpy(cpt_ctx->auth_key, key, key_len);
+		cpt_ctx->auth_key_len = key_len;
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
+		memcpy(fctx->hmac.opad, key, key_len);
+		CPT_P_ENC_CTRL(fctx).auth_input_type = 1;
+	}
+	*ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
+	return 0;
+}
+
+static __rte_always_inline int
+fill_sess_aead(struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_aead_xform *aead_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint32_t cipher_key_len = 0;
+	uint8_t zsk_flag = 0, aes_gcm = 0;
+	aead_form = &xform->aead;
+	void *ctx;
+
+	if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
+	   aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+		sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
+		sess->cpt_op |= CPT_OP_AUTH_GENERATE;
+	} else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
+		aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+		sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
+		sess->cpt_op |= CPT_OP_AUTH_VERIFY;
+	} else {
+		CPT_LOG_DP_ERR("Unknown cipher operation\n");
+		return -1;
+	}
+	switch (aead_form->algo) {
+	case RTE_CRYPTO_AEAD_AES_GCM:
+		enc_type = AES_GCM;
+		cipher_key_len = 16;
+		aes_gcm = 1;
+		break;
+	case RTE_CRYPTO_AEAD_AES_CCM:
+		CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
+			       aead_form->algo);
+		return -1;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
+			       aead_form->algo);
+		return -1;
+	}
+	if (aead_form->key.length < cipher_key_len) {
+		CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
+			       (unsigned int long)aead_form->key.length);
+		return -1;
+	}
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->mac_len = aead_form->digest_length;
+	sess->iv_offset = aead_form->iv.offset;
+	sess->iv_length = aead_form->iv.length;
+	sess->aad_length = aead_form->aad_length;
+	ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+
+	cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
+			aead_form->key.length, NULL);
+
+	cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, aead_form->digest_length);
+
+	return 0;
+}
+
+static __rte_always_inline int
+fill_sess_cipher(struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_cipher_xform *c_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	uint32_t cipher_key_len = 0;
+	uint8_t zsk_flag = 0, aes_gcm = 0, aes_ctr = 0, is_null = 0;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER)
+		return -1;
+
+	c_form = &xform->cipher;
+
+	if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
+		sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
+	else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
+		sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
+	else {
+		CPT_LOG_DP_ERR("Unknown cipher operation\n");
+		return -1;
+	}
+
+	switch (c_form->algo) {
+	case RTE_CRYPTO_CIPHER_AES_CBC:
+		enc_type = AES_CBC;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CBC:
+		enc_type = DES3_CBC;
+		cipher_key_len = 24;
+		break;
+	case RTE_CRYPTO_CIPHER_DES_CBC:
+		/* DES is implemented using 3DES in hardware */
+		enc_type = DES3_CBC;
+		cipher_key_len = 8;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_CTR:
+		enc_type = AES_CTR;
+		cipher_key_len = 16;
+		aes_ctr = 1;
+		break;
+	case RTE_CRYPTO_CIPHER_NULL:
+		enc_type = 0;
+		is_null = 1;
+		break;
+	case RTE_CRYPTO_CIPHER_KASUMI_F8:
+		enc_type = KASUMI_F8_ECB;
+		cipher_key_len = 16;
+		zsk_flag = K_F8;
+		break;
+	case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
+		enc_type = SNOW3G_UEA2;
+		cipher_key_len = 16;
+		zsk_flag = ZS_EA;
+		break;
+	case RTE_CRYPTO_CIPHER_ZUC_EEA3:
+		enc_type = ZUC_EEA3;
+		cipher_key_len = 16;
+		zsk_flag = ZS_EA;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_XTS:
+		enc_type = AES_XTS;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_ECB:
+		enc_type = DES3_ECB;
+		cipher_key_len = 24;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_ECB:
+		enc_type = AES_ECB;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CTR:
+	case RTE_CRYPTO_CIPHER_AES_F8:
+	case RTE_CRYPTO_CIPHER_ARC4:
+		CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
+			       c_form->algo);
+		return -1;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
+			       c_form->algo);
+		return -1;
+	}
+
+	if (c_form->key.length < cipher_key_len) {
+		CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
+			       (unsigned long) c_form->key.length);
+		return -1;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->aes_ctr = aes_ctr;
+	sess->iv_offset = c_form->iv.offset;
+	sess->iv_length = c_form->iv.length;
+	sess->is_null = is_null;
+
+	cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type, c_form->key.data,
+			    c_form->key.length, NULL);
+
+	return 0;
+}
+
+static __rte_always_inline int
+fill_sess_auth(struct rte_crypto_sym_xform *xform,
+	       struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_auth_xform *a_form;
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint8_t zsk_flag = 0, aes_gcm = 0, is_null = 0;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
+		goto error_out;
+
+	a_form = &xform->auth;
+
+	if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
+		sess->cpt_op |= CPT_OP_AUTH_VERIFY;
+	else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
+		sess->cpt_op |= CPT_OP_AUTH_GENERATE;
+	else {
+		CPT_LOG_DP_ERR("Unknown auth operation");
+		return -1;
+	}
+
+	if (a_form->key.length > 64) {
+		CPT_LOG_DP_ERR("Auth key length is big");
+		return -1;
+	}
+
+	switch (a_form->algo) {
+	case RTE_CRYPTO_AUTH_SHA1_HMAC:
+		/* Fall through */
+	case RTE_CRYPTO_AUTH_SHA1:
+		auth_type = SHA1_TYPE;
+		break;
+	case RTE_CRYPTO_AUTH_SHA256_HMAC:
+	case RTE_CRYPTO_AUTH_SHA256:
+		auth_type = SHA2_SHA256;
+		break;
+	case RTE_CRYPTO_AUTH_SHA512_HMAC:
+	case RTE_CRYPTO_AUTH_SHA512:
+		auth_type = SHA2_SHA512;
+		break;
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		auth_type = GMAC_TYPE;
+		aes_gcm = 1;
+		break;
+	case RTE_CRYPTO_AUTH_SHA224_HMAC:
+	case RTE_CRYPTO_AUTH_SHA224:
+		auth_type = SHA2_SHA224;
+		break;
+	case RTE_CRYPTO_AUTH_SHA384_HMAC:
+	case RTE_CRYPTO_AUTH_SHA384:
+		auth_type = SHA2_SHA384;
+		break;
+	case RTE_CRYPTO_AUTH_MD5_HMAC:
+	case RTE_CRYPTO_AUTH_MD5:
+		auth_type = MD5_TYPE;
+		break;
+	case RTE_CRYPTO_AUTH_KASUMI_F9:
+		auth_type = KASUMI_F9_ECB;
+		/*
+		 * Indicate that direction needs to be taken out
+		 * from end of src
+		 */
+		zsk_flag = K_F9;
+		break;
+	case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
+		auth_type = SNOW3G_UIA2;
+		zsk_flag = ZS_IA;
+		break;
+	case RTE_CRYPTO_AUTH_ZUC_EIA3:
+		auth_type = ZUC_EIA3;
+		zsk_flag = ZS_IA;
+		break;
+	case RTE_CRYPTO_AUTH_NULL:
+		auth_type = 0;
+		is_null = 1;
+		break;
+	case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+	case RTE_CRYPTO_AUTH_AES_CMAC:
+	case RTE_CRYPTO_AUTH_AES_CBC_MAC:
+		CPT_LOG_DP_ERR("Crypto: Unsupported hash algo %u",
+			       a_form->algo);
+		goto error_out;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined Hash algo %u specified",
+			       a_form->algo);
+		goto error_out;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->mac_len = a_form->digest_length;
+	sess->is_null = is_null;
+	if (zsk_flag) {
+		sess->auth_iv_offset = a_form->iv.offset;
+		sess->auth_iv_length = a_form->iv.length;
+	}
+	cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type, a_form->key.data,
+			    a_form->key.length, a_form->digest_length);
+
+	return 0;
+
+error_out:
+	return -1;
+}
+
+static __rte_always_inline int
+fill_sess_gmac(struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_auth_xform *a_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint8_t zsk_flag = 0, aes_gcm = 0;
+	void *ctx;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
+		return -1;
+
+	a_form = &xform->auth;
+
+	if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
+		sess->cpt_op |= CPT_OP_ENCODE;
+	else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
+		sess->cpt_op |= CPT_OP_DECODE;
+	else {
+		CPT_LOG_DP_ERR("Unknown auth operation");
+		return -1;
+	}
+
+	switch (a_form->algo) {
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		enc_type = AES_GCM;
+		auth_type = GMAC_TYPE;
+		break;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
+			       a_form->algo);
+		return -1;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->is_gmac = 1;
+	sess->iv_offset = a_form->iv.offset;
+	sess->iv_length = a_form->iv.length;
+	sess->mac_len = a_form->digest_length;
+	ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+
+	cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
+			a_form->key.length, NULL);
+	cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, a_form->digest_length);
+
+	return 0;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v2 19/33] crypto/octeontx: add supported sessions

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding AEAD, cipher & auth sessions support.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_ops.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 51f374d..438208c 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -298,6 +298,23 @@ otx_cpt_session_cfg(struct rte_cryptodev *dev,
 	chain = xform;
 	while (chain) {
 		switch (chain->type) {
+		case RTE_CRYPTO_SYM_XFORM_AEAD:
+			if (fill_sess_aead(chain, sess_private_data))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_CIPHER:
+			if (fill_sess_cipher(chain, sess_private_data))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_AUTH:
+			if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
+				if (fill_sess_gmac(chain, sess_private_data))
+					goto err;
+			} else {
+				if (fill_sess_auth(chain, sess_private_data))
+					goto err;
+			}
+			break;
 		default:
 			CPT_LOG_ERR("Invalid crypto xform type");
 			break;
-- 
2.7.4

[dpdk-dev] [PATCH v2 20/33] common/cpt: add common defines for microcode

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h | 121 +++++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 0d2d0db..17b0de3 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -12,6 +12,12 @@
  * This file defines macros and structures according to microcode spec
  *
  */
+/* SE opcodes */
+#define CPT_MAJOR_OP_FC		0x33
+#define CPT_MAJOR_OP_HASH	0x34
+#define CPT_MAJOR_OP_HMAC	0x35
+#define CPT_MAJOR_OP_ZUC_SNOW3G	0x37
+#define CPT_MAJOR_OP_KASUMI	0x38
 
 #define CPT_BYTE_16		16
 #define CPT_BYTE_24		24
@@ -30,6 +36,10 @@
 #define CPT_FROM_CTX		0
 #define CPT_FROM_DPTR		1
 
+#define SE_CORE_REQ		1
+
+#define CTRL_DMA_MODE_SGIO	2	/* DMA Mode but SGIO is already setup */
+
 #define FC_GEN			0x1
 #define ZUC_SNOW3G		0x2
 #define KASUMI			0x3
@@ -54,6 +64,25 @@
 /* #define CPT_ALWAYS_USE_SG_MODE */
 #define CPT_ALWAYS_USE_SEPARATE_BUF
 
+/*
+ * Parameters for Flexi Crypto
+ * requests
+ */
+#define VALID_AAD_BUF 0x01
+#define VALID_MAC_BUF 0x02
+#define VALID_IV_BUF 0x04
+#define SINGLE_BUF_INPLACE 0x08
+#define SINGLE_BUF_HEADTAILROOM 0x10
+
+#define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff)
+#define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff)
+#define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff)
+#define ENCR_DLEN(__d_lens) (__d_lens >> 32)
+#define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff)
+
+/* FC offset_control at start of DPTR in bytes */
+#define OFF_CTRL_LEN  8 /* bytes */
+
 typedef enum {
 	MD5_TYPE        = 1,
 	SHA1_TYPE       = 2,
@@ -104,6 +133,48 @@ typedef enum {
 	AES_256_BIT = 0x3
 } mc_aes_type_t;
 
+typedef enum {
+	/* Microcode errors */
+	NO_ERR = 0x00,
+	ERR_OPCODE_UNSUPPORTED = 0x01,
+
+	/* SCATTER GATHER */
+	ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,
+	ERR_SCATTER_GATHER_LIST = 0x03,
+	ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,
+
+	/* SE GC */
+	ERR_GC_LENGTH_INVALID = 0x41,
+	ERR_GC_RANDOM_LEN_INVALID = 0x42,
+	ERR_GC_DATA_LEN_INVALID = 0x43,
+	ERR_GC_DRBG_TYPE_INVALID = 0x44,
+	ERR_GC_CTX_LEN_INVALID = 0x45,
+	ERR_GC_CIPHER_UNSUPPORTED = 0x46,
+	ERR_GC_AUTH_UNSUPPORTED = 0x47,
+	ERR_GC_OFFSET_INVALID = 0x48,
+	ERR_GC_HASH_MODE_UNSUPPORTED = 0x49,
+	ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,
+	ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,
+	ERR_GC_ICV_MISCOMPARE = 0x4c,
+	ERR_GC_DATA_UNALIGNED = 0x4d,
+
+	/* API Layer */
+	ERR_BAD_ALT_CCODE = 0xfd,
+	ERR_REQ_PENDING = 0xfe,
+	ERR_REQ_TIMEOUT = 0xff,
+
+	ERR_BAD_INPUT_LENGTH = (0x40000000 | 384),    /* 0x40000180 */
+	ERR_BAD_KEY_LENGTH,
+	ERR_BAD_KEY_HANDLE,
+	ERR_BAD_CONTEXT_HANDLE,
+	ERR_BAD_SCALAR_LENGTH,
+	ERR_BAD_DIGEST_LENGTH,
+	ERR_BAD_INPUT_ARG,
+	ERR_BAD_RECORD_PADDING,
+	ERR_NB_REQUEST_PENDING,
+	ERR_EIO,
+	ERR_ENODEV,
+} mc_error_code_t;
 
 typedef struct sglist_comp {
 	union {
@@ -220,6 +291,49 @@ struct cpt_ctx {
 	uint8_t  auth_key[64];
 };
 
+/* Buffer pointer */
+typedef struct buf_ptr {
+	void *vaddr;
+	phys_addr_t dma_addr;
+	uint32_t size;
+	uint32_t resv;
+} buf_ptr_t;
+
+/* IOV Pointer */
+typedef struct{
+	int buf_cnt;
+	buf_ptr_t bufs[0];
+} iov_ptr_t;
+
+typedef union opcode_info {
+	uint16_t flags;
+	struct {
+		uint8_t major;
+		uint8_t minor;
+	} s;
+} opcode_info_t;
+
+typedef struct fc_params {
+	/* 0th cache line */
+	union {
+		buf_ptr_t bufs[1];
+		struct {
+			iov_ptr_t *src_iov;
+			iov_ptr_t *dst_iov;
+		};
+	};
+	void *iv_buf;
+	void *auth_iv_buf;
+	buf_ptr_t meta_buf;
+	buf_ptr_t ctx_buf;
+	uint64_t rsvd2;
+
+	/* 1st cache line */
+	buf_ptr_t aad_buf;
+	buf_ptr_t mac_buf;
+
+} fc_params_t;
+
 typedef struct fc_params digest_params_t;
 
 /* Cipher Algorithms */
@@ -228,8 +342,15 @@ typedef mc_cipher_type_t cipher_type_t;
 /* Auth Algorithms */
 typedef mc_hash_type_t auth_type_t;
 
+/* Helper macros */
+
 #define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
 
+#define SRC_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
+#define DST_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
+
 #define SESS_PRIV(__sess) \
 	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
 
-- 
2.7.4

[dpdk-dev] [PATCH v2 21/33] common/cpt: add microcode interface for encryption

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding microcode interface additions for supporting encryption.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 1003 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 1003 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index a9aef68..add5f95 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -5,6 +5,10 @@
 #ifndef _CPT_UCODE_H_
 #define _CPT_UCODE_H_
 
+#include <stdbool.h>
+
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
 #include "cpt_mcode_defines.h"
 
 /*
@@ -64,6 +68,14 @@ gen_key_snow3g(uint8_t *ck, uint32_t *keyx)
 	}
 }
 
+static __rte_always_inline void
+cpt_fc_salt_update(void *ctx,
+		   uint8_t *salt)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	memcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);
+}
+
 static __rte_always_inline int
 cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,
 		    uint16_t key_len, uint8_t *salt)
@@ -217,6 +229,564 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,
 	return 0;
 }
 
+static __rte_always_inline uint32_t
+fill_sg_comp(sg_comp_t *list,
+	     uint32_t i,
+	     phys_addr_t dma_addr,
+	     void *vaddr,
+	     uint32_t size)
+{
+	sg_comp_t *to = &list[i>>2];
+
+	to->u.s.len[i%4] = rte_cpu_to_be_16(size);
+	to->ptr[i%4] = rte_cpu_to_be_64(dma_addr);
+	(void) vaddr;
+	i++;
+	return i;
+}
+
+static __rte_always_inline uint32_t
+fill_sg_comp_from_buf(sg_comp_t *list,
+		      uint32_t i,
+		      buf_ptr_t *from)
+{
+	sg_comp_t *to = &list[i>>2];
+
+	to->u.s.len[i%4] = rte_cpu_to_be_16(from->size);
+	to->ptr[i%4] = rte_cpu_to_be_64(from->dma_addr);
+	i++;
+	return i;
+}
+
+static __rte_always_inline uint32_t
+fill_sg_comp_from_buf_min(sg_comp_t *list,
+			  uint32_t i,
+			  buf_ptr_t *from,
+			  uint32_t *psize)
+{
+	sg_comp_t *to = &list[i >> 2];
+	uint32_t size = *psize;
+	uint32_t e_len;
+
+	e_len = (size > from->size) ? from->size : size;
+	to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
+	to->ptr[i % 4] = rte_cpu_to_be_64(from->dma_addr);
+	*psize -= e_len;
+	i++;
+	return i;
+}
+
+/*
+ * This fills the MC expected SGIO list
+ * from IOV given by user.
+ */
+static __rte_always_inline uint32_t
+fill_sg_comp_from_iov(sg_comp_t *list,
+		      uint32_t i,
+		      iov_ptr_t *from, uint32_t from_offset,
+		      uint32_t *psize, buf_ptr_t *extra_buf,
+		      uint32_t extra_offset)
+{
+	int32_t j;
+	uint32_t extra_len = extra_buf ? extra_buf->size : 0;
+	uint32_t size = *psize - extra_len;
+	buf_ptr_t *bufs;
+
+	bufs = from->bufs;
+	for (j = 0; (j < from->buf_cnt) && size; j++) {
+		phys_addr_t e_dma_addr;
+		uint32_t e_len;
+		sg_comp_t *to = &list[i >> 2];
+
+		if (!bufs[j].size)
+			continue;
+
+		if (unlikely(from_offset)) {
+			if (from_offset >= bufs[j].size) {
+				from_offset -= bufs[j].size;
+				continue;
+			}
+			e_dma_addr = bufs[j].dma_addr + from_offset;
+			e_len = (size > (bufs[j].size - from_offset)) ?
+				(bufs[j].size - from_offset) : size;
+			from_offset = 0;
+		} else {
+			e_dma_addr = bufs[j].dma_addr;
+			e_len = (size > bufs[j].size) ?
+				bufs[j].size : size;
+		}
+
+		to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
+		to->ptr[i % 4] = rte_cpu_to_be_64(e_dma_addr);
+
+		if (extra_len && (e_len >= extra_offset)) {
+			/* Break the data at given offset */
+			uint32_t next_len = e_len - extra_offset;
+			phys_addr_t next_dma = e_dma_addr + extra_offset;
+
+			if (!extra_offset) {
+				i--;
+			} else {
+				e_len = extra_offset;
+				size -= e_len;
+				to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
+			}
+
+			/* Insert extra data ptr */
+			if (extra_len) {
+				i++;
+				to = &list[i >> 2];
+				to->u.s.len[i % 4] =
+					rte_cpu_to_be_16(extra_buf->size);
+				to->ptr[i % 4] =
+					rte_cpu_to_be_64(extra_buf->dma_addr);
+
+				/* size already decremented by extra len */
+			}
+
+			/* insert the rest of the data */
+			if (next_len) {
+				i++;
+				to = &list[i >> 2];
+				to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
+				to->ptr[i % 4] = rte_cpu_to_be_64(next_dma);
+				size -= next_len;
+			}
+			extra_len = 0;
+
+		} else {
+			size -= e_len;
+		}
+		if (extra_offset)
+			extra_offset -= size;
+		i++;
+	}
+
+	*psize = size;
+	return (uint32_t)i;
+}
+
+static __rte_always_inline int
+cpt_enc_hmac_prep(uint32_t flags,
+		  uint64_t d_offs,
+		  uint64_t d_lens,
+		  fc_params_t *fc_params,
+		  void *op,
+		  void **prep_req)
+{
+	uint32_t iv_offset = 0;
+	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t cipher_type, hash_type;
+	uint32_t mac_len, size;
+	uint8_t iv_len = 16;
+	struct cpt_request_info *req;
+	buf_ptr_t *meta_p, *aad_buf = NULL;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len, aad_len = 0;
+	uint32_t passthrough_len = 0;
+	void *m_vaddr, *offset_vaddr;
+	uint64_t m_dma, offset_dma, ctx_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr;
+	uint64_t c_dma;
+	int32_t m_size;
+	opcode_info_t opcode;
+
+	meta_p = &fc_params->meta_buf;
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs);
+	auth_offset = AUTH_OFFSET(d_offs);
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * We dont support both aad
+		 * and auth data separately
+		 */
+		auth_data_len = 0;
+		auth_offset = 0;
+		aad_len = fc_params->aad_buf.size;
+		aad_buf = &fc_params->aad_buf;
+	}
+	cpt_ctx = fc_params->ctx_buf.vaddr;
+	cipher_type = cpt_ctx->enc_cipher;
+	hash_type = cpt_ctx->hash_type;
+	mac_len = cpt_ctx->mac_len;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* start cpt request info struct at 8 byte boundary */
+	size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+		(uint8_t *)m_vaddr;
+
+	req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
+
+	size += sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	if (hash_type == GMAC_TYPE)
+		encr_data_len = 0;
+
+	if (unlikely(!(flags & VALID_IV_BUF))) {
+		iv_len = 0;
+		iv_offset = ENCR_IV_OFFSET(d_offs);
+	}
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * When AAD is given, data above encr_offset is pass through
+		 * Since AAD is given as separate pointer and not as offset,
+		 * this is a special case as we need to fragment input data
+		 * into passthrough + encr_data and then insert AAD in between.
+		 */
+		if (hash_type != GMAC_TYPE) {
+			passthrough_len = encr_offset;
+			auth_offset = passthrough_len + iv_len;
+			encr_offset = passthrough_len + aad_len + iv_len;
+			auth_data_len = aad_len + encr_data_len;
+		} else {
+			passthrough_len = 16 + aad_len;
+			auth_offset = passthrough_len + iv_len;
+			auth_data_len = aad_len;
+		}
+	} else {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/* Initialising ctrl and opcode
+	 * fields in cpt request structure
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	/*
+	 * We are using DMA mode but indicate that
+	 * SGIO list is already populated.
+	 */
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	/* Encryption */
+	opcode.s.major = CPT_MAJOR_OP_FC;
+	opcode.s.minor = 0;
+
+	auth_dlen = auth_offset + auth_data_len;
+	enc_dlen = encr_data_len + encr_offset;
+	if (unlikely(encr_data_len & 0xf)) {
+		if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
+			enc_dlen = ROUNDUP8(encr_data_len) + encr_offset;
+		else if (likely((cipher_type == AES_CBC) ||
+				(cipher_type == AES_ECB)))
+			enc_dlen = ROUNDUP16(encr_data_len) + encr_offset;
+	}
+
+	if (unlikely(hash_type == GMAC_TYPE)) {
+		encr_offset = auth_dlen;
+		enc_dlen = 0;
+	}
+
+	if (unlikely(auth_dlen > enc_dlen)) {
+		inputlen = auth_dlen;
+		outputlen = auth_dlen + mac_len;
+	} else {
+		inputlen = enc_dlen;
+		outputlen = enc_dlen + mac_len;
+	}
+
+	/*GP op header */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((flags & SINGLE_BUF_INPLACE) &&
+		   (flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = fc_params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+
+		/* This falls under strict SG mode */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+		size = OFF_CTRL_LEN + iv_len;
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+
+		i = 0;
+
+		/* Offset control word that includes iv */
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+		/* Add input data */
+		size = inputlen - iv_len;
+		if (likely(size)) {
+			uint32_t aad_offset = aad_len ? passthrough_len : 0;
+
+			if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+				i = fill_sg_comp_from_buf_min(gather_comp, i,
+							      fc_params->bufs,
+							      &size);
+			} else {
+
+				i = fill_sg_comp_from_iov(gather_comp, i,
+							  fc_params->src_iov,
+							  0, &size,
+							  aad_buf, aad_offset);
+			}
+
+			if (unlikely(size)) {
+				CPT_LOG_DP_ERR("Insufficient buffer space,"
+					   " size %d need\n", size);
+				return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter list
+		 */
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* Add IV */
+		if (likely(iv_len)) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* output data or output data + digest*/
+		if (unlikely(flags & VALID_MAC_BUF)) {
+			size = outputlen - iv_len - mac_len;
+			if (size) {
+				uint32_t aad_offset =
+					aad_len ? passthrough_len : 0;
+
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+								scatter_comp,
+								i,
+								fc_params->bufs,
+								&size);
+				} else {
+					i = fill_sg_comp_from_iov(scatter_comp,
+								i,
+							     fc_params->dst_iov,
+								0,
+								&size,
+								aad_buf,
+								aad_offset);
+				}
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+			/* mac_data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(scatter_comp, i,
+							  &fc_params->mac_buf);
+			}
+		} else {
+			/* Output including mac */
+			size = outputlen - iv_len;
+			if (likely(size)) {
+				uint32_t aad_offset =
+					aad_len ? passthrough_len : 0;
+
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+								scatter_comp,
+								i,
+								fc_params->bufs,
+								&size);
+				} else {
+					i = fill_sg_comp_from_iov(scatter_comp,
+								i,
+							     fc_params->dst_iov,
+								0,
+								&size,
+								aad_buf,
+								aad_offset);
+				}
+				if (unlikely(size)) {
+					CPT_LOG_DP_ERR("Insufficient "
+					"buffer space, size %d need\n", size);
+					return ERR_BAD_INPUT_ARG;
+				}
+			}
+		}
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	ctx_dma = fc_params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, fctx);
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = ctx_dma;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op  = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline void *__hot
+cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
+		     fc_params_t *fc_params, void *op, int *ret_val)
+{
+	struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+	uint8_t fc_type;
+	void *prep_req = NULL;
+	int ret;
+
+	fc_type = ctx->fc_type;
+
+	/* Common api for rest of the ops */
+	if (likely(fc_type == FC_GEN)) {
+		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
+					fc_params, op, &prep_req);
+	} else {
+		ret = ERR_EIO;
+	}
+
+	if (unlikely(!prep_req))
+		*ret_val = ret;
+	return prep_req;
+}
+
 static __rte_always_inline int
 cpt_fc_auth_set_key(void *ctx, auth_type_t type, uint8_t *key,
 		    uint16_t key_len, uint16_t mac_len)
@@ -618,4 +1188,437 @@ fill_sess_gmac(struct rte_crypto_sym_xform *xform,
 	return 0;
 }
 
+static __rte_always_inline void *
+alloc_op_meta(struct rte_mbuf *m_src,
+	      buf_ptr_t *buf,
+	      int32_t len,
+	      struct rte_mempool *cpt_meta_pool)
+{
+	uint8_t *mdata;
+
+#ifndef CPT_ALWAYS_USE_SEPARATE_BUF
+	if (likely(m_src && (m_src->nb_segs == 1))) {
+		int32_t tailroom;
+		phys_addr_t mphys;
+
+		/* Check if tailroom is sufficient to hold meta data */
+		tailroom = rte_pktmbuf_tailroom(m_src);
+		if (likely(tailroom > len + 8)) {
+			mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;
+			mphys = m_src->buf_physaddr + m_src->buf_len;
+			mdata -= len;
+			mphys -= len;
+			buf->vaddr = mdata;
+			buf->dma_addr = mphys;
+			buf->size = len;
+			/* Indicate that this is a mbuf allocated mdata */
+			mdata = (uint8_t *)((uint64_t)mdata | 1ull);
+			return mdata;
+		}
+	}
+#else
+	(void) m_src;
+#endif
+
+	if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))
+		return NULL;
+
+	buf->vaddr = mdata;
+	buf->dma_addr = rte_mempool_virt2iova(mdata);
+	buf->size = len;
+
+	return mdata;
+}
+
+/**
+ * cpt_free_metabuf - free metabuf to mempool.
+ * @param instance: pointer to instance.
+ * @param objp: pointer to the metabuf.
+ */
+static __rte_always_inline void
+free_op_meta(void *mdata, struct rte_mempool *cpt_meta_pool)
+{
+	bool nofree = ((uintptr_t)mdata & 1ull);
+
+	if (likely(nofree))
+		return;
+	rte_mempool_put(cpt_meta_pool, mdata);
+}
+
+static __rte_always_inline uint32_t
+prepare_iov_from_pkt(struct rte_mbuf *pkt,
+		     iov_ptr_t *iovec, uint32_t start_offset)
+{
+	uint16_t index = 0;
+	void *seg_data = NULL;
+	phys_addr_t seg_phys;
+	int32_t seg_size = 0;
+
+	if (!pkt) {
+		iovec->buf_cnt = 0;
+		return 0;
+	}
+
+	if (!start_offset) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+	} else {
+		while (start_offset >= pkt->data_len) {
+			start_offset -= pkt->data_len;
+			pkt = pkt->next;
+		}
+
+		seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);
+		seg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset);
+		seg_size = pkt->data_len - start_offset;
+		if (!seg_size)
+			return 1;
+	}
+
+	/* first seg */
+	iovec->bufs[index].vaddr = seg_data;
+	iovec->bufs[index].dma_addr = seg_phys;
+	iovec->bufs[index].size = seg_size;
+	index++;
+	pkt = pkt->next;
+
+	while (unlikely(pkt != NULL)) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+		if (!seg_size)
+			break;
+
+		iovec->bufs[index].vaddr = seg_data;
+		iovec->bufs[index].dma_addr = seg_phys;
+		iovec->bufs[index].size = seg_size;
+
+		index++;
+
+		/* FIXME: Not depending on wqe.w0.s.bufs to break */
+		pkt = pkt->next;
+	}
+
+	iovec->buf_cnt = index;
+	return 0;
+}
+
+static __rte_always_inline uint32_t
+prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,
+			     fc_params_t *param,
+			     uint32_t *flags)
+{
+	uint16_t index = 0;
+	void *seg_data = NULL;
+	phys_addr_t seg_phys;
+	uint32_t seg_size = 0;
+	iov_ptr_t *iovec;
+
+	seg_data = rte_pktmbuf_mtod(pkt, void *);
+	seg_phys = rte_pktmbuf_mtophys(pkt);
+	seg_size = pkt->data_len;
+
+	/* first seg */
+	if (likely(!pkt->next)) {
+		uint32_t headroom, tailroom;
+
+		*flags |= SINGLE_BUF_INPLACE;
+		headroom = rte_pktmbuf_headroom(pkt);
+		tailroom = rte_pktmbuf_tailroom(pkt);
+		if (likely((headroom >= 24) &&
+		    (tailroom >= 8))) {
+			/* In 83XX this is prerequivisit for Direct mode */
+			*flags |= SINGLE_BUF_HEADTAILROOM;
+		}
+		param->bufs[0].vaddr = seg_data;
+		param->bufs[0].dma_addr = seg_phys;
+		param->bufs[0].size = seg_size;
+		return 0;
+	}
+	iovec = param->src_iov;
+	iovec->bufs[index].vaddr = seg_data;
+	iovec->bufs[index].dma_addr = seg_phys;
+	iovec->bufs[index].size = seg_size;
+	index++;
+	pkt = pkt->next;
+
+	while (unlikely(pkt != NULL)) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+
+		if (!seg_size)
+			break;
+
+		iovec->bufs[index].vaddr = seg_data;
+		iovec->bufs[index].dma_addr = seg_phys;
+		iovec->bufs[index].size = seg_size;
+
+		index++;
+
+		pkt = pkt->next;
+	}
+
+	iovec->buf_cnt = index;
+	return 0;
+}
+
+static __rte_always_inline void *
+fill_fc_params(struct rte_crypto_op *cop,
+	       struct cpt_sess_misc *sess_misc,
+	       void **mdata_ptr,
+	       int *op_ret)
+{
+	uint32_t space = 0;
+	struct rte_crypto_sym_op *sym_op = cop->sym;
+	void *mdata;
+	uintptr_t *op;
+	uint32_t mc_hash_off;
+	uint32_t flags = 0;
+	uint64_t d_offs, d_lens;
+	void *prep_req = NULL;
+	struct rte_mbuf *m_src, *m_dst;
+	uint8_t cpt_op = sess_misc->cpt_op;
+	uint8_t zsk_flag = sess_misc->zsk_flag;
+	uint8_t aes_gcm = sess_misc->aes_gcm;
+	uint16_t mac_len = sess_misc->mac_len;
+#ifdef CPT_ALWAYS_USE_SG_MODE
+	uint8_t inplace = 0;
+#else
+	uint8_t inplace = 1;
+#endif
+	fc_params_t fc_params;
+	char src[SRC_IOV_SIZE];
+	char dst[SRC_IOV_SIZE];
+	uint32_t iv_buf[4];
+	struct cptvf_meta_info *cpt_m_info =
+				(struct cptvf_meta_info *)(*mdata_ptr);
+
+	if (likely(sess_misc->iv_length)) {
+		flags |= VALID_IV_BUF;
+		fc_params.iv_buf = rte_crypto_op_ctod_offset(cop,
+				   uint8_t *, sess_misc->iv_offset);
+		if (sess_misc->aes_ctr &&
+		    unlikely(sess_misc->iv_length != 16)) {
+			memcpy((uint8_t *)iv_buf,
+				rte_crypto_op_ctod_offset(cop,
+				uint8_t *, sess_misc->iv_offset), 12);
+			iv_buf[3] = rte_cpu_to_be_32(0x1);
+			fc_params.iv_buf = iv_buf;
+		}
+	}
+
+	if (zsk_flag) {
+		fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
+					uint8_t *,
+					sess_misc->auth_iv_offset);
+		if (zsk_flag == K_F9) {
+			CPT_LOG_DP_ERR("Should not reach here for "
+			"kasumi F9\n");
+		}
+		if (zsk_flag != ZS_EA)
+			inplace = 0;
+	}
+	m_src = sym_op->m_src;
+	m_dst = sym_op->m_dst;
+
+	if (aes_gcm) {
+		uint8_t *salt;
+		uint8_t *aad_data;
+		uint16_t aad_len;
+
+		d_offs = sym_op->aead.data.offset;
+		d_lens = sym_op->aead.data.length;
+		mc_hash_off = sym_op->aead.data.offset +
+			      sym_op->aead.data.length;
+
+		aad_data = sym_op->aead.aad.data;
+		aad_len = sess_misc->aad_length;
+		if (likely((aad_data + aad_len) ==
+			   rte_pktmbuf_mtod_offset(m_src,
+				uint8_t *,
+				sym_op->aead.data.offset))) {
+			d_offs = (d_offs - aad_len) | (d_offs << 16);
+			d_lens = (d_lens + aad_len) | (d_lens << 32);
+		} else {
+			fc_params.aad_buf.vaddr = sym_op->aead.aad.data;
+			fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;
+			fc_params.aad_buf.size = aad_len;
+			flags |= VALID_AAD_BUF;
+			inplace = 0;
+			d_offs = d_offs << 16;
+			d_lens = d_lens << 32;
+		}
+
+		salt = fc_params.iv_buf;
+		if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
+			cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
+			sess_misc->salt = *(uint32_t *)salt;
+		}
+		fc_params.iv_buf = salt + 4;
+		if (likely(mac_len)) {
+			struct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst :
+					     m_src;
+
+			if (!m)
+				m = m_src;
+
+			/* hmac immediately following data is best case */
+			if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
+			    mc_hash_off !=
+			    (uint8_t *)sym_op->aead.digest.data)) {
+				flags |= VALID_MAC_BUF;
+				fc_params.mac_buf.size = sess_misc->mac_len;
+				fc_params.mac_buf.vaddr =
+				  sym_op->aead.digest.data;
+				fc_params.mac_buf.dma_addr =
+				 sym_op->aead.digest.phys_addr;
+				inplace = 0;
+			}
+		}
+	} else {
+		d_offs = sym_op->cipher.data.offset;
+		d_lens = sym_op->cipher.data.length;
+		mc_hash_off = sym_op->cipher.data.offset +
+			      sym_op->cipher.data.length;
+		d_offs = (d_offs << 16) | sym_op->auth.data.offset;
+		d_lens = (d_lens << 32) | sym_op->auth.data.length;
+
+		if (mc_hash_off < (sym_op->auth.data.offset +
+				   sym_op->auth.data.length)){
+			mc_hash_off = (sym_op->auth.data.offset +
+				       sym_op->auth.data.length);
+		}
+		/* for gmac, salt should be updated like in gcm */
+		if (unlikely(sess_misc->is_gmac)) {
+			uint8_t *salt;
+			salt = fc_params.iv_buf;
+			if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
+				cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
+				sess_misc->salt = *(uint32_t *)salt;
+			}
+			fc_params.iv_buf = salt + 4;
+		}
+			/* */
+		if (likely(mac_len)) {
+			struct rte_mbuf *m =
+			(cpt_op & CPT_OP_ENCODE) ? m_dst : m_src;
+
+			if (!m)
+				m = m_src;
+
+		/* hmac immediately following data is best case */
+			if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
+			    mc_hash_off !=
+			     (uint8_t *)sym_op->auth.digest.data)) {
+				flags |= VALID_MAC_BUF;
+				fc_params.mac_buf.size =
+					sess_misc->mac_len;
+				fc_params.mac_buf.vaddr =
+					sym_op->auth.digest.data;
+				fc_params.mac_buf.dma_addr =
+				sym_op->auth.digest.phys_addr;
+				inplace = 0;
+			}
+		}
+	}
+	fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);
+	fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;
+
+	if (unlikely(sess_misc->is_null || sess_misc->cpt_op == CPT_OP_DECODE))
+		inplace = 0;
+
+	if (likely(!m_dst && inplace)) {
+		/* Case of single buffer without AAD buf or
+		 * separate mac buf in place and
+		 * not air crypto
+		 */
+		fc_params.dst_iov = fc_params.src_iov = (void *)src;
+
+		if (unlikely(prepare_iov_from_pkt_inplace(m_src,
+							  &fc_params,
+							  &flags))) {
+			CPT_LOG_DP_ERR("Prepare inplace src iov failed\n");
+			*op_ret = -1;
+			return NULL;
+		}
+
+	} else {
+		/* Out of place processing */
+		fc_params.src_iov = (void *)src;
+		fc_params.dst_iov = (void *)dst;
+
+		/*Store SG I/O in the api for reuse */
+		if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {
+			CPT_LOG_DP_ERR("Prepare src iov failed\n");
+			*op_ret = -1;
+			return NULL;
+		}
+
+		if (unlikely(m_dst != NULL)) {
+			uint32_t pkt_len;
+
+			/* Try to make room as much as src has */
+			m_dst = sym_op->m_dst;
+			pkt_len = rte_pktmbuf_pkt_len(m_dst);
+
+			if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {
+				pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;
+				if (!rte_pktmbuf_append(m_dst, pkt_len)) {
+					CPT_LOG_DP_ERR("Not enough space in "
+					 "m_dst %p, need %u more\n",
+					 m_dst, pkt_len);
+					return NULL;
+				}
+			}
+
+			if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {
+				CPT_LOG_DP_ERR("Prepare dst iov failed for "
+				 "m_dst %p\n", m_dst);
+				return NULL;
+			}
+		} else {
+			fc_params.dst_iov = (void *)src;
+		}
+
+	}
+
+	if (likely(flags & SINGLE_BUF_HEADTAILROOM))
+		mdata = alloc_op_meta(m_src,
+				      &fc_params.meta_buf,
+				      cpt_m_info->cptvf_op_sb_mlen,
+				      cpt_m_info->cptvf_meta_pool);
+	else
+		mdata = alloc_op_meta(NULL,
+				      &fc_params.meta_buf,
+				      cpt_m_info->cptvf_op_mlen,
+				      cpt_m_info->cptvf_meta_pool);
+
+	if (unlikely(mdata == NULL)) {
+		CPT_LOG_DP_ERR("Error allocating meta buffer for request\n");
+		return NULL;
+	}
+
+	op = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull);
+	op[0] = (uintptr_t)mdata;
+	op[1] = (uintptr_t)cop;
+	op[2] = op[3] = 0; /* Used to indicate auth verify */
+	space += 4 * sizeof(uint64_t);
+
+	fc_params.meta_buf.vaddr = (uint8_t *)op + space;
+	fc_params.meta_buf.dma_addr += space;
+	fc_params.meta_buf.size -= space;
+
+	/* Finally prepare the instruction */
+	if (cpt_op & CPT_OP_ENCODE)
+		prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
+						&fc_params, op, op_ret);
+
+	if (unlikely(!prep_req))
+		free_op_meta(mdata, cpt_m_info->cptvf_meta_pool);
+	*mdata_ptr = mdata;
+	return prep_req;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v2 22/33] common/cpt: add microcode interface for decryption

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding microcode interface additions for supporting decryption.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 436 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 436 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index add5f95..e14d9c3 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -763,6 +763,439 @@ cpt_enc_hmac_prep(uint32_t flags,
 	return 0;
 }
 
+static __rte_always_inline int
+cpt_dec_hmac_prep(uint32_t flags,
+		  uint64_t d_offs,
+		  uint64_t d_lens,
+		  fc_params_t *fc_params,
+		  void *op,
+		  void **prep_req)
+{
+	uint32_t iv_offset = 0, size;
+	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+	struct cpt_ctx *cpt_ctx;
+	int32_t hash_type, mac_len, m_size;
+	uint8_t iv_len = 16;
+	struct cpt_request_info *req;
+	buf_ptr_t *meta_p, *aad_buf = NULL;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len, aad_len = 0;
+	uint32_t passthrough_len = 0;
+	void *m_vaddr, *offset_vaddr;
+	uint64_t m_dma, offset_dma, ctx_dma;
+	opcode_info_t opcode;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr;
+	uint64_t c_dma;
+
+	meta_p = &fc_params->meta_buf;
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs);
+	auth_offset = AUTH_OFFSET(d_offs);
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * We dont support both aad
+		 * and auth data separately
+		 */
+		auth_data_len = 0;
+		auth_offset = 0;
+		aad_len = fc_params->aad_buf.size;
+		aad_buf = &fc_params->aad_buf;
+	}
+
+	cpt_ctx = fc_params->ctx_buf.vaddr;
+	hash_type = cpt_ctx->hash_type;
+	mac_len = cpt_ctx->mac_len;
+
+	if (hash_type == GMAC_TYPE)
+		encr_data_len = 0;
+
+	if (unlikely(!(flags & VALID_IV_BUF))) {
+		iv_len = 0;
+		iv_offset = ENCR_IV_OFFSET(d_offs);
+	}
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * When AAD is given, data above encr_offset is pass through
+		 * Since AAD is given as separate pointer and not as offset,
+		 * this is a special case as we need to fragment input data
+		 * into passthrough + encr_data and then insert AAD in between.
+		 */
+		if (hash_type != GMAC_TYPE) {
+			passthrough_len = encr_offset;
+			auth_offset = passthrough_len + iv_len;
+			encr_offset = passthrough_len + aad_len + iv_len;
+			auth_data_len = aad_len + encr_data_len;
+		} else {
+			passthrough_len = 16 + aad_len;
+			auth_offset = passthrough_len + iv_len;
+			auth_data_len = aad_len;
+		}
+	} else {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+	       (uint8_t *)m_vaddr;
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* start cpt request info structure at 8 byte alignment */
+	size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+		(uint8_t *)m_vaddr;
+
+	req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
+
+	size += sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields in cpt request structure
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	/*
+	 * We are using DMA mode but indicate that
+	 * SGIO list is already populated.
+	 */
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	/* Decryption */
+	opcode.s.major = CPT_MAJOR_OP_FC;
+	opcode.s.minor = 1;
+
+	enc_dlen = encr_offset + encr_data_len;
+	auth_dlen = auth_offset + auth_data_len;
+
+	if (auth_dlen > enc_dlen) {
+		inputlen = auth_dlen + mac_len;
+		outputlen = auth_dlen;
+	} else {
+		inputlen = enc_dlen + mac_len;
+		outputlen = enc_dlen;
+	}
+
+	if (hash_type == GMAC_TYPE)
+		encr_offset = inputlen;
+
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((flags & SINGLE_BUF_INPLACE) &&
+		   (flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = fc_params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+		req->ist.ei1 = offset_dma;
+
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+
+		/* In direct mode,changing the alternate completion code address
+		 * to start of rptr,the assumption is that most auth iv failure
+		 * are reported at first byte only.This will not give the
+		 * correct alternate completion code the auth iv fail is
+		 * reported  after some bytes.
+		 * FIXME
+		 */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					iv_len);
+		/* since this is decryption,
+		 * don't touch the content of
+		 * alternate ccode space as it contains
+		 * hmac.
+		 */
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+						      OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+	} else {
+		uint64_t dptr_dma, rptr_dma;
+		uint32_t g_size_bytes, s_size_bytes;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint8_t i = 0;
+
+		/* This falls under strict SG mode */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+		size = OFF_CTRL_LEN + iv_len;
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+						      OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word that includes iv */
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+		/* Add input data */
+		if (flags & VALID_MAC_BUF) {
+			size = inputlen - iv_len - mac_len;
+			if (size) {
+				/* input data only */
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+								gather_comp, i,
+								fc_params->bufs,
+								&size);
+				} else {
+					uint32_t aad_offset = aad_len ?
+						passthrough_len : 0;
+
+					i = fill_sg_comp_from_iov(gather_comp,
+							   i,
+							   fc_params->src_iov,
+							   0, &size,
+							   aad_buf,
+							   aad_offset);
+				}
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+
+			/* mac data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(gather_comp, i,
+							  &fc_params->mac_buf);
+			}
+		} else {
+			/* input data + mac */
+			size = inputlen - iv_len;
+			if (size) {
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+								gather_comp, i,
+								fc_params->bufs,
+								&size);
+				} else {
+					uint32_t aad_offset = aad_len ?
+						passthrough_len : 0;
+
+					if (!fc_params->src_iov)
+						return ERR_BAD_INPUT_ARG;
+
+				       i = fill_sg_comp_from_iov(gather_comp, i,
+							     fc_params->src_iov,
+							     0, &size,
+							     aad_buf,
+							     aad_offset);
+				}
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* Add iv */
+		if (iv_len) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* Add output data */
+		size = outputlen - iv_len;
+		if (size) {
+			if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+				/* handle single buffer here */
+				i = fill_sg_comp_from_buf_min(scatter_comp, i,
+							      fc_params->bufs,
+							      &size);
+			} else {
+				uint32_t aad_offset = aad_len ?
+					passthrough_len : 0;
+
+				if (!fc_params->dst_iov)
+					return ERR_BAD_INPUT_ARG;
+
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  fc_params->dst_iov, 0,
+							  &size, aad_buf,
+							  aad_offset);
+			}
+
+			if (unlikely(size))
+				return ERR_BAD_INPUT_ARG;
+		}
+
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+		size += COMPLETION_CODE_SIZE;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	ctx_dma = fc_params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, fctx);
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = ctx_dma;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline void *
+cpt_fc_dec_hmac_prep(uint32_t flags,
+		     uint64_t d_offs,
+		     uint64_t d_lens,
+		     fc_params_t *fc_params,
+		     void *op, int *ret_val)
+{
+	struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+	uint8_t fc_type;
+	void *prep_req = NULL;
+	int ret;
+
+	fc_type = ctx->fc_type;
+
+	if (likely(fc_type == FC_GEN)) {
+		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
+					fc_params, op, &prep_req);
+	} else {
+		/*
+		 * For AUTH_ONLY case,
+		 * MC only supports digest generation and verification
+		 * should be done in software by memcmp()
+		 */
+
+		ret = ERR_EIO;
+	}
+
+	if (unlikely(!prep_req))
+		*ret_val = ret;
+	return prep_req;
+}
+
 static __rte_always_inline void *__hot
 cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 		     fc_params_t *fc_params, void *op, int *ret_val)
@@ -1614,6 +2047,9 @@ fill_fc_params(struct rte_crypto_op *cop,
 	if (cpt_op & CPT_OP_ENCODE)
 		prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
 						&fc_params, op, op_ret);
+	else
+		prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,
+						&fc_params, op, op_ret);
 
 	if (unlikely(!prep_req))
 		free_op_meta(mdata, cpt_m_info->cptvf_meta_pool);
-- 
2.7.4

[dpdk-dev] [PATCH v2 23/33] common/cpt: add crypo op enqueue request manager framework

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding crypto enqueue op request manager framework. This routine won't
submit to the hardware yet.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_request_mgr.h | 68 ++++++++++++++++++++++++++++++++++++
 drivers/common/cpt/cpt_ucode.h       | 43 +++++++++++++++++++++++
 2 files changed, 111 insertions(+)

diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index 733c402..c082e21 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -5,8 +5,13 @@
 #ifndef _CPT_REQUEST_MGR_H_
 #define _CPT_REQUEST_MGR_H_
 
+#include "cpt_common.h"
 #include "cpt_mcode_defines.h"
 
+#if CPT_MODEL == CRYPTO_OCTEONTX
+#include "../../crypto/octeontx/otx_cryptodev_hw_access.h"
+#endif
+
 /*
  * This file defines the agreement between the common layer and the individual
  * crypto drivers for OcteonTX series. Datapath in otx* directory include this
@@ -29,4 +34,67 @@ cpt_get_session_size(void)
 	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
 }
 
+static __rte_always_inline int __hot
+cpt_pmd_crypto_operation(struct cpt_instance *instance,
+		struct rte_crypto_op *op, struct pending_queue *pqueue,
+		uint8_t cpt_driver_id)
+{
+	struct cpt_sess_misc *sess = NULL;
+	struct rte_crypto_sym_op *sym_op = op->sym;
+	void *prep_req = NULL, *mdata = NULL;
+	int ret = 0;
+	uint64_t cpt_op;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	RTE_SET_USED(pqueue);
+
+	if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
+		int sess_len;
+
+		sess_len = cpt_get_session_size();
+
+		sess = rte_calloc(__func__, 1, sess_len, 8);
+		if (!sess)
+			return -ENOMEM;
+
+		sess->ctx_dma_addr =  rte_malloc_virt2iova(sess) +
+			sizeof(struct cpt_sess_misc);
+
+		ret = instance_session_cfg(sym_op->xform, (void *)sess);
+		if (unlikely(ret))
+			return -EINVAL;
+	} else {
+		sess = (struct cpt_sess_misc *)
+		get_sym_session_private_data(sym_op->session,
+		cpt_driver_id);
+	}
+
+	cpt_op = sess->cpt_op;
+
+	mdata = &(cptvf->meta_info);
+
+	if (likely(cpt_op & CPT_OP_CIPHER_MASK))
+		prep_req = fill_fc_params(op, sess, &mdata, &ret);
+
+	if (unlikely(!prep_req)) {
+		CPT_LOG_DP_ERR("prep cryto req : op %p, cpt_op 0x%x "
+		 "ret 0x%x\n", op, (unsigned int)cpt_op, ret);
+		goto req_fail;
+	}
+
+	if (unlikely(ret)) {
+		if (unlikely(ret == -EAGAIN))
+			goto req_fail;
+		CPT_LOG_DP_ERR("Error enqueing crypto request : error "
+		 "code %d\n", ret);
+		goto req_fail;
+	}
+
+	return 0;
+
+req_fail:
+	if (mdata)
+		free_op_meta(mdata, cptvf->meta_info.cptvf_meta_pool);
+	return ret;
+}
+
 #endif /* _CPT_REQUEST_MGR_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index e14d9c3..6949d35 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -2057,4 +2057,47 @@ fill_fc_params(struct rte_crypto_op *cop,
 	return prep_req;
 }
 
+static __rte_always_inline int
+instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
+{
+	struct rte_crypto_sym_xform *chain;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (cpt_is_algo_supported(xform))
+		goto err;
+
+	chain = xform;
+	while (chain) {
+		switch (chain->type) {
+		case RTE_CRYPTO_SYM_XFORM_AEAD:
+			if (fill_sess_aead(chain, sess))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_CIPHER:
+			if (fill_sess_cipher(chain, sess))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_AUTH:
+			if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
+				if (fill_sess_gmac(chain, sess))
+					goto err;
+			} else {
+				if (fill_sess_auth(chain, sess))
+					goto err;
+			}
+			break;
+		default:
+			CPT_LOG_DP_ERR("Invalid crypto xform type");
+			break;
+		}
+		chain = chain->next;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v2 24/33] common/cpt: add support for zuc and snow3g

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding microcode interface for supporting ZUC and SNOW3G.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 618 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 618 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 6949d35..383dff2 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -1164,6 +1164,618 @@ cpt_dec_hmac_prep(uint32_t flags,
 	return 0;
 }
 
+static __rte_always_inline int
+cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
+			uint64_t d_offs,
+			uint64_t d_lens,
+			fc_params_t *params,
+			void *op,
+			void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t mac_len = 0;
+	uint8_t snow3g, j;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset = 0, auth_offset = 0;
+	uint32_t encr_data_len = 0, auth_data_len = 0;
+	int flags, iv_len = 16, m_size;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma, offset_ctrl;
+	uint64_t *offset_vaddr, offset_dma;
+	uint32_t *iv_s, iv[4];
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	mac_len = cpt_ctx->mac_len;
+	snow3g = cpt_ctx->snow3g;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields for cpt request
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+	opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+			  (0 << 3) | (flags & 0x7));
+
+	if (flags == 0x1) {
+		/*
+		 * Microcode expects offsets in bytes
+		 * TODO: Rounding off
+		 */
+		auth_data_len = AUTH_DLEN(d_lens);
+
+		/* EIA3 or UIA2 */
+		auth_offset = AUTH_OFFSET(d_offs);
+		auth_offset = auth_offset / 8;
+
+		/* consider iv len */
+		auth_offset += iv_len;
+
+		inputlen = auth_offset +
+			(RTE_ALIGN(auth_data_len, 8) / 8);
+		outputlen = mac_len;
+
+		offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
+
+	} else {
+		/* EEA3 or UEA2 */
+		/*
+		 * Microcode expects offsets in bytes
+		 * TODO: Rounding off
+		 */
+		encr_data_len = ENCR_DLEN(d_lens);
+
+
+		encr_offset = ENCR_OFFSET(d_offs);
+		encr_offset = encr_offset / 8;
+		/* consider iv len */
+		encr_offset += iv_len;
+
+		inputlen = encr_offset +
+			(RTE_ALIGN(encr_data_len, 8) / 8);
+		outputlen = inputlen;
+
+		/* iv offset is 0 */
+		offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+	}
+
+	/* IV */
+	iv_s = (flags == 0x1) ? params->auth_iv_buf :
+		params->iv_buf;
+
+	if (snow3g) {
+		/*
+		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+		 */
+
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[3 - j];
+	} else {
+		/* ZUC doesn't need a swap */
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[j];
+	}
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+		   (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					    OFF_CTRL_LEN - iv_len);
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			memcpy(iv_d, iv, 16);
+		}
+
+		*offset_vaddr = offset_ctrl;
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint32_t *iv_d;
+
+		/*save space for iv */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+
+		m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+		m_dma += OFF_CTRL_LEN + iv_len;
+		m_size -= OFF_CTRL_LEN + iv_len;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word followed by iv */
+
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+		/* iv offset is 0 */
+		*offset_vaddr = offset_ctrl;
+
+		iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+		memcpy(iv_d, iv, 16);
+
+		/* input data */
+		size = inputlen - iv_len;
+		if (size) {
+
+			i = fill_sg_comp_from_iov(gather_comp, i,
+						  params->src_iov,
+						  0, &size, NULL, 0);
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		if (flags == 0x1) {
+			/* IV in SLIST only for EEA3 & UEA2 */
+			iv_len = 0;
+		}
+
+		if (iv_len) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* Add output data */
+		if (req_flags & VALID_MAC_BUF) {
+			size = outputlen - iv_len - mac_len;
+			if (size) {
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  params->dst_iov, 0,
+							  &size, NULL, 0);
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+
+			/* mac data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(scatter_comp, i,
+							  &params->mac_buf);
+			}
+		} else {
+			/* Output including mac */
+			size = outputlen - iv_len;
+			if (size) {
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  params->dst_iov, 0,
+							  &size, NULL, 0);
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, zs_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
+			uint64_t d_offs,
+			uint64_t d_lens,
+			fc_params_t *params,
+			void *op,
+			void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint8_t snow3g, iv_len = 16;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset;
+	uint32_t encr_data_len;
+	int flags, m_size;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	uint32_t *iv_s, iv[4], j;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+
+	(void)req_flags;
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	/*
+	 * Microcode expects offsets in bytes
+	 * TODO: Rounding off
+	 */
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	snow3g = cpt_ctx->snow3g;
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields for cpt request
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+	opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+			  (0 << 3) | (flags & 0x7));
+
+	/* consider iv len */
+	encr_offset += iv_len;
+
+	inputlen = encr_offset +
+		(RTE_ALIGN(encr_data_len, 8) / 8);
+	outputlen = inputlen;
+
+	/* IV */
+	iv_s = params->iv_buf;
+	if (snow3g) {
+		/*
+		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+		 */
+
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[3 - j];
+	} else {
+		/* ZUC doesn't need a swap */
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[j];
+	}
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+		   (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					    OFF_CTRL_LEN - iv_len);
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			memcpy(iv_d, iv, 16);
+		}
+
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint32_t *iv_d;
+
+		/* save space for offset and iv... */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+
+		m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+		m_dma += OFF_CTRL_LEN + iv_len;
+		m_size -= OFF_CTRL_LEN + iv_len;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word */
+
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+
+		i = fill_sg_comp(gather_comp, i, offset_dma, offset_vaddr,
+				 OFF_CTRL_LEN + iv_len);
+
+		iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+		memcpy(iv_d, iv, 16);
+
+		/* Add input data */
+		size = inputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(gather_comp, i,
+						  params->src_iov,
+						  0, &size, NULL, 0);
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* IV */
+		i = fill_sg_comp(scatter_comp, i,
+				 offset_dma + OFF_CTRL_LEN,
+				 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+				 iv_len);
+
+		/* Add output data */
+		size = outputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, zs_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
 static __rte_always_inline void *
 cpt_fc_dec_hmac_prep(uint32_t flags,
 		     uint64_t d_offs,
@@ -1181,6 +1793,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,
 	if (likely(fc_type == FC_GEN)) {
 		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
 					fc_params, op, &prep_req);
+	} else if (fc_type == ZUC_SNOW3G) {
+		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
+					      fc_params, op, &prep_req);
 	} else {
 		/*
 		 * For AUTH_ONLY case,
@@ -1211,6 +1826,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	if (likely(fc_type == FC_GEN)) {
 		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
 					fc_params, op, &prep_req);
+	} else if (fc_type == ZUC_SNOW3G) {
+		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
+					      fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
-- 
2.7.4

[dpdk-dev] [PATCH v2 25/33] common/cpt: add support for kasumi

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding microcode interface for supporting kasumi.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 477 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 477 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 383dff2..f618203 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -1776,6 +1776,477 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
 	return 0;
 }
 
+static __rte_always_inline int
+cpt_kasumi_enc_prep(uint32_t req_flags,
+		    uint64_t d_offs,
+		    uint64_t d_lens,
+		    fc_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen = 0;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t mac_len = 0;
+	uint8_t i = 0;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len;
+	int flags, m_size;
+	uint8_t *iv_s, *iv_d, iv_len = 8;
+	uint8_t dir = 0;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	auth_offset = AUTH_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	mac_len = cpt_ctx->mac_len;
+
+	if (flags == 0x0)
+		iv_s = params->iv_buf;
+	else
+		iv_s = params->auth_iv_buf;
+
+	dir = iv_s[8] & 0x1;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields for cpt request
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
+
+	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
+	opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
+			  (dir << 4) | (0 << 3) | (flags & 0x7));
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+	vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+	/* consider iv len */
+	if (flags == 0x0) {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/* save space for offset ctrl and iv */
+	offset_vaddr = m_vaddr;
+	offset_dma = m_dma;
+
+	m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+	m_dma += OFF_CTRL_LEN + iv_len;
+	m_size -= OFF_CTRL_LEN + iv_len;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input Gather List
+	 */
+	i = 0;
+
+	/* Offset control word followed by iv */
+
+	if (flags == 0x0) {
+		inputlen = encr_offset +
+			(RTE_ALIGN(encr_data_len, 8) / 8);
+		outputlen = inputlen;
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+	} else {
+		inputlen = auth_offset +
+			(RTE_ALIGN(auth_data_len, 8) / 8);
+		outputlen = mac_len;
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
+	}
+
+	i = fill_sg_comp(gather_comp, i, offset_dma,
+			 offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+	/* IV */
+	iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;
+	memcpy(iv_d, iv_s, iv_len);
+
+	/* input data */
+	size = inputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i,
+					  params->src_iov, 0,
+					  &size, NULL, 0);
+
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp =
+		(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	if (flags == 0x1) {
+		/* IV in SLIST only for F8 */
+		iv_len = 0;
+	}
+
+	/* IV */
+	if (iv_len) {
+
+		i = fill_sg_comp(scatter_comp, i,
+				 offset_dma + OFF_CTRL_LEN,
+				 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+				 iv_len);
+	}
+
+	/* Add output data */
+	if (req_flags & VALID_MAC_BUF) {
+		size = outputlen - iv_len - mac_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+
+		/* mac data */
+		if (mac_len) {
+			i = fill_sg_comp_from_buf(scatter_comp, i,
+						  &params->mac_buf);
+		}
+	} else {
+		/* Output including mac */
+		size = outputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+	}
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, k_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+
+static __rte_always_inline int
+cpt_kasumi_dec_prep(uint32_t req_flags,
+		    uint64_t d_offs,
+		    uint64_t d_lens,
+		    fc_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint8_t i = 0, iv_len = 8;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset;
+	uint32_t encr_data_len;
+	int flags, m_size;
+	uint8_t dir = 0;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+
+	(void)req_flags;
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode
+	 * fields for cpt req
+	 */
+
+	req->se_req = SE_CORE_REQ;
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+	opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
+
+	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
+	opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
+			  (dir << 4) | (0 << 3) | (flags & 0x7));
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+	/* consider iv len */
+	encr_offset += iv_len;
+
+	inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);
+	outputlen = inputlen;
+
+	/* save space for offset ctrl & iv */
+	offset_vaddr = m_vaddr;
+	offset_dma = m_dma;
+
+	m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+	m_dma += OFF_CTRL_LEN + iv_len;
+	m_size -= OFF_CTRL_LEN + iv_len;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input Gather List
+	 */
+	i = 0;
+
+	/* Offset control word followed by iv */
+	*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+
+	i = fill_sg_comp(gather_comp, i, offset_dma, offset_vaddr,
+			 OFF_CTRL_LEN + iv_len);
+
+
+	/* IV */
+	memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+	       params->iv_buf, iv_len);
+
+	/* Add input data */
+	size = inputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i,
+					  params->src_iov,
+					  0, &size, NULL, 0);
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp =
+		(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	/* IV */
+	i = fill_sg_comp(scatter_comp, i,
+			 offset_dma + OFF_CTRL_LEN,
+			 (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+			 iv_len);
+
+	/* Add output data */
+	size = outputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(scatter_comp, i,
+					  params->dst_iov, 0,
+					  &size, NULL, 0);
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, k_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
 static __rte_always_inline void *
 cpt_fc_dec_hmac_prep(uint32_t flags,
 		     uint64_t d_offs,
@@ -1796,6 +2267,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,
 	} else if (fc_type == ZUC_SNOW3G) {
 		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
 					      fc_params, op, &prep_req);
+	} else if (fc_type == KASUMI) {
+		ret = cpt_kasumi_dec_prep(flags, d_offs, d_lens,
+					  fc_params, op, &prep_req);
 	} else {
 		/*
 		 * For AUTH_ONLY case,
@@ -1829,6 +2303,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	} else if (fc_type == ZUC_SNOW3G) {
 		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
 					      fc_params, op, &prep_req);
+	} else if (fc_type == KASUMI) {
+		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,
+					  fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
-- 
2.7.4

[dpdk-dev] [PATCH v2 26/33] common/cpt: add support for hash

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding microcode interface for supporting verify and authentication

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h |   6 +
 drivers/common/cpt/cpt_request_mgr.h   |   2 +
 drivers/common/cpt/cpt_ucode.h         | 424 ++++++++++++++++++++++++++++++++-
 3 files changed, 431 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 17b0de3..b580289 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -334,6 +334,12 @@ typedef struct fc_params {
 
 } fc_params_t;
 
+/*
+ * Parameters for digest
+ * generate requests
+ * Only src_iov, op, ctx_buf, mac_buf, prep_req
+ * meta_buf, auth_data_len are used for digest gen.
+ */
 typedef struct fc_params digest_params_t;
 
 /* Cipher Algorithms */
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index c082e21..d843ee7 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -74,6 +74,8 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 
 	if (likely(cpt_op & CPT_OP_CIPHER_MASK))
 		prep_req = fill_fc_params(op, sess, &mdata, &ret);
+	else
+		prep_req = fill_digest_params(op, sess, &mdata, &ret);
 
 	if (unlikely(!prep_req)) {
 		CPT_LOG_DP_ERR("prep cryto req : op %p, cpt_op 0x%x "
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index f618203..7d2b3ef 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -4,7 +4,6 @@
 
 #ifndef _CPT_UCODE_H_
 #define _CPT_UCODE_H_
-
 #include <stdbool.h>
 
 #include "cpt_common.h"
@@ -367,6 +366,218 @@ fill_sg_comp_from_iov(sg_comp_t *list,
 }
 
 static __rte_always_inline int
+cpt_digest_gen_prep(uint32_t flags,
+		    uint64_t d_offs,
+		    uint64_t d_lens,
+		    digest_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	struct cpt_request_info *req;
+	uint32_t size, i;
+	int32_t m_size;
+	uint16_t data_len, mac_len, key_len;
+	auth_type_t hash_type;
+	buf_ptr_t *meta_p;
+	struct cpt_ctx *ctx;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr, *m_vaddr;
+	uint64_t c_dma, m_dma;
+	opcode_info_t opcode;
+
+	if (!params || !params->ctx_buf.vaddr)
+		return ERR_BAD_INPUT_ARG;
+
+	(void)d_offs;
+	ctx = params->ctx_buf.vaddr;
+	meta_p = &params->meta_buf;
+
+	if (!meta_p->vaddr || !meta_p->dma_addr)
+		return ERR_BAD_INPUT_ARG;
+
+	if (meta_p->size < sizeof(struct cpt_request_info))
+		return ERR_BAD_INPUT_ARG;
+
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Initialising ctrl and opcode fields */
+
+	req->dma_mode = CTRL_DMA_MODE_SGIO;
+	req->se_req = SE_CORE_REQ;
+
+	hash_type = ctx->hash_type;
+	mac_len = ctx->mac_len;
+	key_len = ctx->auth_key_len;
+	data_len = AUTH_DLEN(d_lens);
+
+	/*GP op header */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(((uint16_t)hash_type << 8));
+	if (ctx->hmac) {
+		opcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;
+		vq_cmd_w0.s.param1 = rte_cpu_to_be_16(key_len);
+		vq_cmd_w0.s.dlen =
+			rte_cpu_to_be_16((data_len + ROUNDUP8(key_len)));
+	} else {
+		opcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;
+		vq_cmd_w0.s.param1 = 0;
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(data_len);
+		/* This is required for null auth only case */
+		if (!hash_type && !ctx->enc_cipher)
+			vq_cmd_w0.s.param2 = rte_cpu_to_be_16(data_len);
+	}
+
+	opcode.s.minor = 0;
+
+	vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input gather list
+	 */
+
+	i = 0;
+
+	if (ctx->hmac) {
+		uint64_t k_dma = params->ctx_buf.dma_addr +
+			offsetof(struct cpt_ctx, auth_key);
+		/* Key */
+		i = fill_sg_comp(gather_comp, i, k_dma,
+				 ctx->auth_key, ROUNDUP8(key_len));
+	}
+
+	/* input data */
+	size = data_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,
+					  0, &size, NULL, 0);
+		if (size) {
+			CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short"
+			" by %dB\n", size);
+			return ERR_BAD_INPUT_ARG;
+		}
+	} else {
+		/*
+		 * Looks like we need to support zero data
+		 * gather ptr in case of hash & hmac
+		 */
+		i++;
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+
+	/*
+	 * Output Gather list
+	 */
+
+	i = 0;
+	scatter_comp =
+		(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	if (flags & VALID_MAC_BUF) {
+		if (params->mac_buf.size < mac_len)
+			return ERR_BAD_INPUT_ARG;
+
+		size = mac_len;
+		i = fill_sg_comp_from_buf_min(scatter_comp, i,
+					      &params->mac_buf, &size);
+	} else {
+		size = mac_len;
+		i = fill_sg_comp_from_iov(scatter_comp, i,
+					  params->src_iov, data_len,
+					  &size, NULL, 0);
+		if (size) {
+			CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short by"
+				   " %dB\n", size);
+			return ERR_BAD_INPUT_ARG;
+		}
+	}
+
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline int
 cpt_enc_hmac_prep(uint32_t flags,
 		  uint64_t d_offs,
 		  uint64_t d_lens,
@@ -2306,6 +2517,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	} else if (fc_type == KASUMI) {
 		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,
 					  fc_params, op, &prep_req);
+	} else if (fc_type == HASH_HMAC) {
+		ret = cpt_digest_gen_prep(flags, d_offs, d_lens,
+					  fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
@@ -3195,4 +3409,212 @@ instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
 	return -1;
 }
 
+static __rte_always_inline void
+find_kasumif9_direction_and_length(uint8_t *src,
+				   uint32_t counter_num_bytes,
+				   uint32_t *addr_length_in_bits,
+				   uint8_t *addr_direction)
+{
+	uint8_t found = 0;
+	while (!found && counter_num_bytes > 0) {
+		counter_num_bytes--;
+		if (src[counter_num_bytes] == 0x00)
+			continue;
+		if (src[counter_num_bytes] == 0x80) {
+			*addr_direction  =  src[counter_num_bytes - 1] & 0x1;
+			*addr_length_in_bits = counter_num_bytes * 8  - 1;
+			found = 1;
+		} else {
+			int i = 0;
+			uint8_t last_byte = src[counter_num_bytes];
+			for (i = 0; i < 8 && found == 0; i++) {
+				if (last_byte & (1 << i)) {
+					*addr_direction = (last_byte >> (i+1))
+							  & 0x1;
+					if (i != 6)
+						*addr_length_in_bits =
+							counter_num_bytes * 8
+							+ (8 - (i + 2));
+					else
+						*addr_length_in_bits =
+							counter_num_bytes * 8;
+
+					found = 1;
+					}
+				}
+			}
+	}
+}
+/*
+ * This handles all auth only except AES_GMAC
+ */
+static __rte_always_inline void *
+fill_digest_params(struct rte_crypto_op *cop,
+		   struct cpt_sess_misc *sess,
+		   void **mdata_ptr,
+		   int *op_ret)
+{
+	uint32_t space = 0;
+	struct rte_crypto_sym_op *sym_op = cop->sym;
+	void *mdata;
+	phys_addr_t mphys;
+	uint64_t *op;
+	uint32_t auth_range_off;
+	uint32_t flags = 0;
+	uint64_t d_offs = 0, d_lens;
+	void *prep_req = NULL;
+	struct rte_mbuf *m_src, *m_dst;
+	uint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK;
+	uint8_t zsk_flag = sess->zsk_flag;
+	uint16_t mac_len = sess->mac_len;
+	fc_params_t params;
+	char src[SRC_IOV_SIZE];
+	uint8_t iv_buf[16];
+	memset(&params, 0, sizeof(fc_params_t));
+	struct cptvf_meta_info *cpt_m_info =
+				(struct cptvf_meta_info *)(*mdata_ptr);
+
+	m_src = sym_op->m_src;
+
+	/* For just digest lets force mempool alloc */
+	mdata = alloc_op_meta(NULL, &params.meta_buf, cpt_m_info->cptvf_op_mlen,
+			      cpt_m_info->cptvf_meta_pool);
+	if (mdata == NULL) {
+		CPT_LOG_DP_ERR("Error allocating meta buffer for"
+		" request\n");
+		*op_ret = -ENOMEM;
+		return NULL;
+	}
+
+	mphys = params.meta_buf.dma_addr;
+
+	op = mdata;
+	op[0] = (uintptr_t)mdata;
+	op[1] = (uintptr_t)cop;
+	op[2] = op[3] = 0; /* Used to indicate auth verify */
+	space += 4 * sizeof(uint64_t);
+
+	auth_range_off = sym_op->auth.data.offset;
+
+	flags = VALID_MAC_BUF;
+	params.src_iov = (void *)src;
+	if (unlikely(zsk_flag)) {
+		/*
+		 * Since for Zuc, Kasumi, Snow3g offsets are in bits
+		 * we will send pass through even for auth only case,
+		 * let MC handle it
+		 */
+		d_offs = auth_range_off;
+		auth_range_off = 0;
+		params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
+					uint8_t *, sess->auth_iv_offset);
+		if (zsk_flag == K_F9) {
+			uint32_t length_in_bits, num_bytes;
+			uint8_t *src, direction = 0;
+			uint32_t counter_num_bytes;
+
+			memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,
+							uint8_t *), 8);
+			/*
+			 * This is kasumi f9, take direction from
+			 * source buffer
+			 */
+			length_in_bits = cop->sym->auth.data.length;
+			num_bytes = (length_in_bits >> 3);
+			counter_num_bytes = num_bytes;
+			src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);
+			find_kasumif9_direction_and_length(src,
+						counter_num_bytes,
+						&length_in_bits,
+						&direction);
+			length_in_bits -= 64;
+			cop->sym->auth.data.offset += 64;
+			d_offs = cop->sym->auth.data.offset;
+			auth_range_off = d_offs / 8;
+			cop->sym->auth.data.length = length_in_bits;
+
+			/* Store it at end of auth iv */
+			iv_buf[8] = direction;
+			params.auth_iv_buf = iv_buf;
+		}
+	}
+
+	d_lens = sym_op->auth.data.length;
+
+	params.ctx_buf.vaddr = SESS_PRIV(sess);
+	params.ctx_buf.dma_addr = sess->ctx_dma_addr;
+
+	if (auth_op == CPT_OP_AUTH_GENERATE) {
+		if (sym_op->auth.digest.data) {
+			/*
+			 * Digest to be generated
+			 * in separate buffer
+			 */
+			params.mac_buf.size =
+				sess->mac_len;
+			params.mac_buf.vaddr =
+				sym_op->auth.digest.data;
+			params.mac_buf.dma_addr =
+				sym_op->auth.digest.phys_addr;
+		} else {
+			uint32_t off = sym_op->auth.data.offset +
+				sym_op->auth.data.length;
+			int32_t dlen, space;
+
+			m_dst = sym_op->m_dst ?
+				sym_op->m_dst : sym_op->m_src;
+			dlen = rte_pktmbuf_pkt_len(m_dst);
+
+			space = off + mac_len - dlen;
+			if (space > 0)
+				if (!rte_pktmbuf_append(m_dst, space)) {
+					CPT_LOG_DP_ERR("Failed to extend "
+					 "mbuf by %uB\n", space);
+					goto err;
+				}
+
+			params.mac_buf.vaddr =
+				rte_pktmbuf_mtod_offset(m_dst,
+							void *, off);
+			params.mac_buf.dma_addr =
+				rte_pktmbuf_mtophys_offset(m_dst, off);
+			params.mac_buf.size = mac_len;
+		}
+	} else {
+		/* Need space for storing generated mac */
+		params.mac_buf.vaddr =
+			(uint8_t *)mdata + space;
+		params.mac_buf.dma_addr = mphys + space;
+		params.mac_buf.size = mac_len;
+		space += RTE_ALIGN_CEIL(mac_len, 8);
+		op[2] = (uintptr_t)params.mac_buf.vaddr;
+		op[3] = mac_len;
+
+	}
+
+	params.meta_buf.vaddr = (uint8_t *)mdata + space;
+	params.meta_buf.dma_addr = mphys + space;
+	params.meta_buf.size -= space;
+
+	/* Out of place processing */
+	params.src_iov = (void *)src;
+
+	/*Store SG I/O in the api for reuse */
+	if (prepare_iov_from_pkt(m_src, params.src_iov,
+				 auth_range_off)) {
+		CPT_LOG_DP_ERR("Prepare src iov failed\n");
+		*op_ret = -1;
+		goto err;
+	}
+
+	prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
+					&params, op, op_ret);
+	*mdata_ptr = mdata;
+	return prep_req;
+err:
+	if (unlikely(!prep_req))
+		free_op_meta(mdata, cpt_m_info->cptvf_meta_pool);
+	return NULL;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v2 27/33] crypto/octeontx: add routines to prepare instructions

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding hardware specific routines which prepare cpt instructions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 56 +++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index b9a634b..cff09b2 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -7,11 +7,14 @@
 
 #include <stdbool.h>
 
+#include <rte_branch_prediction.h>
 #include <rte_io.h>
 #include <rte_memory.h>
+#include <rte_prefetch.h>
 
 #include "cpt_common.h"
 #include "cpt_hw_types.h"
+#include "cpt_pmd_logs.h"
 
 /* Flags to indicate the features supported */
 #define CPT_FLAG_VF_DRIVER		(uint16_t)(1 << 3)
@@ -188,4 +191,57 @@ otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
 	return vqx_dbell.s.dbell_cnt;
 }
 
+static __rte_always_inline void *
+get_cpt_inst(struct command_queue *cqueue)
+{
+	CPT_LOG_DP_DEBUG("CPT queue idx %u\n", cqueue->idx);
+	return &cqueue->qhead[cqueue->idx * CPT_INST_SIZE];
+}
+
+static __rte_always_inline void
+fill_cpt_inst(struct cpt_instance *instance, void *req)
+{
+	struct command_queue *cqueue;
+	cpt_inst_s_t *cpt_ist_p;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct cpt_request_info *user_req = (struct cpt_request_info *)req;
+	cqueue = &cptvf->cqueue;
+	cpt_ist_p = get_cpt_inst(cqueue);
+	rte_prefetch_non_temporal(cpt_ist_p);
+
+	/* EI0, EI1, EI2, EI3 are already prepared */
+	/* HW W0 */
+	cpt_ist_p->u[0] = 0;
+	/* HW W1 */
+	cpt_ist_p->s8x.res_addr = user_req->comp_baddr;
+	/* HW W2 */
+	cpt_ist_p->u[2] = 0;
+	/* HW W3 */
+	cpt_ist_p->s8x.wq_ptr = 0;
+
+	/* MC EI0 */
+	cpt_ist_p->s8x.ei0 = user_req->ist.ei0;
+	/* MC EI1 */
+	cpt_ist_p->s8x.ei1 = user_req->ist.ei1;
+	/* MC EI2 */
+	cpt_ist_p->s8x.ei2 = user_req->ist.ei2;
+	/* MC EI3 */
+	cpt_ist_p->s8x.ei3 = user_req->ist.ei3;
+}
+
+static __rte_always_inline void
+mark_cpt_inst(struct cpt_instance *instance)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct command_queue *queue = &cptvf->cqueue;
+	if (unlikely(++queue->idx >= DEFAULT_CMD_QCHUNK_SIZE)) {
+		uint32_t cchunk = queue->cchunk;
+		MOD_INC(cchunk, DEFAULT_CMD_QCHUNKS);
+		queue->qhead = queue->chead[cchunk].head;
+		queue->idx = 0;
+		queue->cchunk = cchunk;
+	}
+
+}
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v2 28/33] common/cpt: add common code for enqueuing cpt instruction

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h      |  4 +++
 drivers/common/cpt/cpt_request_mgr.h | 50 +++++++++++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 61621dc..6debf42 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -15,6 +15,10 @@
  */
 #define CRYPTO_OCTEONTX		0x1
 
+
+/* Default command timeout in seconds */
+#define DEFAULT_COMMAND_TIMEOUT	4
+
 #define CPT_COUNT_THOLD		32
 #define CPT_TIMER_THOLD		0x3F
 
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index d843ee7..4bf8de3 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -5,6 +5,9 @@
 #ifndef _CPT_REQUEST_MGR_H_
 #define _CPT_REQUEST_MGR_H_
 
+#include <rte_branch_prediction.h>
+#include <rte_cycles.h>
+
 #include "cpt_common.h"
 #include "cpt_mcode_defines.h"
 
@@ -34,6 +37,49 @@ cpt_get_session_size(void)
 	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
 }
 
+static __rte_always_inline int32_t __hot
+cpt_enqueue_req(struct cpt_instance *instance, struct pending_queue *pqueue,
+		void *req)
+{
+	struct cpt_request_info *user_req = (struct cpt_request_info *)req;
+	int32_t ret = 0;
+
+	if (unlikely(!req))
+		return 0;
+
+	if (unlikely(pqueue->pending_count >= DEFAULT_CMD_QLEN))
+		return -EAGAIN;
+
+	fill_cpt_inst(instance, req);
+
+	CPT_LOG_DP_DEBUG("req: %p op: %p dma_mode 0x%x se_req %u\n",
+		   req,
+		   user_req->op,
+		   user_req->dma_mode,
+		   user_req->se_req);
+
+	/* Fill time_out cycles */
+	user_req->time_out = rte_get_timer_cycles() +
+			DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
+	user_req->extra_time = 0;
+
+	/* Default mode of software queue */
+	mark_cpt_inst(instance);
+
+	pqueue->rid_queue[pqueue->enq_tail].rid =
+		(uintptr_t)user_req;
+	/* We will use soft queue length here to limit
+	 * requests
+	 */
+	MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);
+	pqueue->pending_count += 1;
+
+	CPT_LOG_DP_DEBUG("Submitted NB cmd with request: %p "
+			 "op: %p\n", user_req, user_req->op);
+
+	return ret;
+}
+
 static __rte_always_inline int __hot
 cpt_pmd_crypto_operation(struct cpt_instance *instance,
 		struct rte_crypto_op *op, struct pending_queue *pqueue,
@@ -45,7 +91,6 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 	int ret = 0;
 	uint64_t cpt_op;
 	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
-	RTE_SET_USED(pqueue);
 
 	if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 		int sess_len;
@@ -83,6 +128,9 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 		goto req_fail;
 	}
 
+	/* Enqueue prepared instruction to HW */
+	ret = cpt_enqueue_req(instance, pqueue, prep_req);
+
 	if (unlikely(ret)) {
 		if (unlikely(ret == -EAGAIN))
 			goto req_fail;
-- 
2.7.4

[dpdk-dev] [PATCH v2 29/33] crypto/octeontx: add enqueue burst op

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 18 +++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 27 ++++++++++++++++++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index cff09b2..f2d7ee7 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -191,6 +191,15 @@ otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
 	return vqx_dbell.s.dbell_cnt;
 }
 
+static __rte_always_inline void
+otx_cpt_ring_dbell(struct cpt_instance *instance, uint16_t count)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	/* Memory barrier to flush pending writes */
+	rte_smp_wmb();
+	otx_cpt_write_vq_doorbell(cptvf, count);
+}
+
 static __rte_always_inline void *
 get_cpt_inst(struct command_queue *cqueue)
 {
@@ -241,7 +250,16 @@ mark_cpt_inst(struct cpt_instance *instance)
 		queue->idx = 0;
 		queue->cchunk = cchunk;
 	}
+}
 
+static __rte_always_inline uint8_t
+check_nb_command_id(struct cpt_request_info *user_req,
+		struct cpt_instance *instance)
+{
+	/* Required for dequeue operation. Adding a dummy routine for now */
+	RTE_SET_USED(user_req);
+	RTE_SET_USED(instance);
+	return 0;
 }
 
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 438208c..b20cbe0 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -345,6 +345,31 @@ otx_cpt_session_clear(struct rte_cryptodev *dev,
 	}
 }
 
+static uint16_t
+otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	struct cpt_instance *instance = (struct cpt_instance *)qptr;
+	uint16_t count = 0;
+	int ret;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct pending_queue *pqueue = &cptvf->pqueue;
+
+	count = DEFAULT_CMD_QLEN - pqueue->pending_count;
+	if (nb_ops > count)
+		nb_ops = count;
+
+	count = 0;
+	while (likely(count < nb_ops)) {
+		ret = cpt_pmd_crypto_operation(instance, ops[count], pqueue,
+						otx_cryptodev_driver_id);
+		if (unlikely(ret))
+			break;
+		count++;
+	}
+	otx_cpt_ring_dbell(instance, count);
+	return count;
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -436,7 +461,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 
 	c_dev->dev_ops = &cptvf_ops;
 
-	c_dev->enqueue_burst = NULL;
+	c_dev->enqueue_burst = otx_cpt_pkt_enqueue;
 	c_dev->dequeue_burst = NULL;
 
 	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
-- 
2.7.4

[dpdk-dev] [PATCH v2 30/33] common/cpt: add common code for cpt dequeue

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h        |  1 +
 drivers/common/cpt/cpt_mcode_defines.h | 15 +++++++++++++
 drivers/common/cpt/cpt_request_mgr.h   | 39 ++++++++++++++++++++++++++++++++++
 drivers/common/cpt/cpt_ucode.h         | 26 +++++++++++++++++++++++
 4 files changed, 81 insertions(+)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 6debf42..a9e179a 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -15,6 +15,7 @@
  */
 #define CRYPTO_OCTEONTX		0x1
 
+#define TIME_IN_RESET_COUNT	5
 
 /* Default command timeout in seconds */
 #define DEFAULT_COMMAND_TIMEOUT	4
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index b580289..3b64698 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -176,6 +176,21 @@ typedef enum {
 	ERR_ENODEV,
 } mc_error_code_t;
 
+/**
+ * Enumeration cpt_comp_e
+ *
+ * CPT Completion Enumeration
+ * Enumerates the values of CPT_RES_S[COMPCODE].
+ */
+typedef enum {
+	CPT_8X_COMP_E_NOTDONE    = (0x00),
+	CPT_8X_COMP_E_GOOD       = (0x01),
+	CPT_8X_COMP_E_FAULT      = (0x02),
+	CPT_8X_COMP_E_SWERR      = (0x03),
+	CPT_8X_COMP_E_HWERR      = (0x04),
+	CPT_8X_COMP_E_LAST_ENTRY = (0xFF)
+} cpt_comp_e_t;
+
 typedef struct sglist_comp {
 	union {
 		uint64_t len;
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index 4bf8de3..fb11c4f 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -147,4 +147,43 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 	return ret;
 }
 
+static __rte_always_inline int32_t __hot
+cpt_dequeue_burst(struct cpt_instance *instance, uint16_t cnt,
+		  void *resp[], uint8_t cc[], struct pending_queue *pqueue)
+{
+	struct cpt_request_info *user_req;
+	struct rid *rid_e;
+	int i, count, pcount;
+	uint8_t ret;
+
+	pcount = pqueue->pending_count;
+	count = (cnt > pcount) ? pcount : cnt;
+
+	for (i = 0; i < count; i++) {
+		rid_e = &pqueue->rid_queue[pqueue->deq_head];
+		user_req = (struct cpt_request_info *)(rid_e->rid);
+
+		if (likely((i+1) < count))
+			rte_prefetch_non_temporal((void *)rid_e[1].rid);
+
+		ret = check_nb_command_id(user_req, instance);
+
+		if (unlikely(ret == ERR_REQ_PENDING)) {
+			/* Stop checking for completions */
+			break;
+		}
+
+		/* Return completion code and op handle */
+		cc[i] = (uint8_t)ret;
+		resp[i] = user_req->op;
+		CPT_LOG_DP_DEBUG("Request %p Op %p completed with code %d",
+			   user_req, user_req->op, ret);
+
+		MOD_INC(pqueue->deq_head, DEFAULT_CMD_QLEN);
+		pqueue->pending_count -= 1;
+	}
+
+	return i;
+}
+
 #endif /* _CPT_REQUEST_MGR_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 7d2b3ef..eff71c9 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -3366,6 +3366,32 @@ fill_fc_params(struct rte_crypto_op *cop,
 	return prep_req;
 }
 
+static __rte_always_inline void
+compl_auth_verify(struct rte_crypto_op *op,
+		      uint8_t *gen_mac,
+		      uint64_t mac_len)
+{
+	uint8_t *mac;
+	struct rte_crypto_sym_op *sym_op = op->sym;
+
+	if (sym_op->auth.digest.data)
+		mac = sym_op->auth.digest.data;
+	else
+		mac = rte_pktmbuf_mtod_offset(sym_op->m_src,
+					      uint8_t *,
+					      sym_op->auth.data.length +
+					      sym_op->auth.data.offset);
+	if (!mac) {
+		op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		return;
+	}
+
+	if (memcmp(mac, gen_mac, mac_len))
+		op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+	else
+		op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+}
+
 static __rte_always_inline int
 instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
 {
-- 
2.7.4

[dpdk-dev] [PATCH v2 31/33] crypto/octeontx: add dequeue burst op

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 63 +++++++++++++++++++++--
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 47 ++++++++++++++++-
 2 files changed, 105 insertions(+), 5 deletions(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index f2d7ee7..6278cf9 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -8,12 +8,14 @@
 #include <stdbool.h>
 
 #include <rte_branch_prediction.h>
+#include <rte_cycles.h>
 #include <rte_io.h>
 #include <rte_memory.h>
 #include <rte_prefetch.h>
 
 #include "cpt_common.h"
 #include "cpt_hw_types.h"
+#include "cpt_mcode_defines.h"
 #include "cpt_pmd_logs.h"
 
 /* Flags to indicate the features supported */
@@ -256,10 +258,63 @@ static __rte_always_inline uint8_t
 check_nb_command_id(struct cpt_request_info *user_req,
 		struct cpt_instance *instance)
 {
-	/* Required for dequeue operation. Adding a dummy routine for now */
-	RTE_SET_USED(user_req);
-	RTE_SET_USED(instance);
-	return 0;
+	uint8_t ret = ERR_REQ_PENDING;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	volatile cpt_res_s_t *cptres;
+
+	cptres = (volatile cpt_res_s_t *)user_req->completion_addr;
+
+	if (unlikely(cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE)) {
+		/*
+		 * Wait for some time for this command to get completed
+		 * before timing out
+		 */
+		if (rte_get_timer_cycles() < user_req->time_out)
+			return ret;
+		/*
+		 * TODO: See if alternate caddr can be used to not loop
+		 * longer than needed.
+		 */
+		if ((cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE) &&
+		    (user_req->extra_time < TIME_IN_RESET_COUNT)) {
+			user_req->extra_time++;
+			return ret;
+		}
+
+		if (cptres->s8x.compcode != CPT_8X_COMP_E_NOTDONE)
+			goto complete;
+
+		ret = ERR_REQ_TIMEOUT;
+		CPT_LOG_DP_ERR("Request %p timedout\n", user_req);
+		otx_cpt_poll_misc(cptvf);
+		goto exit;
+	}
+
+complete:
+	if (likely(cptres->s8x.compcode == CPT_8X_COMP_E_GOOD)) {
+		ret = 0; /* success */
+		CPT_LOG_DP_DEBUG("MC status %.8x\n",
+			   *((volatile uint32_t *)user_req->alternate_caddr));
+		CPT_LOG_DP_DEBUG("HW status %.8x\n",
+			   *((volatile uint32_t *)user_req->completion_addr));
+	} else if ((cptres->s8x.compcode == CPT_8X_COMP_E_SWERR) ||
+		   (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT)) {
+		ret = (uint8_t)*user_req->alternate_caddr;
+		if (!ret)
+			ret = ERR_BAD_ALT_CCODE;
+		CPT_LOG_DP_DEBUG("Request %p : failed with %s : err code :"
+			   "%x\n", user_req,
+			   (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT) ?
+			   "DMA Fault" : "Software error", ret);
+	} else {
+		CPT_LOG_DP_ERR("Request %p : unexpected completion "
+			   "code %d\n",
+			   user_req, cptres->s8x.compcode);
+		ret = (uint8_t)*user_req->alternate_caddr;
+	}
+
+exit:
+	return ret;
 }
 
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index b20cbe0..d5d1285 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -370,6 +370,51 @@ otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 	return count;
 }
 
+static uint16_t
+otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	struct cpt_instance *instance = (struct cpt_instance *)qptr;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct pending_queue *pqueue = &cptvf->pqueue;
+	uint16_t nb_completed, i = 0;
+	uint8_t compcode[nb_ops];
+
+	nb_completed = cpt_dequeue_burst(instance, nb_ops,
+					 (void **)ops, compcode, pqueue);
+	while (likely(i < nb_completed)) {
+		struct rte_crypto_op *cop;
+		void *metabuf;
+		uintptr_t *rsp;
+		uint8_t status;
+
+		rsp = (void *)ops[i];
+		status = compcode[i];
+		if (likely((i + 1) < nb_completed))
+			rte_prefetch0(ops[i+1]);
+		metabuf = (void *)rsp[0];
+		cop = (void *)rsp[1];
+
+		ops[i] = cop;
+
+		if (likely(status == 0)) {
+			if (likely(!rsp[2]))
+				cop->status =
+					RTE_CRYPTO_OP_STATUS_SUCCESS;
+			else
+				compl_auth_verify(cop, (uint8_t *)rsp[2],
+						  rsp[3]);
+		} else if (status == ERR_GC_ICV_MISCOMPARE) {
+			/*auth data mismatch */
+			cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+		} else {
+			cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		}
+		free_op_meta(metabuf, cptvf->meta_info.cptvf_meta_pool);
+		i++;
+	}
+	return nb_completed;
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -462,7 +507,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	c_dev->dev_ops = &cptvf_ops;
 
 	c_dev->enqueue_burst = otx_cpt_pkt_enqueue;
-	c_dev->dequeue_burst = NULL;
+	c_dev->dequeue_burst = otx_cpt_pkt_dequeue;
 
 	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
 			RTE_CRYPTODEV_FF_HW_ACCELERATED |
-- 
2.7.4

[dpdk-dev] [PATCH v2 32/33] test: adds validation test

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

This patch adds validation tests for octeontx crypto device.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 test/test/meson.build                        |   1 +
 test/test/test_cryptodev.c                   | 308 +++++++++++++++++++++++++++
 test/test/test_cryptodev.h                   |   1 +
 test/test/test_cryptodev_aes_test_vectors.h  |  96 ++++++---
 test/test/test_cryptodev_blockcipher.c       |   9 +-
 test/test/test_cryptodev_blockcipher.h       |   1 +
 test/test/test_cryptodev_des_test_vectors.h  |  12 +-
 test/test/test_cryptodev_hash_test_vectors.h |  72 ++++---
 8 files changed, 439 insertions(+), 61 deletions(-)

diff --git a/test/test/meson.build b/test/test/meson.build
index b1dd6ec..2d59041 100644
--- a/test/test/meson.build
+++ b/test/test/meson.build
@@ -141,6 +141,7 @@ test_names = [
 	'cryptodev_sw_mvsam_autotest',
 	'cryptodev_dpaa2_sec_autotest',
 	'cryptodev_dpaa_sec_autotest',
+	'cryptodev_octeontx_autotest',
 	'cycles_autotest',
 	'debug_autotest',
 	'devargs_autotest',
diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
index a6044b2..1f7ea8f 100644
--- a/test/test/test_cryptodev.c
+++ b/test/test/test_cryptodev.c
@@ -2142,6 +2142,96 @@ test_3DES_cipheronly_mrvl_all(void)
 	return TEST_SUCCESS;
 }
 
+static int
+test_AES_chain_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_AES_CHAIN_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_AES_cipheronly_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_AES_CIPHERONLY_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_3DES_chain_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_3DES_CHAIN_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_3DES_cipheronly_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_3DES_CIPHERONLY_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_authonly_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_AUTHONLY_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
 /* ***** SNOW 3G Tests ***** */
 static int
 create_wireless_algo_hash_session(uint8_t dev_id,
@@ -9951,6 +10041,208 @@ static struct unit_test_suite cryptodev_ccp_testsuite  = {
 	}
 };
 
+static struct unit_test_suite cryptodev_cpt_testsuite  = {
+	.suite_name = "Crypto Device OCTEONTX Unit Test Suite",
+	.setup = testsuite_setup,
+	.teardown = testsuite_teardown,
+	.unit_test_cases = {
+		TEST_CASE_ST(ut_setup, ut_teardown, test_AES_chain_cpt_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+						test_AES_cipheronly_cpt_all),
+		TEST_CASE_ST(ut_setup, ut_teardown, test_3DES_chain_cpt_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+						test_3DES_cipheronly_cpt_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+						test_authonly_cpt_all),
+
+		/** AES GCM Authenticated Encryption */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_6),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_7),
+
+		/** AES GCM Authenticated Decryption */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_6),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_7),
+		/** AES GMAC Authentication */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_verify_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_verify_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_verify_test_case_3),
+
+		/** SNOW 3G encrypt only (UEA2) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_5),
+
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_1_oop),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			     test_snow3g_decryption_test_case_1_oop),
+
+		/** SNOW 3G decrypt only (UEA2) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_5),
+
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_generate_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_generate_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_generate_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_verify_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_verify_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_verify_test_case_3),
+
+		/** ZUC encrypt only (EEA3) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_5),
+
+		/** KASUMI encrypt only (UEA1) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_5),
+		/** KASUMI decrypt only (UEA1) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_5),
+
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1_oop),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_1_oop),
+
+		/** KASUMI hash only (UIA1) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_6),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_5),
+
+		/** NULL tests */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_cipher_only_operation),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_auth_only_operation),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_cipher_auth_operation),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_auth_cipher_operation),
+
+		/** Negative tests */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_HMAC_SHA1_fail_data_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_HMAC_SHA1_fail_tag_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_AES128_GMAC_fail_data_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_AES128_GMAC_fail_tag_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			auth_decryption_AES128CBC_HMAC_SHA1_fail_data_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			auth_decryption_AES128CBC_HMAC_SHA1_fail_tag_corrupt),
+		TEST_CASES_END() /**< NULL terminate unit test array */
+	}
+};
+
 static int
 test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
 {
@@ -10203,6 +10495,21 @@ test_cryptodev_ccp(void)
 	return unit_test_suite_runner(&cryptodev_ccp_testsuite);
 }
 
+static int
+test_cryptodev_octeontx(void)
+{
+	gbl_driver_id =	rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+	if (gbl_driver_id == -1) {
+		RTE_LOG(ERR, USER1, "OCTEONTX PMD must be loaded. Check if "
+				"CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO is "
+				"enabled in config file to run this "
+				"testsuite.\n");
+		return TEST_FAILED;
+	}
+	return unit_test_suite_runner(&cryptodev_cpt_testsuite);
+}
+
 REGISTER_TEST_COMMAND(cryptodev_qat_autotest, test_cryptodev_qat);
 REGISTER_TEST_COMMAND(cryptodev_aesni_mb_autotest, test_cryptodev_aesni_mb);
 REGISTER_TEST_COMMAND(cryptodev_openssl_autotest, test_cryptodev_openssl);
@@ -10217,3 +10524,4 @@ REGISTER_TEST_COMMAND(cryptodev_dpaa2_sec_autotest, test_cryptodev_dpaa2_sec);
 REGISTER_TEST_COMMAND(cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec);
 REGISTER_TEST_COMMAND(cryptodev_ccp_autotest, test_cryptodev_ccp);
 REGISTER_TEST_COMMAND(cryptodev_virtio_autotest, test_cryptodev_virtio);
+REGISTER_TEST_COMMAND(cryptodev_octeontx_autotest, test_cryptodev_octeontx);
diff --git a/test/test/test_cryptodev.h b/test/test/test_cryptodev.h
index 1bd44dc..f2d41ae 100644
--- a/test/test/test_cryptodev.h
+++ b/test/test/test_cryptodev.h
@@ -64,6 +64,7 @@
 #define CRYPTODEV_NAME_MVSAM_PMD		crypto_mvsam
 #define CRYPTODEV_NAME_CCP_PMD		crypto_ccp
 #define CRYPTODEV_NAME_VIRTIO_PMD	crypto_virtio
+#define CRYPTODEV_NAME_OCTEONTX_SYM_PMD	crypto_octeontx
 
 /**
  * Write (spread) data from buffer to mbuf data
diff --git a/test/test/test_cryptodev_aes_test_vectors.h b/test/test/test_cryptodev_aes_test_vectors.h
index 1c4dc66..a92eaf9 100644
--- a/test/test/test_cryptodev_aes_test_vectors.h
+++ b/test/test/test_cryptodev_aes_test_vectors.h
@@ -1254,7 +1254,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1262,7 +1263,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_13,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENC_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1291,7 +1293,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1308,7 +1311,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_13,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest",
@@ -1322,7 +1326,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest "
@@ -1330,7 +1335,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_12,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENC_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1345,7 +1351,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1353,7 +1360,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_12,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest",
@@ -1366,7 +1374,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1376,7 +1385,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SESSIONLESS,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1401,7 +1411,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest "
@@ -1443,7 +1454,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1455,7 +1467,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA224 Encryption Digest",
@@ -1467,7 +1480,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
@@ -1480,7 +1494,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
@@ -1517,7 +1532,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SESSIONLESS,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr =
@@ -1528,7 +1544,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SESSIONLESS,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 };
 
@@ -1545,7 +1562,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC Decryption",
@@ -1559,7 +1577,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Encryption",
@@ -1572,7 +1591,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Encryption Scater gather",
@@ -1595,7 +1615,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Decryption Scatter Gather",
@@ -1617,7 +1638,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CBC Decryption",
@@ -1631,7 +1653,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CBC OOP Encryption",
@@ -1668,7 +1691,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CTR Decryption",
@@ -1681,7 +1705,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CTR Encryption",
@@ -1693,7 +1718,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CTR Decryption",
@@ -1705,7 +1731,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CTR Encryption",
@@ -1718,7 +1745,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CTR Decryption",
@@ -1731,25 +1759,29 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CTR Encryption (12-byte IV)",
 		.test_data = &aes_test_data_1_IV_12_bytes,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
-		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CTR Encryption (12-byte IV)",
 		.test_data = &aes_test_data_2_IV_12_bytes,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
-		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CTR Encryption (12-byte IV)",
 		.test_data = &aes_test_data_3_IV_12_bytes,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
-		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	}
 };
 
diff --git a/test/test/test_cryptodev_blockcipher.c b/test/test/test_cryptodev_blockcipher.c
index f2701f8..2197638 100644
--- a/test/test/test_cryptodev_blockcipher.c
+++ b/test/test/test_cryptodev_blockcipher.c
@@ -72,6 +72,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
 			RTE_STR(CRYPTODEV_NAME_MVSAM_PMD));
 	int virtio_pmd = rte_cryptodev_driver_id_get(
 			RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
+	int cpt_pmd = rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
 
 	int nb_segs = 1;
 
@@ -114,7 +116,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
 			driver_id == armv8_pmd ||
 			driver_id == mrvl_pmd ||
 			driver_id == ccp_pmd ||
-			driver_id == virtio_pmd) { /* Fall through */
+			driver_id == virtio_pmd ||
+			driver_id == cpt_pmd) { /* Fall through */
 		digest_len = tdata->digest.len;
 	} else if (driver_id == aesni_mb_pmd ||
 			driver_id == scheduler_pmd) {
@@ -640,6 +643,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
 			RTE_STR(CRYPTODEV_NAME_MVSAM_PMD));
 	int virtio_pmd = rte_cryptodev_driver_id_get(
 			RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
+	int cpt_pmd = rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
 
 	switch (test_type) {
 	case BLKCIPHER_AES_CHAIN_TYPE:
@@ -706,6 +711,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
 		target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MVSAM;
 	else if (driver_id == virtio_pmd)
 		target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO;
+	else if (driver_id == cpt_pmd)
+		target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX;
 	else
 		TEST_ASSERT(0, "Unrecognized cryptodev type");
 
diff --git a/test/test/test_cryptodev_blockcipher.h b/test/test/test_cryptodev_blockcipher.h
index 6f7c892..2954f6f 100644
--- a/test/test/test_cryptodev_blockcipher.h
+++ b/test/test/test_cryptodev_blockcipher.h
@@ -29,6 +29,7 @@
 #define BLOCKCIPHER_TEST_TARGET_PMD_MVSAM	0x0080 /* Marvell flag */
 #define BLOCKCIPHER_TEST_TARGET_PMD_CCP		0x0040 /* CCP flag */
 #define BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO	0x0200 /* VIRTIO flag */
+#define BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX	0x0100 /* Octeontx flag */
 
 #define BLOCKCIPHER_TEST_OP_CIPHER	(BLOCKCIPHER_TEST_OP_ENCRYPT | \
 					BLOCKCIPHER_TEST_OP_DECRYPT)
diff --git a/test/test/test_cryptodev_des_test_vectors.h b/test/test/test_cryptodev_des_test_vectors.h
index 1033456..0789881 100644
--- a/test/test/test_cryptodev_des_test_vectors.h
+++ b/test/test/test_cryptodev_des_test_vectors.h
@@ -1104,7 +1104,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-192-CBC HMAC-SHA1 Decryption Digest Verify",
@@ -1115,7 +1116,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-192-CBC SHA1 Encryption Digest",
@@ -1276,7 +1278,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MB
+			BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-192-CBC Decryption",
@@ -1288,7 +1291,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MB
+			BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-128-CTR Encryption",
diff --git a/test/test/test_cryptodev_hash_test_vectors.h b/test/test/test_cryptodev_hash_test_vectors.h
index cf86dbb..e7e8411 100644
--- a/test/test/test_cryptodev_hash_test_vectors.h
+++ b/test/test/test_cryptodev_hash_test_vectors.h
@@ -373,14 +373,16 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.test_data = &md5_test_vector,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "MD5 Digest Verify",
 		.test_data = &md5_test_vector,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-MD5 Digest",
@@ -392,7 +394,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-MD5 Digest Verify",
@@ -404,7 +407,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA1 Digest",
@@ -412,7 +416,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA1 Digest Verify",
@@ -420,7 +425,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest",
@@ -433,7 +439,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest Scatter Gather",
@@ -454,7 +461,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest Verify Scatter Gather",
@@ -470,7 +478,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA224 Digest Verify",
@@ -478,7 +487,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA224 Digest",
@@ -490,7 +500,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_QAT
+			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA224 Digest Verify",
@@ -502,7 +513,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_QAT
+			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA256 Digest",
@@ -510,7 +522,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA256 Digest Verify",
@@ -518,7 +531,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA256 Digest",
@@ -531,7 +545,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA256 Digest Verify",
@@ -544,7 +559,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA384 Digest",
@@ -552,7 +568,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA384 Digest Verify",
@@ -560,7 +577,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA384 Digest",
@@ -573,7 +591,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA384 Digest Verify",
@@ -586,7 +605,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA512 Digest",
@@ -594,7 +614,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA512 Digest Verify",
@@ -602,7 +623,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA512 Digest",
@@ -615,7 +637,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA512 Digest Verify",
@@ -628,7 +651,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "CMAC Digest 12B",
-- 
2.7.4

[dpdk-dev] [PATCH v2 33/33] doc: adds doc file

[Anoob Joseph]

From: Anoob Joseph <anoob.joseph@caviumnetworks.com>

This patch adds the features file and the document containing
help to compile and use octeontx crypto.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 doc/guides/cryptodevs/features/octeontx.ini |  60 ++++++++++++++
 doc/guides/cryptodevs/octeontx.rst          | 121 ++++++++++++++++++++++++++++
 2 files changed, 181 insertions(+)
 create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
 create mode 100644 doc/guides/cryptodevs/octeontx.rst

diff --git a/doc/guides/cryptodevs/features/octeontx.ini b/doc/guides/cryptodevs/features/octeontx.ini
new file mode 100644
index 0000000..f5f5229
--- /dev/null
+++ b/doc/guides/cryptodevs/features/octeontx.ini
@@ -0,0 +1,60 @@
+;
+; Supported features of the 'octeontx' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto       = Y
+Sym operation chaining = Y
+HW Accelerated         = Y
+Mbuf scatter gather    = Y
+
+;
+; Supported crypto algorithms of 'octeontx' crypto driver.
+;
+[Cipher]
+NULL           = Y
+3DES CBC       = Y
+3DES ECB       = Y
+AES CBC (128)  = Y
+AES CBC (192)  = Y
+AES CBC (256)  = Y
+AES CTR (128)  = Y
+AES CTR (192)  = Y
+AES CTR (256)  = Y
+AES XTS (128)  = Y
+AES XTS (256)  = Y
+DES CBC        = Y
+KASUMI F8      = Y
+SNOW3G UEA2    = Y
+ZUC EEA3       = Y
+
+;
+; Supported authentication algorithms of 'octeontx' crypto driver.
+;
+[Auth]
+NULL         = Y
+AES GMAC     = Y
+KASUMI F9    = Y
+MD5          = Y
+MD5 HMAC     = Y
+SHA1         = Y
+SHA1 HMAC    = Y
+SHA224       = Y
+SHA224 HMAC  = Y
+SHA256       = Y
+SHA256 HMAC  = Y
+SHA384       = Y
+SHA384 HMAC  = Y
+SHA512       = Y
+SHA512 HMAC  = Y
+SNOW3G UIA2  = Y
+ZUC EIA3     = Y
+
+;
+; Supported AEAD algorithms of 'octeontx' crypto driver.
+;
+[AEAD]
+AES GCM (128) = Y
+AES GCM (192) = Y
+AES GCM (256) = Y
diff --git a/doc/guides/cryptodevs/octeontx.rst b/doc/guides/cryptodevs/octeontx.rst
new file mode 100644
index 0000000..67bd441
--- /dev/null
+++ b/doc/guides/cryptodevs/octeontx.rst
@@ -0,0 +1,121 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+   Copyright(c) 2018 Cavium, Inc
+
+Cavium's OcteonTX Poll Mode Driver
+==================================
+
+The octeontx crypto poll mode driver provides support for offloading
+cryptographic operations on cryptographic accelerator units on OcteonTX
+family of processors (CN8XXX). The octeontx crypto poll mode driver enqueues
+the crypto request to this accelerator and dequeues the response once the
+operation is completed.
+
+Supported Algorithms
+---------------------
+
+Cipher Algorithms
+~~~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_CIPHER_NULL``
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_3DES_ECB``
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_CTR``
+* ``RTE_CRYPTO_CIPHER_AES_XTS``
+* ``RTE_CRYPTO_CIPHER_DES_CBC``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
+
+Hash Algorithms
+~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_AES_GMAC``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
+* ``RTE_CRYPTO_AUTH_MD5``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA1``
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+
+AEAD Algorithms
+~~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_AEAD_AES_GCM``
+
+Compilation
+------------
+
+The OcteonTX board must be running the linux kernel based on sdk-6.2.0 patch 3.
+In this the OcteonTX pf driver is already built in.
+
+For compiling the OcteonTX crypto poll mode driver, please check if the
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO setting is set to `y` in
+config/common_base file.
+
+* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y``
+
+The following are the steps to compile the octeontx poll mode driver:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        make config T=arm64-thunderx-linuxapp-gcc
+        make
+
+The example applications can be compiled using the following:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        export RTE_SDK=$PWD
+        export RTE_TARGET=build
+        cd examples/<application>
+        make
+
+Execution
+----------
+
+The sriov_numvfs should be assigned for the octeontx pf driver using the
+following:
+
+.. code-block:: console
+
+        echo <num vfs> > /sys/bus/pci/devices/<device no>/sriov_numvfs
+
+The device number can be ascertained by running the dpdk-devbind.py scripts in
+the dpdk sources.
+
+Then the corresponding vf should be binded to the vfio-pci driver using the
+following:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        ./usertools/dpdk-devbind.py -u <vf device no>
+        ./usertools/dpdk-devbind.py -b vfio-pci <vf device no>
+
+Appropriate huge page need to be setup in order to run the examples dpdk
+application.
+
+.. code-block:: console
+
+        echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
+        mkdir /mnt/huge
+        mount -t hugetlbfs nodev /mnt/huge
+
+After that the example dpdk application can be executed on the hardware.
+
+.. code-block:: console
+        ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
+        "(1,0,0),(0,0,0)" -f ep1.cfg
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 33/33] doc: adds doc file

[Akhil Goyal]

++John

On 9/4/2018 9:29 AM, Anoob Joseph wrote:

> From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
>
> This patch adds the features file and the document containing
> help to compile and use octeontx crypto.
>
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
> ---
>   doc/guides/cryptodevs/features/octeontx.ini |  60 ++++++++++++++
>   doc/guides/cryptodevs/octeontx.rst          | 121 ++++++++++++++++++++++++++++
>   2 files changed, 181 insertions(+)
>   create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
>   create mode 100644 doc/guides/cryptodevs/octeontx.rst
>
> diff --git a/doc/guides/cryptodevs/features/octeontx.ini b/doc/guides/cryptodevs/features/octeontx.ini
> new file mode 100644
> index 0000000..f5f5229
> --- /dev/null
> +++ b/doc/guides/cryptodevs/features/octeontx.ini
> @@ -0,0 +1,60 @@
> +;
> +; Supported features of the 'octeontx' crypto driver.
> +;
> +; Refer to default.ini for the full list of available PMD features.
> +;
> +[Features]
> +Symmetric crypto       = Y
> +Sym operation chaining = Y
> +HW Accelerated         = Y
> +Mbuf scatter gather    = Y

I do not see feature flags for scatter gather in the code.
Please set what all is supported in the PMD.

#define RTE_CRYPTODEV_FF_IN_PLACE_SGL                   (1ULL << 9)

/**< In-place Scatter-gather (SGL) buffers, with multiple segments,

  * are supported

  */

#define RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT             (1ULL << 10)

/**< Out-of-place Scatter-gather (SGL) buffers are

  * supported in input and output

  */

#define RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT              (1ULL << 11)

/**< Out-of-place Scatter-gather (SGL) buffers are supported

  * in input, combined with linear buffers (LB), with a

  * single segment in output

  */

#define RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT              (1ULL << 12)

/**< Out-of-place Scatter-gather (SGL) buffers are supported

  * in output, combined with linear buffers (LB) in input

  */

> +
> +;
> +; Supported crypto algorithms of 'octeontx' crypto driver.
> +;
> +[Cipher]
> +NULL           = Y
> +3DES CBC       = Y
> +3DES ECB       = Y
> +AES CBC (128)  = Y
> +AES CBC (192)  = Y
> +AES CBC (256)  = Y
> +AES CTR (128)  = Y
> +AES CTR (192)  = Y
> +AES CTR (256)  = Y
> +AES XTS (128)  = Y
> +AES XTS (256)  = Y
> +DES CBC        = Y
> +KASUMI F8      = Y
> +SNOW3G UEA2    = Y
> +ZUC EEA3       = Y
> +
> +;
> +; Supported authentication algorithms of 'octeontx' crypto driver.
> +;
> +[Auth]
> +NULL         = Y
> +AES GMAC     = Y
> +KASUMI F9    = Y
> +MD5          = Y
> +MD5 HMAC     = Y
> +SHA1         = Y
> +SHA1 HMAC    = Y
> +SHA224       = Y
> +SHA224 HMAC  = Y
> +SHA256       = Y
> +SHA256 HMAC  = Y
> +SHA384       = Y
> +SHA384 HMAC  = Y
> +SHA512       = Y
> +SHA512 HMAC  = Y
> +SNOW3G UIA2  = Y
> +ZUC EIA3     = Y
> +
> +;
> +; Supported AEAD algorithms of 'octeontx' crypto driver.
> +;
> +[AEAD]
> +AES GCM (128) = Y
> +AES GCM (192) = Y
> +AES GCM (256) = Y
> diff --git a/doc/guides/cryptodevs/octeontx.rst b/doc/guides/cryptodevs/octeontx.rst
> new file mode 100644
> index 0000000..67bd441
> --- /dev/null
> +++ b/doc/guides/cryptodevs/octeontx.rst
> @@ -0,0 +1,121 @@
> +.. SPDX-License-Identifier: BSD-3-Clause
> +   Copyright(c) 2018 Cavium, Inc
> +
> +Cavium's OcteonTX Poll Mode Driver
> +==================================
> +
> +The octeontx crypto poll mode driver provides support for offloading
> +cryptographic operations on cryptographic accelerator units on OcteonTX
> +family of processors (CN8XXX). The octeontx crypto poll mode driver enqueues
> +the crypto request to this accelerator and dequeues the response once the
> +operation is completed.
> +
> +Supported Algorithms
> +---------------------

remove one extra '-'. Please check at other places as well

> +
> +Cipher Algorithms
> +~~~~~~~~~~~~~~~~~
> +
> +* ``RTE_CRYPTO_CIPHER_NULL``
> +* ``RTE_CRYPTO_CIPHER_3DES_CBC``
> +* ``RTE_CRYPTO_CIPHER_3DES_ECB``
> +* ``RTE_CRYPTO_CIPHER_AES_CBC``
> +* ``RTE_CRYPTO_CIPHER_AES_CTR``
> +* ``RTE_CRYPTO_CIPHER_AES_XTS``
> +* ``RTE_CRYPTO_CIPHER_DES_CBC``
> +* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
> +* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
> +* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
> +
> +Hash Algorithms
> +~~~~~~~~~~~~~~~
> +
> +* ``RTE_CRYPTO_AUTH_NULL``
> +* ``RTE_CRYPTO_AUTH_AES_GMAC``
> +* ``RTE_CRYPTO_AUTH_KASUMI_F9``
> +* ``RTE_CRYPTO_AUTH_MD5``
> +* ``RTE_CRYPTO_AUTH_MD5_HMAC``
> +* ``RTE_CRYPTO_AUTH_SHA1``
> +* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
> +* ``RTE_CRYPTO_AUTH_SHA224``
> +* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
> +* ``RTE_CRYPTO_AUTH_SHA256``
> +* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
> +* ``RTE_CRYPTO_AUTH_SHA384``
> +* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
> +* ``RTE_CRYPTO_AUTH_SHA512``
> +* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
> +* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
> +* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
> +
> +AEAD Algorithms
> +~~~~~~~~~~~~~~~~
> +
> +* ``RTE_CRYPTO_AEAD_AES_GCM``
> +
> +Compilation
> +------------
> +
> +The OcteonTX board must be running the linux kernel based on sdk-6.2.0 patch 3.
> +In this the OcteonTX pf driver is already built in.
> +
> +For compiling the OcteonTX crypto poll mode driver, please check if the
> +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO setting is set to `y` in
> +config/common_base file.
> +
> +* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y``
> +
> +The following are the steps to compile the octeontx poll mode driver:
> +
> +.. code-block:: console
> +
> +        cd <dpdk directory>
> +        make config T=arm64-thunderx-linuxapp-gcc
> +        make
> +
> +The example applications can be compiled using the following:
> +
> +.. code-block:: console
> +
> +        cd <dpdk directory>
> +        export RTE_SDK=$PWD
> +        export RTE_TARGET=build
> +        cd examples/<application>
> +        make
> +
> +Execution
> +----------
> +
> +The sriov_numvfs should be assigned for the octeontx pf driver using the
> +following:
> +
> +.. code-block:: console
> +
> +        echo <num vfs> > /sys/bus/pci/devices/<device no>/sriov_numvfs
> +
> +The device number can be ascertained by running the dpdk-devbind.py scripts in
> +the dpdk sources.
> +
> +Then the corresponding vf should be binded to the vfio-pci driver using the
> +following:
> +
> +.. code-block:: console
> +
> +        cd <dpdk directory>
> +        ./usertools/dpdk-devbind.py -u <vf device no>
> +        ./usertools/dpdk-devbind.py -b vfio-pci <vf device no>
> +
> +Appropriate huge page need to be setup in order to run the examples dpdk
> +application.
> +
> +.. code-block:: console
> +
> +        echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
> +        mkdir /mnt/huge
> +        mount -t hugetlbfs nodev /mnt/huge
> +
> +After that the example dpdk application can be executed on the hardware.
> +
> +.. code-block:: console
> +        ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
> +        "(1,0,0),(0,0,0)" -f ep1.cfg
>

Re: [dpdk-dev] [PATCH v2 00/33] Adding Cavium's OcteonTX crypto PMD

[Joseph, Anoob]

Hi Akhil, Pablo,

Did you get a chance to look at the patches?

Anoob

On 04-09-2018 09:28, Anoob Joseph wrote:
> Ankur Dwivedi (5):
>    config: add Cavium OcteonTX crypto PMD skeleton
>    common/cpt: add common logging support
>    crypto/octeontx: add PCI probe and remove
>    crypto/octeontx: add register addresses
>    test: adds validation test
>
> Anoob Joseph (5):
>    common/cpt: add common code for init routine
>    crypto/octeontx: add hardware init routine
>    common/cpt: add hardware register defines
>    crypto/octeontx: add hardware register access for misc poll
>    doc: adds doc file
>
> Murthy NSSR (5):
>    crypto/octeontx: adds symmetric capabilities
>    common/cpt: add PMD ops helper functions
>    crypto/octeontx: add global resource init
>    crypto/octeontx: add mailbox routines
>    crypto/octeontx: add basic dev ops
>
> Nithin Dabilpuram (5):
>    common/cpt: add common macros for queue pair ops
>    crypto/octeontx: add queue pair functions
>    common/cpt: add common code required for session management
>    crypto/octeontx: add session management ops
>    common/cpt: add common code for fill session data
>
> Ragothaman Jayaraman (5):
>    crypto/octeontx: add supported sessions
>    common/cpt: add common defines for microcode
>    common/cpt: add microcode interface for encryption
>    common/cpt: add microcode interface for decryption
>    common/cpt: add crypo op enqueue request manager framework
>
> Srisivasubramanian S (5):
>    common/cpt: add support for zuc and snow3g
>    common/cpt: add support for kasumi
>    common/cpt: add support for hash
>    crypto/octeontx: add routines to prepare instructions
>    common/cpt: add common code for enqueuing cpt instruction
>
> Tejasree Kondoj (3):
>    crypto/octeontx: add enqueue burst op
>    common/cpt: add common code for cpt dequeue
>    crypto/octeontx: add dequeue burst op
>
>   MAINTAINERS                                        |    7 +
>   config/common_base                                 |    5 +
>   doc/guides/cryptodevs/features/octeontx.ini        |   60 +
>   doc/guides/cryptodevs/octeontx.rst                 |  121 +
>   drivers/common/Makefile                            |    4 +
>   drivers/common/cpt/Makefile                        |   25 +
>   drivers/common/cpt/cpt_common.h                    |  103 +
>   drivers/common/cpt/cpt_hw_types.h                  |  521 +++
>   drivers/common/cpt/cpt_mcode_defines.h             |  378 ++
>   drivers/common/cpt/cpt_pmd_logs.h                  |   52 +
>   drivers/common/cpt/cpt_pmd_ops_helper.c            |   41 +
>   drivers/common/cpt/cpt_pmd_ops_helper.h            |   34 +
>   drivers/common/cpt/cpt_request_mgr.h               |  189 +
>   drivers/common/cpt/cpt_ucode.h                     | 3646 ++++++++++++++++++++
>   drivers/common/cpt/meson.build                     |    8 +
>   drivers/common/cpt/rte_common_cpt_version.map      |    6 +
>   drivers/common/meson.build                         |    2 +-
>   drivers/crypto/Makefile                            |    1 +
>   drivers/crypto/meson.build                         |    2 +-
>   drivers/crypto/octeontx/Makefile                   |   45 +
>   drivers/crypto/octeontx/meson.build                |   17 +
>   drivers/crypto/octeontx/otx_cryptodev.c            |  135 +
>   drivers/crypto/octeontx/otx_cryptodev.h            |   20 +
>   .../crypto/octeontx/otx_cryptodev_capabilities.h   |  595 ++++
>   drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  609 ++++
>   drivers/crypto/octeontx/otx_cryptodev_hw_access.h  |  320 ++
>   drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  180 +
>   drivers/crypto/octeontx/otx_cryptodev_mbox.h       |   92 +
>   drivers/crypto/octeontx/otx_cryptodev_ops.c        |  532 +++
>   drivers/crypto/octeontx/otx_cryptodev_ops.h        |   18 +
>   .../octeontx/rte_pmd_octeontx_crypto_version.map   |    4 +
>   mk/rte.app.mk                                      |    5 +
>   test/test/meson.build                              |    1 +
>   test/test/test_cryptodev.c                         |  308 ++
>   test/test/test_cryptodev.h                         |    1 +
>   test/test/test_cryptodev_aes_test_vectors.h        |   96 +-
>   test/test/test_cryptodev_blockcipher.c             |    9 +-
>   test/test/test_cryptodev_blockcipher.h             |    1 +
>   test/test/test_cryptodev_des_test_vectors.h        |   12 +-
>   test/test/test_cryptodev_hash_test_vectors.h       |   72 +-
>   40 files changed, 8214 insertions(+), 63 deletions(-)
>   create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
>   create mode 100644 doc/guides/cryptodevs/octeontx.rst
>   create mode 100644 drivers/common/cpt/Makefile
>   create mode 100644 drivers/common/cpt/cpt_common.h
>   create mode 100644 drivers/common/cpt/cpt_hw_types.h
>   create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
>   create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
>   create mode 100644 drivers/common/cpt/cpt_request_mgr.h
>   create mode 100644 drivers/common/cpt/cpt_ucode.h
>   create mode 100644 drivers/common/cpt/meson.build
>   create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
>   create mode 100644 drivers/crypto/octeontx/Makefile
>   create mode 100644 drivers/crypto/octeontx/meson.build
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.h
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
>   create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>

Re: [dpdk-dev] [PATCH v2 00/33] Adding Cavium's OcteonTX crypto PMD

[Akhil Goyal]

Hi Anoob,

I would review it early next week.

Thanks,

Akhil

On 9/14/2018 2:46 PM, Joseph, Anoob wrote:

> Hi Akhil, Pablo,
> Did you get a chance to look at the patches?
> Anoob
> On 04-09-2018 09:28, Anoob Joseph wrote:
>> Ankur Dwivedi (5):
>>     config: add Cavium OcteonTX crypto PMD skeleton
>>     common/cpt: add common logging support
>>     crypto/octeontx: add PCI probe and remove
>>     crypto/octeontx: add register addresses
>>     test: adds validation test
>> Anoob Joseph (5):
>>     common/cpt: add common code for init routine
>>     crypto/octeontx: add hardware init routine
>>     common/cpt: add hardware register defines
>>     crypto/octeontx: add hardware register access for misc poll
>>     doc: adds doc file
>> Murthy NSSR (5):
>>     crypto/octeontx: adds symmetric capabilities
>>     common/cpt: add PMD ops helper functions
>>     crypto/octeontx: add global resource init
>>     crypto/octeontx: add mailbox routines
>>     crypto/octeontx: add basic dev ops
>> Nithin Dabilpuram (5):
>>     common/cpt: add common macros for queue pair ops
>>     crypto/octeontx: add queue pair functions
>>     common/cpt: add common code required for session management
>>     crypto/octeontx: add session management ops
>>     common/cpt: add common code for fill session data
>> Ragothaman Jayaraman (5):
>>     crypto/octeontx: add supported sessions
>>     common/cpt: add common defines for microcode
>>     common/cpt: add microcode interface for encryption
>>     common/cpt: add microcode interface for decryption
>>     common/cpt: add crypo op enqueue request manager framework
>> Srisivasubramanian S (5):
>>     common/cpt: add support for zuc and snow3g
>>     common/cpt: add support for kasumi
>>     common/cpt: add support for hash
>>     crypto/octeontx: add routines to prepare instructions
>>     common/cpt: add common code for enqueuing cpt instruction
>> Tejasree Kondoj (3):
>>     crypto/octeontx: add enqueue burst op
>>     common/cpt: add common code for cpt dequeue
>>     crypto/octeontx: add dequeue burst op
>>    MAINTAINERS                                        |    7 +
>>    config/common_base                                 |    5 +
>>    doc/guides/cryptodevs/features/octeontx.ini        |   60 +
>>    doc/guides/cryptodevs/octeontx.rst                 |  121 +
>>    drivers/common/Makefile                            |    4 +
>>    drivers/common/cpt/Makefile                        |   25 +
>>    drivers/common/cpt/cpt_common.h                    |  103 +
>>    drivers/common/cpt/cpt_hw_types.h                  |  521 +++
>>    drivers/common/cpt/cpt_mcode_defines.h             |  378 ++
>>    drivers/common/cpt/cpt_pmd_logs.h                  |   52 +
>>    drivers/common/cpt/cpt_pmd_ops_helper.c            |   41 +
>>    drivers/common/cpt/cpt_pmd_ops_helper.h            |   34 +
>>    drivers/common/cpt/cpt_request_mgr.h               |  189 +
>>    drivers/common/cpt/cpt_ucode.h                     | 3646 ++++++++++++++++++++
>>    drivers/common/cpt/meson.build                     |    8 +
>>    drivers/common/cpt/rte_common_cpt_version.map      |    6 +
>>    drivers/common/meson.build                         |    2 +-
>>    drivers/crypto/Makefile                            |    1 +
>>    drivers/crypto/meson.build                         |    2 +-
>>    drivers/crypto/octeontx/Makefile                   |   45 +
>>    drivers/crypto/octeontx/meson.build                |   17 +
>>    drivers/crypto/octeontx/otx_cryptodev.c            |  135 +
>>    drivers/crypto/octeontx/otx_cryptodev.h            |   20 +
>>    .../crypto/octeontx/otx_cryptodev_capabilities.h   |  595 ++++
>>    drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  609 ++++
>>    drivers/crypto/octeontx/otx_cryptodev_hw_access.h  |  320 ++
>>    drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  180 +
>>    drivers/crypto/octeontx/otx_cryptodev_mbox.h       |   92 +
>>    drivers/crypto/octeontx/otx_cryptodev_ops.c        |  532 +++
>>    drivers/crypto/octeontx/otx_cryptodev_ops.h        |   18 +
>>    .../octeontx/rte_pmd_octeontx_crypto_version.map   |    4 +
>>    mk/rte.app.mk                                      |    5 +
>>    test/test/meson.build                              |    1 +
>>    test/test/test_cryptodev.c                         |  308 ++
>>    test/test/test_cryptodev.h                         |    1 +
>>    test/test/test_cryptodev_aes_test_vectors.h        |   96 +-
>>    test/test/test_cryptodev_blockcipher.c             |    9 +-
>>    test/test/test_cryptodev_blockcipher.h             |    1 +
>>    test/test/test_cryptodev_des_test_vectors.h        |   12 +-
>>    test/test/test_cryptodev_hash_test_vectors.h       |   72 +-
>>    40 files changed, 8214 insertions(+), 63 deletions(-)
>>    create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
>>    create mode 100644 doc/guides/cryptodevs/octeontx.rst
>>    create mode 100644 drivers/common/cpt/Makefile
>>    create mode 100644 drivers/common/cpt/cpt_common.h
>>    create mode 100644 drivers/common/cpt/cpt_hw_types.h
>>    create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
>>    create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
>>    create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
>>    create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
>>    create mode 100644 drivers/common/cpt/cpt_request_mgr.h
>>    create mode 100644 drivers/common/cpt/cpt_ucode.h
>>    create mode 100644 drivers/common/cpt/meson.build
>>    create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
>>    create mode 100644 drivers/crypto/octeontx/Makefile
>>    create mode 100644 drivers/crypto/octeontx/meson.build
>>    create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
>>    create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
>>    create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.h
>>    create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
>>    create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h
>>    create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
>>    create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h
>>    create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
>>    create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
>>    create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>

[dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD

[Anoob Joseph]

Ankur Dwivedi (5):
  common/cpt: add common logging support
  config: add Cavium OCTEONTX crypto PMD skeleton
  crypto/octeontx: add register addresses
  common/cpt: add common code for init routine
  test: adds validation test

Anoob Joseph (5):
  crypto/octeontx: add hardware init routine
  common/cpt: add hardware register defines
  crypto/octeontx: add hardware register access for misc poll
  crypto/octeontx: adds symmetric capabilities
  doc: adds doc file

Murthy NSSR (5):
  common/cpt: add PMD ops helper functions
  crypto/octeontx: add global resource init
  crypto/octeontx: add mailbox routines
  crypto/octeontx: add basic dev ops
  common/cpt: add common macros for queue pair ops

Nithin Dabilpuram (5):
  crypto/octeontx: add queue pair functions
  common/cpt: add common code required for session management
  crypto/octeontx: add session management ops
  common/cpt: add common code for fill session data
  crypto/octeontx: add supported sessions

Ragothaman Jayaraman (4):
  common/cpt: add common defines for microcode
  common/cpt: add microcode interface for encryption
  common/cpt: add microcode interface for decryption
  common/cpt: add crypo op enqueue request manager framework

Srisivasubramanian S (4):
  common/cpt: add support for zuc and snow3g
  common/cpt: add support for kasumi
  common/cpt: add support for hash
  crypto/octeontx: add routines to prepare instructions

Tejasree Kondoj (4):
  common/cpt: add common code for enqueuing cpt instruction
  crypto/octeontx: add enqueue burst op
  common/cpt: add common code for cpt dequeue
  crypto/octeontx: add dequeue burst op

 MAINTAINERS                                        |    7 +
 config/common_base                                 |    5 +
 doc/guides/cryptodevs/features/octeontx.ini        |   62 +
 doc/guides/cryptodevs/index.rst                    |    1 +
 doc/guides/cryptodevs/octeontx.rst                 |  128 +
 drivers/common/Makefile                            |    4 +
 drivers/common/cpt/Makefile                        |   25 +
 drivers/common/cpt/cpt_common.h                    |   91 +
 drivers/common/cpt/cpt_hw_types.h                  |  522 +++
 drivers/common/cpt/cpt_mcode_defines.h             |  386 +++
 drivers/common/cpt/cpt_pmd_logs.h                  |   50 +
 drivers/common/cpt/cpt_pmd_ops_helper.c            |   41 +
 drivers/common/cpt/cpt_pmd_ops_helper.h            |   34 +
 drivers/common/cpt/cpt_request_mgr.h               |  185 +
 drivers/common/cpt/cpt_ucode.h                     | 3650 ++++++++++++++++++++
 drivers/common/cpt/meson.build                     |    8 +
 drivers/common/cpt/rte_common_cpt_version.map      |    6 +
 drivers/common/meson.build                         |    2 +-
 drivers/crypto/Makefile                            |    1 +
 drivers/crypto/meson.build                         |    2 +-
 drivers/crypto/octeontx/Makefile                   |   46 +
 drivers/crypto/octeontx/meson.build                |   18 +
 drivers/crypto/octeontx/otx_cryptodev.c            |  133 +
 drivers/crypto/octeontx/otx_cryptodev.h            |   20 +
 .../crypto/octeontx/otx_cryptodev_capabilities.c   |  604 ++++
 .../crypto/octeontx/otx_cryptodev_capabilities.h   |   17 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  598 ++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h  |  320 ++
 drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  178 +
 drivers/crypto/octeontx/otx_cryptodev_mbox.h       |   92 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c        |  531 +++
 drivers/crypto/octeontx/otx_cryptodev_ops.h        |   18 +
 .../octeontx/rte_pmd_octeontx_crypto_version.map   |    4 +
 mk/rte.app.mk                                      |    5 +
 test/test/meson.build                              |    1 +
 test/test/test_cryptodev.c                         |  316 ++
 test/test/test_cryptodev.h                         |    1 +
 test/test/test_cryptodev_aes_test_vectors.h        |  114 +-
 test/test/test_cryptodev_blockcipher.c             |    9 +-
 test/test/test_cryptodev_blockcipher.h             |    1 +
 test/test/test_cryptodev_des_test_vectors.h        |   12 +-
 test/test/test_cryptodev_hash_test_vectors.h       |   78 +-
 42 files changed, 8255 insertions(+), 71 deletions(-)
 create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
 create mode 100644 doc/guides/cryptodevs/octeontx.rst
 create mode 100644 drivers/common/cpt/Makefile
 create mode 100644 drivers/common/cpt/cpt_common.h
 create mode 100644 drivers/common/cpt/cpt_hw_types.h
 create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
 create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
 create mode 100644 drivers/common/cpt/cpt_request_mgr.h
 create mode 100644 drivers/common/cpt/cpt_ucode.h
 create mode 100644 drivers/common/cpt/meson.build
 create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
 create mode 100644 drivers/crypto/octeontx/Makefile
 create mode 100644 drivers/crypto/octeontx/meson.build
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
 create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map

-- 
2.7.4

[dpdk-dev] [PATCH v3 01/32] common/cpt: add common logging support

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Add common logging macros

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 MAINTAINERS                       |  4 ++++
 drivers/common/cpt/cpt_pmd_logs.h | 50 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)
 create mode 100644 drivers/common/cpt/cpt_pmd_logs.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 5967c1d..52202b9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -772,6 +772,10 @@ F: drivers/crypto/armv8/
 F: doc/guides/cryptodevs/armv8.rst
 F: doc/guides/cryptodevs/features/armv8.ini
 
+Cavium OCTEON TX
+M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
+F: drivers/common/cpt/
+
 Crypto Scheduler
 M: Fan Zhang <roy.fan.zhang@intel.com>
 F: drivers/crypto/scheduler/
diff --git a/drivers/common/cpt/cpt_pmd_logs.h b/drivers/common/cpt/cpt_pmd_logs.h
new file mode 100644
index 0000000..4cbec4e
--- /dev/null
+++ b/drivers/common/cpt/cpt_pmd_logs.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_PMD_LOGS_H_
+#define _CPT_PMD_LOGS_H_
+
+#include <rte_log.h>
+
+/*
+ * This file defines log macros
+ */
+
+#define CPT_PMD_DRV_LOG_RAW(level, fmt, args...) \
+		rte_log(RTE_LOG_ ## level, cpt_logtype, \
+			"cpt: %s(): " fmt "\n", __func__, ##args)
+
+#define CPT_PMD_INIT_FUNC_TRACE() CPT_PMD_DRV_LOG_RAW(DEBUG, " >>")
+
+#define CPT_LOG_INFO(fmt, args...) \
+	CPT_PMD_DRV_LOG_RAW(INFO, fmt, ## args)
+#define CPT_LOG_WARN(fmt, args...) \
+	CPT_PMD_DRV_LOG_RAW(WARNING, fmt, ## args)
+#define CPT_LOG_ERR(fmt, args...) \
+	CPT_PMD_DRV_LOG_RAW(ERR, fmt, ## args)
+
+/*
+ * DP logs, toggled out at compile time if level lower than current level.
+ * DP logs would be logged under 'PMD' type. So for dynamic logging, the
+ * level of 'pmd' has to be used.
+ */
+#define CPT_LOG_DP(level, fmt, args...) \
+	RTE_LOG_DP(level, PMD, fmt "\n", ## args)
+
+#define CPT_LOG_DP_DEBUG(fmt, args...) \
+	CPT_LOG_DP(DEBUG, fmt, ## args)
+#define CPT_LOG_DP_INFO(fmt, args...) \
+	CPT_LOG_DP(INFO, fmt, ## args)
+#define CPT_LOG_DP_WARN(fmt, args...) \
+	CPT_LOG_DP(WARNING, fmt, ## args)
+#define CPT_LOG_DP_ERR(fmt, args...) \
+	CPT_LOG_DP(ERR, fmt, ## args)
+
+/*
+ * cpt_logtype will be used for common logging. This field would be initialized
+ * by otx_* driver routines during PCI probe.
+ */
+int cpt_logtype;
+
+#endif /* _CPT_PMD_LOGS_H_ */
-- 
2.7.4

Re: [dpdk-dev] [PATCH v3 01/32] common/cpt: add common logging support

[Thomas Monjalon]

05/10/2018 14:58, Anoob Joseph:
> +Cavium OCTEON TX
> +M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> +F: drivers/common/cpt/

What is the real wording for this device family?
Sometimes I read OcteonTX with lowercases and no space,
sometimes OCTEONTX without space, sometimes OCTEON TX.

Another note: You should differentiate ethdev and cryptodev devices,
at least in the maintainer file.
We have nicvf, zipvf, ssovf, timvf.
I suggest to add "crypto" to the name of this section.

Re: [dpdk-dev] [PATCH v3 01/32] common/cpt: add common logging support

[Joseph, Anoob]

Hi Thomas,

On 08-10-2018 17:57, Thomas Monjalon wrote:
> External Email
>
> 05/10/2018 14:58, Anoob Joseph:
>> +Cavium OCTEON TX
>> +M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
>> +F: drivers/common/cpt/
> What is the real wording for this device family?
> Sometimes I read OcteonTX with lowercases and no space,
> sometimes OCTEONTX without space, sometimes OCTEON TX.
>
> Another note: You should differentiate ethdev and cryptodev devices,
> at least in the maintainer file.
> We have nicvf, zipvf, ssovf, timvf.
OCTEON TX (with the space) is the registered name of the chip. nicvf, 
zipvf, ssovf, timvf are all multiple blocks on the device and previous 
drivers were named that way. CPT is the similar name for the crypto 
block. Jerin is planning for a common naming convention for the blocks 
on the same family.

Different blocks would be named crypto_octeontx, event_octeontx etc, to 
denote that they are all part of the same device. We had to omit the 
space (between OCTEON & TX), since it would complicate the name for the 
directories.

OcteonTX is a wrong convention. It would be fixed going ahead.
> I suggest to add "crypto" to the name of this section.
This entry is already under "Crypto Drivers". So do we need a separate 
mention of "crypto"?

Anoob

Re: [dpdk-dev] [PATCH v3 01/32] common/cpt: add common logging support

[Thomas Monjalon]

08/10/2018 15:07, Joseph, Anoob:
> On 08-10-2018 17:57, Thomas Monjalon wrote:
> > 05/10/2018 14:58, Anoob Joseph:
> >> +Cavium OCTEON TX
> >> +M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> >> +F: drivers/common/cpt/
> > What is the real wording for this device family?
> > Sometimes I read OcteonTX with lowercases and no space,
> > sometimes OCTEONTX without space, sometimes OCTEON TX.
> >
> > Another note: You should differentiate ethdev and cryptodev devices,
> > at least in the maintainer file.
> > We have nicvf, zipvf, ssovf, timvf.
> OCTEON TX (with the space) is the registered name of the chip. nicvf, 
> zipvf, ssovf, timvf are all multiple blocks on the device and previous 
> drivers were named that way. CPT is the similar name for the crypto 
> block. Jerin is planning for a common naming convention for the blocks 
> on the same family.
> 
> Different blocks would be named crypto_octeontx, event_octeontx etc, to 
> denote that they are all part of the same device. We had to omit the 
> space (between OCTEON & TX), since it would complicate the name for the 
> directories.
> 
> OcteonTX is a wrong convention. It would be fixed going ahead.
> > I suggest to add "crypto" to the name of this section.
> This entry is already under "Crypto Drivers". So do we need a separate 
> mention of "crypto"?

Yes I think it is better to add "crypto", especially for automated processing
of this file, we should avoid to have two times the same section title.

Re: [dpdk-dev] [PATCH v3 01/32] common/cpt: add common logging support

[Anoob Joseph]

Hi Thomas,

On 08-10-2018 19:07, Thomas Monjalon wrote:
> External Email
>
> 08/10/2018 15:07, Joseph, Anoob:
>> On 08-10-2018 17:57, Thomas Monjalon wrote:
>>> 05/10/2018 14:58, Anoob Joseph:
>>>> +Cavium OCTEON TX
>>>> +M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
>>>> +F: drivers/common/cpt/
>>> What is the real wording for this device family?
>>> Sometimes I read OcteonTX with lowercases and no space,
>>> sometimes OCTEONTX without space, sometimes OCTEON TX.
>>>
>>> Another note: You should differentiate ethdev and cryptodev devices,
>>> at least in the maintainer file.
>>> We have nicvf, zipvf, ssovf, timvf.
>> OCTEON TX (with the space) is the registered name of the chip. nicvf,
>> zipvf, ssovf, timvf are all multiple blocks on the device and previous
>> drivers were named that way. CPT is the similar name for the crypto
>> block. Jerin is planning for a common naming convention for the blocks
>> on the same family.
>>
>> Different blocks would be named crypto_octeontx, event_octeontx etc, to
>> denote that they are all part of the same device. We had to omit the
>> space (between OCTEON & TX), since it would complicate the name for the
>> directories.
>>
>> OcteonTX is a wrong convention. It would be fixed going ahead.
>>> I suggest to add "crypto" to the name of this section.
>> This entry is already under "Crypto Drivers". So do we need a separate
>> mention of "crypto"?
> Yes I think it is better to add "crypto", especially for automated processing
> of this file, we should avoid to have two times the same section title.
>
>
I would go ahead with,

Cavium OCTEONTX crypto

Hope this would be fine.

Thanks,
Anoob

[dpdk-dev] [PATCH v3 02/32] config: add Cavium OCTEONTX crypto PMD skeleton

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Adding OCTEONTX crypto PMD skeleton. Updating the maintainers files to
claim responsibility. Also enabling driver by default by adding the
component in common_base.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 MAINTAINERS                                        |   1 +
 config/common_base                                 |   5 +
 drivers/crypto/Makefile                            |   1 +
 drivers/crypto/meson.build                         |   2 +-
 drivers/crypto/octeontx/Makefile                   |  42 +++++++
 drivers/crypto/octeontx/meson.build                |  14 +++
 drivers/crypto/octeontx/otx_cryptodev.c            | 130 +++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev.h            |  20 ++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c        |  15 +++
 drivers/crypto/octeontx/otx_cryptodev_ops.h        |  11 ++
 .../octeontx/rte_pmd_octeontx_crypto_version.map   |   4 +
 mk/rte.app.mk                                      |   1 +
 12 files changed, 245 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/octeontx/Makefile
 create mode 100644 drivers/crypto/octeontx/meson.build
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
 create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 52202b9..b38beb9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -775,6 +775,7 @@ F: doc/guides/cryptodevs/features/armv8.ini
 Cavium OCTEON TX
 M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
 F: drivers/common/cpt/
+F: drivers/crypto/octeontx/
 
 Crypto Scheduler
 M: Fan Zhang <roy.fan.zhang@intel.com>
diff --git a/config/common_base b/config/common_base
index 61c7f6d..cf3da69 100644
--- a/config/common_base
+++ b/config/common_base
@@ -634,6 +634,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
 CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
 
 #
+# Compile PMD for Cavium OCTEON TX crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
+
+#
 # Compile raw device support
 # EXPERIMENTAL: API may change without prior notice
 #
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index c480cbd..c083e64 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -7,6 +7,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += aesni_gcm
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 6ed853b..b09fe1b 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -2,7 +2,7 @@
 # Copyright(c) 2017 Intel Corporation
 
 drivers = ['ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam',
-	'null', 'openssl', 'qat', 'scheduler', 'virtio']
+	'null', 'octeontx', 'openssl', 'qat', 'scheduler', 'virtio']
 
 std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
 config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
new file mode 100644
index 0000000..12fec75
--- /dev/null
+++ b/drivers/crypto/octeontx/Makefile
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_octeontx_crypto.a
+
+# library version
+LIBABIVER := 1
+
+# build flags
+CFLAGS += $(WERROR_FLAGS)
+
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_cryptodev
+LDLIBS += -lrte_pci -lrte_bus_pci
+
+VPATH += $(RTE_SDK)/drivers/crypto/octeontx
+
+CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX
+CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
+
+# PMD code
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
+
+# export include files
+SYMLINK-y-include +=
+
+# versioning export map
+EXPORT_MAP := rte_pmd_octeontx_crypto_version.map
+
+# library dependencies
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_eal
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_cryptodev
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mempool
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mbuf
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_malloc
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
new file mode 100644
index 0000000..6564090
--- /dev/null
+++ b/drivers/crypto/octeontx/meson.build
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+if host_machine.system() != 'linux'
+	build = false
+endif
+
+deps += ['bus_pci']
+name = 'octeontx_crypto'
+
+sources = files('otx_cryptodev.c',
+		'otx_cryptodev_ops.c')
+
+cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
+includes += include_directories('../../common/cpt')
diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c
new file mode 100644
index 0000000..43933dd
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev.c
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_log.h>
+#include <rte_pci.h>
+
+/* CPT common headers */
+#include "cpt_pmd_logs.h"
+
+#include "otx_cryptodev.h"
+#include "otx_cryptodev_ops.h"
+
+static int otx_cryptodev_logtype;
+
+static struct rte_pci_id pci_id_cpt_table[] = {
+	{
+		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_VF_DEVICE_ID),
+	},
+	/* sentinel */
+	{
+		.device_id = 0
+	},
+};
+
+static void
+otx_cpt_logtype_init(void)
+{
+	cpt_logtype = otx_cryptodev_logtype;
+}
+
+static int
+otx_cpt_pci_probe(struct rte_pci_driver *pci_drv,
+			struct rte_pci_device *pci_dev)
+{
+	struct rte_cryptodev *cryptodev;
+	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+	int retval;
+
+	if (pci_drv == NULL)
+		return -ENODEV;
+
+	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+	cryptodev = rte_cryptodev_pmd_allocate(name, rte_socket_id());
+	if (cryptodev == NULL)
+		return -ENOMEM;
+
+	cryptodev->device = &pci_dev->device;
+	cryptodev->device->driver = &pci_drv->driver;
+	cryptodev->driver_id = otx_cryptodev_driver_id;
+
+	/* init user callbacks */
+	TAILQ_INIT(&(cryptodev->link_intr_cbs));
+
+	/* init logtype used in common */
+	otx_cpt_logtype_init();
+
+	/* Invoke PMD device initialization function */
+	retval = otx_cpt_dev_create(cryptodev);
+	if (retval == 0)
+		return 0;
+
+	CPT_LOG_ERR("[DRV %s]: Failed to create device "
+			"(vendor_id: 0x%x device_id: 0x%x",
+			pci_drv->driver.name,
+			(unsigned int) pci_dev->id.vendor_id,
+			(unsigned int) pci_dev->id.device_id);
+
+	cryptodev->attached = RTE_CRYPTODEV_DETACHED;
+
+	return -ENXIO;
+}
+
+static int
+otx_cpt_pci_remove(struct rte_pci_device *pci_dev)
+{
+	struct rte_cryptodev *cryptodev;
+	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+
+	if (pci_dev == NULL)
+		return -EINVAL;
+
+	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+	cryptodev = rte_cryptodev_pmd_get_named_dev(name);
+	if (cryptodev == NULL)
+		return -ENODEV;
+
+	if (pci_dev->driver == NULL)
+		return -ENODEV;
+
+	/* free crypto device */
+	rte_cryptodev_pmd_release_device(cryptodev);
+
+	if (rte_eal_process_type() == RTE_PROC_PRIMARY)
+		rte_free(cryptodev->data->dev_private);
+
+	cryptodev->device = NULL;
+	cryptodev->device->driver = NULL;
+	cryptodev->data = NULL;
+
+	return 0;
+}
+
+static struct rte_pci_driver otx_cryptodev_pmd = {
+	.id_table = pci_id_cpt_table,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+	.probe = otx_cpt_pci_probe,
+	.remove = otx_cpt_pci_remove,
+};
+
+static struct cryptodev_driver otx_cryptodev_drv;
+
+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX_PMD, otx_cryptodev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX_PMD, pci_id_cpt_table);
+RTE_PMD_REGISTER_CRYPTO_DRIVER(otx_cryptodev_drv, otx_cryptodev_pmd.driver,
+		otx_cryptodev_driver_id);
+
+RTE_INIT(otx_cpt_init_log)
+{
+	/* Bus level logs */
+	otx_cryptodev_logtype = rte_log_register("pmd.crypto.octeontx");
+	if (otx_cryptodev_logtype >= 0)
+		rte_log_set_level(otx_cryptodev_logtype, RTE_LOG_NOTICE);
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev.h b/drivers/crypto/octeontx/otx_cryptodev.h
new file mode 100644
index 0000000..62e6f70
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_H_
+#define _OTX_CRYPTODEV_H_
+
+/* Cavium OCTEON TX Crypto PMD device name */
+#define CRYPTODEV_NAME_OCTEONTX_PMD	crypto_octeontx
+
+/* Device ID */
+#define PCI_VENDOR_ID_CAVIUM		0x177d
+#define CPT_81XX_PCI_VF_DEVICE_ID	0xa041
+
+/*
+ * Crypto device driver ID
+ */
+uint8_t otx_cryptodev_driver_id;
+
+#endif /* _OTX_CRYPTODEV_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
new file mode 100644
index 0000000..1b5f108
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_cryptodev.h>
+
+#include "otx_cryptodev.h"
+#include "otx_cryptodev_ops.h"
+
+int
+otx_cpt_dev_create(struct rte_cryptodev *c_dev)
+{
+	RTE_SET_USED(c_dev);
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
new file mode 100644
index 0000000..3f2d829
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_OPS_H_
+#define _OTX_CRYPTODEV_OPS_H_
+
+int
+otx_cpt_dev_create(struct rte_cryptodev *c_dev);
+
+#endif /* _OTX_CRYPTODEV_OPS_H_ */
diff --git a/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
new file mode 100644
index 0000000..521e51f
--- /dev/null
+++ b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
@@ -0,0 +1,4 @@
+DPDK_18.11 {
+
+	local: *;
+};
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index c8a261e..248fce6 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -217,6 +217,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC)         += -L$(LIBSSO_ZUC_PATH)/build -lsso
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -lrte_pmd_armv8
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler
 ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC)   += -lrte_pmd_dpaa2_sec
-- 
2.7.4

Re: [dpdk-dev] [PATCH v3 02/32] config: add Cavium OCTEONTX crypto PMD skeleton

[Thomas Monjalon]

05/10/2018 14:58, Anoob Joseph:
> From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
> 
> Adding OCTEONTX crypto PMD skeleton. Updating the maintainers files to
> claim responsibility. Also enabling driver by default by adding the
> component in common_base.

The title should be
	crypto/octeontx: add PMD skeleton

[dpdk-dev] [PATCH v3 03/32] crypto/octeontx: add register addresses

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 47 +++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
new file mode 100644
index 0000000..288ee41
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
+#define _OTX_CRYPTODEV_HW_ACCESS_H_
+
+/*
+ * CPT Registers map for 81xx
+ */
+
+/* VF registers */
+#define CPTX_VQX_CTL(a, b)		(0x0000100ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_SADDR(a, b)		(0x0000200ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_WAIT(a, b)	(0x0000400ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_INPROG(a, b)		(0x0000410ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE(a, b)		(0x0000420ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ACK(a, b)		(0x0000440ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1S(a, b)	(0x0000460ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1C(a, b)	(0x0000468ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1S(a, b)	(0x0000470ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1C(a, b)	(0x0000478ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT(a, b)		(0x0000500ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT_W1S(a, b)	(0x0000508ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1S(a, b)	(0x0000510ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1C(a, b)	(0x0000518ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DOORBELL(a, b)		(0x0000600ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VFX_PF_MBOXX(a, b, c)	(0x0001000ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b) + \
+					 8ll * ((c) & 0x1))
+
+#endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 04/32] common/cpt: add common code for init routine

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Adding code identified common for OCTEON TX family crypto devices. This
patch is adding the code required by the structures and code path of
init routine.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h | 47 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 drivers/common/cpt/cpt_common.h

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
new file mode 100644
index 0000000..5e2099a
--- /dev/null
+++ b/drivers/common/cpt/cpt_common.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_COMMON_H_
+#define _CPT_COMMON_H_
+
+/*
+ * This file defines common macros and structs
+ */
+
+/*
+ * Macros to determine CPT model. Driver makefile will define CPT_MODEL
+ * accordingly
+ */
+#define CRYPTO_OCTEONTX		0x1
+
+#define AE_TYPE 1
+#define SE_TYPE 2
+
+struct cptvf_meta_info {
+	void *cptvf_meta_pool;
+	int cptvf_op_mlen;
+	int cptvf_op_sb_mlen;
+};
+
+struct rid {
+	/** Request id of a crypto operation */
+	uintptr_t rid;
+};
+
+/*
+ * Pending queue structure
+ *
+ */
+struct pending_queue {
+	/** Tail of queue to be used for enqueue */
+	uint16_t enq_tail;
+	/** Head of queue to be used for dequeue */
+	uint16_t deq_head;
+	/** Array of pending requests */
+	struct rid *rid_queue;
+	/** Pending requests count */
+	uint64_t pending_count;
+};
+
+#endif /* _CPT_COMMON_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 05/32] crypto/octeontx: add hardware init routine

[Anoob Joseph]

Adding hardware init routine for OCTEON TX crypto device. A place holder
is added for misc polling routine. That will be added in the further
patches.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                  |  1 +
 drivers/crypto/octeontx/meson.build               |  1 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 48 ++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 87 +++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 92 ++++++++++++++++++++++-
 5 files changed, 228 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 12fec75..4582540 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -24,6 +24,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
 
 # PMD code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
 
 # export include files
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index 6564090..eca1cf1 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -8,6 +8,7 @@ deps += ['bus_pci']
 name = 'octeontx_crypto'
 
 sources = files('otx_cryptodev.c',
+		'otx_cryptodev_hw_access.c',
 		'otx_cryptodev_ops.c')
 
 cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
new file mode 100644
index 0000000..99fe3cf
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+#include <string.h>
+
+#include <rte_common.h>
+
+#include "otx_cryptodev_hw_access.h"
+
+#include "cpt_pmd_logs.h"
+
+static int
+otx_cpt_vf_init(struct cpt_vf *cptvf)
+{
+	int ret = 0;
+
+	CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
+
+	return ret;
+}
+
+void
+otx_cpt_poll_misc(struct cpt_vf *cptvf)
+{
+	RTE_SET_USED(cptvf);
+}
+
+int
+otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
+{
+	memset(cptvf, 0, sizeof(struct cpt_vf));
+
+	/* Bar0 base address */
+	cptvf->reg_base = reg_base;
+	strncpy(cptvf->dev_name, name, 32);
+
+	cptvf->pdev = pdev;
+
+	/* To clear if there are any pending mbox msgs */
+	otx_cpt_poll_misc(cptvf);
+
+	if (otx_cpt_vf_init(cptvf)) {
+		CPT_LOG_ERR("Failed to initialize CPT VF device");
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 288ee41..1e1877c 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -5,6 +5,85 @@
 #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
 #define _OTX_CRYPTODEV_HW_ACCESS_H_
 
+#include <stdbool.h>
+
+#include <rte_memory.h>
+
+#include "cpt_common.h"
+
+#define CPT_INTR_POLL_INTERVAL_MS	(50)
+
+/* Default command queue length */
+#define DEFAULT_CMD_QCHUNKS		2
+
+/* cpt instance */
+struct cpt_instance {
+	uint32_t queue_id;
+	uintptr_t rsvd;
+};
+
+struct command_chunk {
+	/** 128-byte aligned real_vaddr */
+	uint8_t *head;
+	/** 128-byte aligned real_dma_addr */
+	phys_addr_t dma_addr;
+};
+
+/**
+ * Command queue structure
+ */
+struct command_queue {
+	/** Command queue host write idx */
+	uint32_t idx;
+	/** Command queue chunk */
+	uint32_t cchunk;
+	/** Command queue head; instructions are inserted here */
+	uint8_t *qhead;
+	/** Command chunk list head */
+	struct command_chunk chead[DEFAULT_CMD_QCHUNKS];
+};
+
+/**
+ * CPT VF device structure
+ */
+struct cpt_vf {
+	/** CPT instance */
+	struct cpt_instance instance;
+	/** Register start address */
+	uint8_t *reg_base;
+	/** Command queue information */
+	struct command_queue cqueue;
+	/** Pending queue information */
+	struct pending_queue pqueue;
+	/** Meta information per vf */
+	struct cptvf_meta_info meta_info;
+
+	/** Below fields are accessed only in control path */
+
+	/** Env specific pdev representing the pci dev */
+	void *pdev;
+	/** Calculated queue size */
+	uint32_t qsize;
+	/** Device index (0...CPT_MAX_VQ_NUM)*/
+	uint8_t  vfid;
+	/** VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
+	uint8_t  vftype;
+	/** VF group (0 - 8) */
+	uint8_t  vfgrp;
+	/** Operating node: Bits (46:44) in BAR0 address */
+	uint8_t  node;
+
+	/** VF-PF mailbox communication */
+
+	/** Flag if acked */
+	bool pf_acked;
+	/** Flag if not acked */
+	bool pf_nacked;
+
+	/** Device name */
+	char dev_name[32];
+} __rte_cache_aligned;
+
 /*
  * CPT Registers map for 81xx
  */
@@ -44,4 +123,12 @@
 					 ((a) & 0x1) + 0x100000ll * (b) + \
 					 8ll * ((c) & 0x1))
 
+/* VF HAL functions */
+
+void
+otx_cpt_poll_misc(struct cpt_vf *cptvf);
+
+int
+otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 1b5f108..3bf6cd2 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -2,14 +2,104 @@
  * Copyright(c) 2018 Cavium, Inc
  */
 
+#include <rte_alarm.h>
+#include <rte_bus_pci.h>
 #include <rte_cryptodev.h>
+#include <rte_malloc.h>
+
+#include "cpt_pmd_logs.h"
 
 #include "otx_cryptodev.h"
+#include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_ops.h"
 
+/* Alarm routines */
+
+static void
+otx_cpt_alarm_cb(void *arg)
+{
+	struct cpt_vf *cptvf = arg;
+	otx_cpt_poll_misc(cptvf);
+	rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,
+			  otx_cpt_alarm_cb, cptvf);
+}
+
+static int
+otx_cpt_periodic_alarm_start(void *arg)
+{
+	return rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,
+				 otx_cpt_alarm_cb, arg);
+}
+
 int
 otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 {
-	RTE_SET_USED(c_dev);
+	struct rte_pci_device *pdev = RTE_DEV_TO_PCI(c_dev->device);
+	struct cpt_vf *cptvf = NULL;
+	void *reg_base;
+	char dev_name[32];
+	int ret;
+
+	if (pdev->mem_resource[0].phys_addr == 0ULL)
+		return -EIO;
+
+	/* for secondary processes, we don't initialise any further as primary
+	 * has already done this work.
+	 */
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	cptvf = rte_zmalloc_socket("otx_cryptodev_private_mem",
+			sizeof(struct cpt_vf), RTE_CACHE_LINE_SIZE,
+			rte_socket_id());
+
+	if (cptvf == NULL) {
+		CPT_LOG_ERR("Cannot allocate memory for device private data");
+		return -ENOMEM;
+	}
+
+	snprintf(dev_name, 32, "%02x:%02x.%x",
+			pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
+
+	reg_base = pdev->mem_resource[0].addr;
+	if (!reg_base) {
+		CPT_LOG_ERR("Failed to map BAR0 of %s", dev_name);
+		ret = -ENODEV;
+		goto fail;
+	}
+
+	ret = otx_cpt_hw_init(cptvf, pdev, reg_base, dev_name);
+	if (ret) {
+		CPT_LOG_ERR("Failed to init cptvf %s", dev_name);
+		ret = -EIO;
+		goto fail;
+	}
+
+	/* Start off timer for mailbox interrupts */
+	otx_cpt_periodic_alarm_start(cptvf);
+
+	c_dev->dev_ops = NULL;
+
+	c_dev->enqueue_burst = NULL;
+	c_dev->dequeue_burst = NULL;
+
+	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+			RTE_CRYPTODEV_FF_HW_ACCELERATED |
+			RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
+			RTE_CRYPTODEV_FF_IN_PLACE_SGL |
+			RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
+			RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
+
+	/* Save dev private data */
+	c_dev->data->dev_private = cptvf;
+
 	return 0;
+
+fail:
+	if (cptvf) {
+		/* Free private data allocated */
+		rte_free(cptvf);
+	}
+
+	return ret;
 }
-- 
2.7.4

[dpdk-dev] [PATCH v3 06/32] common/cpt: add hardware register defines

[Anoob Joseph]

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_hw_types.h | 519 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 519 insertions(+)
 create mode 100644 drivers/common/cpt/cpt_hw_types.h

diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h
new file mode 100644
index 0000000..0a98621
--- /dev/null
+++ b/drivers/common/cpt/cpt_hw_types.h
@@ -0,0 +1,519 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_HW_TYPES_H_
+#define _CPT_HW_TYPES_H_
+
+#include <rte_byteorder.h>
+
+/*
+ * This file defines HRM specific structs.
+ *
+ */
+
+#define CPT_VF_INTR_MBOX_MASK   (1<<0)
+#define CPT_VF_INTR_DOVF_MASK   (1<<1)
+#define CPT_VF_INTR_IRDE_MASK   (1<<2)
+#define CPT_VF_INTR_NWRP_MASK   (1<<3)
+#define CPT_VF_INTR_SWERR_MASK  (1<<4)
+#define CPT_VF_INTR_HWERR_MASK  (1<<5)
+#define CPT_VF_INTR_FAULT_MASK  (1<<6)
+
+/*
+ * CPT_INST_S software command definitions
+ * Words EI (0-3)
+ */
+typedef union {
+	uint64_t u64;
+	struct {
+		uint16_t opcode;
+		uint16_t param1;
+		uint16_t param2;
+		uint16_t dlen;
+	} s;
+} vq_cmd_word0_t;
+
+typedef union {
+	uint64_t u64;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint64_t grp	: 3;
+		uint64_t cptr	: 61;
+#else
+		uint64_t cptr	: 61;
+		uint64_t grp	: 3;
+#endif
+	} s;
+} vq_cmd_word3_t;
+
+typedef struct cpt_vq_command {
+	vq_cmd_word0_t cmd;
+	uint64_t dptr;
+	uint64_t rptr;
+	vq_cmd_word3_t cptr;
+} cpt_vq_cmd_t;
+
+/**
+ * Structure cpt_inst_s
+ *
+ * CPT Instruction Structure
+ * This structure specifies the instruction layout.
+ * Instructions are stored in memory as little-endian unless
+ * CPT()_PF_Q()_CTL[INST_BE] is set.
+ */
+typedef union cpt_inst_s {
+	uint64_t u[8];
+	struct cpt_inst_s_8s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_17_63        : 47;
+		/* [ 16: 16] Done interrupt.
+		 * 0 = No interrupts related to this instruction.
+		 * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]
+		 * will be incremented, and based on the rules described
+		 * there an interrupt may occur.
+		 */
+		uint64_t doneint               : 1;
+		uint64_t reserved_0_15         : 16;
+#else /* Word 0 - Little Endian */
+		uint64_t reserved_0_15         : 16;
+		uint64_t doneint               : 1;
+		uint64_t reserved_17_63        : 47;
+#endif /* Word 0 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
+		/* [127: 64] Result IOVA.
+		 * If nonzero, specifies where to write CPT_RES_S.
+		 * If zero, no result structure will be written.
+		 * Address must be 16-byte aligned.
+		 *
+		 * Bits <63:49> are ignored by hardware; software should
+		 * use a sign-extended bit <48> for forward compatibility.
+		 */
+		uint64_t res_addr              : 64;
+#else /* Word 1 - Little Endian */
+		uint64_t res_addr              : 64;
+#endif /* Word 1 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
+		uint64_t reserved_172_191      : 20;
+		/* [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
+		 * use when CPT submits work to SSO.
+		 * For the SSO to not discard the add-work request, FPA_PF_MAP()
+		 * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
+		 */
+		uint64_t grp                   : 10;
+		/* [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
+		 * when CPT submits work to SSO.
+		 */
+		uint64_t tt                    : 2;
+		/* [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when
+		 * CPT submits work to SSO.
+		 */
+		uint64_t tag                   : 32;
+#else /* Word 2 - Little Endian */
+		uint64_t tag                   : 32;
+		uint64_t tt                    : 2;
+		uint64_t grp                   : 10;
+		uint64_t reserved_172_191      : 20;
+#endif /* Word 2 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
+		/** [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
+		 * work-queue entry that CPT submits work to SSO after all
+		 * context, output data, and result write operations are
+		 * visible to other CNXXXX units and the cores.
+		 * Bits <2:0> must be zero.
+		 * Bits <63:49> are ignored by hardware; software should use a
+		 * sign-extended bit <48> for forward compatibility.
+		 * Internal:Bits <63:49>, <2:0> are ignored by hardware,
+		 * treated as always 0x0.
+		 **/
+		uint64_t wq_ptr                : 64;
+#else /* Word 3 - Little Endian */
+		uint64_t wq_ptr                : 64;
+#endif /* Word 3 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 4 - Big Endian */
+		union {
+			/** [319:256] Engine instruction word 0. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t ei0                   : 64;
+			vq_cmd_word0_t vq_cmd_w0;
+		};
+#else /* Word 4 - Little Endian */
+		union {
+			uint64_t ei0                   : 64;
+			vq_cmd_word0_t vq_cmd_w0;
+		};
+#endif /* Word 4 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 5 - Big Endian */
+		union {
+			/** [383:320] Engine instruction word 1. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t ei1                   : 64;
+			uint64_t dptr;
+		};
+#else /* Word 5 - Little Endian */
+		union {
+			uint64_t ei1                   : 64;
+			uint64_t dptr;
+		};
+#endif /* Word 5 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 6 - Big Endian */
+		union {
+			/** [447:384] Engine instruction word 2. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t ei2                   : 64;
+			uint64_t rptr;
+		};
+#else /* Word 6 - Little Endian */
+		union {
+			uint64_t ei2                   : 64;
+			uint64_t rptr;
+		};
+#endif /* Word 6 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 7 - Big Endian */
+		union {
+			/** [511:448] Engine instruction word 3. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t ei3                   : 64;
+			vq_cmd_word3_t vq_cmd_w3;
+		};
+#else /* Word 7 - Little Endian */
+		union {
+			uint64_t ei3                   : 64;
+			vq_cmd_word3_t vq_cmd_w3;
+		};
+#endif /* Word 7 - End */
+	} s8x;
+} cpt_inst_s_t;
+
+/**
+ * Structure cpt_res_s
+ *
+ * CPT Result Structure
+ * The CPT coprocessor writes the result structure after it completes a
+ * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each
+ * instruction completion produces exactly one result structure.
+ *
+ * This structure is stored in memory as little-endian unless
+ * CPT()_PF_Q()_CTL[INST_BE] is set.
+ */
+typedef union cpt_res_s {
+	uint64_t u[2];
+	struct cpt_res_s_8s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_17_63        : 47;
+		/** [ 16: 16] Done interrupt. This bit is copied from the
+		 * corresponding instruction's CPT_INST_S[DONEINT].
+		 **/
+		uint64_t doneint               : 1;
+		uint64_t reserved_8_15         : 8;
+		/** [  7:  0] Indicates completion/error status of the CPT
+		 * coprocessor for the associated instruction, as enumerated by
+		 * CPT_COMP_E. Core software may write the memory location
+		 * containing [COMPCODE] to 0x0 before ringing the doorbell, and
+		 * then poll for completion by checking for a nonzero value.
+		 *
+		 * Once the core observes a nonzero [COMPCODE] value in this
+		 * case, the CPT coprocessor will have also completed L2/DRAM
+		 * write operations.
+		 **/
+		uint64_t compcode              : 8;
+#else /* Word 0 - Little Endian */
+		uint64_t compcode              : 8;
+		uint64_t reserved_8_15         : 8;
+		uint64_t doneint               : 1;
+		uint64_t reserved_17_63        : 47;
+#endif /* Word 0 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
+		uint64_t reserved_64_127       : 64;
+#else /* Word 1 - Little Endian */
+		uint64_t reserved_64_127       : 64;
+#endif /* Word 1 - End */
+	} s8x;
+} cpt_res_s_t;
+
+/**
+ * Register (NCB) cpt#_vq#_ctl
+ *
+ * CPT VF Queue Control Registers
+ * This register configures queues. This register should be changed (other than
+ * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_ctl_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_1_63         : 63;
+		/** [  0:  0](R/W/H) Enables the logical instruction queue.
+		 * See also CPT()_PF_Q()_CTL[CONT_ERR] and
+		 * CPT()_VQ()_INPROG[INFLIGHT].
+		 * 1 = Queue is enabled.
+		 * 0 = Queue is disabled.
+		 **/
+		uint64_t ena                   : 1;
+#else /* Word 0 - Little Endian */
+		uint64_t ena                   : 1;
+		uint64_t reserved_1_63         : 63;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_ctl_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done
+ *
+ * CPT Queue Done Count Registers
+ * These registers contain the per-queue instruction done count.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		/** [ 19:  0](R/W/H) Done count. When CPT_INST_S[DONEINT] set
+		 * and that instruction completes,CPT()_VQ()_DONE[DONE] is
+		 * incremented when the instruction finishes. Write to this
+		 * field are for diagnostic use only; instead software writes
+		 * CPT()_VQ()_DONE_ACK with the number of decrements for this
+		 * field.
+		 *
+		 * Interrupts are sent as follows:
+		 *
+		 * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,
+		 * the interrupt coalescing timer is held to zero, and an
+		 * interrupt is not sent.
+		 *
+		 * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt
+		 * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE
+		 * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()
+		 * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough
+		 * results have arrived, then the interrupt is sent.  Otherwise,
+		 * it is not sent due to coalescing.
+		 *
+		 * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is
+		 * written but this is not typical), the interrupt coalescing
+		 * timer restarts.  Note after decrementing this interrupt
+		 * equation is recomputed, for example if CPT()_VQ()_DONE[DONE]
+		 * >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is
+		 * zero, the interrupt will be resent immediately.  (This covers
+		 * the race case between software acknowledging an interrupt and
+		 * a result returning.)
+		 *
+		 * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not
+		 * sent, but the counting described above still occurs.
+		 *
+		 * Since CPT instructions complete out-of-order, if software is
+		 * using completion interrupts the suggested scheme is to
+		 * request a DONEINT on each request, and when an interrupt
+		 * arrives perform a "greedy" scan for completions; even if a
+		 * later command is acknowledged first this will not result in
+		 * missing a completion.
+		 *
+		 * Software is responsible for making sure [DONE] does not
+		 * overflow; for example by insuring there are not more than
+		 * 2^20-1 instructions in flight that may request interrupts.
+		 **/
+		uint64_t done                  : 20;
+#else /* Word 0 - Little Endian */
+		uint64_t done                  : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_done_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done_ack
+ *
+ * CPT Queue Done Count Ack Registers
+ * This register is written by software to acknowledge interrupts.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_ack_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		/** [ 19:  0](R/W/H) Number of decrements to CPT()_VQ()_DONE
+		 * [DONE]. Reads CPT()_VQ()_DONE[DONE].
+		 *
+		 * Written by software to acknowledge interrupts. If CPT()_VQ()_
+		 * DONE[DONE] is still nonzero the interrupt will be re-sent if
+		 * the conditions described in CPT()_VQ()_DONE[DONE] are
+		 * satisfied.
+		 **/
+		uint64_t done_ack              : 20;
+#else /* Word 0 - Little Endian */
+		uint64_t done_ack              : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_done_ack_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done_wait
+ *
+ * CPT Queue Done Interrupt Coalescing Wait Registers
+ * Specifies the per queue interrupt coalescing settings.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_wait_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_48_63        : 16;
+		/** [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =
+		 * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When
+		 * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is
+		 * disabled.
+		 **/
+		uint64_t time_wait             : 16;
+		uint64_t reserved_20_31        : 12;
+		/** [ 19:  0](R/W) Number of messages hold-off. When
+		 * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as
+		 * 0x1.
+		 **/
+		uint64_t num_wait              : 20;
+#else /* Word 0 - Little Endian */
+		uint64_t num_wait              : 20;
+		uint64_t reserved_20_31        : 12;
+		uint64_t time_wait             : 16;
+		uint64_t reserved_48_63        : 16;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_done_wait_t;
+
+/**
+ * Register (NCB) cpt#_vq#_doorbell
+ *
+ * CPT Queue Doorbell Registers
+ * Doorbells for the CPT instruction queues.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_doorbell_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		uint64_t dbell_cnt             : 20;
+		/** [ 19:  0](R/W/H) Number of instruction queue 64-bit words
+		 * to add to the CPT instruction doorbell count. Readback value
+		 * is the the current number of pending doorbell requests.
+		 *
+		 * If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.
+		 *
+		 * To reset the count back to zero, write one to clear
+		 * CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value
+		 * of 2^20 minus the read [DBELL_CNT], then write one to
+		 * CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
+		 * CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].
+		 *
+		 * Must be a multiple of 8.  All CPT instructions are 8 words
+		 * and require a doorbell count of multiple of 8.
+		 **/
+#else /* Word 0 - Little Endian */
+		uint64_t dbell_cnt             : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_doorbell_t;
+
+/**
+ * Register (NCB) cpt#_vq#_inprog
+ *
+ * CPT Queue In Progress Count Registers
+ * These registers contain the per-queue instruction in flight registers.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_inprog_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_8_63         : 56;
+		/** [  7:  0](RO/H) Inflight count. Counts the number of
+		 * instructions for the VF for which CPT is fetching, executing
+		 * or responding to instructions. However this does not include
+		 * any interrupts that are awaiting software handling
+		 * (CPT()_VQ()_DONE[DONE] != 0x0).
+		 *
+		 * A queue may not be reconfigured until:
+		 *  1. CPT()_VQ()_CTL[ENA] is cleared by software.
+		 *  2. [INFLIGHT] is polled until equals to zero.
+		 **/
+		uint64_t inflight              : 8;
+#else /* Word 0 - Little Endian */
+		uint64_t inflight              : 8;
+		uint64_t reserved_8_63         : 56;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_inprog_t;
+
+/**
+ * Register (NCB) cpt#_vq#_misc_int
+ *
+ * CPT Queue Misc Interrupt Register
+ * These registers contain the per-queue miscellaneous interrupts.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_misc_int_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_7_63         : 57;
+		/** [  6:  6](R/W1C/H) Translation fault detected. */
+		uint64_t fault		       : 1;
+		/** [  5:  5](R/W1C/H) Hardware error from engines. */
+		uint64_t hwerr		       : 1;
+		/** [  4:  4](R/W1C/H) Software error from engines. */
+		uint64_t swerr                 : 1;
+		/** [  3:  3](R/W1C/H) NCB result write response error. */
+		uint64_t nwrp                  : 1;
+		/** [  2:  2](R/W1C/H) Instruction NCB read response error. */
+		uint64_t irde                  : 1;
+		/** [  1:  1](R/W1C/H) Doorbell overflow. */
+		uint64_t dovf                  : 1;
+		/** [  0:  0](R/W1C/H) PF to VF mailbox interrupt. Set when
+		 * CPT()_VF()_PF_MBOX(0) is written.
+		 **/
+		uint64_t mbox                  : 1;
+#else /* Word 0 - Little Endian */
+		uint64_t mbox                  : 1;
+		uint64_t dovf                  : 1;
+		uint64_t irde                  : 1;
+		uint64_t nwrp                  : 1;
+		uint64_t swerr                 : 1;
+		uint64_t hwerr		       : 1;
+		uint64_t fault		       : 1;
+		uint64_t reserved_5_63         : 59;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_misc_int_t;
+
+/**
+ * Register (NCB) cpt#_vq#_saddr
+ *
+ * CPT Queue Starting Buffer Address Registers
+ * These registers set the instruction buffer starting address.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_saddr_s	{
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_49_63        : 15;
+		/** [ 48:  6](R/W/H) Instruction buffer IOVA <48:6>
+		 * (64-byte aligned). When written, it is the initial buffer
+		 * starting address; when read, it is the next read pointer to
+		 * be requested from L2C. The PTR field is overwritten with the
+		 * next pointer each time that the command buffer segment is
+		 * exhausted. New commands will then be read from the newly
+		 * specified command buffer pointer.
+		 **/
+		uint64_t ptr                   : 43;
+		uint64_t reserved_0_5          : 6;
+#else /* Word 0 - Little Endian */
+		uint64_t reserved_0_5          : 6;
+		uint64_t ptr                   : 43;
+		uint64_t reserved_49_63        : 15;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_saddr_t;
+
+#endif /*_CPT_HW_TYPES_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 07/32] crypto/octeontx: add hardware register access for misc poll

[Anoob Joseph]

Adding hardware register accesses required for misc poll

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 192 +++++++++++++++++++++-
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h |  11 ++
 2 files changed, 202 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index 99fe3cf..369d62b 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -3,11 +3,19 @@
  */
 #include <string.h>
 
+#include <rte_branch_prediction.h>
 #include <rte_common.h>
 
 #include "otx_cryptodev_hw_access.h"
 
 #include "cpt_pmd_logs.h"
+#include "cpt_hw_types.h"
+
+/*
+ * VF HAL functions
+ * Access its own BAR0/4 registers by passing VF number as 0.
+ * OS/PCI maps them accordingly.
+ */
 
 static int
 otx_cpt_vf_init(struct cpt_vf *cptvf)
@@ -19,10 +27,192 @@ otx_cpt_vf_init(struct cpt_vf *cptvf)
 	return ret;
 }
 
+/*
+ * Read Interrupt status of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static uint64_t
+otx_cpt_read_vf_misc_intr_status(struct cpt_vf *cptvf)
+{
+	return CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0));
+}
+
+/*
+ * Clear mailbox interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_mbox_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.mbox = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear instruction NCB read error interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_irde_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.irde = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear NCB result write response error interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_nwrp_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.nwrp = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear swerr interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_swerr_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.swerr = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear hwerr interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_hwerr_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.hwerr = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear translation fault interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_fault_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.fault = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear doorbell overflow interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.dovf = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
 void
 otx_cpt_poll_misc(struct cpt_vf *cptvf)
 {
-	RTE_SET_USED(cptvf);
+	uint64_t intr;
+
+	intr = otx_cpt_read_vf_misc_intr_status(cptvf);
+
+	if (!intr)
+		return;
+
+	/* Check for MISC interrupt types */
+	if (likely(intr & CPT_VF_INTR_MBOX_MASK)) {
+		CPT_LOG_DP_DEBUG("%s: Mailbox interrupt 0x%lx on CPT VF %d",
+			cptvf->dev_name, (unsigned int long)intr, cptvf->vfid);
+		otx_cpt_clear_mbox_intr(cptvf);
+	} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {
+		otx_cpt_clear_irde_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Instruction NCB read error interrupt "
+				"0x%lx on CPT VF %d", cptvf->dev_name,
+				(unsigned int long)intr, cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) {
+		otx_cpt_clear_nwrp_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: NCB response write error interrupt 0x%lx"
+				" on CPT VF %d", cptvf->dev_name,
+				(unsigned int long)intr, cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) {
+		otx_cpt_clear_swerr_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Software error interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) {
+		otx_cpt_clear_hwerr_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Hardware error interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) {
+		otx_cpt_clear_fault_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Translation fault interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_DOVF_MASK)) {
+		otx_cpt_clear_dovf_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Doorbell overflow interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else
+		CPT_LOG_DP_ERR("%s: Unhandled interrupt 0x%lx in CPT VF %d",
+				cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
 }
 
 int
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 1e1877c..73473ed 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -7,6 +7,7 @@
 
 #include <stdbool.h>
 
+#include <rte_io.h>
 #include <rte_memory.h>
 
 #include "cpt_common.h"
@@ -16,6 +17,16 @@
 /* Default command queue length */
 #define DEFAULT_CMD_QCHUNKS		2
 
+#define CPT_CSR_REG_BASE(cpt)		((cpt)->reg_base)
+
+/* Read hw register */
+#define CPT_READ_CSR(__hw_addr, __offset) \
+	rte_read64_relaxed((uint8_t *)__hw_addr + __offset)
+
+/* Write hw register */
+#define CPT_WRITE_CSR(__hw_addr, __offset, __val) \
+	rte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))
+
 /* cpt instance */
 struct cpt_instance {
 	uint32_t queue_id;
-- 
2.7.4

[dpdk-dev] [PATCH v3 08/32] crypto/octeontx: adds symmetric capabilities

[Anoob Joseph]

This patch adds the symmetric algorithms capabilities
supported by octeontx crypto hardware.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                   |   1 +
 drivers/crypto/octeontx/meson.build                |   1 +
 .../crypto/octeontx/otx_cryptodev_capabilities.c   | 604 +++++++++++++++++++++
 .../crypto/octeontx/otx_cryptodev_capabilities.h   |  17 +
 4 files changed, 623 insertions(+)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.h

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 4582540..d755441 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -24,6 +24,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
 
 # PMD code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_capabilities.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
 
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index eca1cf1..4c5a40c 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -8,6 +8,7 @@ deps += ['bus_pci']
 name = 'octeontx_crypto'
 
 sources = files('otx_cryptodev.c',
+		'otx_cryptodev_capabilities.c',
 		'otx_cryptodev_hw_access.c',
 		'otx_cryptodev_ops.c')
 
diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.c b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
new file mode 100644
index 0000000..946571c
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
@@ -0,0 +1,604 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_cryptodev.h>
+
+#include "otx_cryptodev_capabilities.h"
+
+static const struct rte_cryptodev_capabilities otx_capabilities[] = {
+	/* Symmetric capabilities */
+	{	/* NULL (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+			}, },
+		}, },
+	},
+	{	/* AES GMAC (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_AES_GMAC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 12,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* KASUMI (F9) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_KASUMI_F9,
+				.block_size = 8,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+			}, }
+		}, }
+	},
+	{	/* MD5 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_MD5,
+				.block_size = 64,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 16,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* MD5 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 8,
+					.max = 64,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 16,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA1 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA1,
+				.block_size = 64,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 20,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA1 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 20,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA224 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA224,
+				.block_size = 64,
+					.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 28,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA224 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
+				.block_size = 64,
+					.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 28,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA256 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA256,
+				.block_size = 64,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 32,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA256 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 32,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA384 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA384,
+				.block_size = 64,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 48,
+					.increment = 1
+					},
+			}, }
+		}, }
+	},
+	{	/* SHA384 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 48,
+					.increment = 1
+					},
+			}, }
+		}, }
+	},
+	{	/* SHA512 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA512,
+				.block_size = 128,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 64,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA512 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
+				.block_size = 128,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 64,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SNOW 3G (UIA2) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* ZUC (EIA3) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* NULL (CIPHER) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				}
+			}, },
+		}, }
+	},
+	{	/* 3DES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+				.block_size = 8,
+				.key_size = {
+					.min = 24,
+					.max = 24,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 8
+				}
+			}, }
+		}, }
+	},
+	{	/* 3DES ECB */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_3DES_ECB,
+				.block_size = 8,
+				.key_size = {
+					.min = 24,
+					.max = 24,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CBC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES CTR */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CTR,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 16,
+					.increment = 4
+				}
+			}, }
+		}, }
+	},
+	{	/* AES XTS */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_XTS,
+				.block_size = 16,
+				.key_size = {
+					.min = 32,
+					.max = 64,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* DES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_DES_CBC,
+				.block_size = 8,
+				.key_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* KASUMI (F8) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
+				.block_size = 8,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* SNOW 3G (UEA2) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* ZUC (EEA3) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES GCM */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+			{.aead = {
+				.algo = RTE_CRYPTO_AEAD_AES_GCM,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
+				},
+				.aad_size = {
+					.min = 0,
+					.max = 1024,
+					.increment = 1
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 12,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	/* End of symmetric capabilities */
+	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+const struct rte_cryptodev_capabilities *
+otx_get_capabilities(void)
+{
+	return otx_capabilities;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
new file mode 100644
index 0000000..fc62821
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_CAPABILITIES_H_
+#define _OTX_CRYPTODEV_CAPABILITIES_H_
+
+#include <rte_cryptodev.h>
+
+/*
+ * Get capabilities list for the device
+ *
+ */
+const struct rte_cryptodev_capabilities *
+otx_get_capabilities(void);
+
+#endif /* _OTX_CRYPTODEV_CAPABILITIES_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 09/32] common/cpt: add PMD ops helper functions

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding pmd ops helper functions. Control path accessed APIs would be
added as helper functions. Adding microcode defined macros etc as
dependencies to the helper functions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/Makefile                       |  4 +++
 drivers/common/cpt/Makefile                   | 25 ++++++++++++++++
 drivers/common/cpt/cpt_common.h               | 36 +++++++++++++++++++++++
 drivers/common/cpt/cpt_mcode_defines.h        | 38 +++++++++++++++++++++++++
 drivers/common/cpt/cpt_pmd_ops_helper.c       | 41 +++++++++++++++++++++++++++
 drivers/common/cpt/cpt_pmd_ops_helper.h       | 34 ++++++++++++++++++++++
 drivers/common/cpt/meson.build                |  8 ++++++
 drivers/common/cpt/rte_common_cpt_version.map |  6 ++++
 drivers/common/meson.build                    |  2 +-
 mk/rte.app.mk                                 |  4 +++
 10 files changed, 197 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cpt/Makefile
 create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
 create mode 100644 drivers/common/cpt/meson.build
 create mode 100644 drivers/common/cpt/rte_common_cpt_version.map

diff --git a/drivers/common/Makefile b/drivers/common/Makefile
index 5bcff17..29a8f6d 100644
--- a/drivers/common/Makefile
+++ b/drivers/common/Makefile
@@ -4,6 +4,10 @@
 
 include $(RTE_SDK)/mk/rte.vars.mk
 
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+DIRS-y += cpt
+endif
+
 ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL),yy)
 DIRS-y += octeontx
 endif
diff --git a/drivers/common/cpt/Makefile b/drivers/common/cpt/Makefile
new file mode 100644
index 0000000..2340aa9
--- /dev/null
+++ b/drivers/common/cpt/Makefile
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_common_cpt.a
+
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
+EXPORT_MAP := rte_common_cpt_version.map
+
+LIBABIVER := 1
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-y += cpt_pmd_ops_helper.c
+
+LDLIBS += -lrte_eal
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 5e2099a..88f4902 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -18,6 +18,24 @@
 #define AE_TYPE 1
 #define SE_TYPE 2
 
+#ifndef ROUNDUP4
+#define ROUNDUP4(val)	(((val) + 3) & 0xfffffffc)
+#endif
+
+#ifndef ROUNDUP8
+#define ROUNDUP8(val)	(((val) + 7) & 0xfffffff8)
+#endif
+
+#ifndef ROUNDUP16
+#define ROUNDUP16(val)	(((val) + 15) & 0xfffffff0)
+#endif
+
+#ifndef __hot
+#define __hot __attribute__((hot))
+#endif
+
+#define MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
+
 struct cptvf_meta_info {
 	void *cptvf_meta_pool;
 	int cptvf_op_mlen;
@@ -44,4 +62,22 @@ struct pending_queue {
 	uint64_t pending_count;
 };
 
+struct cpt_request_info {
+	/** Data path fields */
+	uint64_t comp_baddr;
+	volatile uint64_t *completion_addr;
+	volatile uint64_t *alternate_caddr;
+	void *op;
+	struct {
+		uint64_t ei0;
+		uint64_t ei1;
+		uint64_t ei2;
+		uint64_t ei3;
+	} ist;
+
+	/** Control path fields */
+	uint64_t time_out;
+	uint8_t extra_time;
+};
+
 #endif /* _CPT_COMMON_H_ */
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
new file mode 100644
index 0000000..83a8a42
--- /dev/null
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_MCODE_DEFINES_H_
+#define _CPT_MCODE_DEFINES_H_
+
+/*
+ * This file defines macros and structures according to microcode spec
+ *
+ */
+
+#define CPT_BYTE_16		16
+#define CPT_BYTE_24		24
+#define CPT_BYTE_32		32
+#define CPT_MAX_SG_IN_OUT_CNT	32
+#define CPT_MAX_SG_CNT		(CPT_MAX_SG_IN_OUT_CNT/2)
+
+#define COMPLETION_CODE_SIZE	8
+#define COMPLETION_CODE_INIT	0
+
+#define SG_LIST_HDR_SIZE	(8u)
+#define SG_ENTRY_SIZE		sizeof(sg_comp_t)
+
+/* #define CPT_ALWAYS_USE_SG_MODE */
+#define CPT_ALWAYS_USE_SEPARATE_BUF
+
+typedef struct sglist_comp {
+	union {
+		uint64_t len;
+		struct {
+			uint16_t len[4];
+		} s;
+	} u;
+	uint64_t ptr[4];
+} sg_comp_t;
+
+#endif /* _CPT_MCODE_DEFINES_H_ */
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.c b/drivers/common/cpt/cpt_pmd_ops_helper.c
new file mode 100644
index 0000000..1c18180
--- /dev/null
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_common.h>
+
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
+#include "cpt_mcode_defines.h"
+#include "cpt_pmd_ops_helper.h"
+
+#define CPT_MAX_IV_LEN 16
+#define CPT_OFFSET_CONTROL_BYTES 8
+
+int32_t
+cpt_pmd_ops_helper_get_mlen_direct_mode(void)
+{
+	uint32_t len = 0;
+
+	/* Request structure */
+	len = sizeof(struct cpt_request_info);
+
+	/* CPT HW result structure plus extra as it is aligned */
+	len += 2*sizeof(cpt_res_s_t);
+
+	return len;
+}
+
+int
+cpt_pmd_ops_helper_get_mlen_sg_mode(void)
+{
+	uint32_t len = 0;
+
+	len += sizeof(struct cpt_request_info);
+	len += CPT_OFFSET_CONTROL_BYTES + CPT_MAX_IV_LEN;
+	len += ROUNDUP8(SG_LIST_HDR_SIZE +
+			(ROUNDUP4(CPT_MAX_SG_IN_OUT_CNT) >> 2) * SG_ENTRY_SIZE);
+	len += 2 * COMPLETION_CODE_SIZE;
+	len += 2 * sizeof(cpt_res_s_t);
+	return len;
+}
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.h b/drivers/common/cpt/cpt_pmd_ops_helper.h
new file mode 100644
index 0000000..dd32f9a
--- /dev/null
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_PMD_OPS_HELPER_H_
+#define _CPT_PMD_OPS_HELPER_H_
+
+/*
+ * This file defines the agreement between the common layer and the individual
+ * crypto drivers for OCTEON TX series. Control path in otx* directory can
+ * directly call functions declared here.
+ */
+
+/*
+ * Get meta length required when operating in direct mode (single buffer
+ * in-place)
+ *
+ * @return
+ *   - length
+ */
+
+int32_t
+cpt_pmd_ops_helper_get_mlen_direct_mode(void);
+
+/*
+ * Get size of contiguous meta buffer to be allocated when working in scatter
+ * gather mode.
+ *
+ * @return
+ *   - length
+ */
+int
+cpt_pmd_ops_helper_get_mlen_sg_mode(void);
+#endif /* _CPT_PMD_OPS_HELPER_H_ */
diff --git a/drivers/common/cpt/meson.build b/drivers/common/cpt/meson.build
new file mode 100644
index 0000000..0a905aa
--- /dev/null
+++ b/drivers/common/cpt/meson.build
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+
+sources = files('cpt_pmd_ops_helper.c')
+
+deps = ['kvargs', 'pci', 'cryptodev']
+includes += include_directories('../../crypto/octeontx')
+allow_experimental_apis = true
diff --git a/drivers/common/cpt/rte_common_cpt_version.map b/drivers/common/cpt/rte_common_cpt_version.map
new file mode 100644
index 0000000..dec614f
--- /dev/null
+++ b/drivers/common/cpt/rte_common_cpt_version.map
@@ -0,0 +1,6 @@
+DPDK_18.11 {
+	global:
+
+	cpt_pmd_ops_helper_get_mlen_direct_mode;
+	cpt_pmd_ops_helper_get_mlen_sg_mode;
+};
diff --git a/drivers/common/meson.build b/drivers/common/meson.build
index f828ce7..dd14f85 100644
--- a/drivers/common/meson.build
+++ b/drivers/common/meson.build
@@ -2,6 +2,6 @@
 # Copyright(c) 2018 Cavium, Inc
 
 std_deps = ['eal']
-drivers = ['mvep', 'octeontx', 'qat']
+drivers = ['cpt', 'mvep', 'octeontx', 'qat']
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 driver_name_fmt = 'rte_common_@0@'
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 248fce6..f4172b3 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -94,6 +94,10 @@ ifeq ($(CONFIG_RTE_EXEC_ENV_LINUXAPP),y)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_KNI)            += -lrte_kni
 endif
 
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+_LDLIBS-y += -lrte_common_cpt
+endif
+
 ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL),yy)
 _LDLIBS-y += -lrte_common_octeontx
 endif
-- 
2.7.4

[dpdk-dev] [PATCH v3 10/32] crypto/octeontx: add global resource init

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding initialization of global resources. This will be saved as
metadata in cptvf and would be used by common code. Exit path for
failure case is also added along with the new routines.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                  |  1 +
 drivers/crypto/octeontx/meson.build               |  3 +-
 drivers/crypto/octeontx/otx_cryptodev.c           |  3 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 11 +++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h |  3 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 90 +++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.h       |  3 +
 7 files changed, 113 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index d755441..1808244 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -16,6 +16,7 @@ CFLAGS += $(WERROR_FLAGS)
 LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
 LDLIBS += -lrte_cryptodev
 LDLIBS += -lrte_pci -lrte_bus_pci
+LDLIBS += -lrte_common_cpt
 
 VPATH += $(RTE_SDK)/drivers/crypto/octeontx
 
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index 4c5a40c..7f65476 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -5,6 +5,7 @@ if host_machine.system() != 'linux'
 endif
 
 deps += ['bus_pci']
+deps += ['common_cpt']
 name = 'octeontx_crypto'
 
 sources = files('otx_cryptodev.c',
@@ -12,5 +13,5 @@ sources = files('otx_cryptodev.c',
 		'otx_cryptodev_hw_access.c',
 		'otx_cryptodev_ops.c')
 
-cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
 includes += include_directories('../../common/cpt')
+cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c
index 43933dd..269f045 100644
--- a/drivers/crypto/octeontx/otx_cryptodev.c
+++ b/drivers/crypto/octeontx/otx_cryptodev.c
@@ -104,6 +104,9 @@ otx_cpt_pci_remove(struct rte_pci_device *pci_dev)
 	cryptodev->device->driver = NULL;
 	cryptodev->data = NULL;
 
+	/* free metapool memory */
+	cleanup_global_resources();
+
 	return 0;
 }
 
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index 369d62b..e8a2b0b 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -236,3 +236,14 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
 
 	return 0;
 }
+
+int
+otx_cpt_deinit_device(void *dev)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	/* Do misc work one last time */
+	otx_cpt_poll_misc(cptvf);
+
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 73473ed..6e5731a 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -142,4 +142,7 @@ otx_cpt_poll_misc(struct cpt_vf *cptvf);
 int
 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
 
+int
+otx_cpt_deinit_device(void *dev);
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 3bf6cd2..68c6b92 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -8,11 +8,69 @@
 #include <rte_malloc.h>
 
 #include "cpt_pmd_logs.h"
+#include "cpt_pmd_ops_helper.h"
 
 #include "otx_cryptodev.h"
 #include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_ops.h"
 
+static int otx_cryptodev_probe_count;
+static rte_spinlock_t otx_probe_count_lock = RTE_SPINLOCK_INITIALIZER;
+
+static struct rte_mempool *otx_cpt_meta_pool;
+static int otx_cpt_op_mlen;
+static int otx_cpt_op_sb_mlen;
+
+/*
+ * Initializes global variables used by fast-path code
+ *
+ * @return
+ *   - 0 on success, errcode on error
+ */
+static int
+init_global_resources(void)
+{
+	/* Get meta len for scatter gather mode */
+	otx_cpt_op_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+
+	/* Extra 4B saved for future considerations */
+	otx_cpt_op_mlen += 4 * sizeof(uint64_t);
+
+	otx_cpt_meta_pool = rte_mempool_create("cpt_metabuf-pool", 4096 * 16,
+					       otx_cpt_op_mlen, 512, 0,
+					       NULL, NULL, NULL, NULL,
+					       SOCKET_ID_ANY, 0);
+	if (!otx_cpt_meta_pool) {
+		CPT_LOG_ERR("cpt metabuf pool not created");
+		return -ENOMEM;
+	}
+
+	/* Get meta len for direct mode */
+	otx_cpt_op_sb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+	/* Extra 4B saved for future considerations */
+	otx_cpt_op_sb_mlen += 4 * sizeof(uint64_t);
+
+	return 0;
+}
+
+void
+cleanup_global_resources(void)
+{
+	/* Take lock */
+	rte_spinlock_lock(&otx_probe_count_lock);
+
+	/* Decrement the cryptodev count */
+	otx_cryptodev_probe_count--;
+
+	/* Free buffers */
+	if (otx_cpt_meta_pool && otx_cryptodev_probe_count == 0)
+		rte_mempool_free(otx_cpt_meta_pool);
+
+	/* Free lock */
+	rte_spinlock_unlock(&otx_probe_count_lock);
+}
+
 /* Alarm routines */
 
 static void
@@ -31,6 +89,20 @@ otx_cpt_periodic_alarm_start(void *arg)
 				 otx_cpt_alarm_cb, arg);
 }
 
+static int
+otx_cpt_periodic_alarm_stop(void *arg)
+{
+	return rte_eal_alarm_cancel(otx_cpt_alarm_cb, arg);
+}
+
+static void
+otx_cpt_common_vars_init(struct cpt_vf *cptvf)
+{
+	cptvf->meta_info.cptvf_meta_pool = otx_cpt_meta_pool;
+	cptvf->meta_info.cptvf_op_mlen = otx_cpt_op_mlen;
+	cptvf->meta_info.cptvf_op_sb_mlen = otx_cpt_op_sb_mlen;
+}
+
 int
 otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 {
@@ -78,6 +150,20 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	/* Start off timer for mailbox interrupts */
 	otx_cpt_periodic_alarm_start(cptvf);
 
+	rte_spinlock_lock(&otx_probe_count_lock);
+	if (!otx_cryptodev_probe_count) {
+		ret = init_global_resources();
+		if (ret) {
+			rte_spinlock_unlock(&otx_probe_count_lock);
+			goto init_fail;
+		}
+	}
+	otx_cryptodev_probe_count++;
+	rte_spinlock_unlock(&otx_probe_count_lock);
+
+	/* Initialize data path variables used by common code */
+	otx_cpt_common_vars_init(cptvf);
+
 	c_dev->dev_ops = NULL;
 
 	c_dev->enqueue_burst = NULL;
@@ -95,6 +181,10 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 
 	return 0;
 
+init_fail:
+	otx_cpt_periodic_alarm_stop(cptvf);
+	otx_cpt_deinit_device(cptvf);
+
 fail:
 	if (cptvf) {
 		/* Free private data allocated */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
index 3f2d829..ac88fa5 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -5,6 +5,9 @@
 #ifndef _OTX_CRYPTODEV_OPS_H_
 #define _OTX_CRYPTODEV_OPS_H_
 
+void
+cleanup_global_resources(void);
+
 int
 otx_cpt_dev_create(struct rte_cryptodev *c_dev);
 
-- 
2.7.4

[dpdk-dev] [PATCH v3 11/32] crypto/octeontx: add mailbox routines

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding mailbox routines to interact with the pf driver

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                  |   1 +
 drivers/crypto/octeontx/meson.build               |   1 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c |  13 ++
 drivers/crypto/octeontx/otx_cryptodev_mbox.c      | 178 ++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_mbox.h      |  92 +++++++++++
 5 files changed, 285 insertions(+)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 1808244..2e78e69 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -27,6 +27,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_capabilities.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_mbox.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
 
 # export include files
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index 7f65476..6511b40 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -11,6 +11,7 @@ name = 'octeontx_crypto'
 sources = files('otx_cryptodev.c',
 		'otx_cryptodev_capabilities.c',
 		'otx_cryptodev_hw_access.c',
+		'otx_cryptodev_mbox.c',
 		'otx_cryptodev_ops.c')
 
 includes += include_directories('../../common/cpt')
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index e8a2b0b..eb9fbcf 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -7,6 +7,7 @@
 #include <rte_common.h>
 
 #include "otx_cryptodev_hw_access.h"
+#include "otx_cryptodev_mbox.h"
 
 #include "cpt_pmd_logs.h"
 #include "cpt_hw_types.h"
@@ -22,8 +23,19 @@ otx_cpt_vf_init(struct cpt_vf *cptvf)
 {
 	int ret = 0;
 
+	/* Check ready with PF */
+	/* Gets chip ID / device Id from PF if ready */
+	ret = otx_cpt_check_pf_ready(cptvf);
+	if (ret) {
+		CPT_LOG_ERR("%s: PF not responding to READY msg",
+				cptvf->dev_name);
+		ret = -EBUSY;
+		goto exit;
+	}
+
 	CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
 
+exit:
 	return ret;
 }
 
@@ -178,6 +190,7 @@ otx_cpt_poll_misc(struct cpt_vf *cptvf)
 	if (likely(intr & CPT_VF_INTR_MBOX_MASK)) {
 		CPT_LOG_DP_DEBUG("%s: Mailbox interrupt 0x%lx on CPT VF %d",
 			cptvf->dev_name, (unsigned int long)intr, cptvf->vfid);
+		otx_cpt_handle_mbox_intr(cptvf);
 		otx_cpt_clear_mbox_intr(cptvf);
 	} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {
 		otx_cpt_clear_irde_intr(cptvf);
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.c b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
new file mode 100644
index 0000000..a8e51a8
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <unistd.h>
+
+#include "otx_cryptodev_hw_access.h"
+#include "otx_cryptodev_mbox.h"
+
+void
+otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	/*
+	 * MBOX[0] contains msg
+	 * MBOX[1] contains data
+	 */
+	mbx.msg  = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VFX_PF_MBOXX(0, 0, 0));
+	mbx.data = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VFX_PF_MBOXX(0, 0, 1));
+
+	CPT_LOG_DP_DEBUG("%s: Mailbox msg 0x%lx from PF",
+		    cptvf->dev_name, (unsigned int long)mbx.msg);
+	switch (mbx.msg) {
+	case OTX_CPT_MSG_READY:
+		{
+			otx_cpt_chipid_vfid_t cid;
+
+			cid.u64 = mbx.data;
+			cptvf->pf_acked = true;
+			cptvf->vfid = cid.s.vfid;
+			CPT_LOG_DP_DEBUG("%s: Received VFID %d chip_id %d",
+					 cptvf->dev_name,
+					 cptvf->vfid, cid.s.chip_id);
+		}
+		break;
+	case OTX_CPT_MSG_QBIND_GRP:
+		cptvf->pf_acked = true;
+		cptvf->vftype = mbx.data;
+		CPT_LOG_DP_DEBUG("%s: VF %d type %s group %d",
+				 cptvf->dev_name, cptvf->vfid,
+				 ((mbx.data == SE_TYPE) ? "SE" : "AE"),
+				 cptvf->vfgrp);
+		break;
+	case OTX_CPT_MBOX_MSG_TYPE_ACK:
+		cptvf->pf_acked = true;
+		break;
+	case OTX_CPT_MBOX_MSG_TYPE_NACK:
+		cptvf->pf_nacked = true;
+		break;
+	default:
+		CPT_LOG_DP_DEBUG("%s: Invalid msg from PF, msg 0x%lx",
+				 cptvf->dev_name, (unsigned int long)mbx.msg);
+		break;
+	}
+}
+
+/* Send a mailbox message to PF
+ * @vf: vf from which this message to be sent
+ * @mbx: Message to be sent
+ */
+static void
+otx_cpt_send_msg_to_pf(struct cpt_vf *cptvf, struct cpt_mbox *mbx)
+{
+	/* Writing mbox(1) causes interrupt */
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VFX_PF_MBOXX(0, 0, 0), mbx->msg);
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VFX_PF_MBOXX(0, 0, 1), mbx->data);
+}
+
+static int32_t
+otx_cpt_send_msg_to_pf_timeout(struct cpt_vf *cptvf, struct cpt_mbox *mbx)
+{
+	int timeout = OTX_CPT_MBOX_MSG_TIMEOUT;
+	int sleep_ms = 10;
+
+	cptvf->pf_acked = false;
+	cptvf->pf_nacked = false;
+
+	otx_cpt_send_msg_to_pf(cptvf, mbx);
+
+	/* Wait for previous message to be acked, timeout 2sec */
+	while (!cptvf->pf_acked) {
+		if (cptvf->pf_nacked)
+			return -EINVAL;
+		usleep(sleep_ms * 1000);
+		otx_cpt_poll_misc(cptvf);
+		if (cptvf->pf_acked)
+			break;
+		timeout -= sleep_ms;
+		if (!timeout) {
+			CPT_LOG_ERR("%s: PF didn't ack mbox msg %lx(vfid %u)",
+				    cptvf->dev_name,
+				    (unsigned int long)(mbx->msg & 0xFF),
+				    cptvf->vfid);
+			return -EBUSY;
+		}
+	}
+	return 0;
+}
+
+int
+otx_cpt_check_pf_ready(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_READY;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to READY msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_QLEN;
+
+	mbx.data = cptvf->qsize;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to vq_size msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vf_grp_msg(struct cpt_vf *cptvf, uint32_t group)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_QBIND_GRP;
+
+	/* Convey group of the VF */
+	mbx.data = group;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to vf_type msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vf_up(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_VF_UP;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to UP msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vf_down(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_VF_DOWN;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to DOWN msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.h b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
new file mode 100644
index 0000000..b05d1c5
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_MBOX_H_
+#define _OTX_CRYPTODEV_MBOX_H_
+
+#include <rte_byteorder.h>
+#include <rte_common.h>
+
+#include "cpt_common.h"
+#include "cpt_pmd_logs.h"
+
+#include "otx_cryptodev_hw_access.h"
+
+#define OTX_CPT_MBOX_MSG_TIMEOUT    2000 /* In Milli Seconds */
+
+#define OTX_CPT_MBOX_MSG_TYPE_REQ	0
+#define OTX_CPT_MBOX_MSG_TYPE_ACK	1
+#define OTX_CPT_MBOX_MSG_TYPE_NACK	2
+#define OTX_CPT_MBOX_MSG_TYPE_NOP	3
+
+/* CPT mailbox structure */
+struct cpt_mbox {
+	/** Message type MBOX[0] */
+	uint64_t msg;
+	/** Data         MBOX[1] */
+	uint64_t data;
+};
+
+typedef enum {
+	OTX_CPT_MSG_VF_UP = 1,
+	OTX_CPT_MSG_VF_DOWN,
+	OTX_CPT_MSG_READY,
+	OTX_CPT_MSG_QLEN,
+	OTX_CPT_MSG_QBIND_GRP,
+	OTX_CPT_MSG_VQ_PRIORITY,
+	OTX_CPT_MSG_PF_TYPE,
+} otx_cpt_mbox_opcode_t;
+
+typedef union {
+	uint64_t u64;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint32_t chip_id;
+		uint8_t vfid;
+		uint8_t reserved[3];
+#else
+		uint8_t reserved[3];
+		uint8_t vfid;
+		uint32_t chip_id;
+#endif
+	} s;
+} otx_cpt_chipid_vfid_t;
+
+/* Poll handler to handle mailbox messages from VFs */
+void
+otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf);
+
+/*
+ * Checks if VF is able to comminicate with PF
+ * and also gets the CPT number this VF is associated to.
+ */
+int
+otx_cpt_check_pf_ready(struct cpt_vf *cptvf);
+
+/*
+ * Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF.
+ * Must be ACKed.
+ */
+int
+otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf);
+
+/*
+ * Communicate VF group required to PF and get the VQ binded to that group
+ */
+int
+otx_cpt_send_vf_grp_msg(struct cpt_vf *cptvf, uint32_t group);
+
+/*
+ * Communicate to PF that VF is UP and running
+ */
+int
+otx_cpt_send_vf_up(struct cpt_vf *cptvf);
+
+/*
+ * Communicate to PF that VF is DOWN and running
+ */
+int
+otx_cpt_send_vf_down(struct cpt_vf *cptvf);
+
+#endif /* _OTX_CRYPTODEV_MBOX_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 12/32] crypto/octeontx: add basic dev ops

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding the following dev ops,
- dev_configure
- dev_start
- dev_stop
- dev_close
- dev_infos_get
- stats_get
- stats_reset

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 56 +++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 30 +++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 95 ++++++++++++++++++++++-
 drivers/crypto/octeontx/otx_cryptodev_ops.h       |  4 +
 4 files changed, 184 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index eb9fbcf..303bcc0 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2018 Cavium, Inc
  */
 #include <string.h>
+#include <unistd.h>
 
 #include <rte_branch_prediction.h>
 #include <rte_common.h>
@@ -260,3 +261,58 @@ otx_cpt_deinit_device(void *dev)
 
 	return 0;
 }
+
+int
+otx_cpt_start_device(void *dev)
+{
+	int rc;
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	rc = otx_cpt_send_vf_up(cptvf);
+	if (rc) {
+		CPT_LOG_ERR("Failed to mark CPT VF device %s UP, rc = %d",
+			    cptvf->dev_name, rc);
+		return -EFAULT;
+	}
+
+	if ((cptvf->vftype != SE_TYPE) && (cptvf->vftype != AE_TYPE)) {
+		CPT_LOG_ERR("Fatal error, unexpected vf type %u, for CPT VF "
+			    "device %s", cptvf->vftype, cptvf->dev_name);
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+void
+otx_cpt_stop_device(void *dev)
+{
+	int rc;
+	uint32_t pending, retries = 5;
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	/* Wait for pending entries to complete */
+	pending = otx_cpt_read_vq_doorbell(cptvf);
+	while (pending) {
+		CPT_LOG_DP_DEBUG("%s: Waiting for pending %u cmds to complete",
+				 cptvf->dev_name, pending);
+		sleep(1);
+		pending = otx_cpt_read_vq_doorbell(cptvf);
+		retries--;
+		if (!retries)
+			break;
+	}
+
+	if (!retries && pending) {
+		CPT_LOG_ERR("%s: Timeout waiting for commands(%u)",
+			    cptvf->dev_name, pending);
+		return;
+	}
+
+	rc = otx_cpt_send_vf_down(cptvf);
+	if (rc) {
+		CPT_LOG_ERR("Failed to bring down vf %s, rc %d",
+			    cptvf->dev_name, rc);
+		return;
+	}
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 6e5731a..b795983 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -11,6 +11,7 @@
 #include <rte_memory.h>
 
 #include "cpt_common.h"
+#include "cpt_hw_types.h"
 
 #define CPT_INTR_POLL_INTERVAL_MS	(50)
 
@@ -145,4 +146,33 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
 int
 otx_cpt_deinit_device(void *dev);
 
+int
+otx_cpt_start_device(void *cptvf);
+
+void
+otx_cpt_stop_device(void *cptvf);
+
+/* Write to VQX_DOORBELL register
+ */
+static __rte_always_inline void
+otx_cpt_write_vq_doorbell(struct cpt_vf *cptvf, uint32_t val)
+{
+	cptx_vqx_doorbell_t vqx_dbell;
+
+	vqx_dbell.u = 0;
+	vqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DOORBELL(0, 0), vqx_dbell.u);
+}
+
+static __rte_always_inline uint32_t
+otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
+{
+	cptx_vqx_doorbell_t vqx_dbell;
+
+	vqx_dbell.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DOORBELL(0, 0));
+	return vqx_dbell.s.dbell_cnt;
+}
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 68c6b92..905b37a 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -5,12 +5,14 @@
 #include <rte_alarm.h>
 #include <rte_bus_pci.h>
 #include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
 #include <rte_malloc.h>
 
 #include "cpt_pmd_logs.h"
 #include "cpt_pmd_ops_helper.h"
 
 #include "otx_cryptodev.h"
+#include "otx_cryptodev_capabilities.h"
 #include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_ops.h"
 
@@ -95,6 +97,97 @@ otx_cpt_periodic_alarm_stop(void *arg)
 	return rte_eal_alarm_cancel(otx_cpt_alarm_cb, arg);
 }
 
+/* PMD ops */
+
+static int
+otx_cpt_dev_config(struct rte_cryptodev *dev __rte_unused,
+		   struct rte_cryptodev_config *config __rte_unused)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+	return 0;
+}
+
+static int
+otx_cpt_dev_start(struct rte_cryptodev *c_dev)
+{
+	void *cptvf = c_dev->data->dev_private;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	return otx_cpt_start_device(cptvf);
+}
+
+static void
+otx_cpt_dev_stop(struct rte_cryptodev *c_dev)
+{
+	void *cptvf = c_dev->data->dev_private;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	otx_cpt_stop_device(cptvf);
+}
+
+static int
+otx_cpt_dev_close(struct rte_cryptodev *c_dev)
+{
+	void *cptvf = c_dev->data->dev_private;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	otx_cpt_periodic_alarm_stop(cptvf);
+	otx_cpt_deinit_device(cptvf);
+
+	return 0;
+}
+
+static void
+otx_cpt_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+	if (info != NULL) {
+		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
+		info->feature_flags = dev->feature_flags;
+		info->capabilities = otx_get_capabilities();
+		info->sym.max_nb_sessions = 0;
+		info->driver_id = otx_cryptodev_driver_id;
+		info->min_mbuf_headroom_req = OTX_CPT_MIN_HEADROOM_REQ;
+		info->min_mbuf_tailroom_req = OTX_CPT_MIN_TAILROOM_REQ;
+	}
+}
+
+static void
+otx_cpt_stats_get(struct rte_cryptodev *dev __rte_unused,
+		  struct rte_cryptodev_stats *stats __rte_unused)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+}
+
+static void
+otx_cpt_stats_reset(struct rte_cryptodev *dev __rte_unused)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+}
+
+static struct rte_cryptodev_ops cptvf_ops = {
+	/* Device related operations */
+	.dev_configure = otx_cpt_dev_config,
+	.dev_start = otx_cpt_dev_start,
+	.dev_stop = otx_cpt_dev_stop,
+	.dev_close = otx_cpt_dev_close,
+	.dev_infos_get = otx_cpt_dev_info_get,
+
+	.stats_get = otx_cpt_stats_get,
+	.stats_reset = otx_cpt_stats_reset,
+	.queue_pair_setup = NULL,
+	.queue_pair_release = NULL,
+	.queue_pair_count = NULL,
+
+	/* Crypto related operations */
+	.sym_session_get_size = NULL,
+	.sym_session_configure = NULL,
+	.sym_session_clear = NULL
+};
+
 static void
 otx_cpt_common_vars_init(struct cpt_vf *cptvf)
 {
@@ -164,7 +257,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	/* Initialize data path variables used by common code */
 	otx_cpt_common_vars_init(cptvf);
 
-	c_dev->dev_ops = NULL;
+	c_dev->dev_ops = &cptvf_ops;
 
 	c_dev->enqueue_burst = NULL;
 	c_dev->dequeue_burst = NULL;
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
index ac88fa5..b3efecf 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -5,6 +5,10 @@
 #ifndef _OTX_CRYPTODEV_OPS_H_
 #define _OTX_CRYPTODEV_OPS_H_
 
+#define OTX_CPT_MIN_HEADROOM_REQ	(24)
+#define OTX_CPT_MIN_TAILROOM_REQ	(8)
+#define CPT_NUM_QS_PER_VF		(1)
+
 void
 cleanup_global_resources(void);
 
-- 
2.7.4

[dpdk-dev] [PATCH v3 13/32] common/cpt: add common macros for queue pair ops

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding common macros required by queue pair op functions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h   | 3 +++
 drivers/common/cpt/cpt_hw_types.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 88f4902..7333c13 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -15,6 +15,9 @@
  */
 #define CRYPTO_OCTEONTX		0x1
 
+#define CPT_COUNT_THOLD		32
+#define CPT_TIMER_THOLD		0x3F
+
 #define AE_TYPE 1
 #define SE_TYPE 2
 
diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h
index 0a98621..cff59c7 100644
--- a/drivers/common/cpt/cpt_hw_types.h
+++ b/drivers/common/cpt/cpt_hw_types.h
@@ -20,6 +20,9 @@
 #define CPT_VF_INTR_HWERR_MASK  (1<<5)
 #define CPT_VF_INTR_FAULT_MASK  (1<<6)
 
+#define CPT_INST_SIZE           (64)
+#define CPT_NEXT_CHUNK_PTR_SIZE (8)
+
 /*
  * CPT_INST_S software command definitions
  * Words EI (0-3)
-- 
2.7.4

[dpdk-dev] [PATCH v3 14/32] crypto/octeontx: add queue pair functions

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding queue pair setup and release functions

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 280 ++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h |   9 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c       |  82 ++++++-
 3 files changed, 369 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index 303bcc0..5e705a8 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -1,11 +1,14 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2018 Cavium, Inc
  */
+#include <assert.h>
 #include <string.h>
 #include <unistd.h>
 
 #include <rte_branch_prediction.h>
 #include <rte_common.h>
+#include <rte_errno.h>
+#include <rte_memzone.h>
 
 #include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_mbox.h"
@@ -177,6 +180,133 @@ otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)
 		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
 }
 
+/* Write to VQX_CTL register
+ */
+static void
+otx_cpt_write_vq_ctl(struct cpt_vf *cptvf, bool val)
+{
+	cptx_vqx_ctl_t vqx_ctl;
+
+	vqx_ctl.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				 CPTX_VQX_CTL(0, 0));
+	vqx_ctl.s.ena = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_CTL(0, 0), vqx_ctl.u);
+}
+
+/* Write to VQX_INPROG register
+ */
+static void
+otx_cpt_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val)
+{
+	cptx_vqx_inprog_t vqx_inprg;
+
+	vqx_inprg.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_INPROG(0, 0));
+	vqx_inprg.s.inflight = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_INPROG(0, 0), vqx_inprg.u);
+}
+
+/* Write to VQX_DONE_WAIT NUMWAIT register
+ */
+static void
+otx_cpt_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val)
+{
+	cptx_vqx_done_wait_t vqx_dwait;
+
+	vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DONE_WAIT(0, 0));
+	vqx_dwait.s.num_wait = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
+}
+
+/* Write to VQX_DONE_WAIT NUM_WAIT register
+ */
+static void
+otx_cpt_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val)
+{
+	cptx_vqx_done_wait_t vqx_dwait;
+
+	vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DONE_WAIT(0, 0));
+	vqx_dwait.s.time_wait = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
+}
+
+/* Write to VQX_SADDR register
+ */
+static void
+otx_cpt_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val)
+{
+	cptx_vqx_saddr_t vqx_saddr;
+
+	vqx_saddr.u = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_SADDR(0, 0), vqx_saddr.u);
+}
+
+static void
+otx_cpt_vfvq_init(struct cpt_vf *cptvf)
+{
+	uint64_t base_addr = 0;
+
+	/* Disable the VQ */
+	otx_cpt_write_vq_ctl(cptvf, 0);
+
+	/* Reset the doorbell */
+	otx_cpt_write_vq_doorbell(cptvf, 0);
+	/* Clear inflight */
+	otx_cpt_write_vq_inprog(cptvf, 0);
+
+	/* Write VQ SADDR */
+	base_addr = (uint64_t)(cptvf->cqueue.chead[0].dma_addr);
+	otx_cpt_write_vq_saddr(cptvf, base_addr);
+
+	/* Configure timerhold / coalescence */
+	otx_cpt_write_vq_done_timewait(cptvf, CPT_TIMER_THOLD);
+	otx_cpt_write_vq_done_numwait(cptvf, CPT_COUNT_THOLD);
+
+	/* Enable the VQ */
+	otx_cpt_write_vq_ctl(cptvf, 1);
+}
+
+static int
+cpt_vq_init(struct cpt_vf *cptvf, uint8_t group)
+{
+	int err;
+
+	/* Convey VQ LEN to PF */
+	err = otx_cpt_send_vq_size_msg(cptvf);
+	if (err) {
+		CPT_LOG_ERR("%s: PF not responding to QLEN msg",
+			    cptvf->dev_name);
+		err = -EBUSY;
+		goto cleanup;
+	}
+
+	/* CPT VF device initialization */
+	otx_cpt_vfvq_init(cptvf);
+
+	/* Send msg to PF to assign currnet Q to required group */
+	cptvf->vfgrp = group;
+	err = otx_cpt_send_vf_grp_msg(cptvf, group);
+	if (err) {
+		CPT_LOG_ERR("%s: PF not responding to VF_GRP msg",
+			    cptvf->dev_name);
+		err = -EBUSY;
+		goto cleanup;
+	}
+
+	CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
+	return 0;
+
+cleanup:
+	return err;
+}
+
 void
 otx_cpt_poll_misc(struct cpt_vf *cptvf)
 {
@@ -263,6 +393,156 @@ otx_cpt_deinit_device(void *dev)
 }
 
 int
+otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance)
+{
+	int ret = -ENOENT, len, qlen, i;
+	int chunk_len, chunks, chunk_size;
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+	struct cpt_instance *cpt_instance;
+	struct command_chunk *chunk_head = NULL, *chunk_prev = NULL;
+	struct command_chunk *chunk = NULL;
+	uint8_t *mem;
+	const struct rte_memzone *rz;
+	uint64_t dma_addr = 0, alloc_len, used_len;
+	uint64_t *next_ptr;
+	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
+
+	CPT_LOG_DP_DEBUG("Initializing cpt resource %s", cptvf->dev_name);
+
+	cpt_instance = &cptvf->instance;
+
+	memset(&cptvf->cqueue, 0, sizeof(cptvf->cqueue));
+	memset(&cptvf->pqueue, 0, sizeof(cptvf->pqueue));
+
+	/* Chunks are of fixed size buffers */
+	chunks = DEFAULT_CMD_QCHUNKS;
+	chunk_len = DEFAULT_CMD_QCHUNK_SIZE;
+
+	qlen = chunks * chunk_len;
+	/* Chunk size includes 8 bytes of next chunk ptr */
+	chunk_size = chunk_len * CPT_INST_SIZE + CPT_NEXT_CHUNK_PTR_SIZE;
+
+	/* For command chunk structures */
+	len = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8);
+
+	/* For pending queue */
+	len += qlen * RTE_ALIGN(sizeof(struct rid), 8);
+
+	/* So that instruction queues start as pg size aligned */
+	len = RTE_ALIGN(len, pg_sz);
+
+	/* For Instruction queues */
+	len += chunks * RTE_ALIGN(chunk_size, 128);
+
+	/* Wastage after instruction queues */
+	len = RTE_ALIGN(len, pg_sz);
+
+	rz = rte_memzone_reserve_aligned(cptvf->dev_name, len, cptvf->node,
+					 RTE_MEMZONE_SIZE_HINT_ONLY |
+					 RTE_MEMZONE_256MB,
+					 RTE_CACHE_LINE_SIZE);
+	if (!rz) {
+		ret = rte_errno;
+		goto cleanup;
+	}
+
+	mem = rz->addr;
+	dma_addr = rz->phys_addr;
+	alloc_len = len;
+
+	memset(mem, 0, len);
+
+	cpt_instance->rsvd = (uintptr_t)rz;
+
+	/* Pending queue setup */
+	cptvf->pqueue.rid_queue = (struct rid *)mem;
+	cptvf->pqueue.enq_tail = 0;
+	cptvf->pqueue.deq_head = 0;
+	cptvf->pqueue.pending_count = 0;
+
+	mem +=  qlen * RTE_ALIGN(sizeof(struct rid), 8);
+	len -=  qlen * RTE_ALIGN(sizeof(struct rid), 8);
+	dma_addr += qlen * RTE_ALIGN(sizeof(struct rid), 8);
+
+	/* Alignment wastage */
+	used_len = alloc_len - len;
+	mem += RTE_ALIGN(used_len, pg_sz) - used_len;
+	len -= RTE_ALIGN(used_len, pg_sz) - used_len;
+	dma_addr += RTE_ALIGN(used_len, pg_sz) - used_len;
+
+	/* Init instruction queues */
+	chunk_head = &cptvf->cqueue.chead[0];
+	i = qlen;
+
+	chunk_prev = NULL;
+	for (i = 0; i < DEFAULT_CMD_QCHUNKS; i++) {
+		int csize;
+
+		chunk = &cptvf->cqueue.chead[i];
+		chunk->head = mem;
+		chunk->dma_addr = dma_addr;
+
+		csize = RTE_ALIGN(chunk_size, 128);
+		mem += csize;
+		dma_addr += csize;
+		len -= csize;
+
+		if (chunk_prev) {
+			next_ptr = (uint64_t *)(chunk_prev->head +
+						chunk_size - 8);
+			*next_ptr = (uint64_t)chunk->dma_addr;
+		}
+		chunk_prev = chunk;
+	}
+	/* Circular loop */
+	next_ptr = (uint64_t *)(chunk_prev->head + chunk_size - 8);
+	*next_ptr = (uint64_t)chunk_head->dma_addr;
+
+	assert(!len);
+
+	/* This is used for CPT(0)_PF_Q(0..15)_CTL.size config */
+	cptvf->qsize = chunk_size / 8;
+	cptvf->cqueue.qhead = chunk_head->head;
+	cptvf->cqueue.idx = 0;
+	cptvf->cqueue.cchunk = 0;
+
+	if (cpt_vq_init(cptvf, group)) {
+		CPT_LOG_ERR("Failed to initialize CPT VQ of device %s",
+			    cptvf->dev_name);
+		ret = -EBUSY;
+		goto cleanup;
+	}
+
+	*instance = cpt_instance;
+
+	CPT_LOG_DP_DEBUG("Crypto device (%s) initialized", cptvf->dev_name);
+
+	return 0;
+cleanup:
+	rte_memzone_free(rz);
+	*instance = NULL;
+	return ret;
+}
+
+int
+otx_cpt_put_resource(struct cpt_instance *instance)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct rte_memzone *rz;
+
+	if (!cptvf) {
+		CPT_LOG_ERR("Invalid CPTVF handle");
+		return -EINVAL;
+	}
+
+	CPT_LOG_DP_DEBUG("Releasing cpt device %s", cptvf->dev_name);
+
+	rz = (struct rte_memzone *)instance->rsvd;
+	rte_memzone_free(rz);
+	return 0;
+}
+
+int
 otx_cpt_start_device(void *dev)
 {
 	int rc;
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index b795983..2698df6 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -17,6 +17,9 @@
 
 /* Default command queue length */
 #define DEFAULT_CMD_QCHUNKS		2
+#define DEFAULT_CMD_QCHUNK_SIZE		1023
+#define DEFAULT_CMD_QLEN \
+		(DEFAULT_CMD_QCHUNK_SIZE * DEFAULT_CMD_QCHUNKS)
 
 #define CPT_CSR_REG_BASE(cpt)		((cpt)->reg_base)
 
@@ -147,6 +150,12 @@ int
 otx_cpt_deinit_device(void *dev);
 
 int
+otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance);
+
+int
+otx_cpt_put_resource(struct cpt_instance *instance);
+
+int
 otx_cpt_start_device(void *cptvf);
 
 void
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 905b37a..ed33334 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -23,6 +23,11 @@ static struct rte_mempool *otx_cpt_meta_pool;
 static int otx_cpt_op_mlen;
 static int otx_cpt_op_sb_mlen;
 
+/* Forward declarations */
+
+static int
+otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id);
+
 /*
  * Initializes global variables used by fast-path code
  *
@@ -131,9 +136,16 @@ static int
 otx_cpt_dev_close(struct rte_cryptodev *c_dev)
 {
 	void *cptvf = c_dev->data->dev_private;
+	int i, ret;
 
 	CPT_PMD_INIT_FUNC_TRACE();
 
+	for (i = 0; i < c_dev->data->nb_queue_pairs; i++) {
+		ret = otx_cpt_que_pair_release(c_dev, i);
+		if (ret)
+			return ret;
+	}
+
 	otx_cpt_periodic_alarm_stop(cptvf);
 	otx_cpt_deinit_device(cptvf);
 
@@ -168,6 +180,72 @@ otx_cpt_stats_reset(struct rte_cryptodev *dev __rte_unused)
 	CPT_PMD_INIT_FUNC_TRACE();
 }
 
+static int
+otx_cpt_que_pair_setup(struct rte_cryptodev *dev,
+		       uint16_t que_pair_id,
+		       const struct rte_cryptodev_qp_conf *qp_conf,
+		       int socket_id __rte_unused,
+		       struct rte_mempool *session_pool __rte_unused)
+{
+	void *cptvf = dev->data->dev_private;
+	struct cpt_instance *instance = NULL;
+	struct rte_pci_device *pci_dev;
+	int ret = -1;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (dev->data->queue_pairs[que_pair_id] != NULL) {
+		ret = otx_cpt_que_pair_release(dev, que_pair_id);
+		if (ret)
+			return ret;
+	}
+
+	if (qp_conf->nb_descriptors > DEFAULT_CMD_QLEN) {
+		CPT_LOG_INFO("Number of descriptors too big %d, using default "
+			     "queue length of %d", qp_conf->nb_descriptors,
+			     DEFAULT_CMD_QLEN);
+	}
+
+	pci_dev = RTE_DEV_TO_PCI(dev->device);
+
+	if (pci_dev->mem_resource[0].addr == NULL) {
+		CPT_LOG_ERR("PCI mem address null");
+		return -EIO;
+	}
+
+	ret = otx_cpt_get_resource(cptvf, 0, &instance);
+	if (ret != 0) {
+		CPT_LOG_ERR("Error getting instance handle from device %s : "
+			    "ret = %d", dev->data->name, ret);
+		return ret;
+	}
+
+	instance->queue_id = que_pair_id;
+	dev->data->queue_pairs[que_pair_id] = instance;
+
+	return 0;
+}
+
+static int
+otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)
+{
+	struct cpt_instance *instance = dev->data->queue_pairs[que_pair_id];
+	int ret;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	ret = otx_cpt_put_resource(instance);
+	if (ret != 0) {
+		CPT_LOG_ERR("Error putting instance handle of device %s : "
+			    "ret = %d", dev->data->name, ret);
+		return ret;
+	}
+
+	dev->data->queue_pairs[que_pair_id] = NULL;
+
+	return 0;
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -178,8 +256,8 @@ static struct rte_cryptodev_ops cptvf_ops = {
 
 	.stats_get = otx_cpt_stats_get,
 	.stats_reset = otx_cpt_stats_reset,
-	.queue_pair_setup = NULL,
-	.queue_pair_release = NULL,
+	.queue_pair_setup = otx_cpt_que_pair_setup,
+	.queue_pair_release = otx_cpt_que_pair_release,
 	.queue_pair_count = NULL,
 
 	/* Crypto related operations */
-- 
2.7.4

[dpdk-dev] [PATCH v3 15/32] common/cpt: add common code required for session management

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding common code required for session configure, session clear and get
session size ops routines

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h | 119 +++++++++++++++++++++++++++++++++
 drivers/common/cpt/cpt_request_mgr.h   |  32 +++++++++
 drivers/common/cpt/cpt_ucode.h         |  47 +++++++++++++
 3 files changed, 198 insertions(+)
 create mode 100644 drivers/common/cpt/cpt_request_mgr.h
 create mode 100644 drivers/common/cpt/cpt_ucode.h

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 83a8a42..235320c 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -5,6 +5,9 @@
 #ifndef _CPT_MCODE_DEFINES_H_
 #define _CPT_MCODE_DEFINES_H_
 
+#include <rte_byteorder.h>
+#include <rte_memory.h>
+
 /*
  * This file defines macros and structures according to microcode spec
  *
@@ -35,4 +38,120 @@ typedef struct sglist_comp {
 	uint64_t ptr[4];
 } sg_comp_t;
 
+struct cpt_sess_misc {
+	/** CPT opcode */
+	uint16_t cpt_op:4;
+	/** ZUC, SNOW3G &  KASUMI flags */
+	uint16_t zsk_flag:4;
+	/** Flag for AES GCM */
+	uint16_t aes_gcm:1;
+	/** Flag for AES CTR */
+	uint16_t aes_ctr:1;
+	/** Flag for NULL cipher/auth */
+	uint16_t is_null:1;
+	/** Flag for GMAC */
+	uint16_t is_gmac:1;
+	/** AAD length */
+	uint16_t aad_length;
+	/** MAC len in bytes */
+	uint8_t mac_len;
+	/** IV length in bytes */
+	uint8_t iv_length;
+	/** Auth IV length in bytes */
+	uint8_t auth_iv_length;
+	/** Reserved field */
+	uint8_t rsvd1;
+	/** IV offset in bytes */
+	uint16_t iv_offset;
+	/** Auth IV offset in bytes */
+	uint16_t auth_iv_offset;
+	/** Salt */
+	uint32_t salt;
+	/** Context DMA address */
+	phys_addr_t ctx_dma_addr;
+};
+
+typedef union {
+	uint64_t flags;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint64_t enc_cipher   : 4;
+		uint64_t reserved1    : 1;
+		uint64_t aes_key      : 2;
+		uint64_t iv_source    : 1;
+		uint64_t hash_type    : 4;
+		uint64_t reserved2    : 3;
+		uint64_t auth_input_type : 1;
+		uint64_t mac_len      : 8;
+		uint64_t reserved3    : 8;
+		uint64_t encr_offset  : 16;
+		uint64_t iv_offset    : 8;
+		uint64_t auth_offset  : 8;
+#else
+		uint64_t auth_offset  : 8;
+		uint64_t iv_offset    : 8;
+		uint64_t encr_offset  : 16;
+		uint64_t reserved3    : 8;
+		uint64_t mac_len      : 8;
+		uint64_t auth_input_type : 1;
+		uint64_t reserved2    : 3;
+		uint64_t hash_type    : 4;
+		uint64_t iv_source    : 1;
+		uint64_t aes_key      : 2;
+		uint64_t reserved1    : 1;
+		uint64_t enc_cipher   : 4;
+#endif
+	} e;
+} encr_ctrl_t;
+
+typedef struct {
+	encr_ctrl_t enc_ctrl;
+	uint8_t  encr_key[32];
+	uint8_t  encr_iv[16];
+} mc_enc_context_t;
+
+typedef struct {
+	uint8_t  ipad[64];
+	uint8_t  opad[64];
+} mc_fc_hmac_context_t;
+
+typedef struct {
+	mc_enc_context_t     enc;
+	mc_fc_hmac_context_t hmac;
+} mc_fc_context_t;
+
+typedef struct {
+	uint8_t encr_auth_iv[16];
+	uint8_t ci_key[16];
+	uint8_t zuc_const[32];
+} mc_zuc_snow3g_ctx_t;
+
+typedef struct {
+	uint8_t reg_A[8];
+	uint8_t ci_key[16];
+} mc_kasumi_ctx_t;
+
+struct cpt_ctx {
+	/* Below fields are accessed by sw */
+	uint64_t enc_cipher	:8;
+	uint64_t hash_type	:8;
+	uint64_t mac_len	:8;
+	uint64_t auth_key_len	:8;
+	uint64_t fc_type	:4;
+	uint64_t hmac		:1;
+	uint64_t zsk_flags	:3;
+	uint64_t k_ecb		:1;
+	uint64_t snow3g		:1;
+	uint64_t rsvd		:22;
+	/* Below fields are accessed by hardware */
+	union {
+		mc_fc_context_t fctx;
+		mc_zuc_snow3g_ctx_t zs_ctx;
+		mc_kasumi_ctx_t k_ctx;
+	};
+	uint8_t  auth_key[64];
+};
+
+#define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
+
 #endif /* _CPT_MCODE_DEFINES_H_ */
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
new file mode 100644
index 0000000..fe184fe
--- /dev/null
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_REQUEST_MGR_H_
+#define _CPT_REQUEST_MGR_H_
+
+#include "cpt_mcode_defines.h"
+
+/*
+ * This file defines the agreement between the common layer and the individual
+ * crypto drivers for OCTEON TX series. Datapath in otx* directory include this
+ * file and all these functions are static inlined for better performance.
+ *
+ */
+
+/*
+ * Get the session size
+ *
+ * This function is used in the data path.
+ *
+ * @return
+ *   - session size
+ */
+static __rte_always_inline unsigned int
+cpt_get_session_size(void)
+{
+	unsigned int ctx_len = sizeof(struct cpt_ctx);
+	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
+}
+
+#endif /* _CPT_REQUEST_MGR_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
new file mode 100644
index 0000000..e4f16fe
--- /dev/null
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_UCODE_H_
+#define _CPT_UCODE_H_
+
+#include "cpt_mcode_defines.h"
+
+/*
+ * This file defines functions that are interfaces to microcode spec.
+ *
+ */
+
+static __rte_always_inline int
+cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
+{
+	/*
+	 * Microcode only supports the following combination.
+	 * Encryption followed by authentication
+	 * Authentication followed by decryption
+	 */
+	if (xform->next) {
+		if ((xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
+		    (xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
+		    (xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)) {
+			/* Unsupported as of now by microcode */
+			CPT_LOG_DP_ERR("Unsupported combination");
+			return -1;
+		}
+		if ((xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
+		    (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
+		    (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)) {
+			/* For GMAC auth there is no cipher operation */
+			if (xform->aead.algo != RTE_CRYPTO_AEAD_AES_GCM ||
+			    xform->next->auth.algo !=
+			    RTE_CRYPTO_AUTH_AES_GMAC) {
+				/* Unsupported as of now by microcode */
+				CPT_LOG_DP_ERR("Unsupported combination");
+				return -1;
+			}
+		}
+	}
+	return 0;
+}
+
+#endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 16/32] crypto/octeontx: add session management ops

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding routines for session configure, session clear and get session
size ops.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_ops.c | 84 +++++++++++++++++++++++++++--
 1 file changed, 81 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index ed33334..653f372 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -10,6 +10,8 @@
 
 #include "cpt_pmd_logs.h"
 #include "cpt_pmd_ops_helper.h"
+#include "cpt_ucode.h"
+#include "cpt_request_mgr.h"
 
 #include "otx_cryptodev.h"
 #include "otx_cryptodev_capabilities.h"
@@ -246,6 +248,82 @@ otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)
 	return 0;
 }
 
+static unsigned int
+otx_cpt_get_session_size(struct rte_cryptodev *dev __rte_unused)
+{
+	return cpt_get_session_size();
+}
+
+static void
+otx_cpt_session_init(void *sym_sess, uint8_t driver_id)
+{
+	struct rte_cryptodev_sym_session *sess = sym_sess;
+	struct cpt_sess_misc *cpt_sess =
+	 (struct cpt_sess_misc *) get_sym_session_private_data(sess, driver_id);
+
+	CPT_PMD_INIT_FUNC_TRACE();
+	cpt_sess->ctx_dma_addr = rte_mempool_virt2iova(cpt_sess) +
+			sizeof(struct cpt_sess_misc);
+}
+
+static int
+otx_cpt_session_cfg(struct rte_cryptodev *dev,
+		    struct rte_crypto_sym_xform *xform,
+		    struct rte_cryptodev_sym_session *sess,
+		    struct rte_mempool *mempool)
+{
+	struct rte_crypto_sym_xform *chain;
+	void *sess_private_data = NULL;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (cpt_is_algo_supported(xform))
+		goto err;
+
+	if (unlikely(sess == NULL)) {
+		CPT_LOG_ERR("invalid session struct");
+		return -EINVAL;
+	}
+
+	if (rte_mempool_get(mempool, &sess_private_data)) {
+		CPT_LOG_ERR("Could not allocate sess_private_data");
+		return -ENOMEM;
+	}
+
+	chain = xform;
+	while (chain) {
+		switch (chain->type) {
+		default:
+			CPT_LOG_ERR("Invalid crypto xform type");
+			break;
+		}
+		chain = chain->next;
+	}
+	set_sym_session_private_data(sess, dev->driver_id, sess_private_data);
+	otx_cpt_session_init(sess, dev->driver_id);
+	return 0;
+
+err:
+	if (sess_private_data)
+		rte_mempool_put(mempool, sess_private_data);
+	return -EPERM;
+}
+
+static void
+otx_cpt_session_clear(struct rte_cryptodev *dev,
+		  struct rte_cryptodev_sym_session *sess)
+{
+	void *sess_priv = get_sym_session_private_data(sess, dev->driver_id);
+
+	CPT_PMD_INIT_FUNC_TRACE();
+	if (sess_priv) {
+		memset(sess_priv, 0, otx_cpt_get_session_size(dev));
+		struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
+		set_sym_session_private_data(sess, dev->driver_id, NULL);
+		rte_mempool_put(sess_mp, sess_priv);
+	}
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -261,9 +339,9 @@ static struct rte_cryptodev_ops cptvf_ops = {
 	.queue_pair_count = NULL,
 
 	/* Crypto related operations */
-	.sym_session_get_size = NULL,
-	.sym_session_configure = NULL,
-	.sym_session_clear = NULL
+	.sym_session_get_size = otx_cpt_get_session_size,
+	.sym_session_configure = otx_cpt_session_cfg,
+	.sym_session_clear = otx_cpt_session_clear
 };
 
 static void
-- 
2.7.4

[dpdk-dev] [PATCH v3 17/32] common/cpt: add common code for fill session data

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding common code required for filling session data for AEAD, cipher &
auth sessions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h |  90 +++++
 drivers/common/cpt/cpt_ucode.h         | 669 +++++++++++++++++++++++++++++++++
 2 files changed, 759 insertions(+)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 235320c..50657a2 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -25,9 +25,88 @@
 #define SG_LIST_HDR_SIZE	(8u)
 #define SG_ENTRY_SIZE		sizeof(sg_comp_t)
 
+#define CPT_DMA_MODE		(1 << 7)
+
+#define CPT_FROM_CTX		0
+#define CPT_FROM_DPTR		1
+
+#define FC_GEN			0x1
+#define ZUC_SNOW3G		0x2
+#define KASUMI			0x3
+#define HASH_HMAC		0x4
+
+#define ZS_EA			0x1
+#define ZS_IA			0x2
+#define K_F8			0x4
+#define K_F9			0x8
+
+#define CPT_OP_CIPHER_ENCRYPT	0x1
+#define CPT_OP_CIPHER_DECRYPT	0x2
+#define CPT_OP_CIPHER_MASK	0x3
+
+#define CPT_OP_AUTH_VERIFY	0x4
+#define CPT_OP_AUTH_GENERATE	0x8
+#define CPT_OP_AUTH_MASK	0xC
+
+#define CPT_OP_ENCODE	(CPT_OP_CIPHER_ENCRYPT | CPT_OP_AUTH_GENERATE)
+#define CPT_OP_DECODE	(CPT_OP_CIPHER_DECRYPT | CPT_OP_AUTH_VERIFY)
+
 /* #define CPT_ALWAYS_USE_SG_MODE */
 #define CPT_ALWAYS_USE_SEPARATE_BUF
 
+typedef enum {
+	MD5_TYPE        = 1,
+	SHA1_TYPE       = 2,
+	SHA2_SHA224     = 3,
+	SHA2_SHA256     = 4,
+	SHA2_SHA384     = 5,
+	SHA2_SHA512     = 6,
+	GMAC_TYPE       = 7,
+	XCBC_TYPE       = 8,
+	SHA3_SHA224     = 10,
+	SHA3_SHA256     = 11,
+	SHA3_SHA384     = 12,
+	SHA3_SHA512     = 13,
+	SHA3_SHAKE256   = 14,
+	SHA3_SHAKE512   = 15,
+
+	/* These are only for software use */
+	ZUC_EIA3        = 0x90,
+	SNOW3G_UIA2     = 0x91,
+	KASUMI_F9_CBC   = 0x92,
+	KASUMI_F9_ECB   = 0x93,
+} mc_hash_type_t;
+
+typedef enum {
+	/* To support passthrough */
+	PASSTHROUGH  = 0x0,
+	/*
+	 * These are defined by MC for Flexi crypto
+	 * for field of 4 bits
+	 */
+	DES3_CBC    = 0x1,
+	DES3_ECB    = 0x2,
+	AES_CBC     = 0x3,
+	AES_ECB     = 0x4,
+	AES_CFB     = 0x5,
+	AES_CTR     = 0x6,
+	AES_GCM     = 0x7,
+	AES_XTS     = 0x8,
+
+	/* These are only for software use */
+	ZUC_EEA3        = 0x90,
+	SNOW3G_UEA2     = 0x91,
+	KASUMI_F8_CBC   = 0x92,
+	KASUMI_F8_ECB   = 0x93,
+} mc_cipher_type_t;
+
+typedef enum {
+	AES_128_BIT = 0x1,
+	AES_192_BIT = 0x2,
+	AES_256_BIT = 0x3
+} mc_aes_type_t;
+
+
 typedef struct sglist_comp {
 	union {
 		uint64_t len;
@@ -152,6 +231,17 @@ struct cpt_ctx {
 	uint8_t  auth_key[64];
 };
 
+typedef struct fc_params digest_params_t;
+
+/* Cipher Algorithms */
+typedef mc_cipher_type_t cipher_type_t;
+
+/* Auth Algorithms */
+typedef mc_hash_type_t auth_type_t;
+
 #define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
 
+#define SESS_PRIV(__sess) \
+	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
+
 #endif /* _CPT_MCODE_DEFINES_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index e4f16fe..4bbb27a 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -12,6 +12,13 @@
  *
  */
 
+static uint8_t zuc_d[32] = {
+	0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
+	0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
+	0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
+	0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC
+};
+
 static __rte_always_inline int
 cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
 {
@@ -44,4 +51,666 @@ cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
 	return 0;
 }
 
+static __rte_always_inline void
+gen_key_snow3g(uint8_t *ck, uint32_t *keyx)
+{
+	int i, base;
+
+	for (i = 0; i < 4; i++) {
+		base = 4 * i;
+		keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
+			(ck[base + 2] << 8) | (ck[base + 3]);
+		keyx[3 - i] = rte_cpu_to_be_32(keyx[3 - i]);
+	}
+}
+
+static __rte_always_inline int
+cpt_fc_ciph_validate_key_aes(uint16_t key_len)
+{
+	switch (key_len) {
+	case CPT_BYTE_16:
+	case CPT_BYTE_24:
+	case CPT_BYTE_32:
+		return 0;
+	default:
+		return -1;
+	}
+}
+
+static __rte_always_inline int
+cpt_fc_ciph_validate_key(cipher_type_t type, struct cpt_ctx *cpt_ctx,
+		uint16_t key_len)
+{
+	int fc_type = 0;
+	switch (type) {
+	case PASSTHROUGH:
+		fc_type = FC_GEN;
+		break;
+	case DES3_CBC:
+	case DES3_ECB:
+		fc_type = FC_GEN;
+		break;
+	case AES_CBC:
+	case AES_ECB:
+	case AES_CFB:
+	case AES_CTR:
+	case AES_GCM:
+		if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
+			return -1;
+		fc_type = FC_GEN;
+		break;
+	case AES_XTS:
+		key_len = key_len / 2;
+		if (unlikely(key_len == CPT_BYTE_24)) {
+			CPT_LOG_DP_ERR("Invalid AES key len for XTS");
+			return -1;
+		}
+		if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
+			return -1;
+		fc_type = FC_GEN;
+		break;
+	case ZUC_EEA3:
+	case SNOW3G_UEA2:
+		if (unlikely(key_len != 16))
+			return -1;
+		/* No support for AEAD yet */
+		if (unlikely(cpt_ctx->hash_type))
+			return -1;
+		fc_type = ZUC_SNOW3G;
+		break;
+	case KASUMI_F8_CBC:
+	case KASUMI_F8_ECB:
+		if (unlikely(key_len != 16))
+			return -1;
+		/* No support for AEAD yet */
+		if (unlikely(cpt_ctx->hash_type))
+			return -1;
+		fc_type = KASUMI;
+		break;
+	default:
+		return -1;
+	}
+	return fc_type;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_passthrough(struct cpt_ctx *cpt_ctx, mc_fc_context_t *fctx)
+{
+	cpt_ctx->enc_cipher = 0;
+	CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_set_aes_key_type(mc_fc_context_t *fctx, uint16_t key_len)
+{
+	mc_aes_type_t aes_key_type = 0;
+	switch (key_len) {
+	case CPT_BYTE_16:
+		aes_key_type = AES_128_BIT;
+		break;
+	case CPT_BYTE_24:
+		aes_key_type = AES_192_BIT;
+		break;
+	case CPT_BYTE_32:
+		aes_key_type = AES_256_BIT;
+		break;
+	default:
+		/* This should not happen */
+		CPT_LOG_DP_ERR("Invalid AES key len");
+		return;
+	}
+	CPT_P_ENC_CTRL(fctx).aes_key = aes_key_type;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_snow3g_uea2(struct cpt_ctx *cpt_ctx, uint8_t *key,
+		uint16_t key_len)
+{
+	uint32_t keyx[4];
+	cpt_ctx->snow3g = 1;
+	gen_key_snow3g(key, keyx);
+	memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
+	cpt_ctx->fc_type = ZUC_SNOW3G;
+	cpt_ctx->zsk_flags = 0;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_zuc_eea3(struct cpt_ctx *cpt_ctx, uint8_t *key,
+		uint16_t key_len)
+{
+	cpt_ctx->snow3g = 0;
+	memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
+	memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
+	cpt_ctx->fc_type = ZUC_SNOW3G;
+	cpt_ctx->zsk_flags = 0;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_kasumi_f8_ecb(struct cpt_ctx *cpt_ctx, uint8_t *key,
+		uint16_t key_len)
+{
+	cpt_ctx->k_ecb = 1;
+	memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+	cpt_ctx->zsk_flags = 0;
+	cpt_ctx->fc_type = KASUMI;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_kasumi_f8_cbc(struct cpt_ctx *cpt_ctx, uint8_t *key,
+		uint16_t key_len)
+{
+	memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+	cpt_ctx->zsk_flags = 0;
+	cpt_ctx->fc_type = KASUMI;
+}
+
+static __rte_always_inline int
+cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,
+		    uint16_t key_len, uint8_t *salt)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	mc_fc_context_t *fctx = &cpt_ctx->fctx;
+	uint64_t *ctrl_flags = NULL;
+	int fc_type;
+
+	/* Validate key before proceeding */
+	fc_type = cpt_fc_ciph_validate_key(type, cpt_ctx, key_len);
+	if (unlikely(fc_type == -1))
+		return -1;
+
+	if (fc_type == FC_GEN) {
+		cpt_ctx->fc_type = FC_GEN;
+		ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags);
+		*ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
+		/*
+		 * We need to always say IV is from DPTR as user can
+		 * sometimes iverride IV per operation.
+		 */
+		CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_DPTR;
+	}
+
+	switch (type) {
+	case PASSTHROUGH:
+		cpt_fc_ciph_set_key_passthrough(cpt_ctx, fctx);
+		goto fc_success;
+	case DES3_CBC:
+		/* CPT performs DES using 3DES with the 8B DES-key
+		 * replicated 2 more times to match the 24B 3DES-key.
+		 * Eg. If org. key is "0x0a 0x0b", then new key is
+		 * "0x0a 0x0b 0x0a 0x0b 0x0a 0x0b"
+		 */
+		if (key_len == 8) {
+			/* Skipping the first 8B as it will be copied
+			 * in the regular code flow
+			 */
+			memcpy(fctx->enc.encr_key+key_len, key, key_len);
+			memcpy(fctx->enc.encr_key+2*key_len, key, key_len);
+		}
+		break;
+	case DES3_ECB:
+		/* For DES3_ECB IV need to be from CTX. */
+		CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_CTX;
+		break;
+	case AES_CBC:
+	case AES_ECB:
+	case AES_CFB:
+	case AES_CTR:
+		cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
+		break;
+	case AES_GCM:
+		/* Even though iv source is from dptr,
+		 * aes_gcm salt is taken from ctx
+		 */
+		if (salt) {
+			memcpy(fctx->enc.encr_iv, salt, 4);
+			/* Assuming it was just salt update
+			 * and nothing else
+			 */
+			if (!key)
+				goto fc_success;
+		}
+		cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
+		break;
+	case AES_XTS:
+		key_len = key_len / 2;
+		cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
+
+		/* Copy key2 for XTS into ipad */
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memcpy(fctx->hmac.ipad, &key[key_len], key_len);
+		break;
+	case SNOW3G_UEA2:
+		cpt_fc_ciph_set_key_snow3g_uea2(cpt_ctx, key, key_len);
+		goto success;
+	case ZUC_EEA3:
+		cpt_fc_ciph_set_key_zuc_eea3(cpt_ctx, key, key_len);
+		goto success;
+	case KASUMI_F8_ECB:
+		cpt_fc_ciph_set_key_kasumi_f8_ecb(cpt_ctx, key, key_len);
+		goto success;
+	case KASUMI_F8_CBC:
+		cpt_fc_ciph_set_key_kasumi_f8_cbc(cpt_ctx, key, key_len);
+		goto success;
+	default:
+		break;
+	}
+
+	/* Only for FC_GEN case */
+
+	/* For GMAC auth, cipher must be NULL */
+	if (cpt_ctx->hash_type != GMAC_TYPE)
+		CPT_P_ENC_CTRL(fctx).enc_cipher = type;
+
+	memcpy(fctx->enc.encr_key, key, key_len);
+
+fc_success:
+	*ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
+
+success:
+	cpt_ctx->enc_cipher = type;
+
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_fc_auth_set_key(void *ctx, auth_type_t type, uint8_t *key,
+		    uint16_t key_len, uint16_t mac_len)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	mc_fc_context_t *fctx = &cpt_ctx->fctx;
+	uint64_t *ctrl_flags = NULL;
+
+	if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
+		uint32_t keyx[4];
+
+		if (key_len != 16)
+			return -1;
+		/* No support for AEAD yet */
+		if (cpt_ctx->enc_cipher)
+			return -1;
+		/* For ZUC/SNOW3G/Kasumi */
+		switch (type) {
+		case SNOW3G_UIA2:
+			cpt_ctx->snow3g = 1;
+			gen_key_snow3g(key, keyx);
+			memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case ZUC_EIA3:
+			cpt_ctx->snow3g = 0;
+			memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
+			memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case KASUMI_F9_ECB:
+			/* Kasumi ECB mode */
+			cpt_ctx->k_ecb = 1;
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->fc_type = KASUMI;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case KASUMI_F9_CBC:
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->fc_type = KASUMI;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		default:
+			return -1;
+		}
+		cpt_ctx->mac_len = 4;
+		cpt_ctx->hash_type = type;
+		return 0;
+	}
+
+	if (!(cpt_ctx->fc_type == FC_GEN && !type)) {
+		if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher)
+			cpt_ctx->fc_type = HASH_HMAC;
+	}
+
+	ctrl_flags = (uint64_t *)&fctx->enc.enc_ctrl.flags;
+	*ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
+
+	/* For GMAC auth, cipher must be NULL */
+	if (type == GMAC_TYPE)
+		CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
+
+	CPT_P_ENC_CTRL(fctx).hash_type = cpt_ctx->hash_type = type;
+	CPT_P_ENC_CTRL(fctx).mac_len = cpt_ctx->mac_len = mac_len;
+
+	if (key_len) {
+		cpt_ctx->hmac = 1;
+		memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key));
+		memcpy(cpt_ctx->auth_key, key, key_len);
+		cpt_ctx->auth_key_len = key_len;
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
+		memcpy(fctx->hmac.opad, key, key_len);
+		CPT_P_ENC_CTRL(fctx).auth_input_type = 1;
+	}
+	*ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
+	return 0;
+}
+
+static __rte_always_inline int
+fill_sess_aead(struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_aead_xform *aead_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint32_t cipher_key_len = 0;
+	uint8_t zsk_flag = 0, aes_gcm = 0;
+	aead_form = &xform->aead;
+	void *ctx;
+
+	if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
+	   aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+		sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
+		sess->cpt_op |= CPT_OP_AUTH_GENERATE;
+	} else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
+		aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+		sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
+		sess->cpt_op |= CPT_OP_AUTH_VERIFY;
+	} else {
+		CPT_LOG_DP_ERR("Unknown cipher operation\n");
+		return -1;
+	}
+	switch (aead_form->algo) {
+	case RTE_CRYPTO_AEAD_AES_GCM:
+		enc_type = AES_GCM;
+		cipher_key_len = 16;
+		aes_gcm = 1;
+		break;
+	case RTE_CRYPTO_AEAD_AES_CCM:
+		CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
+			       aead_form->algo);
+		return -1;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
+			       aead_form->algo);
+		return -1;
+	}
+	if (aead_form->key.length < cipher_key_len) {
+		CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
+			       (unsigned int long)aead_form->key.length);
+		return -1;
+	}
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->mac_len = aead_form->digest_length;
+	sess->iv_offset = aead_form->iv.offset;
+	sess->iv_length = aead_form->iv.length;
+	sess->aad_length = aead_form->aad_length;
+	ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+
+	cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
+			aead_form->key.length, NULL);
+
+	cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, aead_form->digest_length);
+
+	return 0;
+}
+
+static __rte_always_inline int
+fill_sess_cipher(struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_cipher_xform *c_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	uint32_t cipher_key_len = 0;
+	uint8_t zsk_flag = 0, aes_gcm = 0, aes_ctr = 0, is_null = 0;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER)
+		return -1;
+
+	c_form = &xform->cipher;
+
+	if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
+		sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
+	else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
+		sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
+	else {
+		CPT_LOG_DP_ERR("Unknown cipher operation\n");
+		return -1;
+	}
+
+	switch (c_form->algo) {
+	case RTE_CRYPTO_CIPHER_AES_CBC:
+		enc_type = AES_CBC;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CBC:
+		enc_type = DES3_CBC;
+		cipher_key_len = 24;
+		break;
+	case RTE_CRYPTO_CIPHER_DES_CBC:
+		/* DES is implemented using 3DES in hardware */
+		enc_type = DES3_CBC;
+		cipher_key_len = 8;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_CTR:
+		enc_type = AES_CTR;
+		cipher_key_len = 16;
+		aes_ctr = 1;
+		break;
+	case RTE_CRYPTO_CIPHER_NULL:
+		enc_type = 0;
+		is_null = 1;
+		break;
+	case RTE_CRYPTO_CIPHER_KASUMI_F8:
+		enc_type = KASUMI_F8_ECB;
+		cipher_key_len = 16;
+		zsk_flag = K_F8;
+		break;
+	case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
+		enc_type = SNOW3G_UEA2;
+		cipher_key_len = 16;
+		zsk_flag = ZS_EA;
+		break;
+	case RTE_CRYPTO_CIPHER_ZUC_EEA3:
+		enc_type = ZUC_EEA3;
+		cipher_key_len = 16;
+		zsk_flag = ZS_EA;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_XTS:
+		enc_type = AES_XTS;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_ECB:
+		enc_type = DES3_ECB;
+		cipher_key_len = 24;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_ECB:
+		enc_type = AES_ECB;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CTR:
+	case RTE_CRYPTO_CIPHER_AES_F8:
+	case RTE_CRYPTO_CIPHER_ARC4:
+		CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
+			       c_form->algo);
+		return -1;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
+			       c_form->algo);
+		return -1;
+	}
+
+	if (c_form->key.length < cipher_key_len) {
+		CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
+			       (unsigned long) c_form->key.length);
+		return -1;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->aes_ctr = aes_ctr;
+	sess->iv_offset = c_form->iv.offset;
+	sess->iv_length = c_form->iv.length;
+	sess->is_null = is_null;
+
+	cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type, c_form->key.data,
+			    c_form->key.length, NULL);
+
+	return 0;
+}
+
+static __rte_always_inline int
+fill_sess_auth(struct rte_crypto_sym_xform *xform,
+	       struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_auth_xform *a_form;
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint8_t zsk_flag = 0, aes_gcm = 0, is_null = 0;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
+		goto error_out;
+
+	a_form = &xform->auth;
+
+	if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
+		sess->cpt_op |= CPT_OP_AUTH_VERIFY;
+	else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
+		sess->cpt_op |= CPT_OP_AUTH_GENERATE;
+	else {
+		CPT_LOG_DP_ERR("Unknown auth operation");
+		return -1;
+	}
+
+	if (a_form->key.length > 64) {
+		CPT_LOG_DP_ERR("Auth key length is big");
+		return -1;
+	}
+
+	switch (a_form->algo) {
+	case RTE_CRYPTO_AUTH_SHA1_HMAC:
+		/* Fall through */
+	case RTE_CRYPTO_AUTH_SHA1:
+		auth_type = SHA1_TYPE;
+		break;
+	case RTE_CRYPTO_AUTH_SHA256_HMAC:
+	case RTE_CRYPTO_AUTH_SHA256:
+		auth_type = SHA2_SHA256;
+		break;
+	case RTE_CRYPTO_AUTH_SHA512_HMAC:
+	case RTE_CRYPTO_AUTH_SHA512:
+		auth_type = SHA2_SHA512;
+		break;
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		auth_type = GMAC_TYPE;
+		aes_gcm = 1;
+		break;
+	case RTE_CRYPTO_AUTH_SHA224_HMAC:
+	case RTE_CRYPTO_AUTH_SHA224:
+		auth_type = SHA2_SHA224;
+		break;
+	case RTE_CRYPTO_AUTH_SHA384_HMAC:
+	case RTE_CRYPTO_AUTH_SHA384:
+		auth_type = SHA2_SHA384;
+		break;
+	case RTE_CRYPTO_AUTH_MD5_HMAC:
+	case RTE_CRYPTO_AUTH_MD5:
+		auth_type = MD5_TYPE;
+		break;
+	case RTE_CRYPTO_AUTH_KASUMI_F9:
+		auth_type = KASUMI_F9_ECB;
+		/*
+		 * Indicate that direction needs to be taken out
+		 * from end of src
+		 */
+		zsk_flag = K_F9;
+		break;
+	case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
+		auth_type = SNOW3G_UIA2;
+		zsk_flag = ZS_IA;
+		break;
+	case RTE_CRYPTO_AUTH_ZUC_EIA3:
+		auth_type = ZUC_EIA3;
+		zsk_flag = ZS_IA;
+		break;
+	case RTE_CRYPTO_AUTH_NULL:
+		auth_type = 0;
+		is_null = 1;
+		break;
+	case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+	case RTE_CRYPTO_AUTH_AES_CMAC:
+	case RTE_CRYPTO_AUTH_AES_CBC_MAC:
+		CPT_LOG_DP_ERR("Crypto: Unsupported hash algo %u",
+			       a_form->algo);
+		goto error_out;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined Hash algo %u specified",
+			       a_form->algo);
+		goto error_out;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->mac_len = a_form->digest_length;
+	sess->is_null = is_null;
+	if (zsk_flag) {
+		sess->auth_iv_offset = a_form->iv.offset;
+		sess->auth_iv_length = a_form->iv.length;
+	}
+	cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type, a_form->key.data,
+			    a_form->key.length, a_form->digest_length);
+
+	return 0;
+
+error_out:
+	return -1;
+}
+
+static __rte_always_inline int
+fill_sess_gmac(struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_auth_xform *a_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint8_t zsk_flag = 0, aes_gcm = 0;
+	void *ctx;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
+		return -1;
+
+	a_form = &xform->auth;
+
+	if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
+		sess->cpt_op |= CPT_OP_ENCODE;
+	else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
+		sess->cpt_op |= CPT_OP_DECODE;
+	else {
+		CPT_LOG_DP_ERR("Unknown auth operation");
+		return -1;
+	}
+
+	switch (a_form->algo) {
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		enc_type = AES_GCM;
+		auth_type = GMAC_TYPE;
+		break;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
+			       a_form->algo);
+		return -1;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->is_gmac = 1;
+	sess->iv_offset = a_form->iv.offset;
+	sess->iv_length = a_form->iv.length;
+	sess->mac_len = a_form->digest_length;
+	ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+
+	cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
+			a_form->key.length, NULL);
+	cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, a_form->digest_length);
+
+	return 0;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 18/32] crypto/octeontx: add supported sessions

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding AEAD, cipher & auth sessions support.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_ops.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 653f372..16fad49 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -293,6 +293,23 @@ otx_cpt_session_cfg(struct rte_cryptodev *dev,
 	chain = xform;
 	while (chain) {
 		switch (chain->type) {
+		case RTE_CRYPTO_SYM_XFORM_AEAD:
+			if (fill_sess_aead(chain, sess_private_data))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_CIPHER:
+			if (fill_sess_cipher(chain, sess_private_data))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_AUTH:
+			if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
+				if (fill_sess_gmac(chain, sess_private_data))
+					goto err;
+			} else {
+				if (fill_sess_auth(chain, sess_private_data))
+					goto err;
+			}
+			break;
 		default:
 			CPT_LOG_ERR("Invalid crypto xform type");
 			break;
-- 
2.7.4

[dpdk-dev] [PATCH v3 19/32] common/cpt: add common defines for microcode

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h | 117 +++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 50657a2..263fc47 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -12,6 +12,12 @@
  * This file defines macros and structures according to microcode spec
  *
  */
+/* SE opcodes */
+#define CPT_MAJOR_OP_FC		0x33
+#define CPT_MAJOR_OP_HASH	0x34
+#define CPT_MAJOR_OP_HMAC	0x35
+#define CPT_MAJOR_OP_ZUC_SNOW3G	0x37
+#define CPT_MAJOR_OP_KASUMI	0x38
 
 #define CPT_BYTE_16		16
 #define CPT_BYTE_24		24
@@ -54,6 +60,25 @@
 /* #define CPT_ALWAYS_USE_SG_MODE */
 #define CPT_ALWAYS_USE_SEPARATE_BUF
 
+/*
+ * Parameters for Flexi Crypto
+ * requests
+ */
+#define VALID_AAD_BUF 0x01
+#define VALID_MAC_BUF 0x02
+#define VALID_IV_BUF 0x04
+#define SINGLE_BUF_INPLACE 0x08
+#define SINGLE_BUF_HEADTAILROOM 0x10
+
+#define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff)
+#define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff)
+#define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff)
+#define ENCR_DLEN(__d_lens) (__d_lens >> 32)
+#define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff)
+
+/* FC offset_control at start of DPTR in bytes */
+#define OFF_CTRL_LEN  8 /**< bytes */
+
 typedef enum {
 	MD5_TYPE        = 1,
 	SHA1_TYPE       = 2,
@@ -106,6 +131,48 @@ typedef enum {
 	AES_256_BIT = 0x3
 } mc_aes_type_t;
 
+typedef enum {
+	/* Microcode errors */
+	NO_ERR = 0x00,
+	ERR_OPCODE_UNSUPPORTED = 0x01,
+
+	/* SCATTER GATHER */
+	ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,
+	ERR_SCATTER_GATHER_LIST = 0x03,
+	ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,
+
+	/* SE GC */
+	ERR_GC_LENGTH_INVALID = 0x41,
+	ERR_GC_RANDOM_LEN_INVALID = 0x42,
+	ERR_GC_DATA_LEN_INVALID = 0x43,
+	ERR_GC_DRBG_TYPE_INVALID = 0x44,
+	ERR_GC_CTX_LEN_INVALID = 0x45,
+	ERR_GC_CIPHER_UNSUPPORTED = 0x46,
+	ERR_GC_AUTH_UNSUPPORTED = 0x47,
+	ERR_GC_OFFSET_INVALID = 0x48,
+	ERR_GC_HASH_MODE_UNSUPPORTED = 0x49,
+	ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,
+	ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,
+	ERR_GC_ICV_MISCOMPARE = 0x4c,
+	ERR_GC_DATA_UNALIGNED = 0x4d,
+
+	/* API Layer */
+	ERR_BAD_ALT_CCODE = 0xfd,
+	ERR_REQ_PENDING = 0xfe,
+	ERR_REQ_TIMEOUT = 0xff,
+
+	ERR_BAD_INPUT_LENGTH = (0x40000000 | 384),    /* 0x40000180 */
+	ERR_BAD_KEY_LENGTH,
+	ERR_BAD_KEY_HANDLE,
+	ERR_BAD_CONTEXT_HANDLE,
+	ERR_BAD_SCALAR_LENGTH,
+	ERR_BAD_DIGEST_LENGTH,
+	ERR_BAD_INPUT_ARG,
+	ERR_BAD_RECORD_PADDING,
+	ERR_NB_REQUEST_PENDING,
+	ERR_EIO,
+	ERR_ENODEV,
+} mc_error_code_t;
 
 typedef struct sglist_comp {
 	union {
@@ -231,6 +298,49 @@ struct cpt_ctx {
 	uint8_t  auth_key[64];
 };
 
+/* Buffer pointer */
+typedef struct buf_ptr {
+	void *vaddr;
+	phys_addr_t dma_addr;
+	uint32_t size;
+	uint32_t resv;
+} buf_ptr_t;
+
+/* IOV Pointer */
+typedef struct{
+	int buf_cnt;
+	buf_ptr_t bufs[0];
+} iov_ptr_t;
+
+typedef union opcode_info {
+	uint16_t flags;
+	struct {
+		uint8_t major;
+		uint8_t minor;
+	} s;
+} opcode_info_t;
+
+typedef struct fc_params {
+	/* 0th cache line */
+	union {
+		buf_ptr_t bufs[1];
+		struct {
+			iov_ptr_t *src_iov;
+			iov_ptr_t *dst_iov;
+		};
+	};
+	void *iv_buf;
+	void *auth_iv_buf;
+	buf_ptr_t meta_buf;
+	buf_ptr_t ctx_buf;
+	uint64_t rsvd2;
+
+	/* 1st cache line */
+	buf_ptr_t aad_buf;
+	buf_ptr_t mac_buf;
+
+} fc_params_t;
+
 typedef struct fc_params digest_params_t;
 
 /* Cipher Algorithms */
@@ -239,8 +349,15 @@ typedef mc_cipher_type_t cipher_type_t;
 /* Auth Algorithms */
 typedef mc_hash_type_t auth_type_t;
 
+/* Helper macros */
+
 #define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
 
+#define SRC_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
+#define DST_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
+
 #define SESS_PRIV(__sess) \
 	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
 
-- 
2.7.4

[dpdk-dev] [PATCH v3 20/32] common/cpt: add microcode interface for encryption

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding microcode interface additions for supporting encryption.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 987 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 987 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 4bbb27a..f5247d5 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -5,6 +5,10 @@
 #ifndef _CPT_UCODE_H_
 #define _CPT_UCODE_H_
 
+#include <stdbool.h>
+
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
 #include "cpt_mcode_defines.h"
 
 /*
@@ -64,6 +68,14 @@ gen_key_snow3g(uint8_t *ck, uint32_t *keyx)
 	}
 }
 
+static __rte_always_inline void
+cpt_fc_salt_update(void *ctx,
+		   uint8_t *salt)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	memcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);
+}
+
 static __rte_always_inline int
 cpt_fc_ciph_validate_key_aes(uint16_t key_len)
 {
@@ -312,6 +324,550 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,
 	return 0;
 }
 
+static __rte_always_inline uint32_t
+fill_sg_comp(sg_comp_t *list,
+	     uint32_t i,
+	     phys_addr_t dma_addr,
+	     uint32_t size)
+{
+	sg_comp_t *to = &list[i>>2];
+
+	to->u.s.len[i%4] = rte_cpu_to_be_16(size);
+	to->ptr[i%4] = rte_cpu_to_be_64(dma_addr);
+	i++;
+	return i;
+}
+
+static __rte_always_inline uint32_t
+fill_sg_comp_from_buf(sg_comp_t *list,
+		      uint32_t i,
+		      buf_ptr_t *from)
+{
+	sg_comp_t *to = &list[i>>2];
+
+	to->u.s.len[i%4] = rte_cpu_to_be_16(from->size);
+	to->ptr[i%4] = rte_cpu_to_be_64(from->dma_addr);
+	i++;
+	return i;
+}
+
+static __rte_always_inline uint32_t
+fill_sg_comp_from_buf_min(sg_comp_t *list,
+			  uint32_t i,
+			  buf_ptr_t *from,
+			  uint32_t *psize)
+{
+	sg_comp_t *to = &list[i >> 2];
+	uint32_t size = *psize;
+	uint32_t e_len;
+
+	e_len = (size > from->size) ? from->size : size;
+	to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
+	to->ptr[i % 4] = rte_cpu_to_be_64(from->dma_addr);
+	*psize -= e_len;
+	i++;
+	return i;
+}
+
+/*
+ * This fills the MC expected SGIO list
+ * from IOV given by user.
+ */
+static __rte_always_inline uint32_t
+fill_sg_comp_from_iov(sg_comp_t *list,
+		      uint32_t i,
+		      iov_ptr_t *from, uint32_t from_offset,
+		      uint32_t *psize, buf_ptr_t *extra_buf,
+		      uint32_t extra_offset)
+{
+	int32_t j;
+	uint32_t extra_len = extra_buf ? extra_buf->size : 0;
+	uint32_t size = *psize - extra_len;
+	buf_ptr_t *bufs;
+
+	bufs = from->bufs;
+	for (j = 0; (j < from->buf_cnt) && size; j++) {
+		phys_addr_t e_dma_addr;
+		uint32_t e_len;
+		sg_comp_t *to = &list[i >> 2];
+
+		if (!bufs[j].size)
+			continue;
+
+		if (unlikely(from_offset)) {
+			if (from_offset >= bufs[j].size) {
+				from_offset -= bufs[j].size;
+				continue;
+			}
+			e_dma_addr = bufs[j].dma_addr + from_offset;
+			e_len = (size > (bufs[j].size - from_offset)) ?
+				(bufs[j].size - from_offset) : size;
+			from_offset = 0;
+		} else {
+			e_dma_addr = bufs[j].dma_addr;
+			e_len = (size > bufs[j].size) ?
+				bufs[j].size : size;
+		}
+
+		to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
+		to->ptr[i % 4] = rte_cpu_to_be_64(e_dma_addr);
+
+		if (extra_len && (e_len >= extra_offset)) {
+			/* Break the data at given offset */
+			uint32_t next_len = e_len - extra_offset;
+			phys_addr_t next_dma = e_dma_addr + extra_offset;
+
+			if (!extra_offset) {
+				i--;
+			} else {
+				e_len = extra_offset;
+				size -= e_len;
+				to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
+			}
+
+			/* Insert extra data ptr */
+			if (extra_len) {
+				i++;
+				to = &list[i >> 2];
+				to->u.s.len[i % 4] =
+					rte_cpu_to_be_16(extra_buf->size);
+				to->ptr[i % 4] =
+					rte_cpu_to_be_64(extra_buf->dma_addr);
+
+				/* size already decremented by extra len */
+			}
+
+			/* insert the rest of the data */
+			if (next_len) {
+				i++;
+				to = &list[i >> 2];
+				to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
+				to->ptr[i % 4] = rte_cpu_to_be_64(next_dma);
+				size -= next_len;
+			}
+			extra_len = 0;
+
+		} else {
+			size -= e_len;
+		}
+		if (extra_offset)
+			extra_offset -= size;
+		i++;
+	}
+
+	*psize = size;
+	return (uint32_t)i;
+}
+
+static __rte_always_inline int
+cpt_enc_hmac_prep(uint32_t flags,
+		  uint64_t d_offs,
+		  uint64_t d_lens,
+		  fc_params_t *fc_params,
+		  void *op,
+		  void **prep_req)
+{
+	uint32_t iv_offset = 0;
+	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t cipher_type, hash_type;
+	uint32_t mac_len, size;
+	uint8_t iv_len = 16;
+	struct cpt_request_info *req;
+	buf_ptr_t *meta_p, *aad_buf = NULL;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len, aad_len = 0;
+	uint32_t passthrough_len = 0;
+	void *m_vaddr, *offset_vaddr;
+	uint64_t m_dma, offset_dma, ctx_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr;
+	uint64_t c_dma;
+	int32_t m_size;
+	opcode_info_t opcode;
+
+	meta_p = &fc_params->meta_buf;
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs);
+	auth_offset = AUTH_OFFSET(d_offs);
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * We dont support both aad
+		 * and auth data separately
+		 */
+		auth_data_len = 0;
+		auth_offset = 0;
+		aad_len = fc_params->aad_buf.size;
+		aad_buf = &fc_params->aad_buf;
+	}
+	cpt_ctx = fc_params->ctx_buf.vaddr;
+	cipher_type = cpt_ctx->enc_cipher;
+	hash_type = cpt_ctx->hash_type;
+	mac_len = cpt_ctx->mac_len;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* start cpt request info struct at 8 byte boundary */
+	size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+		(uint8_t *)m_vaddr;
+
+	req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
+
+	size += sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	if (hash_type == GMAC_TYPE)
+		encr_data_len = 0;
+
+	if (unlikely(!(flags & VALID_IV_BUF))) {
+		iv_len = 0;
+		iv_offset = ENCR_IV_OFFSET(d_offs);
+	}
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * When AAD is given, data above encr_offset is pass through
+		 * Since AAD is given as separate pointer and not as offset,
+		 * this is a special case as we need to fragment input data
+		 * into passthrough + encr_data and then insert AAD in between.
+		 */
+		if (hash_type != GMAC_TYPE) {
+			passthrough_len = encr_offset;
+			auth_offset = passthrough_len + iv_len;
+			encr_offset = passthrough_len + aad_len + iv_len;
+			auth_data_len = aad_len + encr_data_len;
+		} else {
+			passthrough_len = 16 + aad_len;
+			auth_offset = passthrough_len + iv_len;
+			auth_data_len = aad_len;
+		}
+	} else {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/* Encryption */
+	opcode.s.major = CPT_MAJOR_OP_FC;
+	opcode.s.minor = 0;
+
+	auth_dlen = auth_offset + auth_data_len;
+	enc_dlen = encr_data_len + encr_offset;
+	if (unlikely(encr_data_len & 0xf)) {
+		if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
+			enc_dlen = ROUNDUP8(encr_data_len) + encr_offset;
+		else if (likely((cipher_type == AES_CBC) ||
+				(cipher_type == AES_ECB)))
+			enc_dlen = ROUNDUP16(encr_data_len) + encr_offset;
+	}
+
+	if (unlikely(hash_type == GMAC_TYPE)) {
+		encr_offset = auth_dlen;
+		enc_dlen = 0;
+	}
+
+	if (unlikely(auth_dlen > enc_dlen)) {
+		inputlen = auth_dlen;
+		outputlen = auth_dlen + mac_len;
+	} else {
+		inputlen = enc_dlen;
+		outputlen = enc_dlen + mac_len;
+	}
+
+	/* GP op header */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((flags & SINGLE_BUF_INPLACE) &&
+		   (flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = fc_params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+
+		/* This falls under strict SG mode */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+		size = OFF_CTRL_LEN + iv_len;
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+
+		i = 0;
+
+		/* Offset control word that includes iv */
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 OFF_CTRL_LEN + iv_len);
+
+		/* Add input data */
+		size = inputlen - iv_len;
+		if (likely(size)) {
+			uint32_t aad_offset = aad_len ? passthrough_len : 0;
+
+			if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+				i = fill_sg_comp_from_buf_min(gather_comp, i,
+							      fc_params->bufs,
+							      &size);
+			} else {
+				i = fill_sg_comp_from_iov(gather_comp, i,
+							  fc_params->src_iov,
+							  0, &size,
+							  aad_buf, aad_offset);
+			}
+
+			if (unlikely(size)) {
+				CPT_LOG_DP_ERR("Insufficient buffer space,"
+					       " size %d needed", size);
+				return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter list
+		 */
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* Add IV */
+		if (likely(iv_len)) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* output data or output data + digest*/
+		if (unlikely(flags & VALID_MAC_BUF)) {
+			size = outputlen - iv_len - mac_len;
+			if (size) {
+				uint32_t aad_offset =
+					aad_len ? passthrough_len : 0;
+
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+							scatter_comp,
+							i,
+							fc_params->bufs,
+							&size);
+				} else {
+					i = fill_sg_comp_from_iov(scatter_comp,
+							i,
+							fc_params->dst_iov,
+							0,
+							&size,
+							aad_buf,
+							aad_offset);
+				}
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+			/* mac_data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(scatter_comp, i,
+							  &fc_params->mac_buf);
+			}
+		} else {
+			/* Output including mac */
+			size = outputlen - iv_len;
+			if (likely(size)) {
+				uint32_t aad_offset =
+					aad_len ? passthrough_len : 0;
+
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+							scatter_comp,
+							i,
+							fc_params->bufs,
+							&size);
+				} else {
+					i = fill_sg_comp_from_iov(scatter_comp,
+							i,
+							fc_params->dst_iov,
+							0,
+							&size,
+							aad_buf,
+							aad_offset);
+				}
+				if (unlikely(size)) {
+					CPT_LOG_DP_ERR("Insufficient buffer"
+						       " space, size %d needed",
+						       size);
+					return ERR_BAD_INPUT_ARG;
+				}
+			}
+		}
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	ctx_dma = fc_params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, fctx);
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = ctx_dma;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op  = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline void *__hot
+cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
+		     fc_params_t *fc_params, void *op, int *ret_val)
+{
+	struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+	uint8_t fc_type;
+	void *prep_req = NULL;
+	int ret;
+
+	fc_type = ctx->fc_type;
+
+	/* Common api for rest of the ops */
+	if (likely(fc_type == FC_GEN)) {
+		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
+					fc_params, op, &prep_req);
+	} else {
+		ret = ERR_EIO;
+	}
+
+	if (unlikely(!prep_req))
+		*ret_val = ret;
+	return prep_req;
+}
+
 static __rte_always_inline int
 cpt_fc_auth_set_key(void *ctx, auth_type_t type, uint8_t *key,
 		    uint16_t key_len, uint16_t mac_len)
@@ -713,4 +1269,435 @@ fill_sess_gmac(struct rte_crypto_sym_xform *xform,
 	return 0;
 }
 
+static __rte_always_inline void *
+alloc_op_meta(struct rte_mbuf *m_src,
+	      buf_ptr_t *buf,
+	      int32_t len,
+	      struct rte_mempool *cpt_meta_pool)
+{
+	uint8_t *mdata;
+
+#ifndef CPT_ALWAYS_USE_SEPARATE_BUF
+	if (likely(m_src && (m_src->nb_segs == 1))) {
+		int32_t tailroom;
+		phys_addr_t mphys;
+
+		/* Check if tailroom is sufficient to hold meta data */
+		tailroom = rte_pktmbuf_tailroom(m_src);
+		if (likely(tailroom > len + 8)) {
+			mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;
+			mphys = m_src->buf_physaddr + m_src->buf_len;
+			mdata -= len;
+			mphys -= len;
+			buf->vaddr = mdata;
+			buf->dma_addr = mphys;
+			buf->size = len;
+			/* Indicate that this is a mbuf allocated mdata */
+			mdata = (uint8_t *)((uint64_t)mdata | 1ull);
+			return mdata;
+		}
+	}
+#else
+	RTE_SET_USED(m_src);
+#endif
+
+	if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))
+		return NULL;
+
+	buf->vaddr = mdata;
+	buf->dma_addr = rte_mempool_virt2iova(mdata);
+	buf->size = len;
+
+	return mdata;
+}
+
+/**
+ * cpt_free_metabuf - free metabuf to mempool.
+ * @param instance: pointer to instance.
+ * @param objp: pointer to the metabuf.
+ */
+static __rte_always_inline void
+free_op_meta(void *mdata, struct rte_mempool *cpt_meta_pool)
+{
+	bool nofree = ((uintptr_t)mdata & 1ull);
+
+	if (likely(nofree))
+		return;
+	rte_mempool_put(cpt_meta_pool, mdata);
+}
+
+static __rte_always_inline uint32_t
+prepare_iov_from_pkt(struct rte_mbuf *pkt,
+		     iov_ptr_t *iovec, uint32_t start_offset)
+{
+	uint16_t index = 0;
+	void *seg_data = NULL;
+	phys_addr_t seg_phys;
+	int32_t seg_size = 0;
+
+	if (!pkt) {
+		iovec->buf_cnt = 0;
+		return 0;
+	}
+
+	if (!start_offset) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+	} else {
+		while (start_offset >= pkt->data_len) {
+			start_offset -= pkt->data_len;
+			pkt = pkt->next;
+		}
+
+		seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);
+		seg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset);
+		seg_size = pkt->data_len - start_offset;
+		if (!seg_size)
+			return 1;
+	}
+
+	/* first seg */
+	iovec->bufs[index].vaddr = seg_data;
+	iovec->bufs[index].dma_addr = seg_phys;
+	iovec->bufs[index].size = seg_size;
+	index++;
+	pkt = pkt->next;
+
+	while (unlikely(pkt != NULL)) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+		if (!seg_size)
+			break;
+
+		iovec->bufs[index].vaddr = seg_data;
+		iovec->bufs[index].dma_addr = seg_phys;
+		iovec->bufs[index].size = seg_size;
+
+		index++;
+
+		pkt = pkt->next;
+	}
+
+	iovec->buf_cnt = index;
+	return 0;
+}
+
+static __rte_always_inline uint32_t
+prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,
+			     fc_params_t *param,
+			     uint32_t *flags)
+{
+	uint16_t index = 0;
+	void *seg_data = NULL;
+	phys_addr_t seg_phys;
+	uint32_t seg_size = 0;
+	iov_ptr_t *iovec;
+
+	seg_data = rte_pktmbuf_mtod(pkt, void *);
+	seg_phys = rte_pktmbuf_mtophys(pkt);
+	seg_size = pkt->data_len;
+
+	/* first seg */
+	if (likely(!pkt->next)) {
+		uint32_t headroom, tailroom;
+
+		*flags |= SINGLE_BUF_INPLACE;
+		headroom = rte_pktmbuf_headroom(pkt);
+		tailroom = rte_pktmbuf_tailroom(pkt);
+		if (likely((headroom >= 24) &&
+		    (tailroom >= 8))) {
+			/* In 83XX this is prerequivisit for Direct mode */
+			*flags |= SINGLE_BUF_HEADTAILROOM;
+		}
+		param->bufs[0].vaddr = seg_data;
+		param->bufs[0].dma_addr = seg_phys;
+		param->bufs[0].size = seg_size;
+		return 0;
+	}
+	iovec = param->src_iov;
+	iovec->bufs[index].vaddr = seg_data;
+	iovec->bufs[index].dma_addr = seg_phys;
+	iovec->bufs[index].size = seg_size;
+	index++;
+	pkt = pkt->next;
+
+	while (unlikely(pkt != NULL)) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+
+		if (!seg_size)
+			break;
+
+		iovec->bufs[index].vaddr = seg_data;
+		iovec->bufs[index].dma_addr = seg_phys;
+		iovec->bufs[index].size = seg_size;
+
+		index++;
+
+		pkt = pkt->next;
+	}
+
+	iovec->buf_cnt = index;
+	return 0;
+}
+
+static __rte_always_inline void *
+fill_fc_params(struct rte_crypto_op *cop,
+	       struct cpt_sess_misc *sess_misc,
+	       void **mdata_ptr,
+	       int *op_ret)
+{
+	uint32_t space = 0;
+	struct rte_crypto_sym_op *sym_op = cop->sym;
+	void *mdata;
+	uintptr_t *op;
+	uint32_t mc_hash_off;
+	uint32_t flags = 0;
+	uint64_t d_offs, d_lens;
+	void *prep_req = NULL;
+	struct rte_mbuf *m_src, *m_dst;
+	uint8_t cpt_op = sess_misc->cpt_op;
+	uint8_t zsk_flag = sess_misc->zsk_flag;
+	uint8_t aes_gcm = sess_misc->aes_gcm;
+	uint16_t mac_len = sess_misc->mac_len;
+#ifdef CPT_ALWAYS_USE_SG_MODE
+	uint8_t inplace = 0;
+#else
+	uint8_t inplace = 1;
+#endif
+	fc_params_t fc_params;
+	char src[SRC_IOV_SIZE];
+	char dst[SRC_IOV_SIZE];
+	uint32_t iv_buf[4];
+	struct cptvf_meta_info *cpt_m_info =
+				(struct cptvf_meta_info *)(*mdata_ptr);
+
+	if (likely(sess_misc->iv_length)) {
+		flags |= VALID_IV_BUF;
+		fc_params.iv_buf = rte_crypto_op_ctod_offset(cop,
+				   uint8_t *, sess_misc->iv_offset);
+		if (sess_misc->aes_ctr &&
+		    unlikely(sess_misc->iv_length != 16)) {
+			memcpy((uint8_t *)iv_buf,
+				rte_crypto_op_ctod_offset(cop,
+				uint8_t *, sess_misc->iv_offset), 12);
+			iv_buf[3] = rte_cpu_to_be_32(0x1);
+			fc_params.iv_buf = iv_buf;
+		}
+	}
+
+	if (zsk_flag) {
+		fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
+					uint8_t *,
+					sess_misc->auth_iv_offset);
+		if (zsk_flag == K_F9) {
+			CPT_LOG_DP_ERR("Should not reach here for "
+			"kasumi F9\n");
+		}
+		if (zsk_flag != ZS_EA)
+			inplace = 0;
+	}
+	m_src = sym_op->m_src;
+	m_dst = sym_op->m_dst;
+
+	if (aes_gcm) {
+		uint8_t *salt;
+		uint8_t *aad_data;
+		uint16_t aad_len;
+
+		d_offs = sym_op->aead.data.offset;
+		d_lens = sym_op->aead.data.length;
+		mc_hash_off = sym_op->aead.data.offset +
+			      sym_op->aead.data.length;
+
+		aad_data = sym_op->aead.aad.data;
+		aad_len = sess_misc->aad_length;
+		if (likely((aad_data + aad_len) ==
+			   rte_pktmbuf_mtod_offset(m_src,
+				uint8_t *,
+				sym_op->aead.data.offset))) {
+			d_offs = (d_offs - aad_len) | (d_offs << 16);
+			d_lens = (d_lens + aad_len) | (d_lens << 32);
+		} else {
+			fc_params.aad_buf.vaddr = sym_op->aead.aad.data;
+			fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;
+			fc_params.aad_buf.size = aad_len;
+			flags |= VALID_AAD_BUF;
+			inplace = 0;
+			d_offs = d_offs << 16;
+			d_lens = d_lens << 32;
+		}
+
+		salt = fc_params.iv_buf;
+		if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
+			cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
+			sess_misc->salt = *(uint32_t *)salt;
+		}
+		fc_params.iv_buf = salt + 4;
+		if (likely(mac_len)) {
+			struct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst :
+					     m_src;
+
+			if (!m)
+				m = m_src;
+
+			/* hmac immediately following data is best case */
+			if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
+			    mc_hash_off !=
+			    (uint8_t *)sym_op->aead.digest.data)) {
+				flags |= VALID_MAC_BUF;
+				fc_params.mac_buf.size = sess_misc->mac_len;
+				fc_params.mac_buf.vaddr =
+				  sym_op->aead.digest.data;
+				fc_params.mac_buf.dma_addr =
+				 sym_op->aead.digest.phys_addr;
+				inplace = 0;
+			}
+		}
+	} else {
+		d_offs = sym_op->cipher.data.offset;
+		d_lens = sym_op->cipher.data.length;
+		mc_hash_off = sym_op->cipher.data.offset +
+			      sym_op->cipher.data.length;
+		d_offs = (d_offs << 16) | sym_op->auth.data.offset;
+		d_lens = (d_lens << 32) | sym_op->auth.data.length;
+
+		if (mc_hash_off < (sym_op->auth.data.offset +
+				   sym_op->auth.data.length)){
+			mc_hash_off = (sym_op->auth.data.offset +
+				       sym_op->auth.data.length);
+		}
+		/* for gmac, salt should be updated like in gcm */
+		if (unlikely(sess_misc->is_gmac)) {
+			uint8_t *salt;
+			salt = fc_params.iv_buf;
+			if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
+				cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
+				sess_misc->salt = *(uint32_t *)salt;
+			}
+			fc_params.iv_buf = salt + 4;
+		}
+		if (likely(mac_len)) {
+			struct rte_mbuf *m;
+
+			m = (cpt_op & CPT_OP_ENCODE) ? m_dst : m_src;
+			if (!m)
+				m = m_src;
+
+			/* hmac immediately following data is best case */
+			if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
+			    mc_hash_off !=
+			     (uint8_t *)sym_op->auth.digest.data)) {
+				flags |= VALID_MAC_BUF;
+				fc_params.mac_buf.size =
+					sess_misc->mac_len;
+				fc_params.mac_buf.vaddr =
+					sym_op->auth.digest.data;
+				fc_params.mac_buf.dma_addr =
+				sym_op->auth.digest.phys_addr;
+				inplace = 0;
+			}
+		}
+	}
+	fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);
+	fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;
+
+	if (unlikely(sess_misc->is_null || sess_misc->cpt_op == CPT_OP_DECODE))
+		inplace = 0;
+
+	if (likely(!m_dst && inplace)) {
+		/* Case of single buffer without AAD buf or
+		 * separate mac buf in place and
+		 * not air crypto
+		 */
+		fc_params.dst_iov = fc_params.src_iov = (void *)src;
+
+		if (unlikely(prepare_iov_from_pkt_inplace(m_src,
+							  &fc_params,
+							  &flags))) {
+			CPT_LOG_DP_ERR("Prepare inplace src iov failed");
+			*op_ret = -1;
+			return NULL;
+		}
+
+	} else {
+		/* Out of place processing */
+		fc_params.src_iov = (void *)src;
+		fc_params.dst_iov = (void *)dst;
+
+		/* Store SG I/O in the api for reuse */
+		if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {
+			CPT_LOG_DP_ERR("Prepare src iov failed");
+			*op_ret = -1;
+			return NULL;
+		}
+
+		if (unlikely(m_dst != NULL)) {
+			uint32_t pkt_len;
+
+			/* Try to make room as much as src has */
+			m_dst = sym_op->m_dst;
+			pkt_len = rte_pktmbuf_pkt_len(m_dst);
+
+			if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {
+				pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;
+				if (!rte_pktmbuf_append(m_dst, pkt_len)) {
+					CPT_LOG_DP_ERR("Not enough space in "
+						       "m_dst %p, need %u"
+						       " more",
+						       m_dst, pkt_len);
+					return NULL;
+				}
+			}
+
+			if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {
+				CPT_LOG_DP_ERR("Prepare dst iov failed for "
+					       "m_dst %p", m_dst);
+				return NULL;
+			}
+		} else {
+			fc_params.dst_iov = (void *)src;
+		}
+	}
+
+	if (likely(flags & SINGLE_BUF_HEADTAILROOM))
+		mdata = alloc_op_meta(m_src,
+				      &fc_params.meta_buf,
+				      cpt_m_info->cptvf_op_sb_mlen,
+				      cpt_m_info->cptvf_meta_pool);
+	else
+		mdata = alloc_op_meta(NULL,
+				      &fc_params.meta_buf,
+				      cpt_m_info->cptvf_op_mlen,
+				      cpt_m_info->cptvf_meta_pool);
+
+	if (unlikely(mdata == NULL)) {
+		CPT_LOG_DP_ERR("Error allocating meta buffer for request");
+		return NULL;
+	}
+
+	op = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull);
+	op[0] = (uintptr_t)mdata;
+	op[1] = (uintptr_t)cop;
+	op[2] = op[3] = 0; /* Used to indicate auth verify */
+	space += 4 * sizeof(uint64_t);
+
+	fc_params.meta_buf.vaddr = (uint8_t *)op + space;
+	fc_params.meta_buf.dma_addr += space;
+	fc_params.meta_buf.size -= space;
+
+	/* Finally prepare the instruction */
+	if (cpt_op & CPT_OP_ENCODE)
+		prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
+						&fc_params, op, op_ret);
+
+	if (unlikely(!prep_req))
+		free_op_meta(mdata, cpt_m_info->cptvf_meta_pool);
+	*mdata_ptr = mdata;
+	return prep_req;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 21/32] common/cpt: add microcode interface for decryption

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding microcode interface additions for supporting decryption.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 417 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 417 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index f5247d5..9d4d4c8 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -844,6 +844,420 @@ cpt_enc_hmac_prep(uint32_t flags,
 	return 0;
 }
 
+static __rte_always_inline int
+cpt_dec_hmac_prep(uint32_t flags,
+		  uint64_t d_offs,
+		  uint64_t d_lens,
+		  fc_params_t *fc_params,
+		  void *op,
+		  void **prep_req)
+{
+	uint32_t iv_offset = 0, size;
+	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+	struct cpt_ctx *cpt_ctx;
+	int32_t hash_type, mac_len, m_size;
+	uint8_t iv_len = 16;
+	struct cpt_request_info *req;
+	buf_ptr_t *meta_p, *aad_buf = NULL;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len, aad_len = 0;
+	uint32_t passthrough_len = 0;
+	void *m_vaddr, *offset_vaddr;
+	uint64_t m_dma, offset_dma, ctx_dma;
+	opcode_info_t opcode;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr;
+	uint64_t c_dma;
+
+	meta_p = &fc_params->meta_buf;
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs);
+	auth_offset = AUTH_OFFSET(d_offs);
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * We dont support both aad
+		 * and auth data separately
+		 */
+		auth_data_len = 0;
+		auth_offset = 0;
+		aad_len = fc_params->aad_buf.size;
+		aad_buf = &fc_params->aad_buf;
+	}
+
+	cpt_ctx = fc_params->ctx_buf.vaddr;
+	hash_type = cpt_ctx->hash_type;
+	mac_len = cpt_ctx->mac_len;
+
+	if (hash_type == GMAC_TYPE)
+		encr_data_len = 0;
+
+	if (unlikely(!(flags & VALID_IV_BUF))) {
+		iv_len = 0;
+		iv_offset = ENCR_IV_OFFSET(d_offs);
+	}
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * When AAD is given, data above encr_offset is pass through
+		 * Since AAD is given as separate pointer and not as offset,
+		 * this is a special case as we need to fragment input data
+		 * into passthrough + encr_data and then insert AAD in between.
+		 */
+		if (hash_type != GMAC_TYPE) {
+			passthrough_len = encr_offset;
+			auth_offset = passthrough_len + iv_len;
+			encr_offset = passthrough_len + aad_len + iv_len;
+			auth_data_len = aad_len + encr_data_len;
+		} else {
+			passthrough_len = 16 + aad_len;
+			auth_offset = passthrough_len + iv_len;
+			auth_data_len = aad_len;
+		}
+	} else {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+	       (uint8_t *)m_vaddr;
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* start cpt request info structure at 8 byte alignment */
+	size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+		(uint8_t *)m_vaddr;
+
+	req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
+
+	size += sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Decryption */
+	opcode.s.major = CPT_MAJOR_OP_FC;
+	opcode.s.minor = 1;
+
+	enc_dlen = encr_offset + encr_data_len;
+	auth_dlen = auth_offset + auth_data_len;
+
+	if (auth_dlen > enc_dlen) {
+		inputlen = auth_dlen + mac_len;
+		outputlen = auth_dlen;
+	} else {
+		inputlen = enc_dlen + mac_len;
+		outputlen = enc_dlen;
+	}
+
+	if (hash_type == GMAC_TYPE)
+		encr_offset = inputlen;
+
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((flags & SINGLE_BUF_INPLACE) &&
+		   (flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = fc_params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+		req->ist.ei1 = offset_dma;
+
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr +
+					outputlen - iv_len);
+		/* since this is decryption,
+		 * don't touch the content of
+		 * alternate ccode space as it contains
+		 * hmac.
+		 */
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+						      OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+	} else {
+		uint64_t dptr_dma, rptr_dma;
+		uint32_t g_size_bytes, s_size_bytes;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint8_t i = 0;
+
+		/* This falls under strict SG mode */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+		size = OFF_CTRL_LEN + iv_len;
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+						      OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word that includes iv */
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 OFF_CTRL_LEN + iv_len);
+
+		/* Add input data */
+		if (flags & VALID_MAC_BUF) {
+			size = inputlen - iv_len - mac_len;
+			if (size) {
+				/* input data only */
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+							gather_comp, i,
+							fc_params->bufs,
+							&size);
+				} else {
+					uint32_t aad_offset = aad_len ?
+						passthrough_len : 0;
+
+					i = fill_sg_comp_from_iov(gather_comp,
+							i,
+							fc_params->src_iov,
+							0, &size,
+							aad_buf,
+							aad_offset);
+				}
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+
+			/* mac data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(gather_comp, i,
+							  &fc_params->mac_buf);
+			}
+		} else {
+			/* input data + mac */
+			size = inputlen - iv_len;
+			if (size) {
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+							gather_comp, i,
+							fc_params->bufs,
+							&size);
+				} else {
+					uint32_t aad_offset = aad_len ?
+						passthrough_len : 0;
+
+					if (!fc_params->src_iov)
+						return ERR_BAD_INPUT_ARG;
+
+					i = fill_sg_comp_from_iov(
+							gather_comp, i,
+							fc_params->src_iov,
+							0, &size,
+							aad_buf,
+							aad_offset);
+				}
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* Add iv */
+		if (iv_len) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* Add output data */
+		size = outputlen - iv_len;
+		if (size) {
+			if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+				/* handle single buffer here */
+				i = fill_sg_comp_from_buf_min(scatter_comp, i,
+							      fc_params->bufs,
+							      &size);
+			} else {
+				uint32_t aad_offset = aad_len ?
+					passthrough_len : 0;
+
+				if (!fc_params->dst_iov)
+					return ERR_BAD_INPUT_ARG;
+
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  fc_params->dst_iov, 0,
+							  &size, aad_buf,
+							  aad_offset);
+			}
+
+			if (unlikely(size))
+				return ERR_BAD_INPUT_ARG;
+		}
+
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+		size += COMPLETION_CODE_SIZE;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	ctx_dma = fc_params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, fctx);
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = ctx_dma;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline void *
+cpt_fc_dec_hmac_prep(uint32_t flags,
+		     uint64_t d_offs,
+		     uint64_t d_lens,
+		     fc_params_t *fc_params,
+		     void *op, int *ret_val)
+{
+	struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+	uint8_t fc_type;
+	void *prep_req = NULL;
+	int ret;
+
+	fc_type = ctx->fc_type;
+
+	if (likely(fc_type == FC_GEN)) {
+		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
+					fc_params, op, &prep_req);
+	} else {
+		/*
+		 * For AUTH_ONLY case,
+		 * MC only supports digest generation and verification
+		 * should be done in software by memcmp()
+		 */
+
+		ret = ERR_EIO;
+	}
+
+	if (unlikely(!prep_req))
+		*ret_val = ret;
+	return prep_req;
+}
+
 static __rte_always_inline void *__hot
 cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 		     fc_params_t *fc_params, void *op, int *ret_val)
@@ -1693,6 +2107,9 @@ fill_fc_params(struct rte_crypto_op *cop,
 	if (cpt_op & CPT_OP_ENCODE)
 		prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
 						&fc_params, op, op_ret);
+	else
+		prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,
+						&fc_params, op, op_ret);
 
 	if (unlikely(!prep_req))
 		free_op_meta(mdata, cpt_m_info->cptvf_meta_pool);
-- 
2.7.4

[dpdk-dev] [PATCH v3 22/32] common/cpt: add crypo op enqueue request manager framework

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding crypto enqueue op request manager framework. This routine won't
submit to the hardware yet.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_request_mgr.h | 68 ++++++++++++++++++++++++++++++++++++
 drivers/common/cpt/cpt_ucode.h       | 43 +++++++++++++++++++++++
 2 files changed, 111 insertions(+)

diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index fe184fe..58a87c3 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -5,8 +5,13 @@
 #ifndef _CPT_REQUEST_MGR_H_
 #define _CPT_REQUEST_MGR_H_
 
+#include "cpt_common.h"
 #include "cpt_mcode_defines.h"
 
+#if CPT_MODEL == CRYPTO_OCTEONTX
+#include "../../crypto/octeontx/otx_cryptodev_hw_access.h"
+#endif
+
 /*
  * This file defines the agreement between the common layer and the individual
  * crypto drivers for OCTEON TX series. Datapath in otx* directory include this
@@ -29,4 +34,67 @@ cpt_get_session_size(void)
 	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
 }
 
+static __rte_always_inline int __hot
+cpt_pmd_crypto_operation(struct cpt_instance *instance,
+		struct rte_crypto_op *op, struct pending_queue *pqueue,
+		uint8_t cpt_driver_id)
+{
+	struct cpt_sess_misc *sess = NULL;
+	struct rte_crypto_sym_op *sym_op = op->sym;
+	void *prep_req = NULL, *mdata = NULL;
+	int ret = 0;
+	uint64_t cpt_op;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	RTE_SET_USED(pqueue);
+
+	if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
+		int sess_len;
+
+		sess_len = cpt_get_session_size();
+
+		sess = rte_calloc(__func__, 1, sess_len, 8);
+		if (!sess)
+			return -ENOMEM;
+
+		sess->ctx_dma_addr =  rte_malloc_virt2iova(sess) +
+			sizeof(struct cpt_sess_misc);
+
+		ret = instance_session_cfg(sym_op->xform, (void *)sess);
+		if (unlikely(ret))
+			return -EINVAL;
+	} else {
+		sess = (struct cpt_sess_misc *)
+		get_sym_session_private_data(sym_op->session,
+		cpt_driver_id);
+	}
+
+	cpt_op = sess->cpt_op;
+
+	mdata = &(cptvf->meta_info);
+
+	if (likely(cpt_op & CPT_OP_CIPHER_MASK))
+		prep_req = fill_fc_params(op, sess, &mdata, &ret);
+
+	if (unlikely(!prep_req)) {
+		CPT_LOG_DP_ERR("prep cryto req : op %p, cpt_op 0x%x "
+			       "ret 0x%x", op, (unsigned int)cpt_op, ret);
+		goto req_fail;
+	}
+
+	if (unlikely(ret)) {
+		if (unlikely(ret == -EAGAIN))
+			goto req_fail;
+		CPT_LOG_DP_ERR("Error enqueing crypto request : error "
+			       "code %d", ret);
+		goto req_fail;
+	}
+
+	return 0;
+
+req_fail:
+	if (mdata)
+		free_op_meta(mdata, cptvf->meta_info.cptvf_meta_pool);
+	return ret;
+}
+
 #endif /* _CPT_REQUEST_MGR_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 9d4d4c8..9085667 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -2117,4 +2117,47 @@ fill_fc_params(struct rte_crypto_op *cop,
 	return prep_req;
 }
 
+static __rte_always_inline int
+instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
+{
+	struct rte_crypto_sym_xform *chain;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (cpt_is_algo_supported(xform))
+		goto err;
+
+	chain = xform;
+	while (chain) {
+		switch (chain->type) {
+		case RTE_CRYPTO_SYM_XFORM_AEAD:
+			if (fill_sess_aead(chain, sess))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_CIPHER:
+			if (fill_sess_cipher(chain, sess))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_AUTH:
+			if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
+				if (fill_sess_gmac(chain, sess))
+					goto err;
+			} else {
+				if (fill_sess_auth(chain, sess))
+					goto err;
+			}
+			break;
+		default:
+			CPT_LOG_DP_ERR("Invalid crypto xform type");
+			break;
+		}
+		chain = chain->next;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 23/32] common/cpt: add support for zuc and snow3g

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding microcode interface for supporting ZUC and SNOW3G.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 596 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 596 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 9085667..5d7743c 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -1226,6 +1226,596 @@ cpt_dec_hmac_prep(uint32_t flags,
 	return 0;
 }
 
+static __rte_always_inline int
+cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
+			uint64_t d_offs,
+			uint64_t d_lens,
+			fc_params_t *params,
+			void *op,
+			void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t mac_len = 0;
+	uint8_t snow3g, j;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset = 0, auth_offset = 0;
+	uint32_t encr_data_len = 0, auth_data_len = 0;
+	int flags, iv_len = 16, m_size;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma, offset_ctrl;
+	uint64_t *offset_vaddr, offset_dma;
+	uint32_t *iv_s, iv[4];
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	mac_len = cpt_ctx->mac_len;
+	snow3g = cpt_ctx->snow3g;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+	opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+			  (0 << 3) | (flags & 0x7));
+
+	if (flags == 0x1) {
+		/*
+		 * Microcode expects offsets in bytes
+		 * TODO: Rounding off
+		 */
+		auth_data_len = AUTH_DLEN(d_lens);
+
+		/* EIA3 or UIA2 */
+		auth_offset = AUTH_OFFSET(d_offs);
+		auth_offset = auth_offset / 8;
+
+		/* consider iv len */
+		auth_offset += iv_len;
+
+		inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
+		outputlen = mac_len;
+
+		offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
+
+	} else {
+		/* EEA3 or UEA2 */
+		/*
+		 * Microcode expects offsets in bytes
+		 * TODO: Rounding off
+		 */
+		encr_data_len = ENCR_DLEN(d_lens);
+
+		encr_offset = ENCR_OFFSET(d_offs);
+		encr_offset = encr_offset / 8;
+		/* consider iv len */
+		encr_offset += iv_len;
+
+		inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
+		outputlen = inputlen;
+
+		/* iv offset is 0 */
+		offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+	}
+
+	/* IV */
+	iv_s = (flags == 0x1) ? params->auth_iv_buf :
+		params->iv_buf;
+
+	if (snow3g) {
+		/*
+		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+		 */
+
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[3 - j];
+	} else {
+		/* ZUC doesn't need a swap */
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[j];
+	}
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+		   (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					    OFF_CTRL_LEN - iv_len);
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			memcpy(iv_d, iv, 16);
+		}
+
+		*offset_vaddr = offset_ctrl;
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint32_t *iv_d;
+
+		/* save space for iv */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+
+		m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+		m_dma += OFF_CTRL_LEN + iv_len;
+		m_size -= OFF_CTRL_LEN + iv_len;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word followed by iv */
+
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 OFF_CTRL_LEN + iv_len);
+
+		/* iv offset is 0 */
+		*offset_vaddr = offset_ctrl;
+
+		iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+		memcpy(iv_d, iv, 16);
+
+		/* input data */
+		size = inputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(gather_comp, i,
+						  params->src_iov,
+						  0, &size, NULL, 0);
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		if (flags == 0x1) {
+			/* IV in SLIST only for EEA3 & UEA2 */
+			iv_len = 0;
+		}
+
+		if (iv_len) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN, iv_len);
+		}
+
+		/* Add output data */
+		if (req_flags & VALID_MAC_BUF) {
+			size = outputlen - iv_len - mac_len;
+			if (size) {
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  params->dst_iov, 0,
+							  &size, NULL, 0);
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+
+			/* mac data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(scatter_comp, i,
+							  &params->mac_buf);
+			}
+		} else {
+			/* Output including mac */
+			size = outputlen - iv_len;
+			if (size) {
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  params->dst_iov, 0,
+							  &size, NULL, 0);
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, zs_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
+			uint64_t d_offs,
+			uint64_t d_lens,
+			fc_params_t *params,
+			void *op,
+			void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint8_t snow3g, iv_len = 16;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset;
+	uint32_t encr_data_len;
+	int flags, m_size;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	uint32_t *iv_s, iv[4], j;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	/*
+	 * Microcode expects offsets in bytes
+	 * TODO: Rounding off
+	 */
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	snow3g = cpt_ctx->snow3g;
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+	opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+			  (0 << 3) | (flags & 0x7));
+
+	/* consider iv len */
+	encr_offset += iv_len;
+
+	inputlen = encr_offset +
+		(RTE_ALIGN(encr_data_len, 8) / 8);
+	outputlen = inputlen;
+
+	/* IV */
+	iv_s = params->iv_buf;
+	if (snow3g) {
+		/*
+		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+		 */
+
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[3 - j];
+	} else {
+		/* ZUC doesn't need a swap */
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[j];
+	}
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+		   (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					    OFF_CTRL_LEN - iv_len);
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			memcpy(iv_d, iv, 16);
+		}
+
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint32_t *iv_d;
+
+		/* save space for offset and iv... */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+
+		m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+		m_dma += OFF_CTRL_LEN + iv_len;
+		m_size -= OFF_CTRL_LEN + iv_len;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word */
+
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 OFF_CTRL_LEN + iv_len);
+
+		iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+		memcpy(iv_d, iv, 16);
+
+		/* Add input data */
+		size = inputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(gather_comp, i,
+						  params->src_iov,
+						  0, &size, NULL, 0);
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* IV */
+		i = fill_sg_comp(scatter_comp, i,
+				 offset_dma + OFF_CTRL_LEN,
+				 iv_len);
+
+		/* Add output data */
+		size = outputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, zs_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
 static __rte_always_inline void *
 cpt_fc_dec_hmac_prep(uint32_t flags,
 		     uint64_t d_offs,
@@ -1243,6 +1833,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,
 	if (likely(fc_type == FC_GEN)) {
 		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
 					fc_params, op, &prep_req);
+	} else if (fc_type == ZUC_SNOW3G) {
+		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
+					      fc_params, op, &prep_req);
 	} else {
 		/*
 		 * For AUTH_ONLY case,
@@ -1273,6 +1866,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	if (likely(fc_type == FC_GEN)) {
 		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
 					fc_params, op, &prep_req);
+	} else if (fc_type == ZUC_SNOW3G) {
+		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
+					      fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
-- 
2.7.4

[dpdk-dev] [PATCH v3 24/32] common/cpt: add support for kasumi

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding microcode interface for supporting kasumi.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 450 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 450 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 5d7743c..05cf95c 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -1816,6 +1816,450 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
 	return 0;
 }
 
+static __rte_always_inline int
+cpt_kasumi_enc_prep(uint32_t req_flags,
+		    uint64_t d_offs,
+		    uint64_t d_lens,
+		    fc_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen = 0;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t mac_len = 0;
+	uint8_t i = 0;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len;
+	int flags, m_size;
+	uint8_t *iv_s, *iv_d, iv_len = 8;
+	uint8_t dir = 0;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	auth_offset = AUTH_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	mac_len = cpt_ctx->mac_len;
+
+	if (flags == 0x0)
+		iv_s = params->iv_buf;
+	else
+		iv_s = params->auth_iv_buf;
+
+	dir = iv_s[8] & 0x1;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
+
+	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
+	opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
+			  (dir << 4) | (0 << 3) | (flags & 0x7));
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+	vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+	/* consider iv len */
+	if (flags == 0x0) {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/* save space for offset ctrl and iv */
+	offset_vaddr = m_vaddr;
+	offset_dma = m_dma;
+
+	m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+	m_dma += OFF_CTRL_LEN + iv_len;
+	m_size -= OFF_CTRL_LEN + iv_len;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input Gather List
+	 */
+	i = 0;
+
+	/* Offset control word followed by iv */
+
+	if (flags == 0x0) {
+		inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
+		outputlen = inputlen;
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+	} else {
+		inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
+		outputlen = mac_len;
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
+	}
+
+	i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
+
+	/* IV */
+	iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;
+	memcpy(iv_d, iv_s, iv_len);
+
+	/* input data */
+	size = inputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i,
+					  params->src_iov, 0,
+					  &size, NULL, 0);
+
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	if (flags == 0x1) {
+		/* IV in SLIST only for F8 */
+		iv_len = 0;
+	}
+
+	/* IV */
+	if (iv_len) {
+		i = fill_sg_comp(scatter_comp, i,
+				 offset_dma + OFF_CTRL_LEN,
+				 iv_len);
+	}
+
+	/* Add output data */
+	if (req_flags & VALID_MAC_BUF) {
+		size = outputlen - iv_len - mac_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+
+		/* mac data */
+		if (mac_len) {
+			i = fill_sg_comp_from_buf(scatter_comp, i,
+						  &params->mac_buf);
+		}
+	} else {
+		/* Output including mac */
+		size = outputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+	}
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, k_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_kasumi_dec_prep(uint64_t d_offs,
+		    uint64_t d_lens,
+		    fc_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint8_t i = 0, iv_len = 8;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset;
+	uint32_t encr_data_len;
+	int flags, m_size;
+	uint8_t dir = 0;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
+
+	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
+	opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
+			  (dir << 4) | (0 << 3) | (flags & 0x7));
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+	/* consider iv len */
+	encr_offset += iv_len;
+
+	inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);
+	outputlen = inputlen;
+
+	/* save space for offset ctrl & iv */
+	offset_vaddr = m_vaddr;
+	offset_dma = m_dma;
+
+	m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+	m_dma += OFF_CTRL_LEN + iv_len;
+	m_size -= OFF_CTRL_LEN + iv_len;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input Gather List
+	 */
+	i = 0;
+
+	/* Offset control word followed by iv */
+	*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+
+	i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
+
+	/* IV */
+	memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+	       params->iv_buf, iv_len);
+
+	/* Add input data */
+	size = inputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i,
+					  params->src_iov,
+					  0, &size, NULL, 0);
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	/* IV */
+	i = fill_sg_comp(scatter_comp, i,
+			 offset_dma + OFF_CTRL_LEN,
+			 iv_len);
+
+	/* Add output data */
+	size = outputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(scatter_comp, i,
+					  params->dst_iov, 0,
+					  &size, NULL, 0);
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, k_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
 static __rte_always_inline void *
 cpt_fc_dec_hmac_prep(uint32_t flags,
 		     uint64_t d_offs,
@@ -1836,6 +2280,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,
 	} else if (fc_type == ZUC_SNOW3G) {
 		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
 					      fc_params, op, &prep_req);
+	} else if (fc_type == KASUMI) {
+		ret = cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, op,
+					  &prep_req);
 	} else {
 		/*
 		 * For AUTH_ONLY case,
@@ -1869,6 +2316,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	} else if (fc_type == ZUC_SNOW3G) {
 		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
 					      fc_params, op, &prep_req);
+	} else if (fc_type == KASUMI) {
+		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,
+					  fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
-- 
2.7.4

[dpdk-dev] [PATCH v3 25/32] common/cpt: add support for hash

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding microcode interface for supporting verify and authentication

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h |   7 +
 drivers/common/cpt/cpt_request_mgr.h   |   2 +
 drivers/common/cpt/cpt_ucode.h         | 415 ++++++++++++++++++++++++++++++++-
 3 files changed, 423 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 263fc47..60be8b3 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -18,6 +18,7 @@
 #define CPT_MAJOR_OP_HMAC	0x35
 #define CPT_MAJOR_OP_ZUC_SNOW3G	0x37
 #define CPT_MAJOR_OP_KASUMI	0x38
+#define CPT_MAJOR_OP_MISC	0x01
 
 #define CPT_BYTE_16		16
 #define CPT_BYTE_24		24
@@ -341,6 +342,12 @@ typedef struct fc_params {
 
 } fc_params_t;
 
+/*
+ * Parameters for digest
+ * generate requests
+ * Only src_iov, op, ctx_buf, mac_buf, prep_req
+ * meta_buf, auth_data_len are used for digest gen.
+ */
 typedef struct fc_params digest_params_t;
 
 /* Cipher Algorithms */
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index 58a87c3..4d21f46 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -74,6 +74,8 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 
 	if (likely(cpt_op & CPT_OP_CIPHER_MASK))
 		prep_req = fill_fc_params(op, sess, &mdata, &ret);
+	else
+		prep_req = fill_digest_params(op, sess, &mdata, &ret);
 
 	if (unlikely(!prep_req)) {
 		CPT_LOG_DP_ERR("prep cryto req : op %p, cpt_op 0x%x "
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 05cf95c..4d892f2 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -4,7 +4,6 @@
 
 #ifndef _CPT_UCODE_H_
 #define _CPT_UCODE_H_
-
 #include <stdbool.h>
 
 #include "cpt_common.h"
@@ -460,6 +459,214 @@ fill_sg_comp_from_iov(sg_comp_t *list,
 }
 
 static __rte_always_inline int
+cpt_digest_gen_prep(uint32_t flags,
+		    uint64_t d_lens,
+		    digest_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	struct cpt_request_info *req;
+	uint32_t size, i;
+	int32_t m_size;
+	uint16_t data_len, mac_len, key_len;
+	auth_type_t hash_type;
+	buf_ptr_t *meta_p;
+	struct cpt_ctx *ctx;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr, *m_vaddr;
+	uint64_t c_dma, m_dma;
+	opcode_info_t opcode;
+
+	if (!params || !params->ctx_buf.vaddr)
+		return ERR_BAD_INPUT_ARG;
+
+	ctx = params->ctx_buf.vaddr;
+	meta_p = &params->meta_buf;
+
+	if (!meta_p->vaddr || !meta_p->dma_addr)
+		return ERR_BAD_INPUT_ARG;
+
+	if (meta_p->size < sizeof(struct cpt_request_info))
+		return ERR_BAD_INPUT_ARG;
+
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	hash_type = ctx->hash_type;
+	mac_len = ctx->mac_len;
+	key_len = ctx->auth_key_len;
+	data_len = AUTH_DLEN(d_lens);
+
+	/*GP op header */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(((uint16_t)hash_type << 8));
+	if (ctx->hmac) {
+		opcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;
+		vq_cmd_w0.s.param1 = rte_cpu_to_be_16(key_len);
+		vq_cmd_w0.s.dlen =
+			rte_cpu_to_be_16((data_len + ROUNDUP8(key_len)));
+	} else {
+		opcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;
+		vq_cmd_w0.s.param1 = 0;
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(data_len);
+	}
+
+	opcode.s.minor = 0;
+
+	/* Null auth only case enters the if */
+	if (unlikely(!hash_type && !ctx->enc_cipher)) {
+		opcode.s.major = CPT_MAJOR_OP_MISC;
+		/* Minor op is passthrough */
+		opcode.s.minor = 0x03;
+		/* Send out completion code only */
+		vq_cmd_w0.s.param2 = 0x1;
+	}
+
+	vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input gather list
+	 */
+
+	i = 0;
+
+	if (ctx->hmac) {
+		uint64_t k_dma = params->ctx_buf.dma_addr +
+			offsetof(struct cpt_ctx, auth_key);
+		/* Key */
+		i = fill_sg_comp(gather_comp, i, k_dma, ROUNDUP8(key_len));
+	}
+
+	/* input data */
+	size = data_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,
+					  0, &size, NULL, 0);
+		if (size) {
+			CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short"
+					 " by %dB", size);
+			return ERR_BAD_INPUT_ARG;
+		}
+	} else {
+		/*
+		 * Looks like we need to support zero data
+		 * gather ptr in case of hash & hmac
+		 */
+		i++;
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Gather list
+	 */
+
+	i = 0;
+	scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	if (flags & VALID_MAC_BUF) {
+		if (params->mac_buf.size < mac_len)
+			return ERR_BAD_INPUT_ARG;
+
+		size = mac_len;
+		i = fill_sg_comp_from_buf_min(scatter_comp, i,
+					      &params->mac_buf, &size);
+	} else {
+		size = mac_len;
+		i = fill_sg_comp_from_iov(scatter_comp, i,
+					  params->src_iov, data_len,
+					  &size, NULL, 0);
+		if (size) {
+			CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short by"
+					 " %dB", size);
+			return ERR_BAD_INPUT_ARG;
+		}
+	}
+
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline int
 cpt_enc_hmac_prep(uint32_t flags,
 		  uint64_t d_offs,
 		  uint64_t d_lens,
@@ -2319,6 +2526,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	} else if (fc_type == KASUMI) {
 		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,
 					  fc_params, op, &prep_req);
+	} else if (fc_type == HASH_HMAC) {
+		ret = cpt_digest_gen_prep(flags, d_lens, fc_params, op,
+					  &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
@@ -3206,4 +3416,207 @@ instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
 	return -1;
 }
 
+static __rte_always_inline void
+find_kasumif9_direction_and_length(uint8_t *src,
+				   uint32_t counter_num_bytes,
+				   uint32_t *addr_length_in_bits,
+				   uint8_t *addr_direction)
+{
+	uint8_t found = 0;
+	while (!found && counter_num_bytes > 0) {
+		counter_num_bytes--;
+		if (src[counter_num_bytes] == 0x00)
+			continue;
+		if (src[counter_num_bytes] == 0x80) {
+			*addr_direction  =  src[counter_num_bytes - 1] & 0x1;
+			*addr_length_in_bits = counter_num_bytes * 8  - 1;
+			found = 1;
+		} else {
+			int i = 0;
+			uint8_t last_byte = src[counter_num_bytes];
+			for (i = 0; i < 8 && found == 0; i++) {
+				if (last_byte & (1 << i)) {
+					*addr_direction = (last_byte >> (i+1))
+							  & 0x1;
+					if (i != 6)
+						*addr_length_in_bits =
+							counter_num_bytes * 8
+							+ (8 - (i + 2));
+					else
+						*addr_length_in_bits =
+							counter_num_bytes * 8;
+					found = 1;
+					}
+				}
+			}
+	}
+}
+
+/*
+ * This handles all auth only except AES_GMAC
+ */
+static __rte_always_inline void *
+fill_digest_params(struct rte_crypto_op *cop,
+		   struct cpt_sess_misc *sess,
+		   void **mdata_ptr,
+		   int *op_ret)
+{
+	uint32_t space = 0;
+	struct rte_crypto_sym_op *sym_op = cop->sym;
+	void *mdata;
+	phys_addr_t mphys;
+	uint64_t *op;
+	uint32_t auth_range_off;
+	uint32_t flags = 0;
+	uint64_t d_offs = 0, d_lens;
+	void *prep_req = NULL;
+	struct rte_mbuf *m_src, *m_dst;
+	uint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK;
+	uint8_t zsk_flag = sess->zsk_flag;
+	uint16_t mac_len = sess->mac_len;
+	fc_params_t params;
+	char src[SRC_IOV_SIZE];
+	uint8_t iv_buf[16];
+	memset(&params, 0, sizeof(fc_params_t));
+	struct cptvf_meta_info *cpt_m_info =
+				(struct cptvf_meta_info *)(*mdata_ptr);
+
+	m_src = sym_op->m_src;
+
+	/* For just digest lets force mempool alloc */
+	mdata = alloc_op_meta(NULL, &params.meta_buf, cpt_m_info->cptvf_op_mlen,
+			      cpt_m_info->cptvf_meta_pool);
+	if (mdata == NULL) {
+		CPT_LOG_DP_ERR("Error allocating meta buffer for request");
+		*op_ret = -ENOMEM;
+		return NULL;
+	}
+
+	mphys = params.meta_buf.dma_addr;
+
+	op = mdata;
+	op[0] = (uintptr_t)mdata;
+	op[1] = (uintptr_t)cop;
+	op[2] = op[3] = 0; /* Used to indicate auth verify */
+	space += 4 * sizeof(uint64_t);
+
+	auth_range_off = sym_op->auth.data.offset;
+
+	flags = VALID_MAC_BUF;
+	params.src_iov = (void *)src;
+	if (unlikely(zsk_flag)) {
+		/*
+		 * Since for Zuc, Kasumi, Snow3g offsets are in bits
+		 * we will send pass through even for auth only case,
+		 * let MC handle it
+		 */
+		d_offs = auth_range_off;
+		auth_range_off = 0;
+		params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
+					uint8_t *, sess->auth_iv_offset);
+		if (zsk_flag == K_F9) {
+			uint32_t length_in_bits, num_bytes;
+			uint8_t *src, direction = 0;
+			uint32_t counter_num_bytes;
+
+			memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,
+							uint8_t *), 8);
+			/*
+			 * This is kasumi f9, take direction from
+			 * source buffer
+			 */
+			length_in_bits = cop->sym->auth.data.length;
+			num_bytes = (length_in_bits >> 3);
+			counter_num_bytes = num_bytes;
+			src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);
+			find_kasumif9_direction_and_length(src,
+						counter_num_bytes,
+						&length_in_bits,
+						&direction);
+			length_in_bits -= 64;
+			cop->sym->auth.data.offset += 64;
+			d_offs = cop->sym->auth.data.offset;
+			auth_range_off = d_offs / 8;
+			cop->sym->auth.data.length = length_in_bits;
+
+			/* Store it at end of auth iv */
+			iv_buf[8] = direction;
+			params.auth_iv_buf = iv_buf;
+		}
+	}
+
+	d_lens = sym_op->auth.data.length;
+
+	params.ctx_buf.vaddr = SESS_PRIV(sess);
+	params.ctx_buf.dma_addr = sess->ctx_dma_addr;
+
+	if (auth_op == CPT_OP_AUTH_GENERATE) {
+		if (sym_op->auth.digest.data) {
+			/*
+			 * Digest to be generated
+			 * in separate buffer
+			 */
+			params.mac_buf.size =
+				sess->mac_len;
+			params.mac_buf.vaddr =
+				sym_op->auth.digest.data;
+			params.mac_buf.dma_addr =
+				sym_op->auth.digest.phys_addr;
+		} else {
+			uint32_t off = sym_op->auth.data.offset +
+				sym_op->auth.data.length;
+			int32_t dlen, space;
+
+			m_dst = sym_op->m_dst ?
+				sym_op->m_dst : sym_op->m_src;
+			dlen = rte_pktmbuf_pkt_len(m_dst);
+
+			space = off + mac_len - dlen;
+			if (space > 0)
+				if (!rte_pktmbuf_append(m_dst, space)) {
+					CPT_LOG_DP_ERR("Failed to extend "
+						       "mbuf by %uB", space);
+					goto err;
+				}
+
+			params.mac_buf.vaddr =
+				rte_pktmbuf_mtod_offset(m_dst, void *, off);
+			params.mac_buf.dma_addr =
+				rte_pktmbuf_mtophys_offset(m_dst, off);
+			params.mac_buf.size = mac_len;
+		}
+	} else {
+		/* Need space for storing generated mac */
+		params.mac_buf.vaddr = (uint8_t *)mdata + space;
+		params.mac_buf.dma_addr = mphys + space;
+		params.mac_buf.size = mac_len;
+		space += RTE_ALIGN_CEIL(mac_len, 8);
+		op[2] = (uintptr_t)params.mac_buf.vaddr;
+		op[3] = mac_len;
+	}
+
+	params.meta_buf.vaddr = (uint8_t *)mdata + space;
+	params.meta_buf.dma_addr = mphys + space;
+	params.meta_buf.size -= space;
+
+	/* Out of place processing */
+	params.src_iov = (void *)src;
+
+	/*Store SG I/O in the api for reuse */
+	if (prepare_iov_from_pkt(m_src, params.src_iov, auth_range_off)) {
+		CPT_LOG_DP_ERR("Prepare src iov failed");
+		*op_ret = -1;
+		goto err;
+	}
+
+	prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
+					&params, op, op_ret);
+	*mdata_ptr = mdata;
+	return prep_req;
+err:
+	if (unlikely(!prep_req))
+		free_op_meta(mdata, cpt_m_info->cptvf_meta_pool);
+	return NULL;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 26/32] crypto/octeontx: add routines to prepare instructions

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding hardware specific routines which prepare cpt instructions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 56 +++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 2698df6..affbba1 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -7,11 +7,14 @@
 
 #include <stdbool.h>
 
+#include <rte_branch_prediction.h>
 #include <rte_io.h>
 #include <rte_memory.h>
+#include <rte_prefetch.h>
 
 #include "cpt_common.h"
 #include "cpt_hw_types.h"
+#include "cpt_pmd_logs.h"
 
 #define CPT_INTR_POLL_INTERVAL_MS	(50)
 
@@ -184,4 +187,57 @@ otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
 	return vqx_dbell.s.dbell_cnt;
 }
 
+static __rte_always_inline void *
+get_cpt_inst(struct command_queue *cqueue)
+{
+	CPT_LOG_DP_DEBUG("CPT queue idx %u\n", cqueue->idx);
+	return &cqueue->qhead[cqueue->idx * CPT_INST_SIZE];
+}
+
+static __rte_always_inline void
+fill_cpt_inst(struct cpt_instance *instance, void *req)
+{
+	struct command_queue *cqueue;
+	cpt_inst_s_t *cpt_ist_p;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct cpt_request_info *user_req = (struct cpt_request_info *)req;
+	cqueue = &cptvf->cqueue;
+	cpt_ist_p = get_cpt_inst(cqueue);
+	rte_prefetch_non_temporal(cpt_ist_p);
+
+	/* EI0, EI1, EI2, EI3 are already prepared */
+	/* HW W0 */
+	cpt_ist_p->u[0] = 0;
+	/* HW W1 */
+	cpt_ist_p->s8x.res_addr = user_req->comp_baddr;
+	/* HW W2 */
+	cpt_ist_p->u[2] = 0;
+	/* HW W3 */
+	cpt_ist_p->s8x.wq_ptr = 0;
+
+	/* MC EI0 */
+	cpt_ist_p->s8x.ei0 = user_req->ist.ei0;
+	/* MC EI1 */
+	cpt_ist_p->s8x.ei1 = user_req->ist.ei1;
+	/* MC EI2 */
+	cpt_ist_p->s8x.ei2 = user_req->ist.ei2;
+	/* MC EI3 */
+	cpt_ist_p->s8x.ei3 = user_req->ist.ei3;
+}
+
+static __rte_always_inline void
+mark_cpt_inst(struct cpt_instance *instance)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct command_queue *queue = &cptvf->cqueue;
+	if (unlikely(++queue->idx >= DEFAULT_CMD_QCHUNK_SIZE)) {
+		uint32_t cchunk = queue->cchunk;
+		MOD_INC(cchunk, DEFAULT_CMD_QCHUNKS);
+		queue->qhead = queue->chead[cchunk].head;
+		queue->idx = 0;
+		queue->cchunk = cchunk;
+	}
+
+}
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v3 27/32] common/cpt: add common code for enqueuing cpt instruction

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h      |  3 +++
 drivers/common/cpt/cpt_request_mgr.h | 46 +++++++++++++++++++++++++++++++++++-
 2 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 7333c13..1823939 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -15,6 +15,9 @@
  */
 #define CRYPTO_OCTEONTX		0x1
 
+/* Default command timeout in seconds */
+#define DEFAULT_COMMAND_TIMEOUT	4
+
 #define CPT_COUNT_THOLD		32
 #define CPT_TIMER_THOLD		0x3F
 
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index 4d21f46..dea89f8 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -5,6 +5,9 @@
 #ifndef _CPT_REQUEST_MGR_H_
 #define _CPT_REQUEST_MGR_H_
 
+#include <rte_branch_prediction.h>
+#include <rte_cycles.h>
+
 #include "cpt_common.h"
 #include "cpt_mcode_defines.h"
 
@@ -34,6 +37,45 @@ cpt_get_session_size(void)
 	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
 }
 
+static __rte_always_inline int32_t __hot
+cpt_enqueue_req(struct cpt_instance *instance, struct pending_queue *pqueue,
+		void *req)
+{
+	struct cpt_request_info *user_req = (struct cpt_request_info *)req;
+	int32_t ret = 0;
+
+	if (unlikely(!req))
+		return 0;
+
+	if (unlikely(pqueue->pending_count >= DEFAULT_CMD_QLEN))
+		return -EAGAIN;
+
+	fill_cpt_inst(instance, req);
+
+	CPT_LOG_DP_DEBUG("req: %p op: %p ", req, user_req->op);
+
+	/* Fill time_out cycles */
+	user_req->time_out = rte_get_timer_cycles() +
+			DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
+	user_req->extra_time = 0;
+
+	/* Default mode of software queue */
+	mark_cpt_inst(instance);
+
+	pqueue->rid_queue[pqueue->enq_tail].rid =
+		(uintptr_t)user_req;
+	/* We will use soft queue length here to limit
+	 * requests
+	 */
+	MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);
+	pqueue->pending_count += 1;
+
+	CPT_LOG_DP_DEBUG("Submitted NB cmd with request: %p "
+			 "op: %p", user_req, user_req->op);
+
+	return ret;
+}
+
 static __rte_always_inline int __hot
 cpt_pmd_crypto_operation(struct cpt_instance *instance,
 		struct rte_crypto_op *op, struct pending_queue *pqueue,
@@ -45,7 +87,6 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 	int ret = 0;
 	uint64_t cpt_op;
 	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
-	RTE_SET_USED(pqueue);
 
 	if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 		int sess_len;
@@ -83,6 +124,9 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 		goto req_fail;
 	}
 
+	/* Enqueue prepared instruction to HW */
+	ret = cpt_enqueue_req(instance, pqueue, prep_req);
+
 	if (unlikely(ret)) {
 		if (unlikely(ret == -EAGAIN))
 			goto req_fail;
-- 
2.7.4

[dpdk-dev] [PATCH v3 28/32] crypto/octeontx: add enqueue burst op

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 18 +++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 27 ++++++++++++++++++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index affbba1..6f4d6e1 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -187,6 +187,15 @@ otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
 	return vqx_dbell.s.dbell_cnt;
 }
 
+static __rte_always_inline void
+otx_cpt_ring_dbell(struct cpt_instance *instance, uint16_t count)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	/* Memory barrier to flush pending writes */
+	rte_smp_wmb();
+	otx_cpt_write_vq_doorbell(cptvf, count);
+}
+
 static __rte_always_inline void *
 get_cpt_inst(struct command_queue *cqueue)
 {
@@ -237,7 +246,16 @@ mark_cpt_inst(struct cpt_instance *instance)
 		queue->idx = 0;
 		queue->cchunk = cchunk;
 	}
+}
 
+static __rte_always_inline uint8_t
+check_nb_command_id(struct cpt_request_info *user_req,
+		struct cpt_instance *instance)
+{
+	/* Required for dequeue operation. Adding a dummy routine for now */
+	RTE_SET_USED(user_req);
+	RTE_SET_USED(instance);
+	return 0;
 }
 
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 16fad49..4240051 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -341,6 +341,31 @@ otx_cpt_session_clear(struct rte_cryptodev *dev,
 	}
 }
 
+static uint16_t
+otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	struct cpt_instance *instance = (struct cpt_instance *)qptr;
+	uint16_t count = 0;
+	int ret;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct pending_queue *pqueue = &cptvf->pqueue;
+
+	count = DEFAULT_CMD_QLEN - pqueue->pending_count;
+	if (nb_ops > count)
+		nb_ops = count;
+
+	count = 0;
+	while (likely(count < nb_ops)) {
+		ret = cpt_pmd_crypto_operation(instance, ops[count], pqueue,
+						otx_cryptodev_driver_id);
+		if (unlikely(ret))
+			break;
+		count++;
+	}
+	otx_cpt_ring_dbell(instance, count);
+	return count;
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -432,7 +457,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 
 	c_dev->dev_ops = &cptvf_ops;
 
-	c_dev->enqueue_burst = NULL;
+	c_dev->enqueue_burst = otx_cpt_pkt_enqueue;
 	c_dev->dequeue_burst = NULL;
 
 	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
-- 
2.7.4

[dpdk-dev] [PATCH v3 29/32] common/cpt: add common code for cpt dequeue

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h        |  2 ++
 drivers/common/cpt/cpt_mcode_defines.h | 15 +++++++++++++
 drivers/common/cpt/cpt_request_mgr.h   | 39 ++++++++++++++++++++++++++++++++++
 drivers/common/cpt/cpt_ucode.h         | 26 +++++++++++++++++++++++
 4 files changed, 82 insertions(+)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 1823939..8461cd6 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -15,6 +15,8 @@
  */
 #define CRYPTO_OCTEONTX		0x1
 
+#define TIME_IN_RESET_COUNT	5
+
 /* Default command timeout in seconds */
 #define DEFAULT_COMMAND_TIMEOUT	4
 
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 60be8b3..becc14f 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -175,6 +175,21 @@ typedef enum {
 	ERR_ENODEV,
 } mc_error_code_t;
 
+/**
+ * Enumeration cpt_comp_e
+ *
+ * CPT Completion Enumeration
+ * Enumerates the values of CPT_RES_S[COMPCODE].
+ */
+typedef enum {
+	CPT_8X_COMP_E_NOTDONE    = (0x00),
+	CPT_8X_COMP_E_GOOD       = (0x01),
+	CPT_8X_COMP_E_FAULT      = (0x02),
+	CPT_8X_COMP_E_SWERR      = (0x03),
+	CPT_8X_COMP_E_HWERR      = (0x04),
+	CPT_8X_COMP_E_LAST_ENTRY = (0xFF)
+} cpt_comp_e_t;
+
 typedef struct sglist_comp {
 	union {
 		uint64_t len;
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index dea89f8..4463cfb 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -143,4 +143,43 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 	return ret;
 }
 
+static __rte_always_inline int32_t __hot
+cpt_dequeue_burst(struct cpt_instance *instance, uint16_t cnt,
+		  void *resp[], uint8_t cc[], struct pending_queue *pqueue)
+{
+	struct cpt_request_info *user_req;
+	struct rid *rid_e;
+	int i, count, pcount;
+	uint8_t ret;
+
+	pcount = pqueue->pending_count;
+	count = (cnt > pcount) ? pcount : cnt;
+
+	for (i = 0; i < count; i++) {
+		rid_e = &pqueue->rid_queue[pqueue->deq_head];
+		user_req = (struct cpt_request_info *)(rid_e->rid);
+
+		if (likely((i+1) < count))
+			rte_prefetch_non_temporal((void *)rid_e[1].rid);
+
+		ret = check_nb_command_id(user_req, instance);
+
+		if (unlikely(ret == ERR_REQ_PENDING)) {
+			/* Stop checking for completions */
+			break;
+		}
+
+		/* Return completion code and op handle */
+		cc[i] = (uint8_t)ret;
+		resp[i] = user_req->op;
+		CPT_LOG_DP_DEBUG("Request %p Op %p completed with code %d",
+			   user_req, user_req->op, ret);
+
+		MOD_INC(pqueue->deq_head, DEFAULT_CMD_QLEN);
+		pqueue->pending_count -= 1;
+	}
+
+	return i;
+}
+
 #endif /* _CPT_REQUEST_MGR_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 4d892f2..c5a9f34 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -3373,6 +3373,32 @@ fill_fc_params(struct rte_crypto_op *cop,
 	return prep_req;
 }
 
+static __rte_always_inline void
+compl_auth_verify(struct rte_crypto_op *op,
+		      uint8_t *gen_mac,
+		      uint64_t mac_len)
+{
+	uint8_t *mac;
+	struct rte_crypto_sym_op *sym_op = op->sym;
+
+	if (sym_op->auth.digest.data)
+		mac = sym_op->auth.digest.data;
+	else
+		mac = rte_pktmbuf_mtod_offset(sym_op->m_src,
+					      uint8_t *,
+					      sym_op->auth.data.length +
+					      sym_op->auth.data.offset);
+	if (!mac) {
+		op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		return;
+	}
+
+	if (memcmp(mac, gen_mac, mac_len))
+		op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+	else
+		op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+}
+
 static __rte_always_inline int
 instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
 {
-- 
2.7.4

[dpdk-dev] [PATCH v3 30/32] crypto/octeontx: add dequeue burst op

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 69 +++++++++++++++++++++--
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 47 ++++++++++++++-
 2 files changed, 110 insertions(+), 6 deletions(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 6f4d6e1..82b15ee 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -1,19 +1,20 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2018 Cavium, Inc
  */
-
 #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
 #define _OTX_CRYPTODEV_HW_ACCESS_H_
 
 #include <stdbool.h>
 
 #include <rte_branch_prediction.h>
+#include <rte_cycles.h>
 #include <rte_io.h>
 #include <rte_memory.h>
 #include <rte_prefetch.h>
 
 #include "cpt_common.h"
 #include "cpt_hw_types.h"
+#include "cpt_mcode_defines.h"
 #include "cpt_pmd_logs.h"
 
 #define CPT_INTR_POLL_INTERVAL_MS	(50)
@@ -252,10 +253,68 @@ static __rte_always_inline uint8_t
 check_nb_command_id(struct cpt_request_info *user_req,
 		struct cpt_instance *instance)
 {
-	/* Required for dequeue operation. Adding a dummy routine for now */
-	RTE_SET_USED(user_req);
-	RTE_SET_USED(instance);
-	return 0;
+	uint8_t ret = ERR_REQ_PENDING;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	volatile cpt_res_s_t *cptres;
+
+	cptres = (volatile cpt_res_s_t *)user_req->completion_addr;
+
+	if (unlikely(cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE)) {
+		/*
+		 * Wait for some time for this command to get completed
+		 * before timing out
+		 */
+		if (rte_get_timer_cycles() < user_req->time_out)
+			return ret;
+		/*
+		 * TODO: See if alternate caddr can be used to not loop
+		 * longer than needed.
+		 */
+		if ((cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE) &&
+		    (user_req->extra_time < TIME_IN_RESET_COUNT)) {
+			user_req->extra_time++;
+			return ret;
+		}
+
+		if (cptres->s8x.compcode != CPT_8X_COMP_E_NOTDONE)
+			goto complete;
+
+		ret = ERR_REQ_TIMEOUT;
+		CPT_LOG_DP_ERR("Request %p timedout", user_req);
+		otx_cpt_poll_misc(cptvf);
+		goto exit;
+	}
+
+complete:
+	if (likely(cptres->s8x.compcode == CPT_8X_COMP_E_GOOD)) {
+		ret = 0; /* success */
+		if (unlikely((uint8_t)*user_req->alternate_caddr)) {
+			ret = (uint8_t)*user_req->alternate_caddr;
+			CPT_LOG_DP_ERR("Request %p : failed with microcode"
+				" error, MC completion code : 0x%x", user_req,
+				ret);
+		}
+		CPT_LOG_DP_DEBUG("MC status %.8x\n",
+			   *((volatile uint32_t *)user_req->alternate_caddr));
+		CPT_LOG_DP_DEBUG("HW status %.8x\n",
+			   *((volatile uint32_t *)user_req->completion_addr));
+	} else if ((cptres->s8x.compcode == CPT_8X_COMP_E_SWERR) ||
+		   (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT)) {
+		ret = (uint8_t)*user_req->alternate_caddr;
+		if (!ret)
+			ret = ERR_BAD_ALT_CCODE;
+		CPT_LOG_DP_DEBUG("Request %p : failed with %s : err code :%x",
+			   user_req,
+			   (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT) ?
+			   "DMA Fault" : "Software error", ret);
+	} else {
+		CPT_LOG_DP_ERR("Request %p : unexpected completion code %d",
+			   user_req, cptres->s8x.compcode);
+		ret = (uint8_t)*user_req->alternate_caddr;
+	}
+
+exit:
+	return ret;
 }
 
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 4240051..23f9659 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -366,6 +366,51 @@ otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 	return count;
 }
 
+static uint16_t
+otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	struct cpt_instance *instance = (struct cpt_instance *)qptr;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct pending_queue *pqueue = &cptvf->pqueue;
+	uint16_t nb_completed, i = 0;
+	uint8_t compcode[nb_ops];
+
+	nb_completed = cpt_dequeue_burst(instance, nb_ops,
+					 (void **)ops, compcode, pqueue);
+	while (likely(i < nb_completed)) {
+		struct rte_crypto_op *cop;
+		void *metabuf;
+		uintptr_t *rsp;
+		uint8_t status;
+
+		rsp = (void *)ops[i];
+		status = compcode[i];
+		if (likely((i + 1) < nb_completed))
+			rte_prefetch0(ops[i+1]);
+		metabuf = (void *)rsp[0];
+		cop = (void *)rsp[1];
+
+		ops[i] = cop;
+
+		if (likely(status == 0)) {
+			if (likely(!rsp[2]))
+				cop->status =
+					RTE_CRYPTO_OP_STATUS_SUCCESS;
+			else
+				compl_auth_verify(cop, (uint8_t *)rsp[2],
+						  rsp[3]);
+		} else if (status == ERR_GC_ICV_MISCOMPARE) {
+			/*auth data mismatch */
+			cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+		} else {
+			cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		}
+		free_op_meta(metabuf, cptvf->meta_info.cptvf_meta_pool);
+		i++;
+	}
+	return nb_completed;
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -458,7 +503,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	c_dev->dev_ops = &cptvf_ops;
 
 	c_dev->enqueue_burst = otx_cpt_pkt_enqueue;
-	c_dev->dequeue_burst = NULL;
+	c_dev->dequeue_burst = otx_cpt_pkt_dequeue;
 
 	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
 			RTE_CRYPTODEV_FF_HW_ACCELERATED |
-- 
2.7.4

[dpdk-dev] [PATCH v3 31/32] test: adds validation test

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

This patch adds validation tests for octeontx crypto device.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 test/test/meson.build                        |   1 +
 test/test/test_cryptodev.c                   | 316 +++++++++++++++++++++++++++
 test/test/test_cryptodev.h                   |   1 +
 test/test/test_cryptodev_aes_test_vectors.h  | 114 ++++++----
 test/test/test_cryptodev_blockcipher.c       |   9 +-
 test/test/test_cryptodev_blockcipher.h       |   1 +
 test/test/test_cryptodev_des_test_vectors.h  |  12 +-
 test/test/test_cryptodev_hash_test_vectors.h |  78 ++++---
 8 files changed, 463 insertions(+), 69 deletions(-)

diff --git a/test/test/meson.build b/test/test/meson.build
index b1dd6ec..2d59041 100644
--- a/test/test/meson.build
+++ b/test/test/meson.build
@@ -141,6 +141,7 @@ test_names = [
 	'cryptodev_sw_mvsam_autotest',
 	'cryptodev_dpaa2_sec_autotest',
 	'cryptodev_dpaa_sec_autotest',
+	'cryptodev_octeontx_autotest',
 	'cycles_autotest',
 	'debug_autotest',
 	'devargs_autotest',
diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
index c63662d..b9731b9 100644
--- a/test/test/test_cryptodev.c
+++ b/test/test/test_cryptodev.c
@@ -2142,6 +2142,96 @@ test_3DES_cipheronly_mrvl_all(void)
 	return TEST_SUCCESS;
 }
 
+static int
+test_AES_chain_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_AES_CHAIN_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_AES_cipheronly_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_AES_CIPHERONLY_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_3DES_chain_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_3DES_CHAIN_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_3DES_cipheronly_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_3DES_CIPHERONLY_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_authonly_cpt_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_AUTHONLY_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
 /* ***** SNOW 3G Tests ***** */
 static int
 create_wireless_algo_hash_session(uint8_t dev_id,
@@ -9951,6 +10041,216 @@ static struct unit_test_suite cryptodev_ccp_testsuite  = {
 	}
 };
 
+static struct unit_test_suite cryptodev_cpt_testsuite  = {
+	.suite_name = "Crypto Device OCTEONTX Unit Test Suite",
+	.setup = testsuite_setup,
+	.teardown = testsuite_teardown,
+	.unit_test_cases = {
+		TEST_CASE_ST(ut_setup, ut_teardown, test_AES_chain_cpt_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+						test_AES_cipheronly_cpt_all),
+		TEST_CASE_ST(ut_setup, ut_teardown, test_3DES_chain_cpt_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+						test_3DES_cipheronly_cpt_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+						test_authonly_cpt_all),
+
+		/** AES GCM Authenticated Encryption */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_6),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_7),
+
+		/** AES GCM Authenticated Decryption */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_6),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_7),
+		/** AES GMAC Authentication */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_verify_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_verify_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_verify_test_case_3),
+
+		/** SNOW 3G encrypt only (UEA2) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_5),
+
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_1_oop),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_1_oop),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_1_oop_sgl),
+
+		/** SNOW 3G decrypt only (UEA2) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_5),
+
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_generate_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_generate_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_generate_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_verify_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_verify_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_verify_test_case_3),
+
+		/** ZUC encrypt only (EEA3) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_6_sgl),
+
+		/** KASUMI encrypt only (UEA1) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1_sgl),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1_oop_sgl),
+		/** KASUMI decrypt only (UEA1) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_5),
+
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1_oop),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_1_oop),
+
+		/** KASUMI hash only (UIA1) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_6),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_5),
+
+		/** NULL tests */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_cipher_only_operation),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_auth_only_operation),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_cipher_auth_operation),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_auth_cipher_operation),
+
+		/** Negative tests */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_HMAC_SHA1_fail_data_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_HMAC_SHA1_fail_tag_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_AES128_GMAC_fail_data_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_AES128_GMAC_fail_tag_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			auth_decryption_AES128CBC_HMAC_SHA1_fail_data_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			auth_decryption_AES128CBC_HMAC_SHA1_fail_tag_corrupt),
+		TEST_CASES_END() /**< NULL terminate unit test array */
+	}
+};
+
 static int
 test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
 {
@@ -10203,6 +10503,21 @@ test_cryptodev_ccp(void)
 	return unit_test_suite_runner(&cryptodev_ccp_testsuite);
 }
 
+static int
+test_cryptodev_octeontx(void)
+{
+	gbl_driver_id =	rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+	if (gbl_driver_id == -1) {
+		RTE_LOG(ERR, USER1, "OCTEONTX PMD must be loaded. Check if "
+				"CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO is "
+				"enabled in config file to run this "
+				"testsuite.\n");
+		return TEST_FAILED;
+	}
+	return unit_test_suite_runner(&cryptodev_cpt_testsuite);
+}
+
 REGISTER_TEST_COMMAND(cryptodev_qat_autotest, test_cryptodev_qat);
 REGISTER_TEST_COMMAND(cryptodev_aesni_mb_autotest, test_cryptodev_aesni_mb);
 REGISTER_TEST_COMMAND(cryptodev_openssl_autotest, test_cryptodev_openssl);
@@ -10217,3 +10532,4 @@ REGISTER_TEST_COMMAND(cryptodev_dpaa2_sec_autotest, test_cryptodev_dpaa2_sec);
 REGISTER_TEST_COMMAND(cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec);
 REGISTER_TEST_COMMAND(cryptodev_ccp_autotest, test_cryptodev_ccp);
 REGISTER_TEST_COMMAND(cryptodev_virtio_autotest, test_cryptodev_virtio);
+REGISTER_TEST_COMMAND(cryptodev_octeontx_autotest, test_cryptodev_octeontx);
diff --git a/test/test/test_cryptodev.h b/test/test/test_cryptodev.h
index 1bd44dc..f2d41ae 100644
--- a/test/test/test_cryptodev.h
+++ b/test/test/test_cryptodev.h
@@ -64,6 +64,7 @@
 #define CRYPTODEV_NAME_MVSAM_PMD		crypto_mvsam
 #define CRYPTODEV_NAME_CCP_PMD		crypto_ccp
 #define CRYPTODEV_NAME_VIRTIO_PMD	crypto_virtio
+#define CRYPTODEV_NAME_OCTEONTX_SYM_PMD	crypto_octeontx
 
 /**
  * Write (spread) data from buffer to mbuf data
diff --git a/test/test/test_cryptodev_aes_test_vectors.h b/test/test/test_cryptodev_aes_test_vectors.h
index 1c4dc66..5db46f4 100644
--- a/test/test/test_cryptodev_aes_test_vectors.h
+++ b/test/test/test_cryptodev_aes_test_vectors.h
@@ -1254,7 +1254,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1262,7 +1263,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_13,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENC_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1276,7 +1278,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1291,7 +1294,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1300,7 +1304,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SG,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1308,7 +1313,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_13,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest",
@@ -1322,7 +1328,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest "
@@ -1330,7 +1337,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_12,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENC_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1345,7 +1353,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1353,7 +1362,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_12,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest",
@@ -1366,7 +1376,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1376,7 +1387,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SESSIONLESS,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1387,7 +1399,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_FEATURE_SG |
 			BLOCKCIPHER_TEST_FEATURE_OOP,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
-			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL
+			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest "
@@ -1401,7 +1414,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest "
@@ -1415,7 +1429,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER
+			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC XCBC Encryption Digest",
@@ -1443,7 +1458,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1455,7 +1471,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA224 Encryption Digest",
@@ -1467,7 +1484,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
@@ -1480,7 +1498,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
@@ -1517,7 +1536,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SESSIONLESS,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr =
@@ -1528,7 +1548,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SESSIONLESS,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 };
 
@@ -1545,7 +1566,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC Decryption",
@@ -1559,7 +1581,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Encryption",
@@ -1572,7 +1595,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Encryption Scater gather",
@@ -1582,7 +1606,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_FEATURE_OOP,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Decryption",
@@ -1595,7 +1620,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Decryption Scatter Gather",
@@ -1603,7 +1629,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_DECRYPT,
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SG,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CBC Encryption",
@@ -1617,7 +1644,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CBC Decryption",
@@ -1631,7 +1659,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CBC OOP Encryption",
@@ -1668,7 +1697,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CTR Decryption",
@@ -1681,7 +1711,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CTR Encryption",
@@ -1693,7 +1724,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CTR Decryption",
@@ -1705,7 +1737,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CTR Encryption",
@@ -1718,7 +1751,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CTR Decryption",
@@ -1731,25 +1765,29 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CTR Encryption (12-byte IV)",
 		.test_data = &aes_test_data_1_IV_12_bytes,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
-		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CTR Encryption (12-byte IV)",
 		.test_data = &aes_test_data_2_IV_12_bytes,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
-		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CTR Encryption (12-byte IV)",
 		.test_data = &aes_test_data_3_IV_12_bytes,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
-		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	}
 };
 
diff --git a/test/test/test_cryptodev_blockcipher.c b/test/test/test_cryptodev_blockcipher.c
index f2701f8..2197638 100644
--- a/test/test/test_cryptodev_blockcipher.c
+++ b/test/test/test_cryptodev_blockcipher.c
@@ -72,6 +72,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
 			RTE_STR(CRYPTODEV_NAME_MVSAM_PMD));
 	int virtio_pmd = rte_cryptodev_driver_id_get(
 			RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
+	int cpt_pmd = rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
 
 	int nb_segs = 1;
 
@@ -114,7 +116,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
 			driver_id == armv8_pmd ||
 			driver_id == mrvl_pmd ||
 			driver_id == ccp_pmd ||
-			driver_id == virtio_pmd) { /* Fall through */
+			driver_id == virtio_pmd ||
+			driver_id == cpt_pmd) { /* Fall through */
 		digest_len = tdata->digest.len;
 	} else if (driver_id == aesni_mb_pmd ||
 			driver_id == scheduler_pmd) {
@@ -640,6 +643,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
 			RTE_STR(CRYPTODEV_NAME_MVSAM_PMD));
 	int virtio_pmd = rte_cryptodev_driver_id_get(
 			RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
+	int cpt_pmd = rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
 
 	switch (test_type) {
 	case BLKCIPHER_AES_CHAIN_TYPE:
@@ -706,6 +711,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
 		target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MVSAM;
 	else if (driver_id == virtio_pmd)
 		target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO;
+	else if (driver_id == cpt_pmd)
+		target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX;
 	else
 		TEST_ASSERT(0, "Unrecognized cryptodev type");
 
diff --git a/test/test/test_cryptodev_blockcipher.h b/test/test/test_cryptodev_blockcipher.h
index 6f7c892..2954f6f 100644
--- a/test/test/test_cryptodev_blockcipher.h
+++ b/test/test/test_cryptodev_blockcipher.h
@@ -29,6 +29,7 @@
 #define BLOCKCIPHER_TEST_TARGET_PMD_MVSAM	0x0080 /* Marvell flag */
 #define BLOCKCIPHER_TEST_TARGET_PMD_CCP		0x0040 /* CCP flag */
 #define BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO	0x0200 /* VIRTIO flag */
+#define BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX	0x0100 /* Octeontx flag */
 
 #define BLOCKCIPHER_TEST_OP_CIPHER	(BLOCKCIPHER_TEST_OP_ENCRYPT | \
 					BLOCKCIPHER_TEST_OP_DECRYPT)
diff --git a/test/test/test_cryptodev_des_test_vectors.h b/test/test/test_cryptodev_des_test_vectors.h
index 1033456..0789881 100644
--- a/test/test/test_cryptodev_des_test_vectors.h
+++ b/test/test/test_cryptodev_des_test_vectors.h
@@ -1104,7 +1104,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-192-CBC HMAC-SHA1 Decryption Digest Verify",
@@ -1115,7 +1116,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-192-CBC SHA1 Encryption Digest",
@@ -1276,7 +1278,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MB
+			BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-192-CBC Decryption",
@@ -1288,7 +1291,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MB
+			BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-128-CTR Encryption",
diff --git a/test/test/test_cryptodev_hash_test_vectors.h b/test/test/test_cryptodev_hash_test_vectors.h
index cf86dbb..c430409 100644
--- a/test/test/test_cryptodev_hash_test_vectors.h
+++ b/test/test/test_cryptodev_hash_test_vectors.h
@@ -373,14 +373,16 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.test_data = &md5_test_vector,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "MD5 Digest Verify",
 		.test_data = &md5_test_vector,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-MD5 Digest",
@@ -392,7 +394,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-MD5 Digest Verify",
@@ -404,7 +407,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA1 Digest",
@@ -412,7 +416,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA1 Digest Verify",
@@ -420,7 +425,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest",
@@ -433,7 +439,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest Scatter Gather",
@@ -441,7 +448,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SG,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest Verify",
@@ -454,7 +462,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest Verify Scatter Gather",
@@ -462,7 +471,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SG,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA224 Digest",
@@ -470,7 +480,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA224 Digest Verify",
@@ -478,7 +489,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA224 Digest",
@@ -490,7 +502,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_QAT
+			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA224 Digest Verify",
@@ -502,7 +515,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_QAT
+			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA256 Digest",
@@ -510,7 +524,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA256 Digest Verify",
@@ -518,7 +533,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA256 Digest",
@@ -531,7 +547,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA256 Digest Verify",
@@ -544,7 +561,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA384 Digest",
@@ -552,7 +570,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA384 Digest Verify",
@@ -560,7 +579,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA384 Digest",
@@ -573,7 +593,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA384 Digest Verify",
@@ -586,7 +607,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA512 Digest",
@@ -594,7 +616,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA512 Digest Verify",
@@ -602,7 +625,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA512 Digest",
@@ -615,7 +639,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA512 Digest Verify",
@@ -628,7 +653,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "CMAC Digest 12B",
-- 
2.7.4

Re: [dpdk-dev] [PATCH v3 31/32] test: adds validation test

[Akhil Goyal]

Hi Anoob,

On 10/5/2018 6:29 PM, Anoob Joseph wrote:
> From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>
> This patch adds validation tests for octeontx crypto device.
>
> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
> ---
>   test/test/meson.build                        |   1 +
>   test/test/test_cryptodev.c                   | 316 +++++++++++++++++++++++++++
>   test/test/test_cryptodev.h                   |   1 +
>   test/test/test_cryptodev_aes_test_vectors.h  | 114 ++++++----
>   test/test/test_cryptodev_blockcipher.c       |   9 +-
>   test/test/test_cryptodev_blockcipher.h       |   1 +
>   test/test/test_cryptodev_des_test_vectors.h  |  12 +-
>   test/test/test_cryptodev_hash_test_vectors.h |  78 ++++---
>   8 files changed, 463 insertions(+), 69 deletions(-)
>
> diff --git a/test/test/meson.build b/test/test/meson.build
> index b1dd6ec..2d59041 100644
> --- a/test/test/meson.build
> +++ b/test/test/meson.build
> @@ -141,6 +141,7 @@ test_names = [
>   	'cryptodev_sw_mvsam_autotest',
>   	'cryptodev_dpaa2_sec_autotest',
>   	'cryptodev_dpaa_sec_autotest',
> +	'cryptodev_octeontx_autotest',
>   	'cycles_autotest',
>   	'debug_autotest',
>   	'devargs_autotest',
> diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
> index c63662d..b9731b9 100644
> --- a/test/test/test_cryptodev.c
> +++ b/test/test/test_cryptodev.c
> @@ -2142,6 +2142,96 @@ test_3DES_cipheronly_mrvl_all(void)
>   	return TEST_SUCCESS;
>   }
>   
> +static int
> +test_AES_chain_cpt_all(void)
> +{
> +	struct crypto_testsuite_params *ts_params = &testsuite_params;
> +	int status;
> +
> +	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
> +		ts_params->op_mpool, ts_params->session_mpool,
> +		ts_params->valid_devs[0],
> +		rte_cryptodev_driver_id_get(
> +		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
> +		BLKCIPHER_AES_CHAIN_TYPE);
> +
> +	TEST_ASSERT_EQUAL(status, 0, "Test failed");
> +
> +	return TEST_SUCCESS;
> +}
> +
> +static int
> +test_AES_cipheronly_cpt_all(void)
> +{
> +	struct crypto_testsuite_params *ts_params = &testsuite_params;
> +	int status;
> +
> +	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
> +		ts_params->op_mpool, ts_params->session_mpool,
> +		ts_params->valid_devs[0],
> +		rte_cryptodev_driver_id_get(
> +		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
> +		BLKCIPHER_AES_CIPHERONLY_TYPE);
> +
> +	TEST_ASSERT_EQUAL(status, 0, "Test failed");
> +
> +	return TEST_SUCCESS;
> +}
> +
> +static int
> +test_3DES_chain_cpt_all(void)
> +{
> +	struct crypto_testsuite_params *ts_params = &testsuite_params;
> +	int status;
> +
> +	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
> +		ts_params->op_mpool, ts_params->session_mpool,
> +		ts_params->valid_devs[0],
> +		rte_cryptodev_driver_id_get(
> +		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
> +		BLKCIPHER_3DES_CHAIN_TYPE);
> +
> +	TEST_ASSERT_EQUAL(status, 0, "Test failed");
> +
> +	return TEST_SUCCESS;
> +}
> +
> +static int
> +test_3DES_cipheronly_cpt_all(void)
> +{
> +	struct crypto_testsuite_params *ts_params = &testsuite_params;
> +	int status;
> +
> +	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
> +		ts_params->op_mpool, ts_params->session_mpool,
> +		ts_params->valid_devs[0],
> +		rte_cryptodev_driver_id_get(
> +		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
> +		BLKCIPHER_3DES_CIPHERONLY_TYPE);
> +
> +	TEST_ASSERT_EQUAL(status, 0, "Test failed");
> +
> +	return TEST_SUCCESS;
> +}
> +
> +static int
> +test_authonly_cpt_all(void)
> +{
> +	struct crypto_testsuite_params *ts_params = &testsuite_params;
> +	int status;
> +
> +	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
> +		ts_params->op_mpool, ts_params->session_mpool,
> +		ts_params->valid_devs[0],
> +		rte_cryptodev_driver_id_get(
> +		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
> +		BLKCIPHER_AUTHONLY_TYPE);
> +
> +	TEST_ASSERT_EQUAL(status, 0, "Test failed");
> +
> +	return TEST_SUCCESS;
> +}
> +
>   /* ***** SNOW 3G Tests ***** */
>   static int
>   create_wireless_algo_hash_session(uint8_t dev_id,
> @@ -9951,6 +10041,216 @@ static struct unit_test_suite cryptodev_ccp_testsuite  = {
>   	}
>   };
>   
> +static struct unit_test_suite cryptodev_cpt_testsuite  = {
Shouldn't this be cryptodev_octeontx_testsuite and for other functions 
as well?
I believe cpt is helper API set, and main PMD is octeontx, so the test 
shall also have octeontx reference.

Thanks,
Akhil

Re: [dpdk-dev] [PATCH v3 31/32] test: adds validation test

[Akhil Goyal]

one more... title should be test/crypto: add octeontx unit tests

On 10/8/2018 6:03 PM, Akhil Goyal wrote:
>
> Hi Anoob,
>
> On 10/5/2018 6:29 PM, Anoob Joseph wrote:
>> From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>>
>> This patch adds validation tests for octeontx crypto device.
>>
>> Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
>> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
>> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
>> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
>> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
>> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
>> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
>> ---
>>   test/test/meson.build                        |   1 +
>>   test/test/test_cryptodev.c                   | 316 
>> +++++++++++++++++++++++++++
>>   test/test/test_cryptodev.h                   |   1 +
>>   test/test/test_cryptodev_aes_test_vectors.h  | 114 ++++++----
>>   test/test/test_cryptodev_blockcipher.c       |   9 +-
>>   test/test/test_cryptodev_blockcipher.h       |   1 +
>>   test/test/test_cryptodev_des_test_vectors.h  |  12 +-
>>   test/test/test_cryptodev_hash_test_vectors.h |  78 ++++---
>>   8 files changed, 463 insertions(+), 69 deletions(-)
>>
>> diff --git a/test/test/meson.build b/test/test/meson.build
>> index b1dd6ec..2d59041 100644
>> --- a/test/test/meson.build
>> +++ b/test/test/meson.build
>> @@ -141,6 +141,7 @@ test_names = [
>>       'cryptodev_sw_mvsam_autotest',
>>       'cryptodev_dpaa2_sec_autotest',
>>       'cryptodev_dpaa_sec_autotest',
>> +    'cryptodev_octeontx_autotest',
>>       'cycles_autotest',
>>       'debug_autotest',
>>       'devargs_autotest',
>> diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
>> index c63662d..b9731b9 100644
>> --- a/test/test/test_cryptodev.c
>> +++ b/test/test/test_cryptodev.c
>> @@ -2142,6 +2142,96 @@ test_3DES_cipheronly_mrvl_all(void)
>>       return TEST_SUCCESS;
>>   }
>>   +static int
>> +test_AES_chain_cpt_all(void)
>> +{
>> +    struct crypto_testsuite_params *ts_params = &testsuite_params;
>> +    int status;
>> +
>> +    status = test_blockcipher_all_tests(ts_params->mbuf_pool,
>> +        ts_params->op_mpool, ts_params->session_mpool,
>> +        ts_params->valid_devs[0],
>> +        rte_cryptodev_driver_id_get(
>> +        RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
>> +        BLKCIPHER_AES_CHAIN_TYPE);
>> +
>> +    TEST_ASSERT_EQUAL(status, 0, "Test failed");
>> +
>> +    return TEST_SUCCESS;
>> +}
>> +
>> +static int
>> +test_AES_cipheronly_cpt_all(void)
>> +{
>> +    struct crypto_testsuite_params *ts_params = &testsuite_params;
>> +    int status;
>> +
>> +    status = test_blockcipher_all_tests(ts_params->mbuf_pool,
>> +        ts_params->op_mpool, ts_params->session_mpool,
>> +        ts_params->valid_devs[0],
>> +        rte_cryptodev_driver_id_get(
>> +        RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
>> +        BLKCIPHER_AES_CIPHERONLY_TYPE);
>> +
>> +    TEST_ASSERT_EQUAL(status, 0, "Test failed");
>> +
>> +    return TEST_SUCCESS;
>> +}
>> +
>> +static int
>> +test_3DES_chain_cpt_all(void)
>> +{
>> +    struct crypto_testsuite_params *ts_params = &testsuite_params;
>> +    int status;
>> +
>> +    status = test_blockcipher_all_tests(ts_params->mbuf_pool,
>> +        ts_params->op_mpool, ts_params->session_mpool,
>> +        ts_params->valid_devs[0],
>> +        rte_cryptodev_driver_id_get(
>> +        RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
>> +        BLKCIPHER_3DES_CHAIN_TYPE);
>> +
>> +    TEST_ASSERT_EQUAL(status, 0, "Test failed");
>> +
>> +    return TEST_SUCCESS;
>> +}
>> +
>> +static int
>> +test_3DES_cipheronly_cpt_all(void)
>> +{
>> +    struct crypto_testsuite_params *ts_params = &testsuite_params;
>> +    int status;
>> +
>> +    status = test_blockcipher_all_tests(ts_params->mbuf_pool,
>> +        ts_params->op_mpool, ts_params->session_mpool,
>> +        ts_params->valid_devs[0],
>> +        rte_cryptodev_driver_id_get(
>> +        RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
>> +        BLKCIPHER_3DES_CIPHERONLY_TYPE);
>> +
>> +    TEST_ASSERT_EQUAL(status, 0, "Test failed");
>> +
>> +    return TEST_SUCCESS;
>> +}
>> +
>> +static int
>> +test_authonly_cpt_all(void)
>> +{
>> +    struct crypto_testsuite_params *ts_params = &testsuite_params;
>> +    int status;
>> +
>> +    status = test_blockcipher_all_tests(ts_params->mbuf_pool,
>> +        ts_params->op_mpool, ts_params->session_mpool,
>> +        ts_params->valid_devs[0],
>> +        rte_cryptodev_driver_id_get(
>> +        RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
>> +        BLKCIPHER_AUTHONLY_TYPE);
>> +
>> +    TEST_ASSERT_EQUAL(status, 0, "Test failed");
>> +
>> +    return TEST_SUCCESS;
>> +}
>> +
>>   /* ***** SNOW 3G Tests ***** */
>>   static int
>>   create_wireless_algo_hash_session(uint8_t dev_id,
>> @@ -9951,6 +10041,216 @@ static struct unit_test_suite 
>> cryptodev_ccp_testsuite  = {
>>       }
>>   };
>>   +static struct unit_test_suite cryptodev_cpt_testsuite  = {
> Shouldn't this be cryptodev_octeontx_testsuite and for other functions 
> as well?
> I believe cpt is helper API set, and main PMD is octeontx, so the test 
> shall also have octeontx reference.
>
> Thanks,
> Akhil

[dpdk-dev] [PATCH v3 32/32] doc: adds doc file

[Anoob Joseph]

This patch adds the features file and the document containing
help to compile and use octeontx crypto.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 MAINTAINERS                                 |   2 +
 doc/guides/cryptodevs/features/octeontx.ini |  62 ++++++++++++++
 doc/guides/cryptodevs/index.rst             |   1 +
 doc/guides/cryptodevs/octeontx.rst          | 128 ++++++++++++++++++++++++++++
 4 files changed, 193 insertions(+)
 create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
 create mode 100644 doc/guides/cryptodevs/octeontx.rst

diff --git a/MAINTAINERS b/MAINTAINERS
index b38beb9..a8319d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -776,6 +776,8 @@ Cavium OCTEON TX
 M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
 F: drivers/common/cpt/
 F: drivers/crypto/octeontx/
+F: doc/guides/cryptodevs/octeontx.rst
+F: doc/guides/cryptodevs/features/octeontx.ini
 
 Crypto Scheduler
 M: Fan Zhang <roy.fan.zhang@intel.com>
diff --git a/doc/guides/cryptodevs/features/octeontx.ini b/doc/guides/cryptodevs/features/octeontx.ini
new file mode 100644
index 0000000..307ab88
--- /dev/null
+++ b/doc/guides/cryptodevs/features/octeontx.ini
@@ -0,0 +1,62 @@
+;
+; Supported features of the 'octeontx' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto       = Y
+Sym operation chaining = Y
+HW Accelerated         = Y
+In Place SGL           = Y
+OOP SGL In LB  Out     = Y
+OOP SGL In SGL Out     = Y
+
+;
+; Supported crypto algorithms of 'octeontx' crypto driver.
+;
+[Cipher]
+NULL           = Y
+3DES CBC       = Y
+3DES ECB       = Y
+AES CBC (128)  = Y
+AES CBC (192)  = Y
+AES CBC (256)  = Y
+AES CTR (128)  = Y
+AES CTR (192)  = Y
+AES CTR (256)  = Y
+AES XTS (128)  = Y
+AES XTS (256)  = Y
+DES CBC        = Y
+KASUMI F8      = Y
+SNOW3G UEA2    = Y
+ZUC EEA3       = Y
+
+;
+; Supported authentication algorithms of 'octeontx' crypto driver.
+;
+[Auth]
+NULL         = Y
+AES GMAC     = Y
+KASUMI F9    = Y
+MD5          = Y
+MD5 HMAC     = Y
+SHA1         = Y
+SHA1 HMAC    = Y
+SHA224       = Y
+SHA224 HMAC  = Y
+SHA256       = Y
+SHA256 HMAC  = Y
+SHA384       = Y
+SHA384 HMAC  = Y
+SHA512       = Y
+SHA512 HMAC  = Y
+SNOW3G UIA2  = Y
+ZUC EIA3     = Y
+
+;
+; Supported AEAD algorithms of 'octeontx' crypto driver.
+;
+[AEAD]
+AES GCM (128) = Y
+AES GCM (192) = Y
+AES GCM (256) = Y
diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst
index e9928a4..bd15885 100644
--- a/doc/guides/cryptodevs/index.rst
+++ b/doc/guides/cryptodevs/index.rst
@@ -17,6 +17,7 @@ Crypto Device Drivers
     dpaa2_sec
     dpaa_sec
     kasumi
+    octeontx
     openssl
     mvsam
     null
diff --git a/doc/guides/cryptodevs/octeontx.rst b/doc/guides/cryptodevs/octeontx.rst
new file mode 100644
index 0000000..2673dd5
--- /dev/null
+++ b/doc/guides/cryptodevs/octeontx.rst
@@ -0,0 +1,128 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+   Copyright(c) 2018 Cavium, Inc
+
+Cavium OCTEONTX Crypto Poll Mode Driver
+=======================================
+
+The OCTEONTX crypto poll mode driver provides support for offloading
+cryptographic operations on cryptographic accelerator units on
+**OCTEON TX** :sup:`®` family of processors (CN8XXX). The OCTEONTX crypto poll
+mode driver enqueues the crypto request to this accelerator and dequeues the
+response once the operation is completed.
+
+Supported Algorithms
+--------------------
+
+Cipher Algorithms
+~~~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_CIPHER_NULL``
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_3DES_ECB``
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_CTR``
+* ``RTE_CRYPTO_CIPHER_AES_XTS``
+* ``RTE_CRYPTO_CIPHER_DES_CBC``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
+
+Hash Algorithms
+~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_AES_GMAC``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
+* ``RTE_CRYPTO_AUTH_MD5``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA1``
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+
+AEAD Algorithms
+~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_AEAD_AES_GCM``
+
+Compilation
+-----------
+
+The **OCTEON TX** :sup:`®` board must be running the linux kernel based on
+sdk-6.2.0 patch 3. In this, the OCTEONTX crypto PF driver is already built in.
+
+For compiling the OCTEONTX crypto poll mode driver, please check if the
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO setting is set to `y` in
+config/common_base file.
+
+* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y``
+
+The following are the steps to compile the OCTEONTX crypto poll mode driver:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        make config T=arm64-thunderx-linuxapp-gcc
+        make
+
+The example applications can be compiled using the following:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        export RTE_SDK=$PWD
+        export RTE_TARGET=build
+        cd examples/<application>
+        make
+
+Execution
+---------
+
+The number of crypto VFs to be enabled can be controlled by setting sysfs entry,
+`sriov_numvfs`, for the corresponding PF driver.
+
+.. code-block:: console
+
+        echo <num_vfs> > /sys/bus/pci/devices/<dev_bus_id>/sriov_numvfs
+
+The device bus ID, `dev_bus_id`, to be used in the above step can be found out
+by using dpdk-devbind.py script. The OCTEONTX crypto PF device need to be
+identified and the corresponding device number can be used to tune various PF
+properties.
+
+
+Once the required VFs are enabled, dpdk-devbind.py script can be used to
+identify the VFs. To be accessible from DPDK, VFs need to be bound to vfio-pci
+driver:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        ./usertools/dpdk-devbind.py -u <vf device no>
+        ./usertools/dpdk-devbind.py -b vfio-pci <vf device no>
+
+Appropriate huge page need to be setup in order to run the DPDK example
+applications.
+
+.. code-block:: console
+
+        echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
+        mkdir /mnt/huge
+        mount -t hugetlbfs nodev /mnt/huge
+
+Example applications can now be executed with crypto operations offloaded to
+OCTEONTX crypto PMD.
+
+.. code-block:: console
+
+        ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
+        "(1,0,0),(0,0,0)" -f ep1.cfg
+
-- 
2.7.4

Re: [dpdk-dev] [PATCH v3 32/32] doc: adds doc file

[Thomas Monjalon]

05/10/2018 14:59, Anoob Joseph:
> This patch adds the features file and the document containing
> help to compile and use octeontx crypto.

Some context is missing in this title.
I suggest:
	doc: add guide for OcteonTX crypto
or
	crypto/octeontx: add documentation

Re: [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD

[Akhil Goyal]

Hi Anoob,

Could you please add the change log in the cover note.

Thanks,
Akhil

On 10/5/2018 6:28 PM, Anoob Joseph wrote:
> Ankur Dwivedi (5):
>    common/cpt: add common logging support
>    config: add Cavium OCTEONTX crypto PMD skeleton
>    crypto/octeontx: add register addresses
>    common/cpt: add common code for init routine
>    test: adds validation test
>
> Anoob Joseph (5):
>    crypto/octeontx: add hardware init routine
>    common/cpt: add hardware register defines
>    crypto/octeontx: add hardware register access for misc poll
>    crypto/octeontx: adds symmetric capabilities
>    doc: adds doc file
>
> Murthy NSSR (5):
>    common/cpt: add PMD ops helper functions
>    crypto/octeontx: add global resource init
>    crypto/octeontx: add mailbox routines
>    crypto/octeontx: add basic dev ops
>    common/cpt: add common macros for queue pair ops
>
> Nithin Dabilpuram (5):
>    crypto/octeontx: add queue pair functions
>    common/cpt: add common code required for session management
>    crypto/octeontx: add session management ops
>    common/cpt: add common code for fill session data
>    crypto/octeontx: add supported sessions
>
> Ragothaman Jayaraman (4):
>    common/cpt: add common defines for microcode
>    common/cpt: add microcode interface for encryption
>    common/cpt: add microcode interface for decryption
>    common/cpt: add crypo op enqueue request manager framework
>
> Srisivasubramanian S (4):
>    common/cpt: add support for zuc and snow3g
>    common/cpt: add support for kasumi
>    common/cpt: add support for hash
>    crypto/octeontx: add routines to prepare instructions
>
> Tejasree Kondoj (4):
>    common/cpt: add common code for enqueuing cpt instruction
>    crypto/octeontx: add enqueue burst op
>    common/cpt: add common code for cpt dequeue
>    crypto/octeontx: add dequeue burst op
>
>   MAINTAINERS                                        |    7 +
>   config/common_base                                 |    5 +
>   doc/guides/cryptodevs/features/octeontx.ini        |   62 +
>   doc/guides/cryptodevs/index.rst                    |    1 +
>   doc/guides/cryptodevs/octeontx.rst                 |  128 +
>   drivers/common/Makefile                            |    4 +
>   drivers/common/cpt/Makefile                        |   25 +
>   drivers/common/cpt/cpt_common.h                    |   91 +
>   drivers/common/cpt/cpt_hw_types.h                  |  522 +++
>   drivers/common/cpt/cpt_mcode_defines.h             |  386 +++
>   drivers/common/cpt/cpt_pmd_logs.h                  |   50 +
>   drivers/common/cpt/cpt_pmd_ops_helper.c            |   41 +
>   drivers/common/cpt/cpt_pmd_ops_helper.h            |   34 +
>   drivers/common/cpt/cpt_request_mgr.h               |  185 +
>   drivers/common/cpt/cpt_ucode.h                     | 3650 ++++++++++++++++++++
>   drivers/common/cpt/meson.build                     |    8 +
>   drivers/common/cpt/rte_common_cpt_version.map      |    6 +
>   drivers/common/meson.build                         |    2 +-
>   drivers/crypto/Makefile                            |    1 +
>   drivers/crypto/meson.build                         |    2 +-
>   drivers/crypto/octeontx/Makefile                   |   46 +
>   drivers/crypto/octeontx/meson.build                |   18 +
>   drivers/crypto/octeontx/otx_cryptodev.c            |  133 +
>   drivers/crypto/octeontx/otx_cryptodev.h            |   20 +
>   .../crypto/octeontx/otx_cryptodev_capabilities.c   |  604 ++++
>   .../crypto/octeontx/otx_cryptodev_capabilities.h   |   17 +
>   drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  598 ++++
>   drivers/crypto/octeontx/otx_cryptodev_hw_access.h  |  320 ++
>   drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  178 +
>   drivers/crypto/octeontx/otx_cryptodev_mbox.h       |   92 +
>   drivers/crypto/octeontx/otx_cryptodev_ops.c        |  531 +++
>   drivers/crypto/octeontx/otx_cryptodev_ops.h        |   18 +
>   .../octeontx/rte_pmd_octeontx_crypto_version.map   |    4 +
>   mk/rte.app.mk                                      |    5 +
>   test/test/meson.build                              |    1 +
>   test/test/test_cryptodev.c                         |  316 ++
>   test/test/test_cryptodev.h                         |    1 +
>   test/test/test_cryptodev_aes_test_vectors.h        |  114 +-
>   test/test/test_cryptodev_blockcipher.c             |    9 +-
>   test/test/test_cryptodev_blockcipher.h             |    1 +
>   test/test/test_cryptodev_des_test_vectors.h        |   12 +-
>   test/test/test_cryptodev_hash_test_vectors.h       |   78 +-
>   42 files changed, 8255 insertions(+), 71 deletions(-)
>   create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
>   create mode 100644 doc/guides/cryptodevs/octeontx.rst
>   create mode 100644 drivers/common/cpt/Makefile
>   create mode 100644 drivers/common/cpt/cpt_common.h
>   create mode 100644 drivers/common/cpt/cpt_hw_types.h
>   create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
>   create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
>   create mode 100644 drivers/common/cpt/cpt_request_mgr.h
>   create mode 100644 drivers/common/cpt/cpt_ucode.h
>   create mode 100644 drivers/common/cpt/meson.build
>   create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
>   create mode 100644 drivers/crypto/octeontx/Makefile
>   create mode 100644 drivers/crypto/octeontx/meson.build
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.h
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
>   create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>

Re: [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD

[Joseph, Anoob]

Hi Akhil,

Do you want me to send revised cover letter patch or just summarizing it 
over email would do?

Thanks,
Anoob
On 05-10-2018 18:34, Akhil Goyal wrote:
> External Email
>
> Hi Anoob,
>
> Could you please add the change log in the cover note.
>
> Thanks,
> Akhil
>
> On 10/5/2018 6:28 PM, Anoob Joseph wrote:
>> Ankur Dwivedi (5):
>>    common/cpt: add common logging support
>>    config: add Cavium OCTEONTX crypto PMD skeleton
>>    crypto/octeontx: add register addresses
>>    common/cpt: add common code for init routine
>>    test: adds validation test
>>
>> Anoob Joseph (5):
>>    crypto/octeontx: add hardware init routine
>>    common/cpt: add hardware register defines
>>    crypto/octeontx: add hardware register access for misc poll
>>    crypto/octeontx: adds symmetric capabilities
>>    doc: adds doc file
>>
>> Murthy NSSR (5):
>>    common/cpt: add PMD ops helper functions
>>    crypto/octeontx: add global resource init
>>    crypto/octeontx: add mailbox routines
>>    crypto/octeontx: add basic dev ops
>>    common/cpt: add common macros for queue pair ops
>>
>> Nithin Dabilpuram (5):
>>    crypto/octeontx: add queue pair functions
>>    common/cpt: add common code required for session management
>>    crypto/octeontx: add session management ops
>>    common/cpt: add common code for fill session data
>>    crypto/octeontx: add supported sessions
>>
>> Ragothaman Jayaraman (4):
>>    common/cpt: add common defines for microcode
>>    common/cpt: add microcode interface for encryption
>>    common/cpt: add microcode interface for decryption
>>    common/cpt: add crypo op enqueue request manager framework
>>
>> Srisivasubramanian S (4):
>>    common/cpt: add support for zuc and snow3g
>>    common/cpt: add support for kasumi
>>    common/cpt: add support for hash
>>    crypto/octeontx: add routines to prepare instructions
>>
>> Tejasree Kondoj (4):
>>    common/cpt: add common code for enqueuing cpt instruction
>>    crypto/octeontx: add enqueue burst op
>>    common/cpt: add common code for cpt dequeue
>>    crypto/octeontx: add dequeue burst op
>>
>>   MAINTAINERS                                        |    7 +
>>   config/common_base                                 |    5 +
>>   doc/guides/cryptodevs/features/octeontx.ini        |   62 +
>>   doc/guides/cryptodevs/index.rst                    |    1 +
>>   doc/guides/cryptodevs/octeontx.rst                 |  128 +
>>   drivers/common/Makefile                            |    4 +
>>   drivers/common/cpt/Makefile                        |   25 +
>>   drivers/common/cpt/cpt_common.h                    |   91 +
>>   drivers/common/cpt/cpt_hw_types.h                  |  522 +++
>>   drivers/common/cpt/cpt_mcode_defines.h             |  386 +++
>>   drivers/common/cpt/cpt_pmd_logs.h                  |   50 +
>>   drivers/common/cpt/cpt_pmd_ops_helper.c            |   41 +
>>   drivers/common/cpt/cpt_pmd_ops_helper.h            |   34 +
>>   drivers/common/cpt/cpt_request_mgr.h               |  185 +
>>   drivers/common/cpt/cpt_ucode.h                     | 3650 
>> ++++++++++++++++++++
>>   drivers/common/cpt/meson.build                     |    8 +
>>   drivers/common/cpt/rte_common_cpt_version.map      |    6 +
>>   drivers/common/meson.build                         |    2 +-
>>   drivers/crypto/Makefile                            |    1 +
>>   drivers/crypto/meson.build                         |    2 +-
>>   drivers/crypto/octeontx/Makefile                   |   46 +
>>   drivers/crypto/octeontx/meson.build                |   18 +
>>   drivers/crypto/octeontx/otx_cryptodev.c            |  133 +
>>   drivers/crypto/octeontx/otx_cryptodev.h            |   20 +
>>   .../crypto/octeontx/otx_cryptodev_capabilities.c   |  604 ++++
>>   .../crypto/octeontx/otx_cryptodev_capabilities.h   |   17 +
>>   drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  598 ++++
>>   drivers/crypto/octeontx/otx_cryptodev_hw_access.h  |  320 ++
>>   drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  178 +
>>   drivers/crypto/octeontx/otx_cryptodev_mbox.h       |   92 +
>>   drivers/crypto/octeontx/otx_cryptodev_ops.c        |  531 +++
>>   drivers/crypto/octeontx/otx_cryptodev_ops.h        |   18 +
>>   .../octeontx/rte_pmd_octeontx_crypto_version.map   |    4 +
>>   mk/rte.app.mk                                      |    5 +
>>   test/test/meson.build                              |    1 +
>>   test/test/test_cryptodev.c                         |  316 ++
>>   test/test/test_cryptodev.h                         |    1 +
>>   test/test/test_cryptodev_aes_test_vectors.h        |  114 +-
>>   test/test/test_cryptodev_blockcipher.c             |    9 +-
>>   test/test/test_cryptodev_blockcipher.h             |    1 +
>>   test/test/test_cryptodev_des_test_vectors.h        |   12 +-
>>   test/test/test_cryptodev_hash_test_vectors.h       |   78 +-
>>   42 files changed, 8255 insertions(+), 71 deletions(-)
>>   create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
>>   create mode 100644 doc/guides/cryptodevs/octeontx.rst
>>   create mode 100644 drivers/common/cpt/Makefile
>>   create mode 100644 drivers/common/cpt/cpt_common.h
>>   create mode 100644 drivers/common/cpt/cpt_hw_types.h
>>   create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
>>   create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
>>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
>>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
>>   create mode 100644 drivers/common/cpt/cpt_request_mgr.h
>>   create mode 100644 drivers/common/cpt/cpt_ucode.h
>>   create mode 100644 drivers/common/cpt/meson.build
>>   create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
>>   create mode 100644 drivers/crypto/octeontx/Makefile
>>   create mode 100644 drivers/crypto/octeontx/meson.build
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
>>   create mode 100644 
>> drivers/crypto/octeontx/otx_cryptodev_capabilities.c
>>   create mode 100644 
>> drivers/crypto/octeontx/otx_cryptodev_capabilities.h
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
>>   create mode 100644 
>> drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>>
>

Re: [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD

[Akhil Goyal]

On 10/5/2018 6:43 PM, Joseph, Anoob wrote:
> Hi Akhil,
>
> Do you want me to send revised cover letter patch or just summarizing 
> it over email would do?
You could do it as you prefer. Just wanted to know the changes that were 
done in every version that are sent.
>
> Thanks,
> Anoob
> On 05-10-2018 18:34, Akhil Goyal wrote:
>> External Email
>>
>> Hi Anoob,
>>
>> Could you please add the change log in the cover note.
>>
>> Thanks,
>> Akhil
>>
>> On 10/5/2018 6:28 PM, Anoob Joseph wrote:
>>> Ankur Dwivedi (5):
>>>    common/cpt: add common logging support
>>>    config: add Cavium OCTEONTX crypto PMD skeleton
>>>    crypto/octeontx: add register addresses
>>>    common/cpt: add common code for init routine
>>>    test: adds validation test
>>>
>>> Anoob Joseph (5):
>>>    crypto/octeontx: add hardware init routine
>>>    common/cpt: add hardware register defines
>>>    crypto/octeontx: add hardware register access for misc poll
>>>    crypto/octeontx: adds symmetric capabilities
>>>    doc: adds doc file
>>>
>>> Murthy NSSR (5):
>>>    common/cpt: add PMD ops helper functions
>>>    crypto/octeontx: add global resource init
>>>    crypto/octeontx: add mailbox routines
>>>    crypto/octeontx: add basic dev ops
>>>    common/cpt: add common macros for queue pair ops
>>>
>>> Nithin Dabilpuram (5):
>>>    crypto/octeontx: add queue pair functions
>>>    common/cpt: add common code required for session management
>>>    crypto/octeontx: add session management ops
>>>    common/cpt: add common code for fill session data
>>>    crypto/octeontx: add supported sessions
>>>
>>> Ragothaman Jayaraman (4):
>>>    common/cpt: add common defines for microcode
>>>    common/cpt: add microcode interface for encryption
>>>    common/cpt: add microcode interface for decryption
>>>    common/cpt: add crypo op enqueue request manager framework
>>>
>>> Srisivasubramanian S (4):
>>>    common/cpt: add support for zuc and snow3g
>>>    common/cpt: add support for kasumi
>>>    common/cpt: add support for hash
>>>    crypto/octeontx: add routines to prepare instructions
>>>
>>> Tejasree Kondoj (4):
>>>    common/cpt: add common code for enqueuing cpt instruction
>>>    crypto/octeontx: add enqueue burst op
>>>    common/cpt: add common code for cpt dequeue
>>>    crypto/octeontx: add dequeue burst op
>>>
>>>   MAINTAINERS                                        |    7 +
>>>   config/common_base                                 |    5 +
>>>   doc/guides/cryptodevs/features/octeontx.ini        |   62 +
>>>   doc/guides/cryptodevs/index.rst                    |    1 +
>>>   doc/guides/cryptodevs/octeontx.rst                 |  128 +
>>>   drivers/common/Makefile                            |    4 +
>>>   drivers/common/cpt/Makefile                        |   25 +
>>>   drivers/common/cpt/cpt_common.h                    |   91 +
>>>   drivers/common/cpt/cpt_hw_types.h                  |  522 +++
>>>   drivers/common/cpt/cpt_mcode_defines.h             |  386 +++
>>>   drivers/common/cpt/cpt_pmd_logs.h                  |   50 +
>>>   drivers/common/cpt/cpt_pmd_ops_helper.c            |   41 +
>>>   drivers/common/cpt/cpt_pmd_ops_helper.h            |   34 +
>>>   drivers/common/cpt/cpt_request_mgr.h               |  185 +
>>>   drivers/common/cpt/cpt_ucode.h                     | 3650 
>>> ++++++++++++++++++++
>>>   drivers/common/cpt/meson.build                     |    8 +
>>>   drivers/common/cpt/rte_common_cpt_version.map      |    6 +
>>>   drivers/common/meson.build                         |    2 +-
>>>   drivers/crypto/Makefile                            |    1 +
>>>   drivers/crypto/meson.build                         |    2 +-
>>>   drivers/crypto/octeontx/Makefile                   |   46 +
>>>   drivers/crypto/octeontx/meson.build                |   18 +
>>>   drivers/crypto/octeontx/otx_cryptodev.c            |  133 +
>>>   drivers/crypto/octeontx/otx_cryptodev.h            |   20 +
>>>   .../crypto/octeontx/otx_cryptodev_capabilities.c   |  604 ++++
>>>   .../crypto/octeontx/otx_cryptodev_capabilities.h   |   17 +
>>>   drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  598 ++++
>>>   drivers/crypto/octeontx/otx_cryptodev_hw_access.h  |  320 ++
>>>   drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  178 +
>>>   drivers/crypto/octeontx/otx_cryptodev_mbox.h       |   92 +
>>>   drivers/crypto/octeontx/otx_cryptodev_ops.c        |  531 +++
>>>   drivers/crypto/octeontx/otx_cryptodev_ops.h        |   18 +
>>>   .../octeontx/rte_pmd_octeontx_crypto_version.map   |    4 +
>>>   mk/rte.app.mk                                      |    5 +
>>>   test/test/meson.build                              |    1 +
>>>   test/test/test_cryptodev.c                         |  316 ++
>>>   test/test/test_cryptodev.h                         |    1 +
>>>   test/test/test_cryptodev_aes_test_vectors.h        |  114 +-
>>>   test/test/test_cryptodev_blockcipher.c             |    9 +-
>>>   test/test/test_cryptodev_blockcipher.h             |    1 +
>>>   test/test/test_cryptodev_des_test_vectors.h        |   12 +-
>>>   test/test/test_cryptodev_hash_test_vectors.h       |   78 +-
>>>   42 files changed, 8255 insertions(+), 71 deletions(-)
>>>   create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
>>>   create mode 100644 doc/guides/cryptodevs/octeontx.rst
>>>   create mode 100644 drivers/common/cpt/Makefile
>>>   create mode 100644 drivers/common/cpt/cpt_common.h
>>>   create mode 100644 drivers/common/cpt/cpt_hw_types.h
>>>   create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
>>>   create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
>>>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
>>>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
>>>   create mode 100644 drivers/common/cpt/cpt_request_mgr.h
>>>   create mode 100644 drivers/common/cpt/cpt_ucode.h
>>>   create mode 100644 drivers/common/cpt/meson.build
>>>   create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
>>>   create mode 100644 drivers/crypto/octeontx/Makefile
>>>   create mode 100644 drivers/crypto/octeontx/meson.build
>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
>>>   create mode 100644 
>>> drivers/crypto/octeontx/otx_cryptodev_capabilities.c
>>>   create mode 100644 
>>> drivers/crypto/octeontx/otx_cryptodev_capabilities.h
>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h
>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h
>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
>>>   create mode 100644 
>>> drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>>>
>>
>

Re: [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD

[Joseph, Anoob]

Hi Akhil,

v2:
* Moved common code identified for crypto devices of OCTEON TX family to 
common/cpt.
* Divided the patches to make sure one feature gets added with one patch.
* Addressed indentation issues.
* Addressed comments from Jerin and Pablo.

v3:
* Merged v2-0001* & v2-0003* patch (Akhil)
* Replaced macro used in capabilities with array and function to return 
it (Thomas)
* Consistent comments in the code base (Akhil)
* Added missing comments for members of structure (Akhil)
* Added missing feature flags for scatter-gather (Akhil)
* Added validation tests for testing the newly introduced flags (Akhil)
* Added missing flags etc in doc (Akhil)
* Improvements in the function cpt_fc_ciph_set_key function (patch 0017)
* Fixed typos (Akhil)
* Other optimizations (removed non-critical members in structures 
accessed in data path etc)

Thanks,
Anoob
On 05-10-2018 18:44, Akhil Goyal wrote:
> External Email
>
> On 10/5/2018 6:43 PM, Joseph, Anoob wrote:
>> Hi Akhil,
>>
>> Do you want me to send revised cover letter patch or just summarizing
>> it over email would do?
> You could do it as you prefer. Just wanted to know the changes that were
> done in every version that are sent.
>>
>> Thanks,
>> Anoob
>> On 05-10-2018 18:34, Akhil Goyal wrote:
>>> External Email
>>>
>>> Hi Anoob,
>>>
>>> Could you please add the change log in the cover note.
>>>
>>> Thanks,
>>> Akhil
>>>
>>> On 10/5/2018 6:28 PM, Anoob Joseph wrote:
>>>> Ankur Dwivedi (5):
>>>>    common/cpt: add common logging support
>>>>    config: add Cavium OCTEONTX crypto PMD skeleton
>>>>    crypto/octeontx: add register addresses
>>>>    common/cpt: add common code for init routine
>>>>    test: adds validation test
>>>>
>>>> Anoob Joseph (5):
>>>>    crypto/octeontx: add hardware init routine
>>>>    common/cpt: add hardware register defines
>>>>    crypto/octeontx: add hardware register access for misc poll
>>>>    crypto/octeontx: adds symmetric capabilities
>>>>    doc: adds doc file
>>>>
>>>> Murthy NSSR (5):
>>>>    common/cpt: add PMD ops helper functions
>>>>    crypto/octeontx: add global resource init
>>>>    crypto/octeontx: add mailbox routines
>>>>    crypto/octeontx: add basic dev ops
>>>>    common/cpt: add common macros for queue pair ops
>>>>
>>>> Nithin Dabilpuram (5):
>>>>    crypto/octeontx: add queue pair functions
>>>>    common/cpt: add common code required for session management
>>>>    crypto/octeontx: add session management ops
>>>>    common/cpt: add common code for fill session data
>>>>    crypto/octeontx: add supported sessions
>>>>
>>>> Ragothaman Jayaraman (4):
>>>>    common/cpt: add common defines for microcode
>>>>    common/cpt: add microcode interface for encryption
>>>>    common/cpt: add microcode interface for decryption
>>>>    common/cpt: add crypo op enqueue request manager framework
>>>>
>>>> Srisivasubramanian S (4):
>>>>    common/cpt: add support for zuc and snow3g
>>>>    common/cpt: add support for kasumi
>>>>    common/cpt: add support for hash
>>>>    crypto/octeontx: add routines to prepare instructions
>>>>
>>>> Tejasree Kondoj (4):
>>>>    common/cpt: add common code for enqueuing cpt instruction
>>>>    crypto/octeontx: add enqueue burst op
>>>>    common/cpt: add common code for cpt dequeue
>>>>    crypto/octeontx: add dequeue burst op
>>>>
>>>>   MAINTAINERS                                        |    7 +
>>>>   config/common_base                                 |    5 +
>>>>   doc/guides/cryptodevs/features/octeontx.ini        |   62 +
>>>>   doc/guides/cryptodevs/index.rst                    |    1 +
>>>>   doc/guides/cryptodevs/octeontx.rst                 |  128 +
>>>>   drivers/common/Makefile                            |    4 +
>>>>   drivers/common/cpt/Makefile                        |   25 +
>>>>   drivers/common/cpt/cpt_common.h                    |   91 +
>>>>   drivers/common/cpt/cpt_hw_types.h                  |  522 +++
>>>>   drivers/common/cpt/cpt_mcode_defines.h             |  386 +++
>>>>   drivers/common/cpt/cpt_pmd_logs.h                  |   50 +
>>>>   drivers/common/cpt/cpt_pmd_ops_helper.c            |   41 +
>>>>   drivers/common/cpt/cpt_pmd_ops_helper.h            |   34 +
>>>>   drivers/common/cpt/cpt_request_mgr.h               |  185 +
>>>>   drivers/common/cpt/cpt_ucode.h                     | 3650
>>>> ++++++++++++++++++++
>>>>   drivers/common/cpt/meson.build                     |    8 +
>>>>   drivers/common/cpt/rte_common_cpt_version.map      |    6 +
>>>>   drivers/common/meson.build                         |    2 +-
>>>>   drivers/crypto/Makefile                            |    1 +
>>>>   drivers/crypto/meson.build                         |    2 +-
>>>>   drivers/crypto/octeontx/Makefile                   |   46 +
>>>>   drivers/crypto/octeontx/meson.build                |   18 +
>>>>   drivers/crypto/octeontx/otx_cryptodev.c            |  133 +
>>>>   drivers/crypto/octeontx/otx_cryptodev.h            |   20 +
>>>>   .../crypto/octeontx/otx_cryptodev_capabilities.c   |  604 ++++
>>>>   .../crypto/octeontx/otx_cryptodev_capabilities.h   |   17 +
>>>>   drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  598 ++++
>>>>   drivers/crypto/octeontx/otx_cryptodev_hw_access.h  |  320 ++
>>>>   drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  178 +
>>>>   drivers/crypto/octeontx/otx_cryptodev_mbox.h       |   92 +
>>>>   drivers/crypto/octeontx/otx_cryptodev_ops.c        |  531 +++
>>>>   drivers/crypto/octeontx/otx_cryptodev_ops.h        |   18 +
>>>>   .../octeontx/rte_pmd_octeontx_crypto_version.map   |    4 +
>>>>   mk/rte.app.mk                                      |    5 +
>>>>   test/test/meson.build                              |    1 +
>>>>   test/test/test_cryptodev.c                         |  316 ++
>>>>   test/test/test_cryptodev.h                         |    1 +
>>>>   test/test/test_cryptodev_aes_test_vectors.h        |  114 +-
>>>>   test/test/test_cryptodev_blockcipher.c             |    9 +-
>>>>   test/test/test_cryptodev_blockcipher.h             |    1 +
>>>>   test/test/test_cryptodev_des_test_vectors.h        |   12 +-
>>>>   test/test/test_cryptodev_hash_test_vectors.h       |   78 +-
>>>>   42 files changed, 8255 insertions(+), 71 deletions(-)
>>>>   create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
>>>>   create mode 100644 doc/guides/cryptodevs/octeontx.rst
>>>>   create mode 100644 drivers/common/cpt/Makefile
>>>>   create mode 100644 drivers/common/cpt/cpt_common.h
>>>>   create mode 100644 drivers/common/cpt/cpt_hw_types.h
>>>>   create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
>>>>   create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
>>>>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
>>>>   create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
>>>>   create mode 100644 drivers/common/cpt/cpt_request_mgr.h
>>>>   create mode 100644 drivers/common/cpt/cpt_ucode.h
>>>>   create mode 100644 drivers/common/cpt/meson.build
>>>>   create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
>>>>   create mode 100644 drivers/crypto/octeontx/Makefile
>>>>   create mode 100644 drivers/crypto/octeontx/meson.build
>>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
>>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
>>>>   create mode 100644
>>>> drivers/crypto/octeontx/otx_cryptodev_capabilities.c
>>>>   create mode 100644
>>>> drivers/crypto/octeontx/otx_cryptodev_capabilities.h
>>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
>>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h
>>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
>>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h
>>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
>>>>   create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
>>>>   create mode 100644
>>>> drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
>>>>
>>>
>>
>

Re: [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD

[Thomas Monjalon]

05/10/2018 14:58, Anoob Joseph:
> Ankur Dwivedi (5):
>   common/cpt: add common logging support
>   config: add Cavium OCTEONTX crypto PMD skeleton
>   crypto/octeontx: add register addresses
>   common/cpt: add common code for init routine
>   test: adds validation test
> 
> Anoob Joseph (5):
>   crypto/octeontx: add hardware init routine
>   common/cpt: add hardware register defines
>   crypto/octeontx: add hardware register access for misc poll
>   crypto/octeontx: adds symmetric capabilities
>   doc: adds doc file
> 
> Murthy NSSR (5):
>   common/cpt: add PMD ops helper functions
>   crypto/octeontx: add global resource init
>   crypto/octeontx: add mailbox routines
>   crypto/octeontx: add basic dev ops
>   common/cpt: add common macros for queue pair ops
> 
> Nithin Dabilpuram (5):
>   crypto/octeontx: add queue pair functions
>   common/cpt: add common code required for session management
>   crypto/octeontx: add session management ops
>   common/cpt: add common code for fill session data
>   crypto/octeontx: add supported sessions
> 
> Ragothaman Jayaraman (4):
>   common/cpt: add common defines for microcode
>   common/cpt: add microcode interface for encryption
>   common/cpt: add microcode interface for decryption
>   common/cpt: add crypo op enqueue request manager framework
> 
> Srisivasubramanian S (4):
>   common/cpt: add support for zuc and snow3g
>   common/cpt: add support for kasumi
>   common/cpt: add support for hash
>   crypto/octeontx: add routines to prepare instructions
> 
> Tejasree Kondoj (4):
>   common/cpt: add common code for enqueuing cpt instruction
>   crypto/octeontx: add enqueue burst op
>   common/cpt: add common code for cpt dequeue
>   crypto/octeontx: add dequeue burst op

A lot of patches are split in 2 parts for common/cpt and crypto/octeontx.
I think it is useless most of the time.
You are allowed to update any related code in the common part
while implementing some features in the crypto driver.

Re: [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD

[Joseph, Anoob]

Hi Thomas,

On 08-10-2018 18:03, Thomas Monjalon wrote:
> External Email
>
> 05/10/2018 14:58, Anoob Joseph:
>> Ankur Dwivedi (5):
>>    common/cpt: add common logging support
>>    config: add Cavium OCTEONTX crypto PMD skeleton
>>    crypto/octeontx: add register addresses
>>    common/cpt: add common code for init routine
>>    test: adds validation test
>>
>> Anoob Joseph (5):
>>    crypto/octeontx: add hardware init routine
>>    common/cpt: add hardware register defines
>>    crypto/octeontx: add hardware register access for misc poll
>>    crypto/octeontx: adds symmetric capabilities
>>    doc: adds doc file
>>
>> Murthy NSSR (5):
>>    common/cpt: add PMD ops helper functions
>>    crypto/octeontx: add global resource init
>>    crypto/octeontx: add mailbox routines
>>    crypto/octeontx: add basic dev ops
>>    common/cpt: add common macros for queue pair ops
>>
>> Nithin Dabilpuram (5):
>>    crypto/octeontx: add queue pair functions
>>    common/cpt: add common code required for session management
>>    crypto/octeontx: add session management ops
>>    common/cpt: add common code for fill session data
>>    crypto/octeontx: add supported sessions
>>
>> Ragothaman Jayaraman (4):
>>    common/cpt: add common defines for microcode
>>    common/cpt: add microcode interface for encryption
>>    common/cpt: add microcode interface for decryption
>>    common/cpt: add crypo op enqueue request manager framework
>>
>> Srisivasubramanian S (4):
>>    common/cpt: add support for zuc and snow3g
>>    common/cpt: add support for kasumi
>>    common/cpt: add support for hash
>>    crypto/octeontx: add routines to prepare instructions
>>
>> Tejasree Kondoj (4):
>>    common/cpt: add common code for enqueuing cpt instruction
>>    crypto/octeontx: add enqueue burst op
>>    common/cpt: add common code for cpt dequeue
>>    crypto/octeontx: add dequeue burst op
> A lot of patches are split in 2 parts for common/cpt and crypto/octeontx.
> I think it is useless most of the time.
> You are allowed to update any related code in the common part
> while implementing some features in the crypto driver.
The tool, check-git-log.sh was giving warnings when we were making 
changes in two places. That's one reason we had to split it this way.

Anoob

Re: [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD

[Thomas Monjalon]

08/10/2018 14:58, Joseph, Anoob:
> On 08-10-2018 18:03, Thomas Monjalon wrote:
> > A lot of patches are split in 2 parts for common/cpt and crypto/octeontx.
> > I think it is useless most of the time.
> > You are allowed to update any related code in the common part
> > while implementing some features in the crypto driver.
> The tool, check-git-log.sh was giving warnings when we were making 
> changes in two places. That's one reason we had to split it this way.

By definition, a tool is silly :-)
It is raising a warning to ask you checking manually.
If you know what you do, you can ignore this warning.

[dpdk-dev] [PATCH v4 00/23] Adding Cavium's OCTEON TX crypto PMD

[Anoob Joseph]

v4:
* Marged the following v3 patches (Akhil & Thomas),
    - 01/32 & 02/32
    - 03/32, 04/32 & 05/32
    - 06/32 & 07/32
    - 13/32 & 14/32
    - 15/32 & 16/32
    - 17/32 & 18/32
    - 27/32 & 28/32
    - 29/32 & 30/32
* Replaced usages OCTEONTX with OCTEON TX (Thomas & Jerin)
* Fixed commit logs in v3 02/32 (Thomas)
* Replaced references to cpt with octeontx in v3 31/32 (Akhil)
* Fixed commit logs in v3 31/32 (Akhil)

v3:
* Merged v2-0001* & v2-0003* patch (Akhil)
* Replaced macro used in capabilities with array and function to return
it (Thomas)
* Consistent comments in the code base (Akhil)
* Added missing comments for members of structure (Akhil)
* Added missing feature flags for scatter-gather (Akhil)
* Added validation tests for testing the newly introduced flags (Akhil)
* Added missing flags etc in doc (Akhil)
* Improvements in the function cpt_fc_ciph_set_key function (patch 0017)
* Fixed typos (Akhil)
* Other optimizations (removed non-critical members in structures
accessed in data path etc)

v2:
* Moved common code identified for crypto devices of OCTEON TX family to
common/cpt.
* Divided the patches to make sure one feature gets added with one patch.
* Addressed indentation issues.
* Addressed comments from Jerin and Pablo.


Ankur Dwivedi (4):
  crypto/octeontx: add hardware init routine
  crypto/octeontx: add hardware register access for misc poll
  crypto/octeontx: add symmetric capabilities
  test/crypto: add OCTEON TX unit tests

Anoob Joseph (4):
  crypto/octeontx: add PMD skeleton
  common/cpt: add PMD ops helper functions
  crypto/octeontx: add global resource init
  doc: add documentation for OCTEON TX crypto

Murthy NSSR (3):
  crypto/octeontx: add mailbox routines
  crypto/octeontx: add basic dev ops
  crypto/octeontx: add queue pair functions

Nithin Dabilpuram (3):
  crypto/octeontx: add session management ops
  crypto/octeontx: add supported sessions
  common/cpt: add common defines for microcode

Ragothaman Jayaraman (3):
  common/cpt: add microcode interface for encryption
  common/cpt: add microcode interface for decryption
  common/cpt: add crypo op enqueue request manager framework

Srisivasubramanian S (3):
  common/cpt: support zuc and snow3g
  common/cpt: support kasumi
  common/cpt: support hash

Tejasree Kondoj (3):
  crypto/octeontx: add routines to prepare instructions
  crypto/octeontx: add enqueue burst op
  crypto/octeontx: add dequeue burst op

 MAINTAINERS                                        |    7 +
 config/common_base                                 |    5 +
 doc/guides/cryptodevs/features/octeontx.ini        |   62 +
 doc/guides/cryptodevs/index.rst                    |    1 +
 doc/guides/cryptodevs/octeontx.rst                 |  128 +
 drivers/common/Makefile                            |    4 +
 drivers/common/cpt/Makefile                        |   25 +
 drivers/common/cpt/cpt_common.h                    |   91 +
 drivers/common/cpt/cpt_hw_types.h                  |  522 +++
 drivers/common/cpt/cpt_mcode_defines.h             |  386 +++
 drivers/common/cpt/cpt_pmd_logs.h                  |   50 +
 drivers/common/cpt/cpt_pmd_ops_helper.c            |   41 +
 drivers/common/cpt/cpt_pmd_ops_helper.h            |   34 +
 drivers/common/cpt/cpt_request_mgr.h               |  185 +
 drivers/common/cpt/cpt_ucode.h                     | 3648 ++++++++++++++++++++
 drivers/common/cpt/meson.build                     |    8 +
 drivers/common/cpt/rte_common_cpt_version.map      |    6 +
 drivers/common/meson.build                         |    2 +-
 drivers/crypto/Makefile                            |    1 +
 drivers/crypto/meson.build                         |    2 +-
 drivers/crypto/octeontx/Makefile                   |   46 +
 drivers/crypto/octeontx/meson.build                |   18 +
 drivers/crypto/octeontx/otx_cryptodev.c            |  133 +
 drivers/crypto/octeontx/otx_cryptodev.h            |   20 +
 .../crypto/octeontx/otx_cryptodev_capabilities.c   |  604 ++++
 .../crypto/octeontx/otx_cryptodev_capabilities.h   |   17 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c  |  598 ++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h  |  320 ++
 drivers/crypto/octeontx/otx_cryptodev_mbox.c       |  178 +
 drivers/crypto/octeontx/otx_cryptodev_mbox.h       |   92 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c        |  531 +++
 drivers/crypto/octeontx/otx_cryptodev_ops.h        |   18 +
 .../octeontx/rte_pmd_octeontx_crypto_version.map   |    4 +
 mk/rte.app.mk                                      |    5 +
 test/test/meson.build                              |    1 +
 test/test/test_cryptodev.c                         |  318 ++
 test/test/test_cryptodev.h                         |    1 +
 test/test/test_cryptodev_aes_test_vectors.h        |  114 +-
 test/test/test_cryptodev_blockcipher.c             |    9 +-
 test/test/test_cryptodev_blockcipher.h             |    1 +
 test/test/test_cryptodev_des_test_vectors.h        |   12 +-
 test/test/test_cryptodev_hash_test_vectors.h       |   78 +-
 42 files changed, 8255 insertions(+), 71 deletions(-)
 create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
 create mode 100644 doc/guides/cryptodevs/octeontx.rst
 create mode 100644 drivers/common/cpt/Makefile
 create mode 100644 drivers/common/cpt/cpt_common.h
 create mode 100644 drivers/common/cpt/cpt_hw_types.h
 create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
 create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
 create mode 100644 drivers/common/cpt/cpt_request_mgr.h
 create mode 100644 drivers/common/cpt/cpt_ucode.h
 create mode 100644 drivers/common/cpt/meson.build
 create mode 100644 drivers/common/cpt/rte_common_cpt_version.map
 create mode 100644 drivers/crypto/octeontx/Makefile
 create mode 100644 drivers/crypto/octeontx/meson.build
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
 create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map

-- 
2.7.4

[dpdk-dev] [PATCH v4 01/23] crypto/octeontx: add PMD skeleton

[Anoob Joseph]

Adding OCTEON TX crypto PMD skeleton. Updating the maintainers files to
claim responsibility. Also enabling driver by default by adding the
component in common_base.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 MAINTAINERS                                        |   5 +
 config/common_base                                 |   5 +
 drivers/common/cpt/cpt_pmd_logs.h                  |  50 ++++++++
 drivers/crypto/Makefile                            |   1 +
 drivers/crypto/meson.build                         |   2 +-
 drivers/crypto/octeontx/Makefile                   |  42 +++++++
 drivers/crypto/octeontx/meson.build                |  14 +++
 drivers/crypto/octeontx/otx_cryptodev.c            | 130 +++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev.h            |  20 ++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c        |  15 +++
 drivers/crypto/octeontx/otx_cryptodev_ops.h        |  11 ++
 .../octeontx/rte_pmd_octeontx_crypto_version.map   |   4 +
 mk/rte.app.mk                                      |   1 +
 13 files changed, 299 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cpt/cpt_pmd_logs.h
 create mode 100644 drivers/crypto/octeontx/Makefile
 create mode 100644 drivers/crypto/octeontx/meson.build
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h
 create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 84b9ff7..001bae9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -779,6 +779,11 @@ F: drivers/crypto/armv8/
 F: doc/guides/cryptodevs/armv8.rst
 F: doc/guides/cryptodevs/features/armv8.ini
 
+Cavium OCTEON TX crypto
+M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
+F: drivers/common/cpt/
+F: drivers/crypto/octeontx/
+
 Crypto Scheduler
 M: Fan Zhang <roy.fan.zhang@intel.com>
 F: drivers/crypto/scheduler/
diff --git a/config/common_base b/config/common_base
index 43c7e9a..85fad0c 100644
--- a/config/common_base
+++ b/config/common_base
@@ -640,6 +640,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
 CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
 
 #
+# Compile PMD for Cavium OCTEON TX crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
+
+#
 # Compile raw device support
 # EXPERIMENTAL: API may change without prior notice
 #
diff --git a/drivers/common/cpt/cpt_pmd_logs.h b/drivers/common/cpt/cpt_pmd_logs.h
new file mode 100644
index 0000000..4cbec4e
--- /dev/null
+++ b/drivers/common/cpt/cpt_pmd_logs.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_PMD_LOGS_H_
+#define _CPT_PMD_LOGS_H_
+
+#include <rte_log.h>
+
+/*
+ * This file defines log macros
+ */
+
+#define CPT_PMD_DRV_LOG_RAW(level, fmt, args...) \
+		rte_log(RTE_LOG_ ## level, cpt_logtype, \
+			"cpt: %s(): " fmt "\n", __func__, ##args)
+
+#define CPT_PMD_INIT_FUNC_TRACE() CPT_PMD_DRV_LOG_RAW(DEBUG, " >>")
+
+#define CPT_LOG_INFO(fmt, args...) \
+	CPT_PMD_DRV_LOG_RAW(INFO, fmt, ## args)
+#define CPT_LOG_WARN(fmt, args...) \
+	CPT_PMD_DRV_LOG_RAW(WARNING, fmt, ## args)
+#define CPT_LOG_ERR(fmt, args...) \
+	CPT_PMD_DRV_LOG_RAW(ERR, fmt, ## args)
+
+/*
+ * DP logs, toggled out at compile time if level lower than current level.
+ * DP logs would be logged under 'PMD' type. So for dynamic logging, the
+ * level of 'pmd' has to be used.
+ */
+#define CPT_LOG_DP(level, fmt, args...) \
+	RTE_LOG_DP(level, PMD, fmt "\n", ## args)
+
+#define CPT_LOG_DP_DEBUG(fmt, args...) \
+	CPT_LOG_DP(DEBUG, fmt, ## args)
+#define CPT_LOG_DP_INFO(fmt, args...) \
+	CPT_LOG_DP(INFO, fmt, ## args)
+#define CPT_LOG_DP_WARN(fmt, args...) \
+	CPT_LOG_DP(WARNING, fmt, ## args)
+#define CPT_LOG_DP_ERR(fmt, args...) \
+	CPT_LOG_DP(ERR, fmt, ## args)
+
+/*
+ * cpt_logtype will be used for common logging. This field would be initialized
+ * by otx_* driver routines during PCI probe.
+ */
+int cpt_logtype;
+
+#endif /* _CPT_PMD_LOGS_H_ */
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index c480cbd..c083e64 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -7,6 +7,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += aesni_gcm
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 6ed853b..b09fe1b 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -2,7 +2,7 @@
 # Copyright(c) 2017 Intel Corporation
 
 drivers = ['ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam',
-	'null', 'openssl', 'qat', 'scheduler', 'virtio']
+	'null', 'octeontx', 'openssl', 'qat', 'scheduler', 'virtio']
 
 std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
 config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
new file mode 100644
index 0000000..12fec75
--- /dev/null
+++ b/drivers/crypto/octeontx/Makefile
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_octeontx_crypto.a
+
+# library version
+LIBABIVER := 1
+
+# build flags
+CFLAGS += $(WERROR_FLAGS)
+
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_cryptodev
+LDLIBS += -lrte_pci -lrte_bus_pci
+
+VPATH += $(RTE_SDK)/drivers/crypto/octeontx
+
+CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX
+CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
+
+# PMD code
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
+
+# export include files
+SYMLINK-y-include +=
+
+# versioning export map
+EXPORT_MAP := rte_pmd_octeontx_crypto_version.map
+
+# library dependencies
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_eal
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_cryptodev
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mempool
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mbuf
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_malloc
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
new file mode 100644
index 0000000..6564090
--- /dev/null
+++ b/drivers/crypto/octeontx/meson.build
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+if host_machine.system() != 'linux'
+	build = false
+endif
+
+deps += ['bus_pci']
+name = 'octeontx_crypto'
+
+sources = files('otx_cryptodev.c',
+		'otx_cryptodev_ops.c')
+
+cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
+includes += include_directories('../../common/cpt')
diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c
new file mode 100644
index 0000000..43933dd
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev.c
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_log.h>
+#include <rte_pci.h>
+
+/* CPT common headers */
+#include "cpt_pmd_logs.h"
+
+#include "otx_cryptodev.h"
+#include "otx_cryptodev_ops.h"
+
+static int otx_cryptodev_logtype;
+
+static struct rte_pci_id pci_id_cpt_table[] = {
+	{
+		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_VF_DEVICE_ID),
+	},
+	/* sentinel */
+	{
+		.device_id = 0
+	},
+};
+
+static void
+otx_cpt_logtype_init(void)
+{
+	cpt_logtype = otx_cryptodev_logtype;
+}
+
+static int
+otx_cpt_pci_probe(struct rte_pci_driver *pci_drv,
+			struct rte_pci_device *pci_dev)
+{
+	struct rte_cryptodev *cryptodev;
+	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+	int retval;
+
+	if (pci_drv == NULL)
+		return -ENODEV;
+
+	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+	cryptodev = rte_cryptodev_pmd_allocate(name, rte_socket_id());
+	if (cryptodev == NULL)
+		return -ENOMEM;
+
+	cryptodev->device = &pci_dev->device;
+	cryptodev->device->driver = &pci_drv->driver;
+	cryptodev->driver_id = otx_cryptodev_driver_id;
+
+	/* init user callbacks */
+	TAILQ_INIT(&(cryptodev->link_intr_cbs));
+
+	/* init logtype used in common */
+	otx_cpt_logtype_init();
+
+	/* Invoke PMD device initialization function */
+	retval = otx_cpt_dev_create(cryptodev);
+	if (retval == 0)
+		return 0;
+
+	CPT_LOG_ERR("[DRV %s]: Failed to create device "
+			"(vendor_id: 0x%x device_id: 0x%x",
+			pci_drv->driver.name,
+			(unsigned int) pci_dev->id.vendor_id,
+			(unsigned int) pci_dev->id.device_id);
+
+	cryptodev->attached = RTE_CRYPTODEV_DETACHED;
+
+	return -ENXIO;
+}
+
+static int
+otx_cpt_pci_remove(struct rte_pci_device *pci_dev)
+{
+	struct rte_cryptodev *cryptodev;
+	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+
+	if (pci_dev == NULL)
+		return -EINVAL;
+
+	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+	cryptodev = rte_cryptodev_pmd_get_named_dev(name);
+	if (cryptodev == NULL)
+		return -ENODEV;
+
+	if (pci_dev->driver == NULL)
+		return -ENODEV;
+
+	/* free crypto device */
+	rte_cryptodev_pmd_release_device(cryptodev);
+
+	if (rte_eal_process_type() == RTE_PROC_PRIMARY)
+		rte_free(cryptodev->data->dev_private);
+
+	cryptodev->device = NULL;
+	cryptodev->device->driver = NULL;
+	cryptodev->data = NULL;
+
+	return 0;
+}
+
+static struct rte_pci_driver otx_cryptodev_pmd = {
+	.id_table = pci_id_cpt_table,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+	.probe = otx_cpt_pci_probe,
+	.remove = otx_cpt_pci_remove,
+};
+
+static struct cryptodev_driver otx_cryptodev_drv;
+
+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX_PMD, otx_cryptodev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX_PMD, pci_id_cpt_table);
+RTE_PMD_REGISTER_CRYPTO_DRIVER(otx_cryptodev_drv, otx_cryptodev_pmd.driver,
+		otx_cryptodev_driver_id);
+
+RTE_INIT(otx_cpt_init_log)
+{
+	/* Bus level logs */
+	otx_cryptodev_logtype = rte_log_register("pmd.crypto.octeontx");
+	if (otx_cryptodev_logtype >= 0)
+		rte_log_set_level(otx_cryptodev_logtype, RTE_LOG_NOTICE);
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev.h b/drivers/crypto/octeontx/otx_cryptodev.h
new file mode 100644
index 0000000..6c2871d
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_H_
+#define _OTX_CRYPTODEV_H_
+
+/* Cavium OCTEON TX crypto PMD device name */
+#define CRYPTODEV_NAME_OCTEONTX_PMD	crypto_octeontx
+
+/* Device ID */
+#define PCI_VENDOR_ID_CAVIUM		0x177d
+#define CPT_81XX_PCI_VF_DEVICE_ID	0xa041
+
+/*
+ * Crypto device driver ID
+ */
+uint8_t otx_cryptodev_driver_id;
+
+#endif /* _OTX_CRYPTODEV_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
new file mode 100644
index 0000000..1b5f108
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_cryptodev.h>
+
+#include "otx_cryptodev.h"
+#include "otx_cryptodev_ops.h"
+
+int
+otx_cpt_dev_create(struct rte_cryptodev *c_dev)
+{
+	RTE_SET_USED(c_dev);
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
new file mode 100644
index 0000000..3f2d829
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_OPS_H_
+#define _OTX_CRYPTODEV_OPS_H_
+
+int
+otx_cpt_dev_create(struct rte_cryptodev *c_dev);
+
+#endif /* _OTX_CRYPTODEV_OPS_H_ */
diff --git a/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
new file mode 100644
index 0000000..521e51f
--- /dev/null
+++ b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map
@@ -0,0 +1,4 @@
+DPDK_18.11 {
+
+	local: *;
+};
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 73d20c3..9661cdf 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -217,6 +217,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC)         += -L$(LIBSSO_ZUC_PATH)/build -lsso
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -lrte_pmd_armv8
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler
 ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC)   += -lrte_pmd_dpaa2_sec
-- 
2.7.4

[dpdk-dev] [PATCH v4 02/23] crypto/octeontx: add hardware init routine

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Adding hardware init routine for OCTEON TX crypto device. A place holder
is added for misc polling routine. That will be added in the further
patches.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h                   |  47 ++++++++
 drivers/crypto/octeontx/Makefile                  |   1 +
 drivers/crypto/octeontx/meson.build               |   1 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c |  48 ++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 134 ++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       |  92 ++++++++++++++-
 6 files changed, 322 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cpt/cpt_common.h
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
new file mode 100644
index 0000000..5e2099a
--- /dev/null
+++ b/drivers/common/cpt/cpt_common.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_COMMON_H_
+#define _CPT_COMMON_H_
+
+/*
+ * This file defines common macros and structs
+ */
+
+/*
+ * Macros to determine CPT model. Driver makefile will define CPT_MODEL
+ * accordingly
+ */
+#define CRYPTO_OCTEONTX		0x1
+
+#define AE_TYPE 1
+#define SE_TYPE 2
+
+struct cptvf_meta_info {
+	void *cptvf_meta_pool;
+	int cptvf_op_mlen;
+	int cptvf_op_sb_mlen;
+};
+
+struct rid {
+	/** Request id of a crypto operation */
+	uintptr_t rid;
+};
+
+/*
+ * Pending queue structure
+ *
+ */
+struct pending_queue {
+	/** Tail of queue to be used for enqueue */
+	uint16_t enq_tail;
+	/** Head of queue to be used for dequeue */
+	uint16_t deq_head;
+	/** Array of pending requests */
+	struct rid *rid_queue;
+	/** Pending requests count */
+	uint64_t pending_count;
+};
+
+#endif /* _CPT_COMMON_H_ */
diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 12fec75..4582540 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -24,6 +24,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
 
 # PMD code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
 
 # export include files
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index 6564090..eca1cf1 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -8,6 +8,7 @@ deps += ['bus_pci']
 name = 'octeontx_crypto'
 
 sources = files('otx_cryptodev.c',
+		'otx_cryptodev_hw_access.c',
 		'otx_cryptodev_ops.c')
 
 cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
new file mode 100644
index 0000000..99fe3cf
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+#include <string.h>
+
+#include <rte_common.h>
+
+#include "otx_cryptodev_hw_access.h"
+
+#include "cpt_pmd_logs.h"
+
+static int
+otx_cpt_vf_init(struct cpt_vf *cptvf)
+{
+	int ret = 0;
+
+	CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
+
+	return ret;
+}
+
+void
+otx_cpt_poll_misc(struct cpt_vf *cptvf)
+{
+	RTE_SET_USED(cptvf);
+}
+
+int
+otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
+{
+	memset(cptvf, 0, sizeof(struct cpt_vf));
+
+	/* Bar0 base address */
+	cptvf->reg_base = reg_base;
+	strncpy(cptvf->dev_name, name, 32);
+
+	cptvf->pdev = pdev;
+
+	/* To clear if there are any pending mbox msgs */
+	otx_cpt_poll_misc(cptvf);
+
+	if (otx_cpt_vf_init(cptvf)) {
+		CPT_LOG_ERR("Failed to initialize CPT VF device");
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
new file mode 100644
index 0000000..1e1877c
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
+#define _OTX_CRYPTODEV_HW_ACCESS_H_
+
+#include <stdbool.h>
+
+#include <rte_memory.h>
+
+#include "cpt_common.h"
+
+#define CPT_INTR_POLL_INTERVAL_MS	(50)
+
+/* Default command queue length */
+#define DEFAULT_CMD_QCHUNKS		2
+
+/* cpt instance */
+struct cpt_instance {
+	uint32_t queue_id;
+	uintptr_t rsvd;
+};
+
+struct command_chunk {
+	/** 128-byte aligned real_vaddr */
+	uint8_t *head;
+	/** 128-byte aligned real_dma_addr */
+	phys_addr_t dma_addr;
+};
+
+/**
+ * Command queue structure
+ */
+struct command_queue {
+	/** Command queue host write idx */
+	uint32_t idx;
+	/** Command queue chunk */
+	uint32_t cchunk;
+	/** Command queue head; instructions are inserted here */
+	uint8_t *qhead;
+	/** Command chunk list head */
+	struct command_chunk chead[DEFAULT_CMD_QCHUNKS];
+};
+
+/**
+ * CPT VF device structure
+ */
+struct cpt_vf {
+	/** CPT instance */
+	struct cpt_instance instance;
+	/** Register start address */
+	uint8_t *reg_base;
+	/** Command queue information */
+	struct command_queue cqueue;
+	/** Pending queue information */
+	struct pending_queue pqueue;
+	/** Meta information per vf */
+	struct cptvf_meta_info meta_info;
+
+	/** Below fields are accessed only in control path */
+
+	/** Env specific pdev representing the pci dev */
+	void *pdev;
+	/** Calculated queue size */
+	uint32_t qsize;
+	/** Device index (0...CPT_MAX_VQ_NUM)*/
+	uint8_t  vfid;
+	/** VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
+	uint8_t  vftype;
+	/** VF group (0 - 8) */
+	uint8_t  vfgrp;
+	/** Operating node: Bits (46:44) in BAR0 address */
+	uint8_t  node;
+
+	/** VF-PF mailbox communication */
+
+	/** Flag if acked */
+	bool pf_acked;
+	/** Flag if not acked */
+	bool pf_nacked;
+
+	/** Device name */
+	char dev_name[32];
+} __rte_cache_aligned;
+
+/*
+ * CPT Registers map for 81xx
+ */
+
+/* VF registers */
+#define CPTX_VQX_CTL(a, b)		(0x0000100ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_SADDR(a, b)		(0x0000200ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_WAIT(a, b)	(0x0000400ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_INPROG(a, b)		(0x0000410ll + 0x1000000000ll * \
+					 ((a) & 0x0) + 0x100000ll * (b))
+#define CPTX_VQX_DONE(a, b)		(0x0000420ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ACK(a, b)		(0x0000440ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1S(a, b)	(0x0000460ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_INT_W1C(a, b)	(0x0000468ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1S(a, b)	(0x0000470ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DONE_ENA_W1C(a, b)	(0x0000478ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT(a, b)		(0x0000500ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_INT_W1S(a, b)	(0x0000508ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1S(a, b)	(0x0000510ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_MISC_ENA_W1C(a, b)	(0x0000518ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VQX_DOORBELL(a, b)		(0x0000600ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b))
+#define CPTX_VFX_PF_MBOXX(a, b, c)	(0x0001000ll + 0x1000000000ll * \
+					 ((a) & 0x1) + 0x100000ll * (b) + \
+					 8ll * ((c) & 0x1))
+
+/* VF HAL functions */
+
+void
+otx_cpt_poll_misc(struct cpt_vf *cptvf);
+
+int
+otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
+
+#endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 1b5f108..3bf6cd2 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -2,14 +2,104 @@
  * Copyright(c) 2018 Cavium, Inc
  */
 
+#include <rte_alarm.h>
+#include <rte_bus_pci.h>
 #include <rte_cryptodev.h>
+#include <rte_malloc.h>
+
+#include "cpt_pmd_logs.h"
 
 #include "otx_cryptodev.h"
+#include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_ops.h"
 
+/* Alarm routines */
+
+static void
+otx_cpt_alarm_cb(void *arg)
+{
+	struct cpt_vf *cptvf = arg;
+	otx_cpt_poll_misc(cptvf);
+	rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,
+			  otx_cpt_alarm_cb, cptvf);
+}
+
+static int
+otx_cpt_periodic_alarm_start(void *arg)
+{
+	return rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,
+				 otx_cpt_alarm_cb, arg);
+}
+
 int
 otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 {
-	RTE_SET_USED(c_dev);
+	struct rte_pci_device *pdev = RTE_DEV_TO_PCI(c_dev->device);
+	struct cpt_vf *cptvf = NULL;
+	void *reg_base;
+	char dev_name[32];
+	int ret;
+
+	if (pdev->mem_resource[0].phys_addr == 0ULL)
+		return -EIO;
+
+	/* for secondary processes, we don't initialise any further as primary
+	 * has already done this work.
+	 */
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	cptvf = rte_zmalloc_socket("otx_cryptodev_private_mem",
+			sizeof(struct cpt_vf), RTE_CACHE_LINE_SIZE,
+			rte_socket_id());
+
+	if (cptvf == NULL) {
+		CPT_LOG_ERR("Cannot allocate memory for device private data");
+		return -ENOMEM;
+	}
+
+	snprintf(dev_name, 32, "%02x:%02x.%x",
+			pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
+
+	reg_base = pdev->mem_resource[0].addr;
+	if (!reg_base) {
+		CPT_LOG_ERR("Failed to map BAR0 of %s", dev_name);
+		ret = -ENODEV;
+		goto fail;
+	}
+
+	ret = otx_cpt_hw_init(cptvf, pdev, reg_base, dev_name);
+	if (ret) {
+		CPT_LOG_ERR("Failed to init cptvf %s", dev_name);
+		ret = -EIO;
+		goto fail;
+	}
+
+	/* Start off timer for mailbox interrupts */
+	otx_cpt_periodic_alarm_start(cptvf);
+
+	c_dev->dev_ops = NULL;
+
+	c_dev->enqueue_burst = NULL;
+	c_dev->dequeue_burst = NULL;
+
+	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+			RTE_CRYPTODEV_FF_HW_ACCELERATED |
+			RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
+			RTE_CRYPTODEV_FF_IN_PLACE_SGL |
+			RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
+			RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
+
+	/* Save dev private data */
+	c_dev->data->dev_private = cptvf;
+
 	return 0;
+
+fail:
+	if (cptvf) {
+		/* Free private data allocated */
+		rte_free(cptvf);
+	}
+
+	return ret;
 }
-- 
2.7.4

[dpdk-dev] [PATCH v4 03/23] crypto/octeontx: add hardware register access for misc poll

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Adding hardware register accesses required for misc poll

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_hw_types.h                 | 519 ++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 192 +++++++-
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h |  11 +
 3 files changed, 721 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cpt/cpt_hw_types.h

diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h
new file mode 100644
index 0000000..0a98621
--- /dev/null
+++ b/drivers/common/cpt/cpt_hw_types.h
@@ -0,0 +1,519 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_HW_TYPES_H_
+#define _CPT_HW_TYPES_H_
+
+#include <rte_byteorder.h>
+
+/*
+ * This file defines HRM specific structs.
+ *
+ */
+
+#define CPT_VF_INTR_MBOX_MASK   (1<<0)
+#define CPT_VF_INTR_DOVF_MASK   (1<<1)
+#define CPT_VF_INTR_IRDE_MASK   (1<<2)
+#define CPT_VF_INTR_NWRP_MASK   (1<<3)
+#define CPT_VF_INTR_SWERR_MASK  (1<<4)
+#define CPT_VF_INTR_HWERR_MASK  (1<<5)
+#define CPT_VF_INTR_FAULT_MASK  (1<<6)
+
+/*
+ * CPT_INST_S software command definitions
+ * Words EI (0-3)
+ */
+typedef union {
+	uint64_t u64;
+	struct {
+		uint16_t opcode;
+		uint16_t param1;
+		uint16_t param2;
+		uint16_t dlen;
+	} s;
+} vq_cmd_word0_t;
+
+typedef union {
+	uint64_t u64;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint64_t grp	: 3;
+		uint64_t cptr	: 61;
+#else
+		uint64_t cptr	: 61;
+		uint64_t grp	: 3;
+#endif
+	} s;
+} vq_cmd_word3_t;
+
+typedef struct cpt_vq_command {
+	vq_cmd_word0_t cmd;
+	uint64_t dptr;
+	uint64_t rptr;
+	vq_cmd_word3_t cptr;
+} cpt_vq_cmd_t;
+
+/**
+ * Structure cpt_inst_s
+ *
+ * CPT Instruction Structure
+ * This structure specifies the instruction layout.
+ * Instructions are stored in memory as little-endian unless
+ * CPT()_PF_Q()_CTL[INST_BE] is set.
+ */
+typedef union cpt_inst_s {
+	uint64_t u[8];
+	struct cpt_inst_s_8s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_17_63        : 47;
+		/* [ 16: 16] Done interrupt.
+		 * 0 = No interrupts related to this instruction.
+		 * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]
+		 * will be incremented, and based on the rules described
+		 * there an interrupt may occur.
+		 */
+		uint64_t doneint               : 1;
+		uint64_t reserved_0_15         : 16;
+#else /* Word 0 - Little Endian */
+		uint64_t reserved_0_15         : 16;
+		uint64_t doneint               : 1;
+		uint64_t reserved_17_63        : 47;
+#endif /* Word 0 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
+		/* [127: 64] Result IOVA.
+		 * If nonzero, specifies where to write CPT_RES_S.
+		 * If zero, no result structure will be written.
+		 * Address must be 16-byte aligned.
+		 *
+		 * Bits <63:49> are ignored by hardware; software should
+		 * use a sign-extended bit <48> for forward compatibility.
+		 */
+		uint64_t res_addr              : 64;
+#else /* Word 1 - Little Endian */
+		uint64_t res_addr              : 64;
+#endif /* Word 1 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
+		uint64_t reserved_172_191      : 20;
+		/* [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
+		 * use when CPT submits work to SSO.
+		 * For the SSO to not discard the add-work request, FPA_PF_MAP()
+		 * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
+		 */
+		uint64_t grp                   : 10;
+		/* [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
+		 * when CPT submits work to SSO.
+		 */
+		uint64_t tt                    : 2;
+		/* [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when
+		 * CPT submits work to SSO.
+		 */
+		uint64_t tag                   : 32;
+#else /* Word 2 - Little Endian */
+		uint64_t tag                   : 32;
+		uint64_t tt                    : 2;
+		uint64_t grp                   : 10;
+		uint64_t reserved_172_191      : 20;
+#endif /* Word 2 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
+		/** [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
+		 * work-queue entry that CPT submits work to SSO after all
+		 * context, output data, and result write operations are
+		 * visible to other CNXXXX units and the cores.
+		 * Bits <2:0> must be zero.
+		 * Bits <63:49> are ignored by hardware; software should use a
+		 * sign-extended bit <48> for forward compatibility.
+		 * Internal:Bits <63:49>, <2:0> are ignored by hardware,
+		 * treated as always 0x0.
+		 **/
+		uint64_t wq_ptr                : 64;
+#else /* Word 3 - Little Endian */
+		uint64_t wq_ptr                : 64;
+#endif /* Word 3 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 4 - Big Endian */
+		union {
+			/** [319:256] Engine instruction word 0. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t ei0                   : 64;
+			vq_cmd_word0_t vq_cmd_w0;
+		};
+#else /* Word 4 - Little Endian */
+		union {
+			uint64_t ei0                   : 64;
+			vq_cmd_word0_t vq_cmd_w0;
+		};
+#endif /* Word 4 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 5 - Big Endian */
+		union {
+			/** [383:320] Engine instruction word 1. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t ei1                   : 64;
+			uint64_t dptr;
+		};
+#else /* Word 5 - Little Endian */
+		union {
+			uint64_t ei1                   : 64;
+			uint64_t dptr;
+		};
+#endif /* Word 5 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 6 - Big Endian */
+		union {
+			/** [447:384] Engine instruction word 2. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t ei2                   : 64;
+			uint64_t rptr;
+		};
+#else /* Word 6 - Little Endian */
+		union {
+			uint64_t ei2                   : 64;
+			uint64_t rptr;
+		};
+#endif /* Word 6 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 7 - Big Endian */
+		union {
+			/** [511:448] Engine instruction word 3. Passed to the
+			 * AE/SE.
+			 **/
+			uint64_t ei3                   : 64;
+			vq_cmd_word3_t vq_cmd_w3;
+		};
+#else /* Word 7 - Little Endian */
+		union {
+			uint64_t ei3                   : 64;
+			vq_cmd_word3_t vq_cmd_w3;
+		};
+#endif /* Word 7 - End */
+	} s8x;
+} cpt_inst_s_t;
+
+/**
+ * Structure cpt_res_s
+ *
+ * CPT Result Structure
+ * The CPT coprocessor writes the result structure after it completes a
+ * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each
+ * instruction completion produces exactly one result structure.
+ *
+ * This structure is stored in memory as little-endian unless
+ * CPT()_PF_Q()_CTL[INST_BE] is set.
+ */
+typedef union cpt_res_s {
+	uint64_t u[2];
+	struct cpt_res_s_8s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_17_63        : 47;
+		/** [ 16: 16] Done interrupt. This bit is copied from the
+		 * corresponding instruction's CPT_INST_S[DONEINT].
+		 **/
+		uint64_t doneint               : 1;
+		uint64_t reserved_8_15         : 8;
+		/** [  7:  0] Indicates completion/error status of the CPT
+		 * coprocessor for the associated instruction, as enumerated by
+		 * CPT_COMP_E. Core software may write the memory location
+		 * containing [COMPCODE] to 0x0 before ringing the doorbell, and
+		 * then poll for completion by checking for a nonzero value.
+		 *
+		 * Once the core observes a nonzero [COMPCODE] value in this
+		 * case, the CPT coprocessor will have also completed L2/DRAM
+		 * write operations.
+		 **/
+		uint64_t compcode              : 8;
+#else /* Word 0 - Little Endian */
+		uint64_t compcode              : 8;
+		uint64_t reserved_8_15         : 8;
+		uint64_t doneint               : 1;
+		uint64_t reserved_17_63        : 47;
+#endif /* Word 0 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
+		uint64_t reserved_64_127       : 64;
+#else /* Word 1 - Little Endian */
+		uint64_t reserved_64_127       : 64;
+#endif /* Word 1 - End */
+	} s8x;
+} cpt_res_s_t;
+
+/**
+ * Register (NCB) cpt#_vq#_ctl
+ *
+ * CPT VF Queue Control Registers
+ * This register configures queues. This register should be changed (other than
+ * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_ctl_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_1_63         : 63;
+		/** [  0:  0](R/W/H) Enables the logical instruction queue.
+		 * See also CPT()_PF_Q()_CTL[CONT_ERR] and
+		 * CPT()_VQ()_INPROG[INFLIGHT].
+		 * 1 = Queue is enabled.
+		 * 0 = Queue is disabled.
+		 **/
+		uint64_t ena                   : 1;
+#else /* Word 0 - Little Endian */
+		uint64_t ena                   : 1;
+		uint64_t reserved_1_63         : 63;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_ctl_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done
+ *
+ * CPT Queue Done Count Registers
+ * These registers contain the per-queue instruction done count.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		/** [ 19:  0](R/W/H) Done count. When CPT_INST_S[DONEINT] set
+		 * and that instruction completes,CPT()_VQ()_DONE[DONE] is
+		 * incremented when the instruction finishes. Write to this
+		 * field are for diagnostic use only; instead software writes
+		 * CPT()_VQ()_DONE_ACK with the number of decrements for this
+		 * field.
+		 *
+		 * Interrupts are sent as follows:
+		 *
+		 * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,
+		 * the interrupt coalescing timer is held to zero, and an
+		 * interrupt is not sent.
+		 *
+		 * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt
+		 * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE
+		 * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()
+		 * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough
+		 * results have arrived, then the interrupt is sent.  Otherwise,
+		 * it is not sent due to coalescing.
+		 *
+		 * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is
+		 * written but this is not typical), the interrupt coalescing
+		 * timer restarts.  Note after decrementing this interrupt
+		 * equation is recomputed, for example if CPT()_VQ()_DONE[DONE]
+		 * >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is
+		 * zero, the interrupt will be resent immediately.  (This covers
+		 * the race case between software acknowledging an interrupt and
+		 * a result returning.)
+		 *
+		 * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not
+		 * sent, but the counting described above still occurs.
+		 *
+		 * Since CPT instructions complete out-of-order, if software is
+		 * using completion interrupts the suggested scheme is to
+		 * request a DONEINT on each request, and when an interrupt
+		 * arrives perform a "greedy" scan for completions; even if a
+		 * later command is acknowledged first this will not result in
+		 * missing a completion.
+		 *
+		 * Software is responsible for making sure [DONE] does not
+		 * overflow; for example by insuring there are not more than
+		 * 2^20-1 instructions in flight that may request interrupts.
+		 **/
+		uint64_t done                  : 20;
+#else /* Word 0 - Little Endian */
+		uint64_t done                  : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_done_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done_ack
+ *
+ * CPT Queue Done Count Ack Registers
+ * This register is written by software to acknowledge interrupts.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_ack_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		/** [ 19:  0](R/W/H) Number of decrements to CPT()_VQ()_DONE
+		 * [DONE]. Reads CPT()_VQ()_DONE[DONE].
+		 *
+		 * Written by software to acknowledge interrupts. If CPT()_VQ()_
+		 * DONE[DONE] is still nonzero the interrupt will be re-sent if
+		 * the conditions described in CPT()_VQ()_DONE[DONE] are
+		 * satisfied.
+		 **/
+		uint64_t done_ack              : 20;
+#else /* Word 0 - Little Endian */
+		uint64_t done_ack              : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_done_ack_t;
+
+/**
+ * Register (NCB) cpt#_vq#_done_wait
+ *
+ * CPT Queue Done Interrupt Coalescing Wait Registers
+ * Specifies the per queue interrupt coalescing settings.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_done_wait_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_48_63        : 16;
+		/** [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =
+		 * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When
+		 * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is
+		 * disabled.
+		 **/
+		uint64_t time_wait             : 16;
+		uint64_t reserved_20_31        : 12;
+		/** [ 19:  0](R/W) Number of messages hold-off. When
+		 * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing
+		 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as
+		 * 0x1.
+		 **/
+		uint64_t num_wait              : 20;
+#else /* Word 0 - Little Endian */
+		uint64_t num_wait              : 20;
+		uint64_t reserved_20_31        : 12;
+		uint64_t time_wait             : 16;
+		uint64_t reserved_48_63        : 16;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_done_wait_t;
+
+/**
+ * Register (NCB) cpt#_vq#_doorbell
+ *
+ * CPT Queue Doorbell Registers
+ * Doorbells for the CPT instruction queues.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_doorbell_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		uint64_t dbell_cnt             : 20;
+		/** [ 19:  0](R/W/H) Number of instruction queue 64-bit words
+		 * to add to the CPT instruction doorbell count. Readback value
+		 * is the the current number of pending doorbell requests.
+		 *
+		 * If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.
+		 *
+		 * To reset the count back to zero, write one to clear
+		 * CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value
+		 * of 2^20 minus the read [DBELL_CNT], then write one to
+		 * CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
+		 * CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].
+		 *
+		 * Must be a multiple of 8.  All CPT instructions are 8 words
+		 * and require a doorbell count of multiple of 8.
+		 **/
+#else /* Word 0 - Little Endian */
+		uint64_t dbell_cnt             : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_doorbell_t;
+
+/**
+ * Register (NCB) cpt#_vq#_inprog
+ *
+ * CPT Queue In Progress Count Registers
+ * These registers contain the per-queue instruction in flight registers.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_inprog_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_8_63         : 56;
+		/** [  7:  0](RO/H) Inflight count. Counts the number of
+		 * instructions for the VF for which CPT is fetching, executing
+		 * or responding to instructions. However this does not include
+		 * any interrupts that are awaiting software handling
+		 * (CPT()_VQ()_DONE[DONE] != 0x0).
+		 *
+		 * A queue may not be reconfigured until:
+		 *  1. CPT()_VQ()_CTL[ENA] is cleared by software.
+		 *  2. [INFLIGHT] is polled until equals to zero.
+		 **/
+		uint64_t inflight              : 8;
+#else /* Word 0 - Little Endian */
+		uint64_t inflight              : 8;
+		uint64_t reserved_8_63         : 56;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_inprog_t;
+
+/**
+ * Register (NCB) cpt#_vq#_misc_int
+ *
+ * CPT Queue Misc Interrupt Register
+ * These registers contain the per-queue miscellaneous interrupts.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_misc_int_s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_7_63         : 57;
+		/** [  6:  6](R/W1C/H) Translation fault detected. */
+		uint64_t fault		       : 1;
+		/** [  5:  5](R/W1C/H) Hardware error from engines. */
+		uint64_t hwerr		       : 1;
+		/** [  4:  4](R/W1C/H) Software error from engines. */
+		uint64_t swerr                 : 1;
+		/** [  3:  3](R/W1C/H) NCB result write response error. */
+		uint64_t nwrp                  : 1;
+		/** [  2:  2](R/W1C/H) Instruction NCB read response error. */
+		uint64_t irde                  : 1;
+		/** [  1:  1](R/W1C/H) Doorbell overflow. */
+		uint64_t dovf                  : 1;
+		/** [  0:  0](R/W1C/H) PF to VF mailbox interrupt. Set when
+		 * CPT()_VF()_PF_MBOX(0) is written.
+		 **/
+		uint64_t mbox                  : 1;
+#else /* Word 0 - Little Endian */
+		uint64_t mbox                  : 1;
+		uint64_t dovf                  : 1;
+		uint64_t irde                  : 1;
+		uint64_t nwrp                  : 1;
+		uint64_t swerr                 : 1;
+		uint64_t hwerr		       : 1;
+		uint64_t fault		       : 1;
+		uint64_t reserved_5_63         : 59;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_misc_int_t;
+
+/**
+ * Register (NCB) cpt#_vq#_saddr
+ *
+ * CPT Queue Starting Buffer Address Registers
+ * These registers set the instruction buffer starting address.
+ */
+typedef union {
+	uint64_t u;
+	struct cptx_vqx_saddr_s	{
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+		uint64_t reserved_49_63        : 15;
+		/** [ 48:  6](R/W/H) Instruction buffer IOVA <48:6>
+		 * (64-byte aligned). When written, it is the initial buffer
+		 * starting address; when read, it is the next read pointer to
+		 * be requested from L2C. The PTR field is overwritten with the
+		 * next pointer each time that the command buffer segment is
+		 * exhausted. New commands will then be read from the newly
+		 * specified command buffer pointer.
+		 **/
+		uint64_t ptr                   : 43;
+		uint64_t reserved_0_5          : 6;
+#else /* Word 0 - Little Endian */
+		uint64_t reserved_0_5          : 6;
+		uint64_t ptr                   : 43;
+		uint64_t reserved_49_63        : 15;
+#endif /* Word 0 - End */
+	} s;
+} cptx_vqx_saddr_t;
+
+#endif /*_CPT_HW_TYPES_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index 99fe3cf..369d62b 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -3,11 +3,19 @@
  */
 #include <string.h>
 
+#include <rte_branch_prediction.h>
 #include <rte_common.h>
 
 #include "otx_cryptodev_hw_access.h"
 
 #include "cpt_pmd_logs.h"
+#include "cpt_hw_types.h"
+
+/*
+ * VF HAL functions
+ * Access its own BAR0/4 registers by passing VF number as 0.
+ * OS/PCI maps them accordingly.
+ */
 
 static int
 otx_cpt_vf_init(struct cpt_vf *cptvf)
@@ -19,10 +27,192 @@ otx_cpt_vf_init(struct cpt_vf *cptvf)
 	return ret;
 }
 
+/*
+ * Read Interrupt status of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static uint64_t
+otx_cpt_read_vf_misc_intr_status(struct cpt_vf *cptvf)
+{
+	return CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0));
+}
+
+/*
+ * Clear mailbox interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_mbox_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.mbox = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear instruction NCB read error interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_irde_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.irde = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear NCB result write response error interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_nwrp_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.nwrp = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear swerr interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_swerr_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.swerr = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear hwerr interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_hwerr_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.hwerr = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear translation fault interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_fault_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.fault = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
+/*
+ * Clear doorbell overflow interrupt of the VF
+ *
+ * @param   cptvf	cptvf structure
+ */
+static void
+otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)
+{
+	cptx_vqx_misc_int_t vqx_misc_int;
+
+	vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				      CPTX_VQX_MISC_INT(0, 0));
+	/* W1C for the VF */
+	vqx_misc_int.s.dovf = 1;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
+}
+
 void
 otx_cpt_poll_misc(struct cpt_vf *cptvf)
 {
-	RTE_SET_USED(cptvf);
+	uint64_t intr;
+
+	intr = otx_cpt_read_vf_misc_intr_status(cptvf);
+
+	if (!intr)
+		return;
+
+	/* Check for MISC interrupt types */
+	if (likely(intr & CPT_VF_INTR_MBOX_MASK)) {
+		CPT_LOG_DP_DEBUG("%s: Mailbox interrupt 0x%lx on CPT VF %d",
+			cptvf->dev_name, (unsigned int long)intr, cptvf->vfid);
+		otx_cpt_clear_mbox_intr(cptvf);
+	} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {
+		otx_cpt_clear_irde_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Instruction NCB read error interrupt "
+				"0x%lx on CPT VF %d", cptvf->dev_name,
+				(unsigned int long)intr, cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) {
+		otx_cpt_clear_nwrp_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: NCB response write error interrupt 0x%lx"
+				" on CPT VF %d", cptvf->dev_name,
+				(unsigned int long)intr, cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) {
+		otx_cpt_clear_swerr_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Software error interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) {
+		otx_cpt_clear_hwerr_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Hardware error interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) {
+		otx_cpt_clear_fault_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Translation fault interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else if (unlikely(intr & CPT_VF_INTR_DOVF_MASK)) {
+		otx_cpt_clear_dovf_intr(cptvf);
+		CPT_LOG_DP_DEBUG("%s: Doorbell overflow interrupt 0x%lx on CPT VF "
+				"%d", cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
+	} else
+		CPT_LOG_DP_ERR("%s: Unhandled interrupt 0x%lx in CPT VF %d",
+				cptvf->dev_name, (unsigned int long)intr,
+				cptvf->vfid);
 }
 
 int
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 1e1877c..73473ed 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -7,6 +7,7 @@
 
 #include <stdbool.h>
 
+#include <rte_io.h>
 #include <rte_memory.h>
 
 #include "cpt_common.h"
@@ -16,6 +17,16 @@
 /* Default command queue length */
 #define DEFAULT_CMD_QCHUNKS		2
 
+#define CPT_CSR_REG_BASE(cpt)		((cpt)->reg_base)
+
+/* Read hw register */
+#define CPT_READ_CSR(__hw_addr, __offset) \
+	rte_read64_relaxed((uint8_t *)__hw_addr + __offset)
+
+/* Write hw register */
+#define CPT_WRITE_CSR(__hw_addr, __offset, __val) \
+	rte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))
+
 /* cpt instance */
 struct cpt_instance {
 	uint32_t queue_id;
-- 
2.7.4

[dpdk-dev] [PATCH v4 04/23] crypto/octeontx: add symmetric capabilities

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

This patch adds the symmetric algorithms capabilities
supported by octeontx crypto hardware.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                   |   1 +
 drivers/crypto/octeontx/meson.build                |   1 +
 .../crypto/octeontx/otx_cryptodev_capabilities.c   | 604 +++++++++++++++++++++
 .../crypto/octeontx/otx_cryptodev_capabilities.h   |  17 +
 4 files changed, 623 insertions(+)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_capabilities.h

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 4582540..d755441 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -24,6 +24,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
 
 # PMD code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_capabilities.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
 
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index eca1cf1..4c5a40c 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -8,6 +8,7 @@ deps += ['bus_pci']
 name = 'octeontx_crypto'
 
 sources = files('otx_cryptodev.c',
+		'otx_cryptodev_capabilities.c',
 		'otx_cryptodev_hw_access.c',
 		'otx_cryptodev_ops.c')
 
diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.c b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
new file mode 100644
index 0000000..946571c
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
@@ -0,0 +1,604 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_cryptodev.h>
+
+#include "otx_cryptodev_capabilities.h"
+
+static const struct rte_cryptodev_capabilities otx_capabilities[] = {
+	/* Symmetric capabilities */
+	{	/* NULL (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+			}, },
+		}, },
+	},
+	{	/* AES GMAC (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_AES_GMAC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 12,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* KASUMI (F9) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_KASUMI_F9,
+				.block_size = 8,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+			}, }
+		}, }
+	},
+	{	/* MD5 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_MD5,
+				.block_size = 64,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 16,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* MD5 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 8,
+					.max = 64,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 16,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA1 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA1,
+				.block_size = 64,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 20,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA1 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 20,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA224 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA224,
+				.block_size = 64,
+					.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 28,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA224 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
+				.block_size = 64,
+					.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 28,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA256 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA256,
+				.block_size = 64,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 32,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA256 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 32,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA384 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA384,
+				.block_size = 64,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 48,
+					.increment = 1
+					},
+			}, }
+		}, }
+	},
+	{	/* SHA384 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 48,
+					.increment = 1
+					},
+			}, }
+		}, }
+	},
+	{	/* SHA512 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA512,
+				.block_size = 128,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 64,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SHA512 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
+				.block_size = 128,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 64,
+					.increment = 1
+				},
+			}, }
+		}, }
+	},
+	{	/* SNOW 3G (UIA2) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* ZUC (EIA3) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* NULL (CIPHER) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				}
+			}, },
+		}, }
+	},
+	{	/* 3DES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+				.block_size = 8,
+				.key_size = {
+					.min = 24,
+					.max = 24,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 8
+				}
+			}, }
+		}, }
+	},
+	{	/* 3DES ECB */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_3DES_ECB,
+				.block_size = 8,
+				.key_size = {
+					.min = 24,
+					.max = 24,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CBC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES CTR */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CTR,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 16,
+					.increment = 4
+				}
+			}, }
+		}, }
+	},
+	{	/* AES XTS */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_XTS,
+				.block_size = 16,
+				.key_size = {
+					.min = 32,
+					.max = 64,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* DES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_DES_CBC,
+				.block_size = 8,
+				.key_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* KASUMI (F8) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
+				.block_size = 8,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* SNOW 3G (UEA2) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* ZUC (EEA3) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES GCM */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+			{.aead = {
+				.algo = RTE_CRYPTO_AEAD_AES_GCM,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
+				},
+				.aad_size = {
+					.min = 0,
+					.max = 1024,
+					.increment = 1
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 12,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	/* End of symmetric capabilities */
+	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+const struct rte_cryptodev_capabilities *
+otx_get_capabilities(void)
+{
+	return otx_capabilities;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.h b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
new file mode 100644
index 0000000..fc62821
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_CAPABILITIES_H_
+#define _OTX_CRYPTODEV_CAPABILITIES_H_
+
+#include <rte_cryptodev.h>
+
+/*
+ * Get capabilities list for the device
+ *
+ */
+const struct rte_cryptodev_capabilities *
+otx_get_capabilities(void);
+
+#endif /* _OTX_CRYPTODEV_CAPABILITIES_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v4 05/23] common/cpt: add PMD ops helper functions

[Anoob Joseph]

Adding pmd ops helper functions. Control path accessed APIs would be
added as helper functions. Adding microcode defined macros etc as
dependencies to the helper functions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/Makefile                       |  4 +++
 drivers/common/cpt/Makefile                   | 25 ++++++++++++++++
 drivers/common/cpt/cpt_common.h               | 36 +++++++++++++++++++++++
 drivers/common/cpt/cpt_mcode_defines.h        | 38 +++++++++++++++++++++++++
 drivers/common/cpt/cpt_pmd_ops_helper.c       | 41 +++++++++++++++++++++++++++
 drivers/common/cpt/cpt_pmd_ops_helper.h       | 34 ++++++++++++++++++++++
 drivers/common/cpt/meson.build                |  8 ++++++
 drivers/common/cpt/rte_common_cpt_version.map |  6 ++++
 drivers/common/meson.build                    |  2 +-
 mk/rte.app.mk                                 |  4 +++
 10 files changed, 197 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cpt/Makefile
 create mode 100644 drivers/common/cpt/cpt_mcode_defines.h
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.c
 create mode 100644 drivers/common/cpt/cpt_pmd_ops_helper.h
 create mode 100644 drivers/common/cpt/meson.build
 create mode 100644 drivers/common/cpt/rte_common_cpt_version.map

diff --git a/drivers/common/Makefile b/drivers/common/Makefile
index 5bcff17..29a8f6d 100644
--- a/drivers/common/Makefile
+++ b/drivers/common/Makefile
@@ -4,6 +4,10 @@
 
 include $(RTE_SDK)/mk/rte.vars.mk
 
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+DIRS-y += cpt
+endif
+
 ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL),yy)
 DIRS-y += octeontx
 endif
diff --git a/drivers/common/cpt/Makefile b/drivers/common/cpt/Makefile
new file mode 100644
index 0000000..2340aa9
--- /dev/null
+++ b/drivers/common/cpt/Makefile
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_common_cpt.a
+
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
+EXPORT_MAP := rte_common_cpt_version.map
+
+LIBABIVER := 1
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-y += cpt_pmd_ops_helper.c
+
+LDLIBS += -lrte_eal
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 5e2099a..88f4902 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -18,6 +18,24 @@
 #define AE_TYPE 1
 #define SE_TYPE 2
 
+#ifndef ROUNDUP4
+#define ROUNDUP4(val)	(((val) + 3) & 0xfffffffc)
+#endif
+
+#ifndef ROUNDUP8
+#define ROUNDUP8(val)	(((val) + 7) & 0xfffffff8)
+#endif
+
+#ifndef ROUNDUP16
+#define ROUNDUP16(val)	(((val) + 15) & 0xfffffff0)
+#endif
+
+#ifndef __hot
+#define __hot __attribute__((hot))
+#endif
+
+#define MOD_INC(i, l)   ((i) == (l - 1) ? (i) = 0 : (i)++)
+
 struct cptvf_meta_info {
 	void *cptvf_meta_pool;
 	int cptvf_op_mlen;
@@ -44,4 +62,22 @@ struct pending_queue {
 	uint64_t pending_count;
 };
 
+struct cpt_request_info {
+	/** Data path fields */
+	uint64_t comp_baddr;
+	volatile uint64_t *completion_addr;
+	volatile uint64_t *alternate_caddr;
+	void *op;
+	struct {
+		uint64_t ei0;
+		uint64_t ei1;
+		uint64_t ei2;
+		uint64_t ei3;
+	} ist;
+
+	/** Control path fields */
+	uint64_t time_out;
+	uint8_t extra_time;
+};
+
 #endif /* _CPT_COMMON_H_ */
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
new file mode 100644
index 0000000..83a8a42
--- /dev/null
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_MCODE_DEFINES_H_
+#define _CPT_MCODE_DEFINES_H_
+
+/*
+ * This file defines macros and structures according to microcode spec
+ *
+ */
+
+#define CPT_BYTE_16		16
+#define CPT_BYTE_24		24
+#define CPT_BYTE_32		32
+#define CPT_MAX_SG_IN_OUT_CNT	32
+#define CPT_MAX_SG_CNT		(CPT_MAX_SG_IN_OUT_CNT/2)
+
+#define COMPLETION_CODE_SIZE	8
+#define COMPLETION_CODE_INIT	0
+
+#define SG_LIST_HDR_SIZE	(8u)
+#define SG_ENTRY_SIZE		sizeof(sg_comp_t)
+
+/* #define CPT_ALWAYS_USE_SG_MODE */
+#define CPT_ALWAYS_USE_SEPARATE_BUF
+
+typedef struct sglist_comp {
+	union {
+		uint64_t len;
+		struct {
+			uint16_t len[4];
+		} s;
+	} u;
+	uint64_t ptr[4];
+} sg_comp_t;
+
+#endif /* _CPT_MCODE_DEFINES_H_ */
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.c b/drivers/common/cpt/cpt_pmd_ops_helper.c
new file mode 100644
index 0000000..1c18180
--- /dev/null
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <rte_common.h>
+
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
+#include "cpt_mcode_defines.h"
+#include "cpt_pmd_ops_helper.h"
+
+#define CPT_MAX_IV_LEN 16
+#define CPT_OFFSET_CONTROL_BYTES 8
+
+int32_t
+cpt_pmd_ops_helper_get_mlen_direct_mode(void)
+{
+	uint32_t len = 0;
+
+	/* Request structure */
+	len = sizeof(struct cpt_request_info);
+
+	/* CPT HW result structure plus extra as it is aligned */
+	len += 2*sizeof(cpt_res_s_t);
+
+	return len;
+}
+
+int
+cpt_pmd_ops_helper_get_mlen_sg_mode(void)
+{
+	uint32_t len = 0;
+
+	len += sizeof(struct cpt_request_info);
+	len += CPT_OFFSET_CONTROL_BYTES + CPT_MAX_IV_LEN;
+	len += ROUNDUP8(SG_LIST_HDR_SIZE +
+			(ROUNDUP4(CPT_MAX_SG_IN_OUT_CNT) >> 2) * SG_ENTRY_SIZE);
+	len += 2 * COMPLETION_CODE_SIZE;
+	len += 2 * sizeof(cpt_res_s_t);
+	return len;
+}
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.h b/drivers/common/cpt/cpt_pmd_ops_helper.h
new file mode 100644
index 0000000..dd32f9a
--- /dev/null
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_PMD_OPS_HELPER_H_
+#define _CPT_PMD_OPS_HELPER_H_
+
+/*
+ * This file defines the agreement between the common layer and the individual
+ * crypto drivers for OCTEON TX series. Control path in otx* directory can
+ * directly call functions declared here.
+ */
+
+/*
+ * Get meta length required when operating in direct mode (single buffer
+ * in-place)
+ *
+ * @return
+ *   - length
+ */
+
+int32_t
+cpt_pmd_ops_helper_get_mlen_direct_mode(void);
+
+/*
+ * Get size of contiguous meta buffer to be allocated when working in scatter
+ * gather mode.
+ *
+ * @return
+ *   - length
+ */
+int
+cpt_pmd_ops_helper_get_mlen_sg_mode(void);
+#endif /* _CPT_PMD_OPS_HELPER_H_ */
diff --git a/drivers/common/cpt/meson.build b/drivers/common/cpt/meson.build
new file mode 100644
index 0000000..0a905aa
--- /dev/null
+++ b/drivers/common/cpt/meson.build
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+
+sources = files('cpt_pmd_ops_helper.c')
+
+deps = ['kvargs', 'pci', 'cryptodev']
+includes += include_directories('../../crypto/octeontx')
+allow_experimental_apis = true
diff --git a/drivers/common/cpt/rte_common_cpt_version.map b/drivers/common/cpt/rte_common_cpt_version.map
new file mode 100644
index 0000000..dec614f
--- /dev/null
+++ b/drivers/common/cpt/rte_common_cpt_version.map
@@ -0,0 +1,6 @@
+DPDK_18.11 {
+	global:
+
+	cpt_pmd_ops_helper_get_mlen_direct_mode;
+	cpt_pmd_ops_helper_get_mlen_sg_mode;
+};
diff --git a/drivers/common/meson.build b/drivers/common/meson.build
index f828ce7..dd14f85 100644
--- a/drivers/common/meson.build
+++ b/drivers/common/meson.build
@@ -2,6 +2,6 @@
 # Copyright(c) 2018 Cavium, Inc
 
 std_deps = ['eal']
-drivers = ['mvep', 'octeontx', 'qat']
+drivers = ['cpt', 'mvep', 'octeontx', 'qat']
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 driver_name_fmt = 'rte_common_@0@'
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 9661cdf..946d3e9 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -94,6 +94,10 @@ ifeq ($(CONFIG_RTE_EXEC_ENV_LINUXAPP),y)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_KNI)            += -lrte_kni
 endif
 
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+_LDLIBS-y += -lrte_common_cpt
+endif
+
 ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL),yy)
 _LDLIBS-y += -lrte_common_octeontx
 endif
-- 
2.7.4

[dpdk-dev] [PATCH v4 06/23] crypto/octeontx: add global resource init

[Anoob Joseph]

Adding initialization of global resources. This will be saved as
metadata in cptvf and would be used by common code. Exit path for
failure case is also added along with the new routines.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                  |  1 +
 drivers/crypto/octeontx/meson.build               |  3 +-
 drivers/crypto/octeontx/otx_cryptodev.c           |  3 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 11 +++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h |  3 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 90 +++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.h       |  3 +
 7 files changed, 113 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index d755441..1808244 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -16,6 +16,7 @@ CFLAGS += $(WERROR_FLAGS)
 LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
 LDLIBS += -lrte_cryptodev
 LDLIBS += -lrte_pci -lrte_bus_pci
+LDLIBS += -lrte_common_cpt
 
 VPATH += $(RTE_SDK)/drivers/crypto/octeontx
 
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index 4c5a40c..7f65476 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -5,6 +5,7 @@ if host_machine.system() != 'linux'
 endif
 
 deps += ['bus_pci']
+deps += ['common_cpt']
 name = 'octeontx_crypto'
 
 sources = files('otx_cryptodev.c',
@@ -12,5 +13,5 @@ sources = files('otx_cryptodev.c',
 		'otx_cryptodev_hw_access.c',
 		'otx_cryptodev_ops.c')
 
-cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
 includes += include_directories('../../common/cpt')
+cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'
diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c
index 43933dd..269f045 100644
--- a/drivers/crypto/octeontx/otx_cryptodev.c
+++ b/drivers/crypto/octeontx/otx_cryptodev.c
@@ -104,6 +104,9 @@ otx_cpt_pci_remove(struct rte_pci_device *pci_dev)
 	cryptodev->device->driver = NULL;
 	cryptodev->data = NULL;
 
+	/* free metapool memory */
+	cleanup_global_resources();
+
 	return 0;
 }
 
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index 369d62b..e8a2b0b 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -236,3 +236,14 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
 
 	return 0;
 }
+
+int
+otx_cpt_deinit_device(void *dev)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	/* Do misc work one last time */
+	otx_cpt_poll_misc(cptvf);
+
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 73473ed..6e5731a 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -142,4 +142,7 @@ otx_cpt_poll_misc(struct cpt_vf *cptvf);
 int
 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
 
+int
+otx_cpt_deinit_device(void *dev);
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 3bf6cd2..68c6b92 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -8,11 +8,69 @@
 #include <rte_malloc.h>
 
 #include "cpt_pmd_logs.h"
+#include "cpt_pmd_ops_helper.h"
 
 #include "otx_cryptodev.h"
 #include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_ops.h"
 
+static int otx_cryptodev_probe_count;
+static rte_spinlock_t otx_probe_count_lock = RTE_SPINLOCK_INITIALIZER;
+
+static struct rte_mempool *otx_cpt_meta_pool;
+static int otx_cpt_op_mlen;
+static int otx_cpt_op_sb_mlen;
+
+/*
+ * Initializes global variables used by fast-path code
+ *
+ * @return
+ *   - 0 on success, errcode on error
+ */
+static int
+init_global_resources(void)
+{
+	/* Get meta len for scatter gather mode */
+	otx_cpt_op_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+
+	/* Extra 4B saved for future considerations */
+	otx_cpt_op_mlen += 4 * sizeof(uint64_t);
+
+	otx_cpt_meta_pool = rte_mempool_create("cpt_metabuf-pool", 4096 * 16,
+					       otx_cpt_op_mlen, 512, 0,
+					       NULL, NULL, NULL, NULL,
+					       SOCKET_ID_ANY, 0);
+	if (!otx_cpt_meta_pool) {
+		CPT_LOG_ERR("cpt metabuf pool not created");
+		return -ENOMEM;
+	}
+
+	/* Get meta len for direct mode */
+	otx_cpt_op_sb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+	/* Extra 4B saved for future considerations */
+	otx_cpt_op_sb_mlen += 4 * sizeof(uint64_t);
+
+	return 0;
+}
+
+void
+cleanup_global_resources(void)
+{
+	/* Take lock */
+	rte_spinlock_lock(&otx_probe_count_lock);
+
+	/* Decrement the cryptodev count */
+	otx_cryptodev_probe_count--;
+
+	/* Free buffers */
+	if (otx_cpt_meta_pool && otx_cryptodev_probe_count == 0)
+		rte_mempool_free(otx_cpt_meta_pool);
+
+	/* Free lock */
+	rte_spinlock_unlock(&otx_probe_count_lock);
+}
+
 /* Alarm routines */
 
 static void
@@ -31,6 +89,20 @@ otx_cpt_periodic_alarm_start(void *arg)
 				 otx_cpt_alarm_cb, arg);
 }
 
+static int
+otx_cpt_periodic_alarm_stop(void *arg)
+{
+	return rte_eal_alarm_cancel(otx_cpt_alarm_cb, arg);
+}
+
+static void
+otx_cpt_common_vars_init(struct cpt_vf *cptvf)
+{
+	cptvf->meta_info.cptvf_meta_pool = otx_cpt_meta_pool;
+	cptvf->meta_info.cptvf_op_mlen = otx_cpt_op_mlen;
+	cptvf->meta_info.cptvf_op_sb_mlen = otx_cpt_op_sb_mlen;
+}
+
 int
 otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 {
@@ -78,6 +150,20 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	/* Start off timer for mailbox interrupts */
 	otx_cpt_periodic_alarm_start(cptvf);
 
+	rte_spinlock_lock(&otx_probe_count_lock);
+	if (!otx_cryptodev_probe_count) {
+		ret = init_global_resources();
+		if (ret) {
+			rte_spinlock_unlock(&otx_probe_count_lock);
+			goto init_fail;
+		}
+	}
+	otx_cryptodev_probe_count++;
+	rte_spinlock_unlock(&otx_probe_count_lock);
+
+	/* Initialize data path variables used by common code */
+	otx_cpt_common_vars_init(cptvf);
+
 	c_dev->dev_ops = NULL;
 
 	c_dev->enqueue_burst = NULL;
@@ -95,6 +181,10 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 
 	return 0;
 
+init_fail:
+	otx_cpt_periodic_alarm_stop(cptvf);
+	otx_cpt_deinit_device(cptvf);
+
 fail:
 	if (cptvf) {
 		/* Free private data allocated */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
index 3f2d829..ac88fa5 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -5,6 +5,9 @@
 #ifndef _OTX_CRYPTODEV_OPS_H_
 #define _OTX_CRYPTODEV_OPS_H_
 
+void
+cleanup_global_resources(void);
+
 int
 otx_cpt_dev_create(struct rte_cryptodev *c_dev);
 
-- 
2.7.4

[dpdk-dev] [PATCH v4 07/23] crypto/octeontx: add mailbox routines

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding mailbox routines to interact with the pf driver

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/Makefile                  |   1 +
 drivers/crypto/octeontx/meson.build               |   1 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c |  13 ++
 drivers/crypto/octeontx/otx_cryptodev_mbox.c      | 178 ++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_mbox.h      |  92 +++++++++++
 5 files changed, 285 insertions(+)
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.c
 create mode 100644 drivers/crypto/octeontx/otx_cryptodev_mbox.h

diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile
index 1808244..2e78e69 100644
--- a/drivers/crypto/octeontx/Makefile
+++ b/drivers/crypto/octeontx/Makefile
@@ -27,6 +27,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_capabilities.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_mbox.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
 
 # export include files
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index 7f65476..6511b40 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -11,6 +11,7 @@ name = 'octeontx_crypto'
 sources = files('otx_cryptodev.c',
 		'otx_cryptodev_capabilities.c',
 		'otx_cryptodev_hw_access.c',
+		'otx_cryptodev_mbox.c',
 		'otx_cryptodev_ops.c')
 
 includes += include_directories('../../common/cpt')
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index e8a2b0b..eb9fbcf 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -7,6 +7,7 @@
 #include <rte_common.h>
 
 #include "otx_cryptodev_hw_access.h"
+#include "otx_cryptodev_mbox.h"
 
 #include "cpt_pmd_logs.h"
 #include "cpt_hw_types.h"
@@ -22,8 +23,19 @@ otx_cpt_vf_init(struct cpt_vf *cptvf)
 {
 	int ret = 0;
 
+	/* Check ready with PF */
+	/* Gets chip ID / device Id from PF if ready */
+	ret = otx_cpt_check_pf_ready(cptvf);
+	if (ret) {
+		CPT_LOG_ERR("%s: PF not responding to READY msg",
+				cptvf->dev_name);
+		ret = -EBUSY;
+		goto exit;
+	}
+
 	CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
 
+exit:
 	return ret;
 }
 
@@ -178,6 +190,7 @@ otx_cpt_poll_misc(struct cpt_vf *cptvf)
 	if (likely(intr & CPT_VF_INTR_MBOX_MASK)) {
 		CPT_LOG_DP_DEBUG("%s: Mailbox interrupt 0x%lx on CPT VF %d",
 			cptvf->dev_name, (unsigned int long)intr, cptvf->vfid);
+		otx_cpt_handle_mbox_intr(cptvf);
 		otx_cpt_clear_mbox_intr(cptvf);
 	} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {
 		otx_cpt_clear_irde_intr(cptvf);
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.c b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
new file mode 100644
index 0000000..a8e51a8
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#include <unistd.h>
+
+#include "otx_cryptodev_hw_access.h"
+#include "otx_cryptodev_mbox.h"
+
+void
+otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	/*
+	 * MBOX[0] contains msg
+	 * MBOX[1] contains data
+	 */
+	mbx.msg  = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VFX_PF_MBOXX(0, 0, 0));
+	mbx.data = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				CPTX_VFX_PF_MBOXX(0, 0, 1));
+
+	CPT_LOG_DP_DEBUG("%s: Mailbox msg 0x%lx from PF",
+		    cptvf->dev_name, (unsigned int long)mbx.msg);
+	switch (mbx.msg) {
+	case OTX_CPT_MSG_READY:
+		{
+			otx_cpt_chipid_vfid_t cid;
+
+			cid.u64 = mbx.data;
+			cptvf->pf_acked = true;
+			cptvf->vfid = cid.s.vfid;
+			CPT_LOG_DP_DEBUG("%s: Received VFID %d chip_id %d",
+					 cptvf->dev_name,
+					 cptvf->vfid, cid.s.chip_id);
+		}
+		break;
+	case OTX_CPT_MSG_QBIND_GRP:
+		cptvf->pf_acked = true;
+		cptvf->vftype = mbx.data;
+		CPT_LOG_DP_DEBUG("%s: VF %d type %s group %d",
+				 cptvf->dev_name, cptvf->vfid,
+				 ((mbx.data == SE_TYPE) ? "SE" : "AE"),
+				 cptvf->vfgrp);
+		break;
+	case OTX_CPT_MBOX_MSG_TYPE_ACK:
+		cptvf->pf_acked = true;
+		break;
+	case OTX_CPT_MBOX_MSG_TYPE_NACK:
+		cptvf->pf_nacked = true;
+		break;
+	default:
+		CPT_LOG_DP_DEBUG("%s: Invalid msg from PF, msg 0x%lx",
+				 cptvf->dev_name, (unsigned int long)mbx.msg);
+		break;
+	}
+}
+
+/* Send a mailbox message to PF
+ * @vf: vf from which this message to be sent
+ * @mbx: Message to be sent
+ */
+static void
+otx_cpt_send_msg_to_pf(struct cpt_vf *cptvf, struct cpt_mbox *mbx)
+{
+	/* Writing mbox(1) causes interrupt */
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VFX_PF_MBOXX(0, 0, 0), mbx->msg);
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VFX_PF_MBOXX(0, 0, 1), mbx->data);
+}
+
+static int32_t
+otx_cpt_send_msg_to_pf_timeout(struct cpt_vf *cptvf, struct cpt_mbox *mbx)
+{
+	int timeout = OTX_CPT_MBOX_MSG_TIMEOUT;
+	int sleep_ms = 10;
+
+	cptvf->pf_acked = false;
+	cptvf->pf_nacked = false;
+
+	otx_cpt_send_msg_to_pf(cptvf, mbx);
+
+	/* Wait for previous message to be acked, timeout 2sec */
+	while (!cptvf->pf_acked) {
+		if (cptvf->pf_nacked)
+			return -EINVAL;
+		usleep(sleep_ms * 1000);
+		otx_cpt_poll_misc(cptvf);
+		if (cptvf->pf_acked)
+			break;
+		timeout -= sleep_ms;
+		if (!timeout) {
+			CPT_LOG_ERR("%s: PF didn't ack mbox msg %lx(vfid %u)",
+				    cptvf->dev_name,
+				    (unsigned int long)(mbx->msg & 0xFF),
+				    cptvf->vfid);
+			return -EBUSY;
+		}
+	}
+	return 0;
+}
+
+int
+otx_cpt_check_pf_ready(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_READY;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to READY msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_QLEN;
+
+	mbx.data = cptvf->qsize;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to vq_size msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vf_grp_msg(struct cpt_vf *cptvf, uint32_t group)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_QBIND_GRP;
+
+	/* Convey group of the VF */
+	mbx.data = group;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to vf_type msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vf_up(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_VF_UP;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to UP msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
+
+int
+otx_cpt_send_vf_down(struct cpt_vf *cptvf)
+{
+	struct cpt_mbox mbx = {0, 0};
+
+	mbx.msg = OTX_CPT_MSG_VF_DOWN;
+	if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+		CPT_LOG_ERR("%s: PF didn't respond to DOWN msg",
+			    cptvf->dev_name);
+		return 1;
+	}
+	return 0;
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.h b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
new file mode 100644
index 0000000..b05d1c5
--- /dev/null
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _OTX_CRYPTODEV_MBOX_H_
+#define _OTX_CRYPTODEV_MBOX_H_
+
+#include <rte_byteorder.h>
+#include <rte_common.h>
+
+#include "cpt_common.h"
+#include "cpt_pmd_logs.h"
+
+#include "otx_cryptodev_hw_access.h"
+
+#define OTX_CPT_MBOX_MSG_TIMEOUT    2000 /* In Milli Seconds */
+
+#define OTX_CPT_MBOX_MSG_TYPE_REQ	0
+#define OTX_CPT_MBOX_MSG_TYPE_ACK	1
+#define OTX_CPT_MBOX_MSG_TYPE_NACK	2
+#define OTX_CPT_MBOX_MSG_TYPE_NOP	3
+
+/* CPT mailbox structure */
+struct cpt_mbox {
+	/** Message type MBOX[0] */
+	uint64_t msg;
+	/** Data         MBOX[1] */
+	uint64_t data;
+};
+
+typedef enum {
+	OTX_CPT_MSG_VF_UP = 1,
+	OTX_CPT_MSG_VF_DOWN,
+	OTX_CPT_MSG_READY,
+	OTX_CPT_MSG_QLEN,
+	OTX_CPT_MSG_QBIND_GRP,
+	OTX_CPT_MSG_VQ_PRIORITY,
+	OTX_CPT_MSG_PF_TYPE,
+} otx_cpt_mbox_opcode_t;
+
+typedef union {
+	uint64_t u64;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint32_t chip_id;
+		uint8_t vfid;
+		uint8_t reserved[3];
+#else
+		uint8_t reserved[3];
+		uint8_t vfid;
+		uint32_t chip_id;
+#endif
+	} s;
+} otx_cpt_chipid_vfid_t;
+
+/* Poll handler to handle mailbox messages from VFs */
+void
+otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf);
+
+/*
+ * Checks if VF is able to comminicate with PF
+ * and also gets the CPT number this VF is associated to.
+ */
+int
+otx_cpt_check_pf_ready(struct cpt_vf *cptvf);
+
+/*
+ * Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF.
+ * Must be ACKed.
+ */
+int
+otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf);
+
+/*
+ * Communicate VF group required to PF and get the VQ binded to that group
+ */
+int
+otx_cpt_send_vf_grp_msg(struct cpt_vf *cptvf, uint32_t group);
+
+/*
+ * Communicate to PF that VF is UP and running
+ */
+int
+otx_cpt_send_vf_up(struct cpt_vf *cptvf);
+
+/*
+ * Communicate to PF that VF is DOWN and running
+ */
+int
+otx_cpt_send_vf_down(struct cpt_vf *cptvf);
+
+#endif /* _OTX_CRYPTODEV_MBOX_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v4 08/23] crypto/octeontx: add basic dev ops

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding the following dev ops,
- dev_configure
- dev_start
- dev_stop
- dev_close
- dev_infos_get
- stats_get
- stats_reset

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 56 +++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 30 +++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 95 ++++++++++++++++++++++-
 drivers/crypto/octeontx/otx_cryptodev_ops.h       |  4 +
 4 files changed, 184 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index eb9fbcf..303bcc0 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2018 Cavium, Inc
  */
 #include <string.h>
+#include <unistd.h>
 
 #include <rte_branch_prediction.h>
 #include <rte_common.h>
@@ -260,3 +261,58 @@ otx_cpt_deinit_device(void *dev)
 
 	return 0;
 }
+
+int
+otx_cpt_start_device(void *dev)
+{
+	int rc;
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	rc = otx_cpt_send_vf_up(cptvf);
+	if (rc) {
+		CPT_LOG_ERR("Failed to mark CPT VF device %s UP, rc = %d",
+			    cptvf->dev_name, rc);
+		return -EFAULT;
+	}
+
+	if ((cptvf->vftype != SE_TYPE) && (cptvf->vftype != AE_TYPE)) {
+		CPT_LOG_ERR("Fatal error, unexpected vf type %u, for CPT VF "
+			    "device %s", cptvf->vftype, cptvf->dev_name);
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+void
+otx_cpt_stop_device(void *dev)
+{
+	int rc;
+	uint32_t pending, retries = 5;
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+
+	/* Wait for pending entries to complete */
+	pending = otx_cpt_read_vq_doorbell(cptvf);
+	while (pending) {
+		CPT_LOG_DP_DEBUG("%s: Waiting for pending %u cmds to complete",
+				 cptvf->dev_name, pending);
+		sleep(1);
+		pending = otx_cpt_read_vq_doorbell(cptvf);
+		retries--;
+		if (!retries)
+			break;
+	}
+
+	if (!retries && pending) {
+		CPT_LOG_ERR("%s: Timeout waiting for commands(%u)",
+			    cptvf->dev_name, pending);
+		return;
+	}
+
+	rc = otx_cpt_send_vf_down(cptvf);
+	if (rc) {
+		CPT_LOG_ERR("Failed to bring down vf %s, rc %d",
+			    cptvf->dev_name, rc);
+		return;
+	}
+}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 6e5731a..b795983 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -11,6 +11,7 @@
 #include <rte_memory.h>
 
 #include "cpt_common.h"
+#include "cpt_hw_types.h"
 
 #define CPT_INTR_POLL_INTERVAL_MS	(50)
 
@@ -145,4 +146,33 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
 int
 otx_cpt_deinit_device(void *dev);
 
+int
+otx_cpt_start_device(void *cptvf);
+
+void
+otx_cpt_stop_device(void *cptvf);
+
+/* Write to VQX_DOORBELL register
+ */
+static __rte_always_inline void
+otx_cpt_write_vq_doorbell(struct cpt_vf *cptvf, uint32_t val)
+{
+	cptx_vqx_doorbell_t vqx_dbell;
+
+	vqx_dbell.u = 0;
+	vqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DOORBELL(0, 0), vqx_dbell.u);
+}
+
+static __rte_always_inline uint32_t
+otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
+{
+	cptx_vqx_doorbell_t vqx_dbell;
+
+	vqx_dbell.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DOORBELL(0, 0));
+	return vqx_dbell.s.dbell_cnt;
+}
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 68c6b92..905b37a 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -5,12 +5,14 @@
 #include <rte_alarm.h>
 #include <rte_bus_pci.h>
 #include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
 #include <rte_malloc.h>
 
 #include "cpt_pmd_logs.h"
 #include "cpt_pmd_ops_helper.h"
 
 #include "otx_cryptodev.h"
+#include "otx_cryptodev_capabilities.h"
 #include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_ops.h"
 
@@ -95,6 +97,97 @@ otx_cpt_periodic_alarm_stop(void *arg)
 	return rte_eal_alarm_cancel(otx_cpt_alarm_cb, arg);
 }
 
+/* PMD ops */
+
+static int
+otx_cpt_dev_config(struct rte_cryptodev *dev __rte_unused,
+		   struct rte_cryptodev_config *config __rte_unused)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+	return 0;
+}
+
+static int
+otx_cpt_dev_start(struct rte_cryptodev *c_dev)
+{
+	void *cptvf = c_dev->data->dev_private;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	return otx_cpt_start_device(cptvf);
+}
+
+static void
+otx_cpt_dev_stop(struct rte_cryptodev *c_dev)
+{
+	void *cptvf = c_dev->data->dev_private;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	otx_cpt_stop_device(cptvf);
+}
+
+static int
+otx_cpt_dev_close(struct rte_cryptodev *c_dev)
+{
+	void *cptvf = c_dev->data->dev_private;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	otx_cpt_periodic_alarm_stop(cptvf);
+	otx_cpt_deinit_device(cptvf);
+
+	return 0;
+}
+
+static void
+otx_cpt_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+	if (info != NULL) {
+		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
+		info->feature_flags = dev->feature_flags;
+		info->capabilities = otx_get_capabilities();
+		info->sym.max_nb_sessions = 0;
+		info->driver_id = otx_cryptodev_driver_id;
+		info->min_mbuf_headroom_req = OTX_CPT_MIN_HEADROOM_REQ;
+		info->min_mbuf_tailroom_req = OTX_CPT_MIN_TAILROOM_REQ;
+	}
+}
+
+static void
+otx_cpt_stats_get(struct rte_cryptodev *dev __rte_unused,
+		  struct rte_cryptodev_stats *stats __rte_unused)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+}
+
+static void
+otx_cpt_stats_reset(struct rte_cryptodev *dev __rte_unused)
+{
+	CPT_PMD_INIT_FUNC_TRACE();
+}
+
+static struct rte_cryptodev_ops cptvf_ops = {
+	/* Device related operations */
+	.dev_configure = otx_cpt_dev_config,
+	.dev_start = otx_cpt_dev_start,
+	.dev_stop = otx_cpt_dev_stop,
+	.dev_close = otx_cpt_dev_close,
+	.dev_infos_get = otx_cpt_dev_info_get,
+
+	.stats_get = otx_cpt_stats_get,
+	.stats_reset = otx_cpt_stats_reset,
+	.queue_pair_setup = NULL,
+	.queue_pair_release = NULL,
+	.queue_pair_count = NULL,
+
+	/* Crypto related operations */
+	.sym_session_get_size = NULL,
+	.sym_session_configure = NULL,
+	.sym_session_clear = NULL
+};
+
 static void
 otx_cpt_common_vars_init(struct cpt_vf *cptvf)
 {
@@ -164,7 +257,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	/* Initialize data path variables used by common code */
 	otx_cpt_common_vars_init(cptvf);
 
-	c_dev->dev_ops = NULL;
+	c_dev->dev_ops = &cptvf_ops;
 
 	c_dev->enqueue_burst = NULL;
 	c_dev->dequeue_burst = NULL;
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h
index ac88fa5..b3efecf 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h
@@ -5,6 +5,10 @@
 #ifndef _OTX_CRYPTODEV_OPS_H_
 #define _OTX_CRYPTODEV_OPS_H_
 
+#define OTX_CPT_MIN_HEADROOM_REQ	(24)
+#define OTX_CPT_MIN_TAILROOM_REQ	(8)
+#define CPT_NUM_QS_PER_VF		(1)
+
 void
 cleanup_global_resources(void);
 
-- 
2.7.4

[dpdk-dev] [PATCH v4 09/23] crypto/octeontx: add queue pair functions

[Anoob Joseph]

From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>

Adding queue pair setup and release functions

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h                   |   3 +
 drivers/common/cpt/cpt_hw_types.h                 |   3 +
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 280 ++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h |   9 +
 drivers/crypto/octeontx/otx_cryptodev_ops.c       |  82 ++++++-
 5 files changed, 375 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 88f4902..7333c13 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -15,6 +15,9 @@
  */
 #define CRYPTO_OCTEONTX		0x1
 
+#define CPT_COUNT_THOLD		32
+#define CPT_TIMER_THOLD		0x3F
+
 #define AE_TYPE 1
 #define SE_TYPE 2
 
diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h
index 0a98621..cff59c7 100644
--- a/drivers/common/cpt/cpt_hw_types.h
+++ b/drivers/common/cpt/cpt_hw_types.h
@@ -20,6 +20,9 @@
 #define CPT_VF_INTR_HWERR_MASK  (1<<5)
 #define CPT_VF_INTR_FAULT_MASK  (1<<6)
 
+#define CPT_INST_SIZE           (64)
+#define CPT_NEXT_CHUNK_PTR_SIZE (8)
+
 /*
  * CPT_INST_S software command definitions
  * Words EI (0-3)
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index 303bcc0..5e705a8 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -1,11 +1,14 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2018 Cavium, Inc
  */
+#include <assert.h>
 #include <string.h>
 #include <unistd.h>
 
 #include <rte_branch_prediction.h>
 #include <rte_common.h>
+#include <rte_errno.h>
+#include <rte_memzone.h>
 
 #include "otx_cryptodev_hw_access.h"
 #include "otx_cryptodev_mbox.h"
@@ -177,6 +180,133 @@ otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)
 		      CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
 }
 
+/* Write to VQX_CTL register
+ */
+static void
+otx_cpt_write_vq_ctl(struct cpt_vf *cptvf, bool val)
+{
+	cptx_vqx_ctl_t vqx_ctl;
+
+	vqx_ctl.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				 CPTX_VQX_CTL(0, 0));
+	vqx_ctl.s.ena = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_CTL(0, 0), vqx_ctl.u);
+}
+
+/* Write to VQX_INPROG register
+ */
+static void
+otx_cpt_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val)
+{
+	cptx_vqx_inprog_t vqx_inprg;
+
+	vqx_inprg.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_INPROG(0, 0));
+	vqx_inprg.s.inflight = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_INPROG(0, 0), vqx_inprg.u);
+}
+
+/* Write to VQX_DONE_WAIT NUMWAIT register
+ */
+static void
+otx_cpt_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val)
+{
+	cptx_vqx_done_wait_t vqx_dwait;
+
+	vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DONE_WAIT(0, 0));
+	vqx_dwait.s.num_wait = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
+}
+
+/* Write to VQX_DONE_WAIT NUM_WAIT register
+ */
+static void
+otx_cpt_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val)
+{
+	cptx_vqx_done_wait_t vqx_dwait;
+
+	vqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
+				   CPTX_VQX_DONE_WAIT(0, 0));
+	vqx_dwait.s.time_wait = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);
+}
+
+/* Write to VQX_SADDR register
+ */
+static void
+otx_cpt_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val)
+{
+	cptx_vqx_saddr_t vqx_saddr;
+
+	vqx_saddr.u = val;
+	CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
+		      CPTX_VQX_SADDR(0, 0), vqx_saddr.u);
+}
+
+static void
+otx_cpt_vfvq_init(struct cpt_vf *cptvf)
+{
+	uint64_t base_addr = 0;
+
+	/* Disable the VQ */
+	otx_cpt_write_vq_ctl(cptvf, 0);
+
+	/* Reset the doorbell */
+	otx_cpt_write_vq_doorbell(cptvf, 0);
+	/* Clear inflight */
+	otx_cpt_write_vq_inprog(cptvf, 0);
+
+	/* Write VQ SADDR */
+	base_addr = (uint64_t)(cptvf->cqueue.chead[0].dma_addr);
+	otx_cpt_write_vq_saddr(cptvf, base_addr);
+
+	/* Configure timerhold / coalescence */
+	otx_cpt_write_vq_done_timewait(cptvf, CPT_TIMER_THOLD);
+	otx_cpt_write_vq_done_numwait(cptvf, CPT_COUNT_THOLD);
+
+	/* Enable the VQ */
+	otx_cpt_write_vq_ctl(cptvf, 1);
+}
+
+static int
+cpt_vq_init(struct cpt_vf *cptvf, uint8_t group)
+{
+	int err;
+
+	/* Convey VQ LEN to PF */
+	err = otx_cpt_send_vq_size_msg(cptvf);
+	if (err) {
+		CPT_LOG_ERR("%s: PF not responding to QLEN msg",
+			    cptvf->dev_name);
+		err = -EBUSY;
+		goto cleanup;
+	}
+
+	/* CPT VF device initialization */
+	otx_cpt_vfvq_init(cptvf);
+
+	/* Send msg to PF to assign currnet Q to required group */
+	cptvf->vfgrp = group;
+	err = otx_cpt_send_vf_grp_msg(cptvf, group);
+	if (err) {
+		CPT_LOG_ERR("%s: PF not responding to VF_GRP msg",
+			    cptvf->dev_name);
+		err = -EBUSY;
+		goto cleanup;
+	}
+
+	CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
+	return 0;
+
+cleanup:
+	return err;
+}
+
 void
 otx_cpt_poll_misc(struct cpt_vf *cptvf)
 {
@@ -263,6 +393,156 @@ otx_cpt_deinit_device(void *dev)
 }
 
 int
+otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance)
+{
+	int ret = -ENOENT, len, qlen, i;
+	int chunk_len, chunks, chunk_size;
+	struct cpt_vf *cptvf = (struct cpt_vf *)dev;
+	struct cpt_instance *cpt_instance;
+	struct command_chunk *chunk_head = NULL, *chunk_prev = NULL;
+	struct command_chunk *chunk = NULL;
+	uint8_t *mem;
+	const struct rte_memzone *rz;
+	uint64_t dma_addr = 0, alloc_len, used_len;
+	uint64_t *next_ptr;
+	uint64_t pg_sz = sysconf(_SC_PAGESIZE);
+
+	CPT_LOG_DP_DEBUG("Initializing cpt resource %s", cptvf->dev_name);
+
+	cpt_instance = &cptvf->instance;
+
+	memset(&cptvf->cqueue, 0, sizeof(cptvf->cqueue));
+	memset(&cptvf->pqueue, 0, sizeof(cptvf->pqueue));
+
+	/* Chunks are of fixed size buffers */
+	chunks = DEFAULT_CMD_QCHUNKS;
+	chunk_len = DEFAULT_CMD_QCHUNK_SIZE;
+
+	qlen = chunks * chunk_len;
+	/* Chunk size includes 8 bytes of next chunk ptr */
+	chunk_size = chunk_len * CPT_INST_SIZE + CPT_NEXT_CHUNK_PTR_SIZE;
+
+	/* For command chunk structures */
+	len = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8);
+
+	/* For pending queue */
+	len += qlen * RTE_ALIGN(sizeof(struct rid), 8);
+
+	/* So that instruction queues start as pg size aligned */
+	len = RTE_ALIGN(len, pg_sz);
+
+	/* For Instruction queues */
+	len += chunks * RTE_ALIGN(chunk_size, 128);
+
+	/* Wastage after instruction queues */
+	len = RTE_ALIGN(len, pg_sz);
+
+	rz = rte_memzone_reserve_aligned(cptvf->dev_name, len, cptvf->node,
+					 RTE_MEMZONE_SIZE_HINT_ONLY |
+					 RTE_MEMZONE_256MB,
+					 RTE_CACHE_LINE_SIZE);
+	if (!rz) {
+		ret = rte_errno;
+		goto cleanup;
+	}
+
+	mem = rz->addr;
+	dma_addr = rz->phys_addr;
+	alloc_len = len;
+
+	memset(mem, 0, len);
+
+	cpt_instance->rsvd = (uintptr_t)rz;
+
+	/* Pending queue setup */
+	cptvf->pqueue.rid_queue = (struct rid *)mem;
+	cptvf->pqueue.enq_tail = 0;
+	cptvf->pqueue.deq_head = 0;
+	cptvf->pqueue.pending_count = 0;
+
+	mem +=  qlen * RTE_ALIGN(sizeof(struct rid), 8);
+	len -=  qlen * RTE_ALIGN(sizeof(struct rid), 8);
+	dma_addr += qlen * RTE_ALIGN(sizeof(struct rid), 8);
+
+	/* Alignment wastage */
+	used_len = alloc_len - len;
+	mem += RTE_ALIGN(used_len, pg_sz) - used_len;
+	len -= RTE_ALIGN(used_len, pg_sz) - used_len;
+	dma_addr += RTE_ALIGN(used_len, pg_sz) - used_len;
+
+	/* Init instruction queues */
+	chunk_head = &cptvf->cqueue.chead[0];
+	i = qlen;
+
+	chunk_prev = NULL;
+	for (i = 0; i < DEFAULT_CMD_QCHUNKS; i++) {
+		int csize;
+
+		chunk = &cptvf->cqueue.chead[i];
+		chunk->head = mem;
+		chunk->dma_addr = dma_addr;
+
+		csize = RTE_ALIGN(chunk_size, 128);
+		mem += csize;
+		dma_addr += csize;
+		len -= csize;
+
+		if (chunk_prev) {
+			next_ptr = (uint64_t *)(chunk_prev->head +
+						chunk_size - 8);
+			*next_ptr = (uint64_t)chunk->dma_addr;
+		}
+		chunk_prev = chunk;
+	}
+	/* Circular loop */
+	next_ptr = (uint64_t *)(chunk_prev->head + chunk_size - 8);
+	*next_ptr = (uint64_t)chunk_head->dma_addr;
+
+	assert(!len);
+
+	/* This is used for CPT(0)_PF_Q(0..15)_CTL.size config */
+	cptvf->qsize = chunk_size / 8;
+	cptvf->cqueue.qhead = chunk_head->head;
+	cptvf->cqueue.idx = 0;
+	cptvf->cqueue.cchunk = 0;
+
+	if (cpt_vq_init(cptvf, group)) {
+		CPT_LOG_ERR("Failed to initialize CPT VQ of device %s",
+			    cptvf->dev_name);
+		ret = -EBUSY;
+		goto cleanup;
+	}
+
+	*instance = cpt_instance;
+
+	CPT_LOG_DP_DEBUG("Crypto device (%s) initialized", cptvf->dev_name);
+
+	return 0;
+cleanup:
+	rte_memzone_free(rz);
+	*instance = NULL;
+	return ret;
+}
+
+int
+otx_cpt_put_resource(struct cpt_instance *instance)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct rte_memzone *rz;
+
+	if (!cptvf) {
+		CPT_LOG_ERR("Invalid CPTVF handle");
+		return -EINVAL;
+	}
+
+	CPT_LOG_DP_DEBUG("Releasing cpt device %s", cptvf->dev_name);
+
+	rz = (struct rte_memzone *)instance->rsvd;
+	rte_memzone_free(rz);
+	return 0;
+}
+
+int
 otx_cpt_start_device(void *dev)
 {
 	int rc;
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index b795983..2698df6 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -17,6 +17,9 @@
 
 /* Default command queue length */
 #define DEFAULT_CMD_QCHUNKS		2
+#define DEFAULT_CMD_QCHUNK_SIZE		1023
+#define DEFAULT_CMD_QLEN \
+		(DEFAULT_CMD_QCHUNK_SIZE * DEFAULT_CMD_QCHUNKS)
 
 #define CPT_CSR_REG_BASE(cpt)		((cpt)->reg_base)
 
@@ -147,6 +150,12 @@ int
 otx_cpt_deinit_device(void *dev);
 
 int
+otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance);
+
+int
+otx_cpt_put_resource(struct cpt_instance *instance);
+
+int
 otx_cpt_start_device(void *cptvf);
 
 void
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 905b37a..ed33334 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -23,6 +23,11 @@ static struct rte_mempool *otx_cpt_meta_pool;
 static int otx_cpt_op_mlen;
 static int otx_cpt_op_sb_mlen;
 
+/* Forward declarations */
+
+static int
+otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id);
+
 /*
  * Initializes global variables used by fast-path code
  *
@@ -131,9 +136,16 @@ static int
 otx_cpt_dev_close(struct rte_cryptodev *c_dev)
 {
 	void *cptvf = c_dev->data->dev_private;
+	int i, ret;
 
 	CPT_PMD_INIT_FUNC_TRACE();
 
+	for (i = 0; i < c_dev->data->nb_queue_pairs; i++) {
+		ret = otx_cpt_que_pair_release(c_dev, i);
+		if (ret)
+			return ret;
+	}
+
 	otx_cpt_periodic_alarm_stop(cptvf);
 	otx_cpt_deinit_device(cptvf);
 
@@ -168,6 +180,72 @@ otx_cpt_stats_reset(struct rte_cryptodev *dev __rte_unused)
 	CPT_PMD_INIT_FUNC_TRACE();
 }
 
+static int
+otx_cpt_que_pair_setup(struct rte_cryptodev *dev,
+		       uint16_t que_pair_id,
+		       const struct rte_cryptodev_qp_conf *qp_conf,
+		       int socket_id __rte_unused,
+		       struct rte_mempool *session_pool __rte_unused)
+{
+	void *cptvf = dev->data->dev_private;
+	struct cpt_instance *instance = NULL;
+	struct rte_pci_device *pci_dev;
+	int ret = -1;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (dev->data->queue_pairs[que_pair_id] != NULL) {
+		ret = otx_cpt_que_pair_release(dev, que_pair_id);
+		if (ret)
+			return ret;
+	}
+
+	if (qp_conf->nb_descriptors > DEFAULT_CMD_QLEN) {
+		CPT_LOG_INFO("Number of descriptors too big %d, using default "
+			     "queue length of %d", qp_conf->nb_descriptors,
+			     DEFAULT_CMD_QLEN);
+	}
+
+	pci_dev = RTE_DEV_TO_PCI(dev->device);
+
+	if (pci_dev->mem_resource[0].addr == NULL) {
+		CPT_LOG_ERR("PCI mem address null");
+		return -EIO;
+	}
+
+	ret = otx_cpt_get_resource(cptvf, 0, &instance);
+	if (ret != 0) {
+		CPT_LOG_ERR("Error getting instance handle from device %s : "
+			    "ret = %d", dev->data->name, ret);
+		return ret;
+	}
+
+	instance->queue_id = que_pair_id;
+	dev->data->queue_pairs[que_pair_id] = instance;
+
+	return 0;
+}
+
+static int
+otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)
+{
+	struct cpt_instance *instance = dev->data->queue_pairs[que_pair_id];
+	int ret;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	ret = otx_cpt_put_resource(instance);
+	if (ret != 0) {
+		CPT_LOG_ERR("Error putting instance handle of device %s : "
+			    "ret = %d", dev->data->name, ret);
+		return ret;
+	}
+
+	dev->data->queue_pairs[que_pair_id] = NULL;
+
+	return 0;
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -178,8 +256,8 @@ static struct rte_cryptodev_ops cptvf_ops = {
 
 	.stats_get = otx_cpt_stats_get,
 	.stats_reset = otx_cpt_stats_reset,
-	.queue_pair_setup = NULL,
-	.queue_pair_release = NULL,
+	.queue_pair_setup = otx_cpt_que_pair_setup,
+	.queue_pair_release = otx_cpt_que_pair_release,
 	.queue_pair_count = NULL,
 
 	/* Crypto related operations */
-- 
2.7.4

[dpdk-dev] [PATCH v4 10/23] crypto/octeontx: add session management ops

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding routines for session configure, session clear and get session
size ops.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h      | 119 ++++++++++++++++++++++++++++
 drivers/common/cpt/cpt_request_mgr.h        |  32 ++++++++
 drivers/common/cpt/cpt_ucode.h              |  47 +++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c |  84 +++++++++++++++++++-
 4 files changed, 279 insertions(+), 3 deletions(-)
 create mode 100644 drivers/common/cpt/cpt_request_mgr.h
 create mode 100644 drivers/common/cpt/cpt_ucode.h

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 83a8a42..235320c 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -5,6 +5,9 @@
 #ifndef _CPT_MCODE_DEFINES_H_
 #define _CPT_MCODE_DEFINES_H_
 
+#include <rte_byteorder.h>
+#include <rte_memory.h>
+
 /*
  * This file defines macros and structures according to microcode spec
  *
@@ -35,4 +38,120 @@ typedef struct sglist_comp {
 	uint64_t ptr[4];
 } sg_comp_t;
 
+struct cpt_sess_misc {
+	/** CPT opcode */
+	uint16_t cpt_op:4;
+	/** ZUC, SNOW3G &  KASUMI flags */
+	uint16_t zsk_flag:4;
+	/** Flag for AES GCM */
+	uint16_t aes_gcm:1;
+	/** Flag for AES CTR */
+	uint16_t aes_ctr:1;
+	/** Flag for NULL cipher/auth */
+	uint16_t is_null:1;
+	/** Flag for GMAC */
+	uint16_t is_gmac:1;
+	/** AAD length */
+	uint16_t aad_length;
+	/** MAC len in bytes */
+	uint8_t mac_len;
+	/** IV length in bytes */
+	uint8_t iv_length;
+	/** Auth IV length in bytes */
+	uint8_t auth_iv_length;
+	/** Reserved field */
+	uint8_t rsvd1;
+	/** IV offset in bytes */
+	uint16_t iv_offset;
+	/** Auth IV offset in bytes */
+	uint16_t auth_iv_offset;
+	/** Salt */
+	uint32_t salt;
+	/** Context DMA address */
+	phys_addr_t ctx_dma_addr;
+};
+
+typedef union {
+	uint64_t flags;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint64_t enc_cipher   : 4;
+		uint64_t reserved1    : 1;
+		uint64_t aes_key      : 2;
+		uint64_t iv_source    : 1;
+		uint64_t hash_type    : 4;
+		uint64_t reserved2    : 3;
+		uint64_t auth_input_type : 1;
+		uint64_t mac_len      : 8;
+		uint64_t reserved3    : 8;
+		uint64_t encr_offset  : 16;
+		uint64_t iv_offset    : 8;
+		uint64_t auth_offset  : 8;
+#else
+		uint64_t auth_offset  : 8;
+		uint64_t iv_offset    : 8;
+		uint64_t encr_offset  : 16;
+		uint64_t reserved3    : 8;
+		uint64_t mac_len      : 8;
+		uint64_t auth_input_type : 1;
+		uint64_t reserved2    : 3;
+		uint64_t hash_type    : 4;
+		uint64_t iv_source    : 1;
+		uint64_t aes_key      : 2;
+		uint64_t reserved1    : 1;
+		uint64_t enc_cipher   : 4;
+#endif
+	} e;
+} encr_ctrl_t;
+
+typedef struct {
+	encr_ctrl_t enc_ctrl;
+	uint8_t  encr_key[32];
+	uint8_t  encr_iv[16];
+} mc_enc_context_t;
+
+typedef struct {
+	uint8_t  ipad[64];
+	uint8_t  opad[64];
+} mc_fc_hmac_context_t;
+
+typedef struct {
+	mc_enc_context_t     enc;
+	mc_fc_hmac_context_t hmac;
+} mc_fc_context_t;
+
+typedef struct {
+	uint8_t encr_auth_iv[16];
+	uint8_t ci_key[16];
+	uint8_t zuc_const[32];
+} mc_zuc_snow3g_ctx_t;
+
+typedef struct {
+	uint8_t reg_A[8];
+	uint8_t ci_key[16];
+} mc_kasumi_ctx_t;
+
+struct cpt_ctx {
+	/* Below fields are accessed by sw */
+	uint64_t enc_cipher	:8;
+	uint64_t hash_type	:8;
+	uint64_t mac_len	:8;
+	uint64_t auth_key_len	:8;
+	uint64_t fc_type	:4;
+	uint64_t hmac		:1;
+	uint64_t zsk_flags	:3;
+	uint64_t k_ecb		:1;
+	uint64_t snow3g		:1;
+	uint64_t rsvd		:22;
+	/* Below fields are accessed by hardware */
+	union {
+		mc_fc_context_t fctx;
+		mc_zuc_snow3g_ctx_t zs_ctx;
+		mc_kasumi_ctx_t k_ctx;
+	};
+	uint8_t  auth_key[64];
+};
+
+#define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
+
 #endif /* _CPT_MCODE_DEFINES_H_ */
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
new file mode 100644
index 0000000..fe184fe
--- /dev/null
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_REQUEST_MGR_H_
+#define _CPT_REQUEST_MGR_H_
+
+#include "cpt_mcode_defines.h"
+
+/*
+ * This file defines the agreement between the common layer and the individual
+ * crypto drivers for OCTEON TX series. Datapath in otx* directory include this
+ * file and all these functions are static inlined for better performance.
+ *
+ */
+
+/*
+ * Get the session size
+ *
+ * This function is used in the data path.
+ *
+ * @return
+ *   - session size
+ */
+static __rte_always_inline unsigned int
+cpt_get_session_size(void)
+{
+	unsigned int ctx_len = sizeof(struct cpt_ctx);
+	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
+}
+
+#endif /* _CPT_REQUEST_MGR_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
new file mode 100644
index 0000000..e4f16fe
--- /dev/null
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Cavium, Inc
+ */
+
+#ifndef _CPT_UCODE_H_
+#define _CPT_UCODE_H_
+
+#include "cpt_mcode_defines.h"
+
+/*
+ * This file defines functions that are interfaces to microcode spec.
+ *
+ */
+
+static __rte_always_inline int
+cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
+{
+	/*
+	 * Microcode only supports the following combination.
+	 * Encryption followed by authentication
+	 * Authentication followed by decryption
+	 */
+	if (xform->next) {
+		if ((xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
+		    (xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
+		    (xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)) {
+			/* Unsupported as of now by microcode */
+			CPT_LOG_DP_ERR("Unsupported combination");
+			return -1;
+		}
+		if ((xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
+		    (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
+		    (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)) {
+			/* For GMAC auth there is no cipher operation */
+			if (xform->aead.algo != RTE_CRYPTO_AEAD_AES_GCM ||
+			    xform->next->auth.algo !=
+			    RTE_CRYPTO_AUTH_AES_GMAC) {
+				/* Unsupported as of now by microcode */
+				CPT_LOG_DP_ERR("Unsupported combination");
+				return -1;
+			}
+		}
+	}
+	return 0;
+}
+
+#endif /*_CPT_UCODE_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index ed33334..653f372 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -10,6 +10,8 @@
 
 #include "cpt_pmd_logs.h"
 #include "cpt_pmd_ops_helper.h"
+#include "cpt_ucode.h"
+#include "cpt_request_mgr.h"
 
 #include "otx_cryptodev.h"
 #include "otx_cryptodev_capabilities.h"
@@ -246,6 +248,82 @@ otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)
 	return 0;
 }
 
+static unsigned int
+otx_cpt_get_session_size(struct rte_cryptodev *dev __rte_unused)
+{
+	return cpt_get_session_size();
+}
+
+static void
+otx_cpt_session_init(void *sym_sess, uint8_t driver_id)
+{
+	struct rte_cryptodev_sym_session *sess = sym_sess;
+	struct cpt_sess_misc *cpt_sess =
+	 (struct cpt_sess_misc *) get_sym_session_private_data(sess, driver_id);
+
+	CPT_PMD_INIT_FUNC_TRACE();
+	cpt_sess->ctx_dma_addr = rte_mempool_virt2iova(cpt_sess) +
+			sizeof(struct cpt_sess_misc);
+}
+
+static int
+otx_cpt_session_cfg(struct rte_cryptodev *dev,
+		    struct rte_crypto_sym_xform *xform,
+		    struct rte_cryptodev_sym_session *sess,
+		    struct rte_mempool *mempool)
+{
+	struct rte_crypto_sym_xform *chain;
+	void *sess_private_data = NULL;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (cpt_is_algo_supported(xform))
+		goto err;
+
+	if (unlikely(sess == NULL)) {
+		CPT_LOG_ERR("invalid session struct");
+		return -EINVAL;
+	}
+
+	if (rte_mempool_get(mempool, &sess_private_data)) {
+		CPT_LOG_ERR("Could not allocate sess_private_data");
+		return -ENOMEM;
+	}
+
+	chain = xform;
+	while (chain) {
+		switch (chain->type) {
+		default:
+			CPT_LOG_ERR("Invalid crypto xform type");
+			break;
+		}
+		chain = chain->next;
+	}
+	set_sym_session_private_data(sess, dev->driver_id, sess_private_data);
+	otx_cpt_session_init(sess, dev->driver_id);
+	return 0;
+
+err:
+	if (sess_private_data)
+		rte_mempool_put(mempool, sess_private_data);
+	return -EPERM;
+}
+
+static void
+otx_cpt_session_clear(struct rte_cryptodev *dev,
+		  struct rte_cryptodev_sym_session *sess)
+{
+	void *sess_priv = get_sym_session_private_data(sess, dev->driver_id);
+
+	CPT_PMD_INIT_FUNC_TRACE();
+	if (sess_priv) {
+		memset(sess_priv, 0, otx_cpt_get_session_size(dev));
+		struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
+		set_sym_session_private_data(sess, dev->driver_id, NULL);
+		rte_mempool_put(sess_mp, sess_priv);
+	}
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -261,9 +339,9 @@ static struct rte_cryptodev_ops cptvf_ops = {
 	.queue_pair_count = NULL,
 
 	/* Crypto related operations */
-	.sym_session_get_size = NULL,
-	.sym_session_configure = NULL,
-	.sym_session_clear = NULL
+	.sym_session_get_size = otx_cpt_get_session_size,
+	.sym_session_configure = otx_cpt_session_cfg,
+	.sym_session_clear = otx_cpt_session_clear
 };
 
 static void
-- 
2.7.4

[dpdk-dev] [PATCH v4 11/23] crypto/octeontx: add supported sessions

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Adding AEAD, cipher & auth sessions support.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h      |  90 ++++
 drivers/common/cpt/cpt_ucode.h              | 669 ++++++++++++++++++++++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c |  17 +
 3 files changed, 776 insertions(+)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 235320c..50657a2 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -25,9 +25,88 @@
 #define SG_LIST_HDR_SIZE	(8u)
 #define SG_ENTRY_SIZE		sizeof(sg_comp_t)
 
+#define CPT_DMA_MODE		(1 << 7)
+
+#define CPT_FROM_CTX		0
+#define CPT_FROM_DPTR		1
+
+#define FC_GEN			0x1
+#define ZUC_SNOW3G		0x2
+#define KASUMI			0x3
+#define HASH_HMAC		0x4
+
+#define ZS_EA			0x1
+#define ZS_IA			0x2
+#define K_F8			0x4
+#define K_F9			0x8
+
+#define CPT_OP_CIPHER_ENCRYPT	0x1
+#define CPT_OP_CIPHER_DECRYPT	0x2
+#define CPT_OP_CIPHER_MASK	0x3
+
+#define CPT_OP_AUTH_VERIFY	0x4
+#define CPT_OP_AUTH_GENERATE	0x8
+#define CPT_OP_AUTH_MASK	0xC
+
+#define CPT_OP_ENCODE	(CPT_OP_CIPHER_ENCRYPT | CPT_OP_AUTH_GENERATE)
+#define CPT_OP_DECODE	(CPT_OP_CIPHER_DECRYPT | CPT_OP_AUTH_VERIFY)
+
 /* #define CPT_ALWAYS_USE_SG_MODE */
 #define CPT_ALWAYS_USE_SEPARATE_BUF
 
+typedef enum {
+	MD5_TYPE        = 1,
+	SHA1_TYPE       = 2,
+	SHA2_SHA224     = 3,
+	SHA2_SHA256     = 4,
+	SHA2_SHA384     = 5,
+	SHA2_SHA512     = 6,
+	GMAC_TYPE       = 7,
+	XCBC_TYPE       = 8,
+	SHA3_SHA224     = 10,
+	SHA3_SHA256     = 11,
+	SHA3_SHA384     = 12,
+	SHA3_SHA512     = 13,
+	SHA3_SHAKE256   = 14,
+	SHA3_SHAKE512   = 15,
+
+	/* These are only for software use */
+	ZUC_EIA3        = 0x90,
+	SNOW3G_UIA2     = 0x91,
+	KASUMI_F9_CBC   = 0x92,
+	KASUMI_F9_ECB   = 0x93,
+} mc_hash_type_t;
+
+typedef enum {
+	/* To support passthrough */
+	PASSTHROUGH  = 0x0,
+	/*
+	 * These are defined by MC for Flexi crypto
+	 * for field of 4 bits
+	 */
+	DES3_CBC    = 0x1,
+	DES3_ECB    = 0x2,
+	AES_CBC     = 0x3,
+	AES_ECB     = 0x4,
+	AES_CFB     = 0x5,
+	AES_CTR     = 0x6,
+	AES_GCM     = 0x7,
+	AES_XTS     = 0x8,
+
+	/* These are only for software use */
+	ZUC_EEA3        = 0x90,
+	SNOW3G_UEA2     = 0x91,
+	KASUMI_F8_CBC   = 0x92,
+	KASUMI_F8_ECB   = 0x93,
+} mc_cipher_type_t;
+
+typedef enum {
+	AES_128_BIT = 0x1,
+	AES_192_BIT = 0x2,
+	AES_256_BIT = 0x3
+} mc_aes_type_t;
+
+
 typedef struct sglist_comp {
 	union {
 		uint64_t len;
@@ -152,6 +231,17 @@ struct cpt_ctx {
 	uint8_t  auth_key[64];
 };
 
+typedef struct fc_params digest_params_t;
+
+/* Cipher Algorithms */
+typedef mc_cipher_type_t cipher_type_t;
+
+/* Auth Algorithms */
+typedef mc_hash_type_t auth_type_t;
+
 #define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
 
+#define SESS_PRIV(__sess) \
+	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
+
 #endif /* _CPT_MCODE_DEFINES_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index e4f16fe..4bbb27a 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -12,6 +12,13 @@
  *
  */
 
+static uint8_t zuc_d[32] = {
+	0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
+	0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
+	0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
+	0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC
+};
+
 static __rte_always_inline int
 cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
 {
@@ -44,4 +51,666 @@ cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
 	return 0;
 }
 
+static __rte_always_inline void
+gen_key_snow3g(uint8_t *ck, uint32_t *keyx)
+{
+	int i, base;
+
+	for (i = 0; i < 4; i++) {
+		base = 4 * i;
+		keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
+			(ck[base + 2] << 8) | (ck[base + 3]);
+		keyx[3 - i] = rte_cpu_to_be_32(keyx[3 - i]);
+	}
+}
+
+static __rte_always_inline int
+cpt_fc_ciph_validate_key_aes(uint16_t key_len)
+{
+	switch (key_len) {
+	case CPT_BYTE_16:
+	case CPT_BYTE_24:
+	case CPT_BYTE_32:
+		return 0;
+	default:
+		return -1;
+	}
+}
+
+static __rte_always_inline int
+cpt_fc_ciph_validate_key(cipher_type_t type, struct cpt_ctx *cpt_ctx,
+		uint16_t key_len)
+{
+	int fc_type = 0;
+	switch (type) {
+	case PASSTHROUGH:
+		fc_type = FC_GEN;
+		break;
+	case DES3_CBC:
+	case DES3_ECB:
+		fc_type = FC_GEN;
+		break;
+	case AES_CBC:
+	case AES_ECB:
+	case AES_CFB:
+	case AES_CTR:
+	case AES_GCM:
+		if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
+			return -1;
+		fc_type = FC_GEN;
+		break;
+	case AES_XTS:
+		key_len = key_len / 2;
+		if (unlikely(key_len == CPT_BYTE_24)) {
+			CPT_LOG_DP_ERR("Invalid AES key len for XTS");
+			return -1;
+		}
+		if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
+			return -1;
+		fc_type = FC_GEN;
+		break;
+	case ZUC_EEA3:
+	case SNOW3G_UEA2:
+		if (unlikely(key_len != 16))
+			return -1;
+		/* No support for AEAD yet */
+		if (unlikely(cpt_ctx->hash_type))
+			return -1;
+		fc_type = ZUC_SNOW3G;
+		break;
+	case KASUMI_F8_CBC:
+	case KASUMI_F8_ECB:
+		if (unlikely(key_len != 16))
+			return -1;
+		/* No support for AEAD yet */
+		if (unlikely(cpt_ctx->hash_type))
+			return -1;
+		fc_type = KASUMI;
+		break;
+	default:
+		return -1;
+	}
+	return fc_type;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_passthrough(struct cpt_ctx *cpt_ctx, mc_fc_context_t *fctx)
+{
+	cpt_ctx->enc_cipher = 0;
+	CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_set_aes_key_type(mc_fc_context_t *fctx, uint16_t key_len)
+{
+	mc_aes_type_t aes_key_type = 0;
+	switch (key_len) {
+	case CPT_BYTE_16:
+		aes_key_type = AES_128_BIT;
+		break;
+	case CPT_BYTE_24:
+		aes_key_type = AES_192_BIT;
+		break;
+	case CPT_BYTE_32:
+		aes_key_type = AES_256_BIT;
+		break;
+	default:
+		/* This should not happen */
+		CPT_LOG_DP_ERR("Invalid AES key len");
+		return;
+	}
+	CPT_P_ENC_CTRL(fctx).aes_key = aes_key_type;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_snow3g_uea2(struct cpt_ctx *cpt_ctx, uint8_t *key,
+		uint16_t key_len)
+{
+	uint32_t keyx[4];
+	cpt_ctx->snow3g = 1;
+	gen_key_snow3g(key, keyx);
+	memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
+	cpt_ctx->fc_type = ZUC_SNOW3G;
+	cpt_ctx->zsk_flags = 0;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_zuc_eea3(struct cpt_ctx *cpt_ctx, uint8_t *key,
+		uint16_t key_len)
+{
+	cpt_ctx->snow3g = 0;
+	memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
+	memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
+	cpt_ctx->fc_type = ZUC_SNOW3G;
+	cpt_ctx->zsk_flags = 0;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_kasumi_f8_ecb(struct cpt_ctx *cpt_ctx, uint8_t *key,
+		uint16_t key_len)
+{
+	cpt_ctx->k_ecb = 1;
+	memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+	cpt_ctx->zsk_flags = 0;
+	cpt_ctx->fc_type = KASUMI;
+}
+
+static __rte_always_inline void
+cpt_fc_ciph_set_key_kasumi_f8_cbc(struct cpt_ctx *cpt_ctx, uint8_t *key,
+		uint16_t key_len)
+{
+	memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+	cpt_ctx->zsk_flags = 0;
+	cpt_ctx->fc_type = KASUMI;
+}
+
+static __rte_always_inline int
+cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,
+		    uint16_t key_len, uint8_t *salt)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	mc_fc_context_t *fctx = &cpt_ctx->fctx;
+	uint64_t *ctrl_flags = NULL;
+	int fc_type;
+
+	/* Validate key before proceeding */
+	fc_type = cpt_fc_ciph_validate_key(type, cpt_ctx, key_len);
+	if (unlikely(fc_type == -1))
+		return -1;
+
+	if (fc_type == FC_GEN) {
+		cpt_ctx->fc_type = FC_GEN;
+		ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags);
+		*ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
+		/*
+		 * We need to always say IV is from DPTR as user can
+		 * sometimes iverride IV per operation.
+		 */
+		CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_DPTR;
+	}
+
+	switch (type) {
+	case PASSTHROUGH:
+		cpt_fc_ciph_set_key_passthrough(cpt_ctx, fctx);
+		goto fc_success;
+	case DES3_CBC:
+		/* CPT performs DES using 3DES with the 8B DES-key
+		 * replicated 2 more times to match the 24B 3DES-key.
+		 * Eg. If org. key is "0x0a 0x0b", then new key is
+		 * "0x0a 0x0b 0x0a 0x0b 0x0a 0x0b"
+		 */
+		if (key_len == 8) {
+			/* Skipping the first 8B as it will be copied
+			 * in the regular code flow
+			 */
+			memcpy(fctx->enc.encr_key+key_len, key, key_len);
+			memcpy(fctx->enc.encr_key+2*key_len, key, key_len);
+		}
+		break;
+	case DES3_ECB:
+		/* For DES3_ECB IV need to be from CTX. */
+		CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_CTX;
+		break;
+	case AES_CBC:
+	case AES_ECB:
+	case AES_CFB:
+	case AES_CTR:
+		cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
+		break;
+	case AES_GCM:
+		/* Even though iv source is from dptr,
+		 * aes_gcm salt is taken from ctx
+		 */
+		if (salt) {
+			memcpy(fctx->enc.encr_iv, salt, 4);
+			/* Assuming it was just salt update
+			 * and nothing else
+			 */
+			if (!key)
+				goto fc_success;
+		}
+		cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
+		break;
+	case AES_XTS:
+		key_len = key_len / 2;
+		cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
+
+		/* Copy key2 for XTS into ipad */
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memcpy(fctx->hmac.ipad, &key[key_len], key_len);
+		break;
+	case SNOW3G_UEA2:
+		cpt_fc_ciph_set_key_snow3g_uea2(cpt_ctx, key, key_len);
+		goto success;
+	case ZUC_EEA3:
+		cpt_fc_ciph_set_key_zuc_eea3(cpt_ctx, key, key_len);
+		goto success;
+	case KASUMI_F8_ECB:
+		cpt_fc_ciph_set_key_kasumi_f8_ecb(cpt_ctx, key, key_len);
+		goto success;
+	case KASUMI_F8_CBC:
+		cpt_fc_ciph_set_key_kasumi_f8_cbc(cpt_ctx, key, key_len);
+		goto success;
+	default:
+		break;
+	}
+
+	/* Only for FC_GEN case */
+
+	/* For GMAC auth, cipher must be NULL */
+	if (cpt_ctx->hash_type != GMAC_TYPE)
+		CPT_P_ENC_CTRL(fctx).enc_cipher = type;
+
+	memcpy(fctx->enc.encr_key, key, key_len);
+
+fc_success:
+	*ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
+
+success:
+	cpt_ctx->enc_cipher = type;
+
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_fc_auth_set_key(void *ctx, auth_type_t type, uint8_t *key,
+		    uint16_t key_len, uint16_t mac_len)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	mc_fc_context_t *fctx = &cpt_ctx->fctx;
+	uint64_t *ctrl_flags = NULL;
+
+	if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
+		uint32_t keyx[4];
+
+		if (key_len != 16)
+			return -1;
+		/* No support for AEAD yet */
+		if (cpt_ctx->enc_cipher)
+			return -1;
+		/* For ZUC/SNOW3G/Kasumi */
+		switch (type) {
+		case SNOW3G_UIA2:
+			cpt_ctx->snow3g = 1;
+			gen_key_snow3g(key, keyx);
+			memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case ZUC_EIA3:
+			cpt_ctx->snow3g = 0;
+			memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
+			memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
+			cpt_ctx->fc_type = ZUC_SNOW3G;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case KASUMI_F9_ECB:
+			/* Kasumi ECB mode */
+			cpt_ctx->k_ecb = 1;
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->fc_type = KASUMI;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		case KASUMI_F9_CBC:
+			memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
+			cpt_ctx->fc_type = KASUMI;
+			cpt_ctx->zsk_flags = 0x1;
+			break;
+		default:
+			return -1;
+		}
+		cpt_ctx->mac_len = 4;
+		cpt_ctx->hash_type = type;
+		return 0;
+	}
+
+	if (!(cpt_ctx->fc_type == FC_GEN && !type)) {
+		if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher)
+			cpt_ctx->fc_type = HASH_HMAC;
+	}
+
+	ctrl_flags = (uint64_t *)&fctx->enc.enc_ctrl.flags;
+	*ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
+
+	/* For GMAC auth, cipher must be NULL */
+	if (type == GMAC_TYPE)
+		CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
+
+	CPT_P_ENC_CTRL(fctx).hash_type = cpt_ctx->hash_type = type;
+	CPT_P_ENC_CTRL(fctx).mac_len = cpt_ctx->mac_len = mac_len;
+
+	if (key_len) {
+		cpt_ctx->hmac = 1;
+		memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key));
+		memcpy(cpt_ctx->auth_key, key, key_len);
+		cpt_ctx->auth_key_len = key_len;
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
+		memcpy(fctx->hmac.opad, key, key_len);
+		CPT_P_ENC_CTRL(fctx).auth_input_type = 1;
+	}
+	*ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
+	return 0;
+}
+
+static __rte_always_inline int
+fill_sess_aead(struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_aead_xform *aead_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint32_t cipher_key_len = 0;
+	uint8_t zsk_flag = 0, aes_gcm = 0;
+	aead_form = &xform->aead;
+	void *ctx;
+
+	if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
+	   aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+		sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
+		sess->cpt_op |= CPT_OP_AUTH_GENERATE;
+	} else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
+		aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+		sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
+		sess->cpt_op |= CPT_OP_AUTH_VERIFY;
+	} else {
+		CPT_LOG_DP_ERR("Unknown cipher operation\n");
+		return -1;
+	}
+	switch (aead_form->algo) {
+	case RTE_CRYPTO_AEAD_AES_GCM:
+		enc_type = AES_GCM;
+		cipher_key_len = 16;
+		aes_gcm = 1;
+		break;
+	case RTE_CRYPTO_AEAD_AES_CCM:
+		CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
+			       aead_form->algo);
+		return -1;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
+			       aead_form->algo);
+		return -1;
+	}
+	if (aead_form->key.length < cipher_key_len) {
+		CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
+			       (unsigned int long)aead_form->key.length);
+		return -1;
+	}
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->mac_len = aead_form->digest_length;
+	sess->iv_offset = aead_form->iv.offset;
+	sess->iv_length = aead_form->iv.length;
+	sess->aad_length = aead_form->aad_length;
+	ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+
+	cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
+			aead_form->key.length, NULL);
+
+	cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, aead_form->digest_length);
+
+	return 0;
+}
+
+static __rte_always_inline int
+fill_sess_cipher(struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_cipher_xform *c_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	uint32_t cipher_key_len = 0;
+	uint8_t zsk_flag = 0, aes_gcm = 0, aes_ctr = 0, is_null = 0;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER)
+		return -1;
+
+	c_form = &xform->cipher;
+
+	if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
+		sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
+	else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
+		sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
+	else {
+		CPT_LOG_DP_ERR("Unknown cipher operation\n");
+		return -1;
+	}
+
+	switch (c_form->algo) {
+	case RTE_CRYPTO_CIPHER_AES_CBC:
+		enc_type = AES_CBC;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CBC:
+		enc_type = DES3_CBC;
+		cipher_key_len = 24;
+		break;
+	case RTE_CRYPTO_CIPHER_DES_CBC:
+		/* DES is implemented using 3DES in hardware */
+		enc_type = DES3_CBC;
+		cipher_key_len = 8;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_CTR:
+		enc_type = AES_CTR;
+		cipher_key_len = 16;
+		aes_ctr = 1;
+		break;
+	case RTE_CRYPTO_CIPHER_NULL:
+		enc_type = 0;
+		is_null = 1;
+		break;
+	case RTE_CRYPTO_CIPHER_KASUMI_F8:
+		enc_type = KASUMI_F8_ECB;
+		cipher_key_len = 16;
+		zsk_flag = K_F8;
+		break;
+	case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
+		enc_type = SNOW3G_UEA2;
+		cipher_key_len = 16;
+		zsk_flag = ZS_EA;
+		break;
+	case RTE_CRYPTO_CIPHER_ZUC_EEA3:
+		enc_type = ZUC_EEA3;
+		cipher_key_len = 16;
+		zsk_flag = ZS_EA;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_XTS:
+		enc_type = AES_XTS;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_ECB:
+		enc_type = DES3_ECB;
+		cipher_key_len = 24;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_ECB:
+		enc_type = AES_ECB;
+		cipher_key_len = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CTR:
+	case RTE_CRYPTO_CIPHER_AES_F8:
+	case RTE_CRYPTO_CIPHER_ARC4:
+		CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
+			       c_form->algo);
+		return -1;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
+			       c_form->algo);
+		return -1;
+	}
+
+	if (c_form->key.length < cipher_key_len) {
+		CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
+			       (unsigned long) c_form->key.length);
+		return -1;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->aes_ctr = aes_ctr;
+	sess->iv_offset = c_form->iv.offset;
+	sess->iv_length = c_form->iv.length;
+	sess->is_null = is_null;
+
+	cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type, c_form->key.data,
+			    c_form->key.length, NULL);
+
+	return 0;
+}
+
+static __rte_always_inline int
+fill_sess_auth(struct rte_crypto_sym_xform *xform,
+	       struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_auth_xform *a_form;
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint8_t zsk_flag = 0, aes_gcm = 0, is_null = 0;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
+		goto error_out;
+
+	a_form = &xform->auth;
+
+	if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
+		sess->cpt_op |= CPT_OP_AUTH_VERIFY;
+	else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
+		sess->cpt_op |= CPT_OP_AUTH_GENERATE;
+	else {
+		CPT_LOG_DP_ERR("Unknown auth operation");
+		return -1;
+	}
+
+	if (a_form->key.length > 64) {
+		CPT_LOG_DP_ERR("Auth key length is big");
+		return -1;
+	}
+
+	switch (a_form->algo) {
+	case RTE_CRYPTO_AUTH_SHA1_HMAC:
+		/* Fall through */
+	case RTE_CRYPTO_AUTH_SHA1:
+		auth_type = SHA1_TYPE;
+		break;
+	case RTE_CRYPTO_AUTH_SHA256_HMAC:
+	case RTE_CRYPTO_AUTH_SHA256:
+		auth_type = SHA2_SHA256;
+		break;
+	case RTE_CRYPTO_AUTH_SHA512_HMAC:
+	case RTE_CRYPTO_AUTH_SHA512:
+		auth_type = SHA2_SHA512;
+		break;
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		auth_type = GMAC_TYPE;
+		aes_gcm = 1;
+		break;
+	case RTE_CRYPTO_AUTH_SHA224_HMAC:
+	case RTE_CRYPTO_AUTH_SHA224:
+		auth_type = SHA2_SHA224;
+		break;
+	case RTE_CRYPTO_AUTH_SHA384_HMAC:
+	case RTE_CRYPTO_AUTH_SHA384:
+		auth_type = SHA2_SHA384;
+		break;
+	case RTE_CRYPTO_AUTH_MD5_HMAC:
+	case RTE_CRYPTO_AUTH_MD5:
+		auth_type = MD5_TYPE;
+		break;
+	case RTE_CRYPTO_AUTH_KASUMI_F9:
+		auth_type = KASUMI_F9_ECB;
+		/*
+		 * Indicate that direction needs to be taken out
+		 * from end of src
+		 */
+		zsk_flag = K_F9;
+		break;
+	case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
+		auth_type = SNOW3G_UIA2;
+		zsk_flag = ZS_IA;
+		break;
+	case RTE_CRYPTO_AUTH_ZUC_EIA3:
+		auth_type = ZUC_EIA3;
+		zsk_flag = ZS_IA;
+		break;
+	case RTE_CRYPTO_AUTH_NULL:
+		auth_type = 0;
+		is_null = 1;
+		break;
+	case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+	case RTE_CRYPTO_AUTH_AES_CMAC:
+	case RTE_CRYPTO_AUTH_AES_CBC_MAC:
+		CPT_LOG_DP_ERR("Crypto: Unsupported hash algo %u",
+			       a_form->algo);
+		goto error_out;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined Hash algo %u specified",
+			       a_form->algo);
+		goto error_out;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->mac_len = a_form->digest_length;
+	sess->is_null = is_null;
+	if (zsk_flag) {
+		sess->auth_iv_offset = a_form->iv.offset;
+		sess->auth_iv_length = a_form->iv.length;
+	}
+	cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type, a_form->key.data,
+			    a_form->key.length, a_form->digest_length);
+
+	return 0;
+
+error_out:
+	return -1;
+}
+
+static __rte_always_inline int
+fill_sess_gmac(struct rte_crypto_sym_xform *xform,
+		 struct cpt_sess_misc *sess)
+{
+	struct rte_crypto_auth_xform *a_form;
+	cipher_type_t enc_type = 0; /* NULL Cipher type */
+	auth_type_t auth_type = 0; /* NULL Auth type */
+	uint8_t zsk_flag = 0, aes_gcm = 0;
+	void *ctx;
+
+	if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
+		return -1;
+
+	a_form = &xform->auth;
+
+	if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
+		sess->cpt_op |= CPT_OP_ENCODE;
+	else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
+		sess->cpt_op |= CPT_OP_DECODE;
+	else {
+		CPT_LOG_DP_ERR("Unknown auth operation");
+		return -1;
+	}
+
+	switch (a_form->algo) {
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		enc_type = AES_GCM;
+		auth_type = GMAC_TYPE;
+		break;
+	default:
+		CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
+			       a_form->algo);
+		return -1;
+	}
+
+	sess->zsk_flag = zsk_flag;
+	sess->aes_gcm = aes_gcm;
+	sess->is_gmac = 1;
+	sess->iv_offset = a_form->iv.offset;
+	sess->iv_length = a_form->iv.length;
+	sess->mac_len = a_form->digest_length;
+	ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
+
+	cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
+			a_form->key.length, NULL);
+	cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, a_form->digest_length);
+
+	return 0;
+}
+
 #endif /*_CPT_UCODE_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 653f372..16fad49 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -293,6 +293,23 @@ otx_cpt_session_cfg(struct rte_cryptodev *dev,
 	chain = xform;
 	while (chain) {
 		switch (chain->type) {
+		case RTE_CRYPTO_SYM_XFORM_AEAD:
+			if (fill_sess_aead(chain, sess_private_data))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_CIPHER:
+			if (fill_sess_cipher(chain, sess_private_data))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_AUTH:
+			if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
+				if (fill_sess_gmac(chain, sess_private_data))
+					goto err;
+			} else {
+				if (fill_sess_auth(chain, sess_private_data))
+					goto err;
+			}
+			break;
 		default:
 			CPT_LOG_ERR("Invalid crypto xform type");
 			break;
-- 
2.7.4

[dpdk-dev] [PATCH v4 12/23] common/cpt: add common defines for microcode

[Anoob Joseph]

From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h | 117 +++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 50657a2..263fc47 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -12,6 +12,12 @@
  * This file defines macros and structures according to microcode spec
  *
  */
+/* SE opcodes */
+#define CPT_MAJOR_OP_FC		0x33
+#define CPT_MAJOR_OP_HASH	0x34
+#define CPT_MAJOR_OP_HMAC	0x35
+#define CPT_MAJOR_OP_ZUC_SNOW3G	0x37
+#define CPT_MAJOR_OP_KASUMI	0x38
 
 #define CPT_BYTE_16		16
 #define CPT_BYTE_24		24
@@ -54,6 +60,25 @@
 /* #define CPT_ALWAYS_USE_SG_MODE */
 #define CPT_ALWAYS_USE_SEPARATE_BUF
 
+/*
+ * Parameters for Flexi Crypto
+ * requests
+ */
+#define VALID_AAD_BUF 0x01
+#define VALID_MAC_BUF 0x02
+#define VALID_IV_BUF 0x04
+#define SINGLE_BUF_INPLACE 0x08
+#define SINGLE_BUF_HEADTAILROOM 0x10
+
+#define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff)
+#define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff)
+#define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff)
+#define ENCR_DLEN(__d_lens) (__d_lens >> 32)
+#define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff)
+
+/* FC offset_control at start of DPTR in bytes */
+#define OFF_CTRL_LEN  8 /**< bytes */
+
 typedef enum {
 	MD5_TYPE        = 1,
 	SHA1_TYPE       = 2,
@@ -106,6 +131,48 @@ typedef enum {
 	AES_256_BIT = 0x3
 } mc_aes_type_t;
 
+typedef enum {
+	/* Microcode errors */
+	NO_ERR = 0x00,
+	ERR_OPCODE_UNSUPPORTED = 0x01,
+
+	/* SCATTER GATHER */
+	ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,
+	ERR_SCATTER_GATHER_LIST = 0x03,
+	ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,
+
+	/* SE GC */
+	ERR_GC_LENGTH_INVALID = 0x41,
+	ERR_GC_RANDOM_LEN_INVALID = 0x42,
+	ERR_GC_DATA_LEN_INVALID = 0x43,
+	ERR_GC_DRBG_TYPE_INVALID = 0x44,
+	ERR_GC_CTX_LEN_INVALID = 0x45,
+	ERR_GC_CIPHER_UNSUPPORTED = 0x46,
+	ERR_GC_AUTH_UNSUPPORTED = 0x47,
+	ERR_GC_OFFSET_INVALID = 0x48,
+	ERR_GC_HASH_MODE_UNSUPPORTED = 0x49,
+	ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,
+	ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,
+	ERR_GC_ICV_MISCOMPARE = 0x4c,
+	ERR_GC_DATA_UNALIGNED = 0x4d,
+
+	/* API Layer */
+	ERR_BAD_ALT_CCODE = 0xfd,
+	ERR_REQ_PENDING = 0xfe,
+	ERR_REQ_TIMEOUT = 0xff,
+
+	ERR_BAD_INPUT_LENGTH = (0x40000000 | 384),    /* 0x40000180 */
+	ERR_BAD_KEY_LENGTH,
+	ERR_BAD_KEY_HANDLE,
+	ERR_BAD_CONTEXT_HANDLE,
+	ERR_BAD_SCALAR_LENGTH,
+	ERR_BAD_DIGEST_LENGTH,
+	ERR_BAD_INPUT_ARG,
+	ERR_BAD_RECORD_PADDING,
+	ERR_NB_REQUEST_PENDING,
+	ERR_EIO,
+	ERR_ENODEV,
+} mc_error_code_t;
 
 typedef struct sglist_comp {
 	union {
@@ -231,6 +298,49 @@ struct cpt_ctx {
 	uint8_t  auth_key[64];
 };
 
+/* Buffer pointer */
+typedef struct buf_ptr {
+	void *vaddr;
+	phys_addr_t dma_addr;
+	uint32_t size;
+	uint32_t resv;
+} buf_ptr_t;
+
+/* IOV Pointer */
+typedef struct{
+	int buf_cnt;
+	buf_ptr_t bufs[0];
+} iov_ptr_t;
+
+typedef union opcode_info {
+	uint16_t flags;
+	struct {
+		uint8_t major;
+		uint8_t minor;
+	} s;
+} opcode_info_t;
+
+typedef struct fc_params {
+	/* 0th cache line */
+	union {
+		buf_ptr_t bufs[1];
+		struct {
+			iov_ptr_t *src_iov;
+			iov_ptr_t *dst_iov;
+		};
+	};
+	void *iv_buf;
+	void *auth_iv_buf;
+	buf_ptr_t meta_buf;
+	buf_ptr_t ctx_buf;
+	uint64_t rsvd2;
+
+	/* 1st cache line */
+	buf_ptr_t aad_buf;
+	buf_ptr_t mac_buf;
+
+} fc_params_t;
+
 typedef struct fc_params digest_params_t;
 
 /* Cipher Algorithms */
@@ -239,8 +349,15 @@ typedef mc_cipher_type_t cipher_type_t;
 /* Auth Algorithms */
 typedef mc_hash_type_t auth_type_t;
 
+/* Helper macros */
+
 #define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
 
+#define SRC_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
+#define DST_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
+
 #define SESS_PRIV(__sess) \
 	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
 
-- 
2.7.4

[dpdk-dev] [PATCH v4 13/23] common/cpt: add microcode interface for encryption

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding microcode interface additions for supporting encryption.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 987 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 987 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 4bbb27a..f5247d5 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -5,6 +5,10 @@
 #ifndef _CPT_UCODE_H_
 #define _CPT_UCODE_H_
 
+#include <stdbool.h>
+
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
 #include "cpt_mcode_defines.h"
 
 /*
@@ -64,6 +68,14 @@ gen_key_snow3g(uint8_t *ck, uint32_t *keyx)
 	}
 }
 
+static __rte_always_inline void
+cpt_fc_salt_update(void *ctx,
+		   uint8_t *salt)
+{
+	struct cpt_ctx *cpt_ctx = ctx;
+	memcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);
+}
+
 static __rte_always_inline int
 cpt_fc_ciph_validate_key_aes(uint16_t key_len)
 {
@@ -312,6 +324,550 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,
 	return 0;
 }
 
+static __rte_always_inline uint32_t
+fill_sg_comp(sg_comp_t *list,
+	     uint32_t i,
+	     phys_addr_t dma_addr,
+	     uint32_t size)
+{
+	sg_comp_t *to = &list[i>>2];
+
+	to->u.s.len[i%4] = rte_cpu_to_be_16(size);
+	to->ptr[i%4] = rte_cpu_to_be_64(dma_addr);
+	i++;
+	return i;
+}
+
+static __rte_always_inline uint32_t
+fill_sg_comp_from_buf(sg_comp_t *list,
+		      uint32_t i,
+		      buf_ptr_t *from)
+{
+	sg_comp_t *to = &list[i>>2];
+
+	to->u.s.len[i%4] = rte_cpu_to_be_16(from->size);
+	to->ptr[i%4] = rte_cpu_to_be_64(from->dma_addr);
+	i++;
+	return i;
+}
+
+static __rte_always_inline uint32_t
+fill_sg_comp_from_buf_min(sg_comp_t *list,
+			  uint32_t i,
+			  buf_ptr_t *from,
+			  uint32_t *psize)
+{
+	sg_comp_t *to = &list[i >> 2];
+	uint32_t size = *psize;
+	uint32_t e_len;
+
+	e_len = (size > from->size) ? from->size : size;
+	to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
+	to->ptr[i % 4] = rte_cpu_to_be_64(from->dma_addr);
+	*psize -= e_len;
+	i++;
+	return i;
+}
+
+/*
+ * This fills the MC expected SGIO list
+ * from IOV given by user.
+ */
+static __rte_always_inline uint32_t
+fill_sg_comp_from_iov(sg_comp_t *list,
+		      uint32_t i,
+		      iov_ptr_t *from, uint32_t from_offset,
+		      uint32_t *psize, buf_ptr_t *extra_buf,
+		      uint32_t extra_offset)
+{
+	int32_t j;
+	uint32_t extra_len = extra_buf ? extra_buf->size : 0;
+	uint32_t size = *psize - extra_len;
+	buf_ptr_t *bufs;
+
+	bufs = from->bufs;
+	for (j = 0; (j < from->buf_cnt) && size; j++) {
+		phys_addr_t e_dma_addr;
+		uint32_t e_len;
+		sg_comp_t *to = &list[i >> 2];
+
+		if (!bufs[j].size)
+			continue;
+
+		if (unlikely(from_offset)) {
+			if (from_offset >= bufs[j].size) {
+				from_offset -= bufs[j].size;
+				continue;
+			}
+			e_dma_addr = bufs[j].dma_addr + from_offset;
+			e_len = (size > (bufs[j].size - from_offset)) ?
+				(bufs[j].size - from_offset) : size;
+			from_offset = 0;
+		} else {
+			e_dma_addr = bufs[j].dma_addr;
+			e_len = (size > bufs[j].size) ?
+				bufs[j].size : size;
+		}
+
+		to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
+		to->ptr[i % 4] = rte_cpu_to_be_64(e_dma_addr);
+
+		if (extra_len && (e_len >= extra_offset)) {
+			/* Break the data at given offset */
+			uint32_t next_len = e_len - extra_offset;
+			phys_addr_t next_dma = e_dma_addr + extra_offset;
+
+			if (!extra_offset) {
+				i--;
+			} else {
+				e_len = extra_offset;
+				size -= e_len;
+				to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
+			}
+
+			/* Insert extra data ptr */
+			if (extra_len) {
+				i++;
+				to = &list[i >> 2];
+				to->u.s.len[i % 4] =
+					rte_cpu_to_be_16(extra_buf->size);
+				to->ptr[i % 4] =
+					rte_cpu_to_be_64(extra_buf->dma_addr);
+
+				/* size already decremented by extra len */
+			}
+
+			/* insert the rest of the data */
+			if (next_len) {
+				i++;
+				to = &list[i >> 2];
+				to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
+				to->ptr[i % 4] = rte_cpu_to_be_64(next_dma);
+				size -= next_len;
+			}
+			extra_len = 0;
+
+		} else {
+			size -= e_len;
+		}
+		if (extra_offset)
+			extra_offset -= size;
+		i++;
+	}
+
+	*psize = size;
+	return (uint32_t)i;
+}
+
+static __rte_always_inline int
+cpt_enc_hmac_prep(uint32_t flags,
+		  uint64_t d_offs,
+		  uint64_t d_lens,
+		  fc_params_t *fc_params,
+		  void *op,
+		  void **prep_req)
+{
+	uint32_t iv_offset = 0;
+	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t cipher_type, hash_type;
+	uint32_t mac_len, size;
+	uint8_t iv_len = 16;
+	struct cpt_request_info *req;
+	buf_ptr_t *meta_p, *aad_buf = NULL;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len, aad_len = 0;
+	uint32_t passthrough_len = 0;
+	void *m_vaddr, *offset_vaddr;
+	uint64_t m_dma, offset_dma, ctx_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr;
+	uint64_t c_dma;
+	int32_t m_size;
+	opcode_info_t opcode;
+
+	meta_p = &fc_params->meta_buf;
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs);
+	auth_offset = AUTH_OFFSET(d_offs);
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * We dont support both aad
+		 * and auth data separately
+		 */
+		auth_data_len = 0;
+		auth_offset = 0;
+		aad_len = fc_params->aad_buf.size;
+		aad_buf = &fc_params->aad_buf;
+	}
+	cpt_ctx = fc_params->ctx_buf.vaddr;
+	cipher_type = cpt_ctx->enc_cipher;
+	hash_type = cpt_ctx->hash_type;
+	mac_len = cpt_ctx->mac_len;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* start cpt request info struct at 8 byte boundary */
+	size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+		(uint8_t *)m_vaddr;
+
+	req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
+
+	size += sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	if (hash_type == GMAC_TYPE)
+		encr_data_len = 0;
+
+	if (unlikely(!(flags & VALID_IV_BUF))) {
+		iv_len = 0;
+		iv_offset = ENCR_IV_OFFSET(d_offs);
+	}
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * When AAD is given, data above encr_offset is pass through
+		 * Since AAD is given as separate pointer and not as offset,
+		 * this is a special case as we need to fragment input data
+		 * into passthrough + encr_data and then insert AAD in between.
+		 */
+		if (hash_type != GMAC_TYPE) {
+			passthrough_len = encr_offset;
+			auth_offset = passthrough_len + iv_len;
+			encr_offset = passthrough_len + aad_len + iv_len;
+			auth_data_len = aad_len + encr_data_len;
+		} else {
+			passthrough_len = 16 + aad_len;
+			auth_offset = passthrough_len + iv_len;
+			auth_data_len = aad_len;
+		}
+	} else {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/* Encryption */
+	opcode.s.major = CPT_MAJOR_OP_FC;
+	opcode.s.minor = 0;
+
+	auth_dlen = auth_offset + auth_data_len;
+	enc_dlen = encr_data_len + encr_offset;
+	if (unlikely(encr_data_len & 0xf)) {
+		if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
+			enc_dlen = ROUNDUP8(encr_data_len) + encr_offset;
+		else if (likely((cipher_type == AES_CBC) ||
+				(cipher_type == AES_ECB)))
+			enc_dlen = ROUNDUP16(encr_data_len) + encr_offset;
+	}
+
+	if (unlikely(hash_type == GMAC_TYPE)) {
+		encr_offset = auth_dlen;
+		enc_dlen = 0;
+	}
+
+	if (unlikely(auth_dlen > enc_dlen)) {
+		inputlen = auth_dlen;
+		outputlen = auth_dlen + mac_len;
+	} else {
+		inputlen = enc_dlen;
+		outputlen = enc_dlen + mac_len;
+	}
+
+	/* GP op header */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((flags & SINGLE_BUF_INPLACE) &&
+		   (flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = fc_params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+
+		/* This falls under strict SG mode */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+		size = OFF_CTRL_LEN + iv_len;
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+
+		i = 0;
+
+		/* Offset control word that includes iv */
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 OFF_CTRL_LEN + iv_len);
+
+		/* Add input data */
+		size = inputlen - iv_len;
+		if (likely(size)) {
+			uint32_t aad_offset = aad_len ? passthrough_len : 0;
+
+			if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+				i = fill_sg_comp_from_buf_min(gather_comp, i,
+							      fc_params->bufs,
+							      &size);
+			} else {
+				i = fill_sg_comp_from_iov(gather_comp, i,
+							  fc_params->src_iov,
+							  0, &size,
+							  aad_buf, aad_offset);
+			}
+
+			if (unlikely(size)) {
+				CPT_LOG_DP_ERR("Insufficient buffer space,"
+					       " size %d needed", size);
+				return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter list
+		 */
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* Add IV */
+		if (likely(iv_len)) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* output data or output data + digest*/
+		if (unlikely(flags & VALID_MAC_BUF)) {
+			size = outputlen - iv_len - mac_len;
+			if (size) {
+				uint32_t aad_offset =
+					aad_len ? passthrough_len : 0;
+
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+							scatter_comp,
+							i,
+							fc_params->bufs,
+							&size);
+				} else {
+					i = fill_sg_comp_from_iov(scatter_comp,
+							i,
+							fc_params->dst_iov,
+							0,
+							&size,
+							aad_buf,
+							aad_offset);
+				}
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+			/* mac_data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(scatter_comp, i,
+							  &fc_params->mac_buf);
+			}
+		} else {
+			/* Output including mac */
+			size = outputlen - iv_len;
+			if (likely(size)) {
+				uint32_t aad_offset =
+					aad_len ? passthrough_len : 0;
+
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+							scatter_comp,
+							i,
+							fc_params->bufs,
+							&size);
+				} else {
+					i = fill_sg_comp_from_iov(scatter_comp,
+							i,
+							fc_params->dst_iov,
+							0,
+							&size,
+							aad_buf,
+							aad_offset);
+				}
+				if (unlikely(size)) {
+					CPT_LOG_DP_ERR("Insufficient buffer"
+						       " space, size %d needed",
+						       size);
+					return ERR_BAD_INPUT_ARG;
+				}
+			}
+		}
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	ctx_dma = fc_params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, fctx);
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = ctx_dma;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op  = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline void *__hot
+cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
+		     fc_params_t *fc_params, void *op, int *ret_val)
+{
+	struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+	uint8_t fc_type;
+	void *prep_req = NULL;
+	int ret;
+
+	fc_type = ctx->fc_type;
+
+	/* Common api for rest of the ops */
+	if (likely(fc_type == FC_GEN)) {
+		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
+					fc_params, op, &prep_req);
+	} else {
+		ret = ERR_EIO;
+	}
+
+	if (unlikely(!prep_req))
+		*ret_val = ret;
+	return prep_req;
+}
+
 static __rte_always_inline int
 cpt_fc_auth_set_key(void *ctx, auth_type_t type, uint8_t *key,
 		    uint16_t key_len, uint16_t mac_len)
@@ -713,4 +1269,435 @@ fill_sess_gmac(struct rte_crypto_sym_xform *xform,
 	return 0;
 }
 
+static __rte_always_inline void *
+alloc_op_meta(struct rte_mbuf *m_src,
+	      buf_ptr_t *buf,
+	      int32_t len,
+	      struct rte_mempool *cpt_meta_pool)
+{
+	uint8_t *mdata;
+
+#ifndef CPT_ALWAYS_USE_SEPARATE_BUF
+	if (likely(m_src && (m_src->nb_segs == 1))) {
+		int32_t tailroom;
+		phys_addr_t mphys;
+
+		/* Check if tailroom is sufficient to hold meta data */
+		tailroom = rte_pktmbuf_tailroom(m_src);
+		if (likely(tailroom > len + 8)) {
+			mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;
+			mphys = m_src->buf_physaddr + m_src->buf_len;
+			mdata -= len;
+			mphys -= len;
+			buf->vaddr = mdata;
+			buf->dma_addr = mphys;
+			buf->size = len;
+			/* Indicate that this is a mbuf allocated mdata */
+			mdata = (uint8_t *)((uint64_t)mdata | 1ull);
+			return mdata;
+		}
+	}
+#else
+	RTE_SET_USED(m_src);
+#endif
+
+	if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))
+		return NULL;
+
+	buf->vaddr = mdata;
+	buf->dma_addr = rte_mempool_virt2iova(mdata);
+	buf->size = len;
+
+	return mdata;
+}
+
+/**
+ * cpt_free_metabuf - free metabuf to mempool.
+ * @param instance: pointer to instance.
+ * @param objp: pointer to the metabuf.
+ */
+static __rte_always_inline void
+free_op_meta(void *mdata, struct rte_mempool *cpt_meta_pool)
+{
+	bool nofree = ((uintptr_t)mdata & 1ull);
+
+	if (likely(nofree))
+		return;
+	rte_mempool_put(cpt_meta_pool, mdata);
+}
+
+static __rte_always_inline uint32_t
+prepare_iov_from_pkt(struct rte_mbuf *pkt,
+		     iov_ptr_t *iovec, uint32_t start_offset)
+{
+	uint16_t index = 0;
+	void *seg_data = NULL;
+	phys_addr_t seg_phys;
+	int32_t seg_size = 0;
+
+	if (!pkt) {
+		iovec->buf_cnt = 0;
+		return 0;
+	}
+
+	if (!start_offset) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+	} else {
+		while (start_offset >= pkt->data_len) {
+			start_offset -= pkt->data_len;
+			pkt = pkt->next;
+		}
+
+		seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);
+		seg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset);
+		seg_size = pkt->data_len - start_offset;
+		if (!seg_size)
+			return 1;
+	}
+
+	/* first seg */
+	iovec->bufs[index].vaddr = seg_data;
+	iovec->bufs[index].dma_addr = seg_phys;
+	iovec->bufs[index].size = seg_size;
+	index++;
+	pkt = pkt->next;
+
+	while (unlikely(pkt != NULL)) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+		if (!seg_size)
+			break;
+
+		iovec->bufs[index].vaddr = seg_data;
+		iovec->bufs[index].dma_addr = seg_phys;
+		iovec->bufs[index].size = seg_size;
+
+		index++;
+
+		pkt = pkt->next;
+	}
+
+	iovec->buf_cnt = index;
+	return 0;
+}
+
+static __rte_always_inline uint32_t
+prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,
+			     fc_params_t *param,
+			     uint32_t *flags)
+{
+	uint16_t index = 0;
+	void *seg_data = NULL;
+	phys_addr_t seg_phys;
+	uint32_t seg_size = 0;
+	iov_ptr_t *iovec;
+
+	seg_data = rte_pktmbuf_mtod(pkt, void *);
+	seg_phys = rte_pktmbuf_mtophys(pkt);
+	seg_size = pkt->data_len;
+
+	/* first seg */
+	if (likely(!pkt->next)) {
+		uint32_t headroom, tailroom;
+
+		*flags |= SINGLE_BUF_INPLACE;
+		headroom = rte_pktmbuf_headroom(pkt);
+		tailroom = rte_pktmbuf_tailroom(pkt);
+		if (likely((headroom >= 24) &&
+		    (tailroom >= 8))) {
+			/* In 83XX this is prerequivisit for Direct mode */
+			*flags |= SINGLE_BUF_HEADTAILROOM;
+		}
+		param->bufs[0].vaddr = seg_data;
+		param->bufs[0].dma_addr = seg_phys;
+		param->bufs[0].size = seg_size;
+		return 0;
+	}
+	iovec = param->src_iov;
+	iovec->bufs[index].vaddr = seg_data;
+	iovec->bufs[index].dma_addr = seg_phys;
+	iovec->bufs[index].size = seg_size;
+	index++;
+	pkt = pkt->next;
+
+	while (unlikely(pkt != NULL)) {
+		seg_data = rte_pktmbuf_mtod(pkt, void *);
+		seg_phys = rte_pktmbuf_mtophys(pkt);
+		seg_size = pkt->data_len;
+
+		if (!seg_size)
+			break;
+
+		iovec->bufs[index].vaddr = seg_data;
+		iovec->bufs[index].dma_addr = seg_phys;
+		iovec->bufs[index].size = seg_size;
+
+		index++;
+
+		pkt = pkt->next;
+	}
+
+	iovec->buf_cnt = index;
+	return 0;
+}
+
+static __rte_always_inline void *
+fill_fc_params(struct rte_crypto_op *cop,
+	       struct cpt_sess_misc *sess_misc,
+	       void **mdata_ptr,
+	       int *op_ret)
+{
+	uint32_t space = 0;
+	struct rte_crypto_sym_op *sym_op = cop->sym;
+	void *mdata;
+	uintptr_t *op;
+	uint32_t mc_hash_off;
+	uint32_t flags = 0;
+	uint64_t d_offs, d_lens;
+	void *prep_req = NULL;
+	struct rte_mbuf *m_src, *m_dst;
+	uint8_t cpt_op = sess_misc->cpt_op;
+	uint8_t zsk_flag = sess_misc->zsk_flag;
+	uint8_t aes_gcm = sess_misc->aes_gcm;
+	uint16_t mac_len = sess_misc->mac_len;
+#ifdef CPT_ALWAYS_USE_SG_MODE
+	uint8_t inplace = 0;
+#else
+	uint8_t inplace = 1;
+#endif
+	fc_params_t fc_params;
+	char src[SRC_IOV_SIZE];
+	char dst[SRC_IOV_SIZE];
+	uint32_t iv_buf[4];
+	struct cptvf_meta_info *cpt_m_info =
+				(struct cptvf_meta_info *)(*mdata_ptr);
+
+	if (likely(sess_misc->iv_length)) {
+		flags |= VALID_IV_BUF;
+		fc_params.iv_buf = rte_crypto_op_ctod_offset(cop,
+				   uint8_t *, sess_misc->iv_offset);
+		if (sess_misc->aes_ctr &&
+		    unlikely(sess_misc->iv_length != 16)) {
+			memcpy((uint8_t *)iv_buf,
+				rte_crypto_op_ctod_offset(cop,
+				uint8_t *, sess_misc->iv_offset), 12);
+			iv_buf[3] = rte_cpu_to_be_32(0x1);
+			fc_params.iv_buf = iv_buf;
+		}
+	}
+
+	if (zsk_flag) {
+		fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
+					uint8_t *,
+					sess_misc->auth_iv_offset);
+		if (zsk_flag == K_F9) {
+			CPT_LOG_DP_ERR("Should not reach here for "
+			"kasumi F9\n");
+		}
+		if (zsk_flag != ZS_EA)
+			inplace = 0;
+	}
+	m_src = sym_op->m_src;
+	m_dst = sym_op->m_dst;
+
+	if (aes_gcm) {
+		uint8_t *salt;
+		uint8_t *aad_data;
+		uint16_t aad_len;
+
+		d_offs = sym_op->aead.data.offset;
+		d_lens = sym_op->aead.data.length;
+		mc_hash_off = sym_op->aead.data.offset +
+			      sym_op->aead.data.length;
+
+		aad_data = sym_op->aead.aad.data;
+		aad_len = sess_misc->aad_length;
+		if (likely((aad_data + aad_len) ==
+			   rte_pktmbuf_mtod_offset(m_src,
+				uint8_t *,
+				sym_op->aead.data.offset))) {
+			d_offs = (d_offs - aad_len) | (d_offs << 16);
+			d_lens = (d_lens + aad_len) | (d_lens << 32);
+		} else {
+			fc_params.aad_buf.vaddr = sym_op->aead.aad.data;
+			fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;
+			fc_params.aad_buf.size = aad_len;
+			flags |= VALID_AAD_BUF;
+			inplace = 0;
+			d_offs = d_offs << 16;
+			d_lens = d_lens << 32;
+		}
+
+		salt = fc_params.iv_buf;
+		if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
+			cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
+			sess_misc->salt = *(uint32_t *)salt;
+		}
+		fc_params.iv_buf = salt + 4;
+		if (likely(mac_len)) {
+			struct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst :
+					     m_src;
+
+			if (!m)
+				m = m_src;
+
+			/* hmac immediately following data is best case */
+			if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
+			    mc_hash_off !=
+			    (uint8_t *)sym_op->aead.digest.data)) {
+				flags |= VALID_MAC_BUF;
+				fc_params.mac_buf.size = sess_misc->mac_len;
+				fc_params.mac_buf.vaddr =
+				  sym_op->aead.digest.data;
+				fc_params.mac_buf.dma_addr =
+				 sym_op->aead.digest.phys_addr;
+				inplace = 0;
+			}
+		}
+	} else {
+		d_offs = sym_op->cipher.data.offset;
+		d_lens = sym_op->cipher.data.length;
+		mc_hash_off = sym_op->cipher.data.offset +
+			      sym_op->cipher.data.length;
+		d_offs = (d_offs << 16) | sym_op->auth.data.offset;
+		d_lens = (d_lens << 32) | sym_op->auth.data.length;
+
+		if (mc_hash_off < (sym_op->auth.data.offset +
+				   sym_op->auth.data.length)){
+			mc_hash_off = (sym_op->auth.data.offset +
+				       sym_op->auth.data.length);
+		}
+		/* for gmac, salt should be updated like in gcm */
+		if (unlikely(sess_misc->is_gmac)) {
+			uint8_t *salt;
+			salt = fc_params.iv_buf;
+			if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
+				cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
+				sess_misc->salt = *(uint32_t *)salt;
+			}
+			fc_params.iv_buf = salt + 4;
+		}
+		if (likely(mac_len)) {
+			struct rte_mbuf *m;
+
+			m = (cpt_op & CPT_OP_ENCODE) ? m_dst : m_src;
+			if (!m)
+				m = m_src;
+
+			/* hmac immediately following data is best case */
+			if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
+			    mc_hash_off !=
+			     (uint8_t *)sym_op->auth.digest.data)) {
+				flags |= VALID_MAC_BUF;
+				fc_params.mac_buf.size =
+					sess_misc->mac_len;
+				fc_params.mac_buf.vaddr =
+					sym_op->auth.digest.data;
+				fc_params.mac_buf.dma_addr =
+				sym_op->auth.digest.phys_addr;
+				inplace = 0;
+			}
+		}
+	}
+	fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);
+	fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;
+
+	if (unlikely(sess_misc->is_null || sess_misc->cpt_op == CPT_OP_DECODE))
+		inplace = 0;
+
+	if (likely(!m_dst && inplace)) {
+		/* Case of single buffer without AAD buf or
+		 * separate mac buf in place and
+		 * not air crypto
+		 */
+		fc_params.dst_iov = fc_params.src_iov = (void *)src;
+
+		if (unlikely(prepare_iov_from_pkt_inplace(m_src,
+							  &fc_params,
+							  &flags))) {
+			CPT_LOG_DP_ERR("Prepare inplace src iov failed");
+			*op_ret = -1;
+			return NULL;
+		}
+
+	} else {
+		/* Out of place processing */
+		fc_params.src_iov = (void *)src;
+		fc_params.dst_iov = (void *)dst;
+
+		/* Store SG I/O in the api for reuse */
+		if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {
+			CPT_LOG_DP_ERR("Prepare src iov failed");
+			*op_ret = -1;
+			return NULL;
+		}
+
+		if (unlikely(m_dst != NULL)) {
+			uint32_t pkt_len;
+
+			/* Try to make room as much as src has */
+			m_dst = sym_op->m_dst;
+			pkt_len = rte_pktmbuf_pkt_len(m_dst);
+
+			if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {
+				pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;
+				if (!rte_pktmbuf_append(m_dst, pkt_len)) {
+					CPT_LOG_DP_ERR("Not enough space in "
+						       "m_dst %p, need %u"
+						       " more",
+						       m_dst, pkt_len);
+					return NULL;
+				}
+			}
+
+			if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {
+				CPT_LOG_DP_ERR("Prepare dst iov failed for "
+					       "m_dst %p", m_dst);
+				return NULL;
+			}
+		} else {
+			fc_params.dst_iov = (void *)src;
+		}
+	}
+
+	if (likely(flags & SINGLE_BUF_HEADTAILROOM))
+		mdata = alloc_op_meta(m_src,
+				      &fc_params.meta_buf,
+				      cpt_m_info->cptvf_op_sb_mlen,
+				      cpt_m_info->cptvf_meta_pool);
+	else
+		mdata = alloc_op_meta(NULL,
+				      &fc_params.meta_buf,
+				      cpt_m_info->cptvf_op_mlen,
+				      cpt_m_info->cptvf_meta_pool);
+
+	if (unlikely(mdata == NULL)) {
+		CPT_LOG_DP_ERR("Error allocating meta buffer for request");
+		return NULL;
+	}
+
+	op = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull);
+	op[0] = (uintptr_t)mdata;
+	op[1] = (uintptr_t)cop;
+	op[2] = op[3] = 0; /* Used to indicate auth verify */
+	space += 4 * sizeof(uint64_t);
+
+	fc_params.meta_buf.vaddr = (uint8_t *)op + space;
+	fc_params.meta_buf.dma_addr += space;
+	fc_params.meta_buf.size -= space;
+
+	/* Finally prepare the instruction */
+	if (cpt_op & CPT_OP_ENCODE)
+		prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
+						&fc_params, op, op_ret);
+
+	if (unlikely(!prep_req))
+		free_op_meta(mdata, cpt_m_info->cptvf_meta_pool);
+	*mdata_ptr = mdata;
+	return prep_req;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v4 14/23] common/cpt: add microcode interface for decryption

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding microcode interface additions for supporting decryption.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 417 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 417 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index f5247d5..9d4d4c8 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -844,6 +844,420 @@ cpt_enc_hmac_prep(uint32_t flags,
 	return 0;
 }
 
+static __rte_always_inline int
+cpt_dec_hmac_prep(uint32_t flags,
+		  uint64_t d_offs,
+		  uint64_t d_lens,
+		  fc_params_t *fc_params,
+		  void *op,
+		  void **prep_req)
+{
+	uint32_t iv_offset = 0, size;
+	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+	struct cpt_ctx *cpt_ctx;
+	int32_t hash_type, mac_len, m_size;
+	uint8_t iv_len = 16;
+	struct cpt_request_info *req;
+	buf_ptr_t *meta_p, *aad_buf = NULL;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len, aad_len = 0;
+	uint32_t passthrough_len = 0;
+	void *m_vaddr, *offset_vaddr;
+	uint64_t m_dma, offset_dma, ctx_dma;
+	opcode_info_t opcode;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr;
+	uint64_t c_dma;
+
+	meta_p = &fc_params->meta_buf;
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs);
+	auth_offset = AUTH_OFFSET(d_offs);
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * We dont support both aad
+		 * and auth data separately
+		 */
+		auth_data_len = 0;
+		auth_offset = 0;
+		aad_len = fc_params->aad_buf.size;
+		aad_buf = &fc_params->aad_buf;
+	}
+
+	cpt_ctx = fc_params->ctx_buf.vaddr;
+	hash_type = cpt_ctx->hash_type;
+	mac_len = cpt_ctx->mac_len;
+
+	if (hash_type == GMAC_TYPE)
+		encr_data_len = 0;
+
+	if (unlikely(!(flags & VALID_IV_BUF))) {
+		iv_len = 0;
+		iv_offset = ENCR_IV_OFFSET(d_offs);
+	}
+
+	if (unlikely(flags & VALID_AAD_BUF)) {
+		/*
+		 * When AAD is given, data above encr_offset is pass through
+		 * Since AAD is given as separate pointer and not as offset,
+		 * this is a special case as we need to fragment input data
+		 * into passthrough + encr_data and then insert AAD in between.
+		 */
+		if (hash_type != GMAC_TYPE) {
+			passthrough_len = encr_offset;
+			auth_offset = passthrough_len + iv_len;
+			encr_offset = passthrough_len + aad_len + iv_len;
+			auth_data_len = aad_len + encr_data_len;
+		} else {
+			passthrough_len = 16 + aad_len;
+			auth_offset = passthrough_len + iv_len;
+			auth_data_len = aad_len;
+		}
+	} else {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+	       (uint8_t *)m_vaddr;
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* start cpt request info structure at 8 byte alignment */
+	size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+		(uint8_t *)m_vaddr;
+
+	req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
+
+	size += sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Decryption */
+	opcode.s.major = CPT_MAJOR_OP_FC;
+	opcode.s.minor = 1;
+
+	enc_dlen = encr_offset + encr_data_len;
+	auth_dlen = auth_offset + auth_data_len;
+
+	if (auth_dlen > enc_dlen) {
+		inputlen = auth_dlen + mac_len;
+		outputlen = auth_dlen;
+	} else {
+		inputlen = enc_dlen + mac_len;
+		outputlen = enc_dlen;
+	}
+
+	if (hash_type == GMAC_TYPE)
+		encr_offset = inputlen;
+
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((flags & SINGLE_BUF_INPLACE) &&
+		   (flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = fc_params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+		req->ist.ei1 = offset_dma;
+
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr +
+					outputlen - iv_len);
+		/* since this is decryption,
+		 * don't touch the content of
+		 * alternate ccode space as it contains
+		 * hmac.
+		 */
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+						      OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+	} else {
+		uint64_t dptr_dma, rptr_dma;
+		uint32_t g_size_bytes, s_size_bytes;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint8_t i = 0;
+
+		/* This falls under strict SG mode */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+		size = OFF_CTRL_LEN + iv_len;
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+						      OFF_CTRL_LEN);
+			uint64_t *src = fc_params->iv_buf;
+			dest[0] = src[0];
+			dest[1] = src[1];
+		}
+
+		*(uint64_t *)offset_vaddr =
+			rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
+				((uint64_t)iv_offset << 8) |
+				((uint64_t)auth_offset));
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word that includes iv */
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 OFF_CTRL_LEN + iv_len);
+
+		/* Add input data */
+		if (flags & VALID_MAC_BUF) {
+			size = inputlen - iv_len - mac_len;
+			if (size) {
+				/* input data only */
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+							gather_comp, i,
+							fc_params->bufs,
+							&size);
+				} else {
+					uint32_t aad_offset = aad_len ?
+						passthrough_len : 0;
+
+					i = fill_sg_comp_from_iov(gather_comp,
+							i,
+							fc_params->src_iov,
+							0, &size,
+							aad_buf,
+							aad_offset);
+				}
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+
+			/* mac data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(gather_comp, i,
+							  &fc_params->mac_buf);
+			}
+		} else {
+			/* input data + mac */
+			size = inputlen - iv_len;
+			if (size) {
+				if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+					i = fill_sg_comp_from_buf_min(
+							gather_comp, i,
+							fc_params->bufs,
+							&size);
+				} else {
+					uint32_t aad_offset = aad_len ?
+						passthrough_len : 0;
+
+					if (!fc_params->src_iov)
+						return ERR_BAD_INPUT_ARG;
+
+					i = fill_sg_comp_from_iov(
+							gather_comp, i,
+							fc_params->src_iov,
+							0, &size,
+							aad_buf,
+							aad_offset);
+				}
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* Add iv */
+		if (iv_len) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN,
+					 iv_len);
+		}
+
+		/* Add output data */
+		size = outputlen - iv_len;
+		if (size) {
+			if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+				/* handle single buffer here */
+				i = fill_sg_comp_from_buf_min(scatter_comp, i,
+							      fc_params->bufs,
+							      &size);
+			} else {
+				uint32_t aad_offset = aad_len ?
+					passthrough_len : 0;
+
+				if (!fc_params->dst_iov)
+					return ERR_BAD_INPUT_ARG;
+
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  fc_params->dst_iov, 0,
+							  &size, aad_buf,
+							  aad_offset);
+			}
+
+			if (unlikely(size))
+				return ERR_BAD_INPUT_ARG;
+		}
+
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+		size += COMPLETION_CODE_SIZE;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	ctx_dma = fc_params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, fctx);
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = ctx_dma;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline void *
+cpt_fc_dec_hmac_prep(uint32_t flags,
+		     uint64_t d_offs,
+		     uint64_t d_lens,
+		     fc_params_t *fc_params,
+		     void *op, int *ret_val)
+{
+	struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+	uint8_t fc_type;
+	void *prep_req = NULL;
+	int ret;
+
+	fc_type = ctx->fc_type;
+
+	if (likely(fc_type == FC_GEN)) {
+		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
+					fc_params, op, &prep_req);
+	} else {
+		/*
+		 * For AUTH_ONLY case,
+		 * MC only supports digest generation and verification
+		 * should be done in software by memcmp()
+		 */
+
+		ret = ERR_EIO;
+	}
+
+	if (unlikely(!prep_req))
+		*ret_val = ret;
+	return prep_req;
+}
+
 static __rte_always_inline void *__hot
 cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 		     fc_params_t *fc_params, void *op, int *ret_val)
@@ -1693,6 +2107,9 @@ fill_fc_params(struct rte_crypto_op *cop,
 	if (cpt_op & CPT_OP_ENCODE)
 		prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
 						&fc_params, op, op_ret);
+	else
+		prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,
+						&fc_params, op, op_ret);
 
 	if (unlikely(!prep_req))
 		free_op_meta(mdata, cpt_m_info->cptvf_meta_pool);
-- 
2.7.4

[dpdk-dev] [PATCH v4 15/23] common/cpt: add crypo op enqueue request manager framework

[Anoob Joseph]

From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>

Adding crypto enqueue op request manager framework. This routine won't
submit to the hardware yet.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_request_mgr.h | 68 ++++++++++++++++++++++++++++++++++++
 drivers/common/cpt/cpt_ucode.h       | 43 +++++++++++++++++++++++
 2 files changed, 111 insertions(+)

diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index fe184fe..58a87c3 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -5,8 +5,13 @@
 #ifndef _CPT_REQUEST_MGR_H_
 #define _CPT_REQUEST_MGR_H_
 
+#include "cpt_common.h"
 #include "cpt_mcode_defines.h"
 
+#if CPT_MODEL == CRYPTO_OCTEONTX
+#include "../../crypto/octeontx/otx_cryptodev_hw_access.h"
+#endif
+
 /*
  * This file defines the agreement between the common layer and the individual
  * crypto drivers for OCTEON TX series. Datapath in otx* directory include this
@@ -29,4 +34,67 @@ cpt_get_session_size(void)
 	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
 }
 
+static __rte_always_inline int __hot
+cpt_pmd_crypto_operation(struct cpt_instance *instance,
+		struct rte_crypto_op *op, struct pending_queue *pqueue,
+		uint8_t cpt_driver_id)
+{
+	struct cpt_sess_misc *sess = NULL;
+	struct rte_crypto_sym_op *sym_op = op->sym;
+	void *prep_req = NULL, *mdata = NULL;
+	int ret = 0;
+	uint64_t cpt_op;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	RTE_SET_USED(pqueue);
+
+	if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
+		int sess_len;
+
+		sess_len = cpt_get_session_size();
+
+		sess = rte_calloc(__func__, 1, sess_len, 8);
+		if (!sess)
+			return -ENOMEM;
+
+		sess->ctx_dma_addr =  rte_malloc_virt2iova(sess) +
+			sizeof(struct cpt_sess_misc);
+
+		ret = instance_session_cfg(sym_op->xform, (void *)sess);
+		if (unlikely(ret))
+			return -EINVAL;
+	} else {
+		sess = (struct cpt_sess_misc *)
+		get_sym_session_private_data(sym_op->session,
+		cpt_driver_id);
+	}
+
+	cpt_op = sess->cpt_op;
+
+	mdata = &(cptvf->meta_info);
+
+	if (likely(cpt_op & CPT_OP_CIPHER_MASK))
+		prep_req = fill_fc_params(op, sess, &mdata, &ret);
+
+	if (unlikely(!prep_req)) {
+		CPT_LOG_DP_ERR("prep cryto req : op %p, cpt_op 0x%x "
+			       "ret 0x%x", op, (unsigned int)cpt_op, ret);
+		goto req_fail;
+	}
+
+	if (unlikely(ret)) {
+		if (unlikely(ret == -EAGAIN))
+			goto req_fail;
+		CPT_LOG_DP_ERR("Error enqueing crypto request : error "
+			       "code %d", ret);
+		goto req_fail;
+	}
+
+	return 0;
+
+req_fail:
+	if (mdata)
+		free_op_meta(mdata, cptvf->meta_info.cptvf_meta_pool);
+	return ret;
+}
+
 #endif /* _CPT_REQUEST_MGR_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 9d4d4c8..9085667 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -2117,4 +2117,47 @@ fill_fc_params(struct rte_crypto_op *cop,
 	return prep_req;
 }
 
+static __rte_always_inline int
+instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
+{
+	struct rte_crypto_sym_xform *chain;
+
+	CPT_PMD_INIT_FUNC_TRACE();
+
+	if (cpt_is_algo_supported(xform))
+		goto err;
+
+	chain = xform;
+	while (chain) {
+		switch (chain->type) {
+		case RTE_CRYPTO_SYM_XFORM_AEAD:
+			if (fill_sess_aead(chain, sess))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_CIPHER:
+			if (fill_sess_cipher(chain, sess))
+				goto err;
+			break;
+		case RTE_CRYPTO_SYM_XFORM_AUTH:
+			if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
+				if (fill_sess_gmac(chain, sess))
+					goto err;
+			} else {
+				if (fill_sess_auth(chain, sess))
+					goto err;
+			}
+			break;
+		default:
+			CPT_LOG_DP_ERR("Invalid crypto xform type");
+			break;
+		}
+		chain = chain->next;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v4 16/23] common/cpt: support zuc and snow3g

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding microcode interface for supporting ZUC and SNOW3G.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 596 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 596 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 9085667..5d7743c 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -1226,6 +1226,596 @@ cpt_dec_hmac_prep(uint32_t flags,
 	return 0;
 }
 
+static __rte_always_inline int
+cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
+			uint64_t d_offs,
+			uint64_t d_lens,
+			fc_params_t *params,
+			void *op,
+			void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t mac_len = 0;
+	uint8_t snow3g, j;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset = 0, auth_offset = 0;
+	uint32_t encr_data_len = 0, auth_data_len = 0;
+	int flags, iv_len = 16, m_size;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma, offset_ctrl;
+	uint64_t *offset_vaddr, offset_dma;
+	uint32_t *iv_s, iv[4];
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	mac_len = cpt_ctx->mac_len;
+	snow3g = cpt_ctx->snow3g;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+	opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+			  (0 << 3) | (flags & 0x7));
+
+	if (flags == 0x1) {
+		/*
+		 * Microcode expects offsets in bytes
+		 * TODO: Rounding off
+		 */
+		auth_data_len = AUTH_DLEN(d_lens);
+
+		/* EIA3 or UIA2 */
+		auth_offset = AUTH_OFFSET(d_offs);
+		auth_offset = auth_offset / 8;
+
+		/* consider iv len */
+		auth_offset += iv_len;
+
+		inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
+		outputlen = mac_len;
+
+		offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
+
+	} else {
+		/* EEA3 or UEA2 */
+		/*
+		 * Microcode expects offsets in bytes
+		 * TODO: Rounding off
+		 */
+		encr_data_len = ENCR_DLEN(d_lens);
+
+		encr_offset = ENCR_OFFSET(d_offs);
+		encr_offset = encr_offset / 8;
+		/* consider iv len */
+		encr_offset += iv_len;
+
+		inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
+		outputlen = inputlen;
+
+		/* iv offset is 0 */
+		offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+	}
+
+	/* IV */
+	iv_s = (flags == 0x1) ? params->auth_iv_buf :
+		params->iv_buf;
+
+	if (snow3g) {
+		/*
+		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+		 */
+
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[3 - j];
+	} else {
+		/* ZUC doesn't need a swap */
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[j];
+	}
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+		   (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					    OFF_CTRL_LEN - iv_len);
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			memcpy(iv_d, iv, 16);
+		}
+
+		*offset_vaddr = offset_ctrl;
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint32_t *iv_d;
+
+		/* save space for iv */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+
+		m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+		m_dma += OFF_CTRL_LEN + iv_len;
+		m_size -= OFF_CTRL_LEN + iv_len;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word followed by iv */
+
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 OFF_CTRL_LEN + iv_len);
+
+		/* iv offset is 0 */
+		*offset_vaddr = offset_ctrl;
+
+		iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+		memcpy(iv_d, iv, 16);
+
+		/* input data */
+		size = inputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(gather_comp, i,
+						  params->src_iov,
+						  0, &size, NULL, 0);
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		if (flags == 0x1) {
+			/* IV in SLIST only for EEA3 & UEA2 */
+			iv_len = 0;
+		}
+
+		if (iv_len) {
+			i = fill_sg_comp(scatter_comp, i,
+					 offset_dma + OFF_CTRL_LEN, iv_len);
+		}
+
+		/* Add output data */
+		if (req_flags & VALID_MAC_BUF) {
+			size = outputlen - iv_len - mac_len;
+			if (size) {
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  params->dst_iov, 0,
+							  &size, NULL, 0);
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+
+			/* mac data */
+			if (mac_len) {
+				i = fill_sg_comp_from_buf(scatter_comp, i,
+							  &params->mac_buf);
+			}
+		} else {
+			/* Output including mac */
+			size = outputlen - iv_len;
+			if (size) {
+				i = fill_sg_comp_from_iov(scatter_comp, i,
+							  params->dst_iov, 0,
+							  &size, NULL, 0);
+
+				if (size)
+					return ERR_BAD_INPUT_ARG;
+			}
+		}
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, zs_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
+			uint64_t d_offs,
+			uint64_t d_lens,
+			fc_params_t *params,
+			void *op,
+			void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint8_t snow3g, iv_len = 16;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset;
+	uint32_t encr_data_len;
+	int flags, m_size;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	uint32_t *iv_s, iv[4], j;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	/*
+	 * Microcode expects offsets in bytes
+	 * TODO: Rounding off
+	 */
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	snow3g = cpt_ctx->snow3g;
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+	opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+			  (0 << 3) | (flags & 0x7));
+
+	/* consider iv len */
+	encr_offset += iv_len;
+
+	inputlen = encr_offset +
+		(RTE_ALIGN(encr_data_len, 8) / 8);
+	outputlen = inputlen;
+
+	/* IV */
+	iv_s = params->iv_buf;
+	if (snow3g) {
+		/*
+		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+		 */
+
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[3 - j];
+	} else {
+		/* ZUC doesn't need a swap */
+		for (j = 0; j < 4; j++)
+			iv[j] = iv_s[j];
+	}
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+
+	/*
+	 * In 83XX since we have a limitation of
+	 * IV & Offset control word not part of instruction
+	 * and need to be part of Data Buffer, we check if
+	 * head room is there and then only do the Direct mode processing
+	 */
+	if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+		   (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+		void *dm_vaddr = params->bufs[0].vaddr;
+		uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+		/*
+		 * This flag indicates that there is 24 bytes head room and
+		 * 8 bytes tail room available, so that we get to do
+		 * DIRECT MODE with limitation
+		 */
+
+		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+					    OFF_CTRL_LEN - iv_len);
+		offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+		/* DPTR */
+		req->ist.ei1 = offset_dma;
+		/* RPTR should just exclude offset control word */
+		req->ist.ei2 = dm_dma_addr - iv_len;
+		req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+						    + outputlen - iv_len);
+
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		if (likely(iv_len)) {
+			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+						      + OFF_CTRL_LEN);
+			memcpy(iv_d, iv, 16);
+		}
+
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+	} else {
+		uint32_t i, g_size_bytes, s_size_bytes;
+		uint64_t dptr_dma, rptr_dma;
+		sg_comp_t *gather_comp;
+		sg_comp_t *scatter_comp;
+		uint8_t *in_buffer;
+		uint32_t *iv_d;
+
+		/* save space for offset and iv... */
+		offset_vaddr = m_vaddr;
+		offset_dma = m_dma;
+
+		m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+		m_dma += OFF_CTRL_LEN + iv_len;
+		m_size -= OFF_CTRL_LEN + iv_len;
+
+		opcode.s.major |= CPT_DMA_MODE;
+
+		vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+		/* DPTR has SG list */
+		in_buffer = m_vaddr;
+		dptr_dma = m_dma;
+
+		((uint16_t *)in_buffer)[0] = 0;
+		((uint16_t *)in_buffer)[1] = 0;
+
+		/* TODO Add error check if space will be sufficient */
+		gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+		/*
+		 * Input Gather List
+		 */
+		i = 0;
+
+		/* Offset control word */
+
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+
+		i = fill_sg_comp(gather_comp, i, offset_dma,
+				 OFF_CTRL_LEN + iv_len);
+
+		iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+		memcpy(iv_d, iv, 16);
+
+		/* Add input data */
+		size = inputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(gather_comp, i,
+						  params->src_iov,
+						  0, &size, NULL, 0);
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+		g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		/*
+		 * Output Scatter List
+		 */
+
+		i = 0;
+		scatter_comp =
+			(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+		/* IV */
+		i = fill_sg_comp(scatter_comp, i,
+				 offset_dma + OFF_CTRL_LEN,
+				 iv_len);
+
+		/* Add output data */
+		size = outputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+		s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+		size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+		/* This is DPTR len incase of SG mode */
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+		m_vaddr = (uint8_t *)m_vaddr + size;
+		m_dma += size;
+		m_size -= size;
+
+		/* cpt alternate completion address saved earlier */
+		req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+		*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+		rptr_dma = c_dma - 8;
+
+		req->ist.ei1 = dptr_dma;
+		req->ist.ei2 = rptr_dma;
+	}
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, zs_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
 static __rte_always_inline void *
 cpt_fc_dec_hmac_prep(uint32_t flags,
 		     uint64_t d_offs,
@@ -1243,6 +1833,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,
 	if (likely(fc_type == FC_GEN)) {
 		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
 					fc_params, op, &prep_req);
+	} else if (fc_type == ZUC_SNOW3G) {
+		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
+					      fc_params, op, &prep_req);
 	} else {
 		/*
 		 * For AUTH_ONLY case,
@@ -1273,6 +1866,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	if (likely(fc_type == FC_GEN)) {
 		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
 					fc_params, op, &prep_req);
+	} else if (fc_type == ZUC_SNOW3G) {
+		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
+					      fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
-- 
2.7.4

[dpdk-dev] [PATCH v4 17/23] common/cpt: support kasumi

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding microcode interface for supporting kasumi.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_ucode.h | 450 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 450 insertions(+)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 5d7743c..05cf95c 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -1816,6 +1816,450 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
 	return 0;
 }
 
+static __rte_always_inline int
+cpt_kasumi_enc_prep(uint32_t req_flags,
+		    uint64_t d_offs,
+		    uint64_t d_lens,
+		    fc_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen = 0;
+	struct cpt_ctx *cpt_ctx;
+	uint32_t mac_len = 0;
+	uint8_t i = 0;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset, auth_offset;
+	uint32_t encr_data_len, auth_data_len;
+	int flags, m_size;
+	uint8_t *iv_s, *iv_d, iv_len = 8;
+	uint8_t dir = 0;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	auth_offset = AUTH_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+	auth_data_len = AUTH_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	mac_len = cpt_ctx->mac_len;
+
+	if (flags == 0x0)
+		iv_s = params->iv_buf;
+	else
+		iv_s = params->auth_iv_buf;
+
+	dir = iv_s[8] & 0x1;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
+
+	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
+	opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
+			  (dir << 4) | (0 << 3) | (flags & 0x7));
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+	vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+	/* consider iv len */
+	if (flags == 0x0) {
+		encr_offset += iv_len;
+		auth_offset += iv_len;
+	}
+
+	/* save space for offset ctrl and iv */
+	offset_vaddr = m_vaddr;
+	offset_dma = m_dma;
+
+	m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+	m_dma += OFF_CTRL_LEN + iv_len;
+	m_size -= OFF_CTRL_LEN + iv_len;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input Gather List
+	 */
+	i = 0;
+
+	/* Offset control word followed by iv */
+
+	if (flags == 0x0) {
+		inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
+		outputlen = inputlen;
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+	} else {
+		inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
+		outputlen = mac_len;
+		/* iv offset is 0 */
+		*offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
+	}
+
+	i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
+
+	/* IV */
+	iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;
+	memcpy(iv_d, iv_s, iv_len);
+
+	/* input data */
+	size = inputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i,
+					  params->src_iov, 0,
+					  &size, NULL, 0);
+
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	if (flags == 0x1) {
+		/* IV in SLIST only for F8 */
+		iv_len = 0;
+	}
+
+	/* IV */
+	if (iv_len) {
+		i = fill_sg_comp(scatter_comp, i,
+				 offset_dma + OFF_CTRL_LEN,
+				 iv_len);
+	}
+
+	/* Add output data */
+	if (req_flags & VALID_MAC_BUF) {
+		size = outputlen - iv_len - mac_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+
+		/* mac data */
+		if (mac_len) {
+			i = fill_sg_comp_from_buf(scatter_comp, i,
+						  &params->mac_buf);
+		}
+	} else {
+		/* Output including mac */
+		size = outputlen - iv_len;
+		if (size) {
+			i = fill_sg_comp_from_iov(scatter_comp, i,
+						  params->dst_iov, 0,
+						  &size, NULL, 0);
+
+			if (size)
+				return ERR_BAD_INPUT_ARG;
+		}
+	}
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, k_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline int
+cpt_kasumi_dec_prep(uint64_t d_offs,
+		    uint64_t d_lens,
+		    fc_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	uint32_t size;
+	int32_t inputlen = 0, outputlen;
+	struct cpt_ctx *cpt_ctx;
+	uint8_t i = 0, iv_len = 8;
+	struct cpt_request_info *req;
+	buf_ptr_t *buf_p;
+	uint32_t encr_offset;
+	uint32_t encr_data_len;
+	int flags, m_size;
+	uint8_t dir = 0;
+	void *m_vaddr, *c_vaddr;
+	uint64_t m_dma, c_dma;
+	uint64_t *offset_vaddr, offset_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	opcode_info_t opcode;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+
+	buf_p = &params->meta_buf;
+	m_vaddr = buf_p->vaddr;
+	m_dma = buf_p->dma_addr;
+	m_size = buf_p->size;
+
+	encr_offset = ENCR_OFFSET(d_offs) / 8;
+	encr_data_len = ENCR_DLEN(d_lens);
+
+	cpt_ctx = params->ctx_buf.vaddr;
+	flags = cpt_ctx->zsk_flags;
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* Reserve memory for cpt request info */
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
+
+	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
+	opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
+			  (dir << 4) | (0 << 3) | (flags & 0x7));
+
+	/*
+	 * GP op header, lengths are expected in bits.
+	 */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+	vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+	/* consider iv len */
+	encr_offset += iv_len;
+
+	inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);
+	outputlen = inputlen;
+
+	/* save space for offset ctrl & iv */
+	offset_vaddr = m_vaddr;
+	offset_dma = m_dma;
+
+	m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+	m_dma += OFF_CTRL_LEN + iv_len;
+	m_size -= OFF_CTRL_LEN + iv_len;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input Gather List
+	 */
+	i = 0;
+
+	/* Offset control word followed by iv */
+	*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+
+	i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
+
+	/* IV */
+	memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+	       params->iv_buf, iv_len);
+
+	/* Add input data */
+	size = inputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i,
+					  params->src_iov,
+					  0, &size, NULL, 0);
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	/* IV */
+	i = fill_sg_comp(scatter_comp, i,
+			 offset_dma + OFF_CTRL_LEN,
+			 iv_len);
+
+	/* Add output data */
+	size = outputlen - iv_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(scatter_comp, i,
+					  params->dst_iov, 0,
+					  &size, NULL, 0);
+		if (size)
+			return ERR_BAD_INPUT_ARG;
+	}
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+	vq_cmd_w3.s.grp = 0;
+	vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+		offsetof(struct cpt_ctx, k_ctx);
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
 static __rte_always_inline void *
 cpt_fc_dec_hmac_prep(uint32_t flags,
 		     uint64_t d_offs,
@@ -1836,6 +2280,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,
 	} else if (fc_type == ZUC_SNOW3G) {
 		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
 					      fc_params, op, &prep_req);
+	} else if (fc_type == KASUMI) {
+		ret = cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, op,
+					  &prep_req);
 	} else {
 		/*
 		 * For AUTH_ONLY case,
@@ -1869,6 +2316,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	} else if (fc_type == ZUC_SNOW3G) {
 		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
 					      fc_params, op, &prep_req);
+	} else if (fc_type == KASUMI) {
+		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,
+					  fc_params, op, &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
-- 
2.7.4

[dpdk-dev] [PATCH v4 18/23] common/cpt: support hash

[Anoob Joseph]

From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>

Adding microcode interface for supporting verify and authentication

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_mcode_defines.h |   7 +
 drivers/common/cpt/cpt_request_mgr.h   |   2 +
 drivers/common/cpt/cpt_ucode.h         | 415 ++++++++++++++++++++++++++++++++-
 3 files changed, 423 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 263fc47..60be8b3 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -18,6 +18,7 @@
 #define CPT_MAJOR_OP_HMAC	0x35
 #define CPT_MAJOR_OP_ZUC_SNOW3G	0x37
 #define CPT_MAJOR_OP_KASUMI	0x38
+#define CPT_MAJOR_OP_MISC	0x01
 
 #define CPT_BYTE_16		16
 #define CPT_BYTE_24		24
@@ -341,6 +342,12 @@ typedef struct fc_params {
 
 } fc_params_t;
 
+/*
+ * Parameters for digest
+ * generate requests
+ * Only src_iov, op, ctx_buf, mac_buf, prep_req
+ * meta_buf, auth_data_len are used for digest gen.
+ */
 typedef struct fc_params digest_params_t;
 
 /* Cipher Algorithms */
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index 58a87c3..4d21f46 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -74,6 +74,8 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 
 	if (likely(cpt_op & CPT_OP_CIPHER_MASK))
 		prep_req = fill_fc_params(op, sess, &mdata, &ret);
+	else
+		prep_req = fill_digest_params(op, sess, &mdata, &ret);
 
 	if (unlikely(!prep_req)) {
 		CPT_LOG_DP_ERR("prep cryto req : op %p, cpt_op 0x%x "
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 05cf95c..4d892f2 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -4,7 +4,6 @@
 
 #ifndef _CPT_UCODE_H_
 #define _CPT_UCODE_H_
-
 #include <stdbool.h>
 
 #include "cpt_common.h"
@@ -460,6 +459,214 @@ fill_sg_comp_from_iov(sg_comp_t *list,
 }
 
 static __rte_always_inline int
+cpt_digest_gen_prep(uint32_t flags,
+		    uint64_t d_lens,
+		    digest_params_t *params,
+		    void *op,
+		    void **prep_req)
+{
+	struct cpt_request_info *req;
+	uint32_t size, i;
+	int32_t m_size;
+	uint16_t data_len, mac_len, key_len;
+	auth_type_t hash_type;
+	buf_ptr_t *meta_p;
+	struct cpt_ctx *ctx;
+	sg_comp_t *gather_comp;
+	sg_comp_t *scatter_comp;
+	uint8_t *in_buffer;
+	uint32_t g_size_bytes, s_size_bytes;
+	uint64_t dptr_dma, rptr_dma;
+	vq_cmd_word0_t vq_cmd_w0;
+	vq_cmd_word3_t vq_cmd_w3;
+	void *c_vaddr, *m_vaddr;
+	uint64_t c_dma, m_dma;
+	opcode_info_t opcode;
+
+	if (!params || !params->ctx_buf.vaddr)
+		return ERR_BAD_INPUT_ARG;
+
+	ctx = params->ctx_buf.vaddr;
+	meta_p = &params->meta_buf;
+
+	if (!meta_p->vaddr || !meta_p->dma_addr)
+		return ERR_BAD_INPUT_ARG;
+
+	if (meta_p->size < sizeof(struct cpt_request_info))
+		return ERR_BAD_INPUT_ARG;
+
+	m_vaddr = meta_p->vaddr;
+	m_dma = meta_p->dma_addr;
+	m_size = meta_p->size;
+
+	/*
+	 * Save initial space that followed app data for completion code &
+	 * alternate completion code to fall in same cache line as app data
+	 */
+	m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+	m_dma += COMPLETION_CODE_SIZE;
+	size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+		(uint8_t *)m_vaddr;
+	c_vaddr = (uint8_t *)m_vaddr + size;
+	c_dma = m_dma + size;
+	size += sizeof(cpt_res_s_t);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	req = m_vaddr;
+
+	size = sizeof(struct cpt_request_info);
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	hash_type = ctx->hash_type;
+	mac_len = ctx->mac_len;
+	key_len = ctx->auth_key_len;
+	data_len = AUTH_DLEN(d_lens);
+
+	/*GP op header */
+	vq_cmd_w0.u64 = 0;
+	vq_cmd_w0.s.param2 = rte_cpu_to_be_16(((uint16_t)hash_type << 8));
+	if (ctx->hmac) {
+		opcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;
+		vq_cmd_w0.s.param1 = rte_cpu_to_be_16(key_len);
+		vq_cmd_w0.s.dlen =
+			rte_cpu_to_be_16((data_len + ROUNDUP8(key_len)));
+	} else {
+		opcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;
+		vq_cmd_w0.s.param1 = 0;
+		vq_cmd_w0.s.dlen = rte_cpu_to_be_16(data_len);
+	}
+
+	opcode.s.minor = 0;
+
+	/* Null auth only case enters the if */
+	if (unlikely(!hash_type && !ctx->enc_cipher)) {
+		opcode.s.major = CPT_MAJOR_OP_MISC;
+		/* Minor op is passthrough */
+		opcode.s.minor = 0x03;
+		/* Send out completion code only */
+		vq_cmd_w0.s.param2 = 0x1;
+	}
+
+	vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+	dptr_dma = m_dma;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	/* TODO Add error check if space will be sufficient */
+	gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+	/*
+	 * Input gather list
+	 */
+
+	i = 0;
+
+	if (ctx->hmac) {
+		uint64_t k_dma = params->ctx_buf.dma_addr +
+			offsetof(struct cpt_ctx, auth_key);
+		/* Key */
+		i = fill_sg_comp(gather_comp, i, k_dma, ROUNDUP8(key_len));
+	}
+
+	/* input data */
+	size = data_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,
+					  0, &size, NULL, 0);
+		if (size) {
+			CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short"
+					 " by %dB", size);
+			return ERR_BAD_INPUT_ARG;
+		}
+	} else {
+		/*
+		 * Looks like we need to support zero data
+		 * gather ptr in case of hash & hmac
+		 */
+		i++;
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	/*
+	 * Output Gather list
+	 */
+
+	i = 0;
+	scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+	if (flags & VALID_MAC_BUF) {
+		if (params->mac_buf.size < mac_len)
+			return ERR_BAD_INPUT_ARG;
+
+		size = mac_len;
+		i = fill_sg_comp_from_buf_min(scatter_comp, i,
+					      &params->mac_buf, &size);
+	} else {
+		size = mac_len;
+		i = fill_sg_comp_from_iov(scatter_comp, i,
+					  params->src_iov, data_len,
+					  &size, NULL, 0);
+		if (size) {
+			CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short by"
+					 " %dB", size);
+			return ERR_BAD_INPUT_ARG;
+		}
+	}
+
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+	size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len incase of SG mode */
+	vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+	m_vaddr = (uint8_t *)m_vaddr + size;
+	m_dma += size;
+	m_size -= size;
+
+	/* cpt alternate completion address saved earlier */
+	req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+	*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+	rptr_dma = c_dma - 8;
+
+	req->ist.ei1 = dptr_dma;
+	req->ist.ei2 = rptr_dma;
+	/* First 16-bit swap then 64-bit swap */
+	/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+	 * to eliminate all the swapping
+	 */
+	vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+	/* vq command w3 */
+	vq_cmd_w3.u64 = 0;
+
+	/* 16 byte aligned cpt res address */
+	req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+	*req->completion_addr = COMPLETION_CODE_INIT;
+	req->comp_baddr  = c_dma;
+
+	/* Fill microcode part of instruction */
+	req->ist.ei0 = vq_cmd_w0.u64;
+	req->ist.ei3 = vq_cmd_w3.u64;
+
+	req->op = op;
+
+	*prep_req = req;
+	return 0;
+}
+
+static __rte_always_inline int
 cpt_enc_hmac_prep(uint32_t flags,
 		  uint64_t d_offs,
 		  uint64_t d_lens,
@@ -2319,6 +2526,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	} else if (fc_type == KASUMI) {
 		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,
 					  fc_params, op, &prep_req);
+	} else if (fc_type == HASH_HMAC) {
+		ret = cpt_digest_gen_prep(flags, d_lens, fc_params, op,
+					  &prep_req);
 	} else {
 		ret = ERR_EIO;
 	}
@@ -3206,4 +3416,207 @@ instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
 	return -1;
 }
 
+static __rte_always_inline void
+find_kasumif9_direction_and_length(uint8_t *src,
+				   uint32_t counter_num_bytes,
+				   uint32_t *addr_length_in_bits,
+				   uint8_t *addr_direction)
+{
+	uint8_t found = 0;
+	while (!found && counter_num_bytes > 0) {
+		counter_num_bytes--;
+		if (src[counter_num_bytes] == 0x00)
+			continue;
+		if (src[counter_num_bytes] == 0x80) {
+			*addr_direction  =  src[counter_num_bytes - 1] & 0x1;
+			*addr_length_in_bits = counter_num_bytes * 8  - 1;
+			found = 1;
+		} else {
+			int i = 0;
+			uint8_t last_byte = src[counter_num_bytes];
+			for (i = 0; i < 8 && found == 0; i++) {
+				if (last_byte & (1 << i)) {
+					*addr_direction = (last_byte >> (i+1))
+							  & 0x1;
+					if (i != 6)
+						*addr_length_in_bits =
+							counter_num_bytes * 8
+							+ (8 - (i + 2));
+					else
+						*addr_length_in_bits =
+							counter_num_bytes * 8;
+					found = 1;
+					}
+				}
+			}
+	}
+}
+
+/*
+ * This handles all auth only except AES_GMAC
+ */
+static __rte_always_inline void *
+fill_digest_params(struct rte_crypto_op *cop,
+		   struct cpt_sess_misc *sess,
+		   void **mdata_ptr,
+		   int *op_ret)
+{
+	uint32_t space = 0;
+	struct rte_crypto_sym_op *sym_op = cop->sym;
+	void *mdata;
+	phys_addr_t mphys;
+	uint64_t *op;
+	uint32_t auth_range_off;
+	uint32_t flags = 0;
+	uint64_t d_offs = 0, d_lens;
+	void *prep_req = NULL;
+	struct rte_mbuf *m_src, *m_dst;
+	uint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK;
+	uint8_t zsk_flag = sess->zsk_flag;
+	uint16_t mac_len = sess->mac_len;
+	fc_params_t params;
+	char src[SRC_IOV_SIZE];
+	uint8_t iv_buf[16];
+	memset(&params, 0, sizeof(fc_params_t));
+	struct cptvf_meta_info *cpt_m_info =
+				(struct cptvf_meta_info *)(*mdata_ptr);
+
+	m_src = sym_op->m_src;
+
+	/* For just digest lets force mempool alloc */
+	mdata = alloc_op_meta(NULL, &params.meta_buf, cpt_m_info->cptvf_op_mlen,
+			      cpt_m_info->cptvf_meta_pool);
+	if (mdata == NULL) {
+		CPT_LOG_DP_ERR("Error allocating meta buffer for request");
+		*op_ret = -ENOMEM;
+		return NULL;
+	}
+
+	mphys = params.meta_buf.dma_addr;
+
+	op = mdata;
+	op[0] = (uintptr_t)mdata;
+	op[1] = (uintptr_t)cop;
+	op[2] = op[3] = 0; /* Used to indicate auth verify */
+	space += 4 * sizeof(uint64_t);
+
+	auth_range_off = sym_op->auth.data.offset;
+
+	flags = VALID_MAC_BUF;
+	params.src_iov = (void *)src;
+	if (unlikely(zsk_flag)) {
+		/*
+		 * Since for Zuc, Kasumi, Snow3g offsets are in bits
+		 * we will send pass through even for auth only case,
+		 * let MC handle it
+		 */
+		d_offs = auth_range_off;
+		auth_range_off = 0;
+		params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
+					uint8_t *, sess->auth_iv_offset);
+		if (zsk_flag == K_F9) {
+			uint32_t length_in_bits, num_bytes;
+			uint8_t *src, direction = 0;
+			uint32_t counter_num_bytes;
+
+			memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,
+							uint8_t *), 8);
+			/*
+			 * This is kasumi f9, take direction from
+			 * source buffer
+			 */
+			length_in_bits = cop->sym->auth.data.length;
+			num_bytes = (length_in_bits >> 3);
+			counter_num_bytes = num_bytes;
+			src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);
+			find_kasumif9_direction_and_length(src,
+						counter_num_bytes,
+						&length_in_bits,
+						&direction);
+			length_in_bits -= 64;
+			cop->sym->auth.data.offset += 64;
+			d_offs = cop->sym->auth.data.offset;
+			auth_range_off = d_offs / 8;
+			cop->sym->auth.data.length = length_in_bits;
+
+			/* Store it at end of auth iv */
+			iv_buf[8] = direction;
+			params.auth_iv_buf = iv_buf;
+		}
+	}
+
+	d_lens = sym_op->auth.data.length;
+
+	params.ctx_buf.vaddr = SESS_PRIV(sess);
+	params.ctx_buf.dma_addr = sess->ctx_dma_addr;
+
+	if (auth_op == CPT_OP_AUTH_GENERATE) {
+		if (sym_op->auth.digest.data) {
+			/*
+			 * Digest to be generated
+			 * in separate buffer
+			 */
+			params.mac_buf.size =
+				sess->mac_len;
+			params.mac_buf.vaddr =
+				sym_op->auth.digest.data;
+			params.mac_buf.dma_addr =
+				sym_op->auth.digest.phys_addr;
+		} else {
+			uint32_t off = sym_op->auth.data.offset +
+				sym_op->auth.data.length;
+			int32_t dlen, space;
+
+			m_dst = sym_op->m_dst ?
+				sym_op->m_dst : sym_op->m_src;
+			dlen = rte_pktmbuf_pkt_len(m_dst);
+
+			space = off + mac_len - dlen;
+			if (space > 0)
+				if (!rte_pktmbuf_append(m_dst, space)) {
+					CPT_LOG_DP_ERR("Failed to extend "
+						       "mbuf by %uB", space);
+					goto err;
+				}
+
+			params.mac_buf.vaddr =
+				rte_pktmbuf_mtod_offset(m_dst, void *, off);
+			params.mac_buf.dma_addr =
+				rte_pktmbuf_mtophys_offset(m_dst, off);
+			params.mac_buf.size = mac_len;
+		}
+	} else {
+		/* Need space for storing generated mac */
+		params.mac_buf.vaddr = (uint8_t *)mdata + space;
+		params.mac_buf.dma_addr = mphys + space;
+		params.mac_buf.size = mac_len;
+		space += RTE_ALIGN_CEIL(mac_len, 8);
+		op[2] = (uintptr_t)params.mac_buf.vaddr;
+		op[3] = mac_len;
+	}
+
+	params.meta_buf.vaddr = (uint8_t *)mdata + space;
+	params.meta_buf.dma_addr = mphys + space;
+	params.meta_buf.size -= space;
+
+	/* Out of place processing */
+	params.src_iov = (void *)src;
+
+	/*Store SG I/O in the api for reuse */
+	if (prepare_iov_from_pkt(m_src, params.src_iov, auth_range_off)) {
+		CPT_LOG_DP_ERR("Prepare src iov failed");
+		*op_ret = -1;
+		goto err;
+	}
+
+	prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
+					&params, op, op_ret);
+	*mdata_ptr = mdata;
+	return prep_req;
+err:
+	if (unlikely(!prep_req))
+		free_op_meta(mdata, cpt_m_info->cptvf_meta_pool);
+	return NULL;
+}
+
 #endif /*_CPT_UCODE_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v4 19/23] crypto/octeontx: add routines to prepare instructions

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Adding hardware specific routines which prepare cpt instructions.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 56 +++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 2698df6..affbba1 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -7,11 +7,14 @@
 
 #include <stdbool.h>
 
+#include <rte_branch_prediction.h>
 #include <rte_io.h>
 #include <rte_memory.h>
+#include <rte_prefetch.h>
 
 #include "cpt_common.h"
 #include "cpt_hw_types.h"
+#include "cpt_pmd_logs.h"
 
 #define CPT_INTR_POLL_INTERVAL_MS	(50)
 
@@ -184,4 +187,57 @@ otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
 	return vqx_dbell.s.dbell_cnt;
 }
 
+static __rte_always_inline void *
+get_cpt_inst(struct command_queue *cqueue)
+{
+	CPT_LOG_DP_DEBUG("CPT queue idx %u\n", cqueue->idx);
+	return &cqueue->qhead[cqueue->idx * CPT_INST_SIZE];
+}
+
+static __rte_always_inline void
+fill_cpt_inst(struct cpt_instance *instance, void *req)
+{
+	struct command_queue *cqueue;
+	cpt_inst_s_t *cpt_ist_p;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct cpt_request_info *user_req = (struct cpt_request_info *)req;
+	cqueue = &cptvf->cqueue;
+	cpt_ist_p = get_cpt_inst(cqueue);
+	rte_prefetch_non_temporal(cpt_ist_p);
+
+	/* EI0, EI1, EI2, EI3 are already prepared */
+	/* HW W0 */
+	cpt_ist_p->u[0] = 0;
+	/* HW W1 */
+	cpt_ist_p->s8x.res_addr = user_req->comp_baddr;
+	/* HW W2 */
+	cpt_ist_p->u[2] = 0;
+	/* HW W3 */
+	cpt_ist_p->s8x.wq_ptr = 0;
+
+	/* MC EI0 */
+	cpt_ist_p->s8x.ei0 = user_req->ist.ei0;
+	/* MC EI1 */
+	cpt_ist_p->s8x.ei1 = user_req->ist.ei1;
+	/* MC EI2 */
+	cpt_ist_p->s8x.ei2 = user_req->ist.ei2;
+	/* MC EI3 */
+	cpt_ist_p->s8x.ei3 = user_req->ist.ei3;
+}
+
+static __rte_always_inline void
+mark_cpt_inst(struct cpt_instance *instance)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct command_queue *queue = &cptvf->cqueue;
+	if (unlikely(++queue->idx >= DEFAULT_CMD_QCHUNK_SIZE)) {
+		uint32_t cchunk = queue->cchunk;
+		MOD_INC(cchunk, DEFAULT_CMD_QCHUNKS);
+		queue->qhead = queue->chead[cchunk].head;
+		queue->idx = 0;
+		queue->cchunk = cchunk;
+	}
+
+}
+
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v4 20/23] crypto/octeontx: add enqueue burst op

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h                   |  3 ++
 drivers/common/cpt/cpt_request_mgr.h              | 46 ++++++++++++++++++++++-
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 18 +++++++++
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 27 ++++++++++++-
 4 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 7333c13..1823939 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -15,6 +15,9 @@
  */
 #define CRYPTO_OCTEONTX		0x1
 
+/* Default command timeout in seconds */
+#define DEFAULT_COMMAND_TIMEOUT	4
+
 #define CPT_COUNT_THOLD		32
 #define CPT_TIMER_THOLD		0x3F
 
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index 4d21f46..dea89f8 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -5,6 +5,9 @@
 #ifndef _CPT_REQUEST_MGR_H_
 #define _CPT_REQUEST_MGR_H_
 
+#include <rte_branch_prediction.h>
+#include <rte_cycles.h>
+
 #include "cpt_common.h"
 #include "cpt_mcode_defines.h"
 
@@ -34,6 +37,45 @@ cpt_get_session_size(void)
 	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
 }
 
+static __rte_always_inline int32_t __hot
+cpt_enqueue_req(struct cpt_instance *instance, struct pending_queue *pqueue,
+		void *req)
+{
+	struct cpt_request_info *user_req = (struct cpt_request_info *)req;
+	int32_t ret = 0;
+
+	if (unlikely(!req))
+		return 0;
+
+	if (unlikely(pqueue->pending_count >= DEFAULT_CMD_QLEN))
+		return -EAGAIN;
+
+	fill_cpt_inst(instance, req);
+
+	CPT_LOG_DP_DEBUG("req: %p op: %p ", req, user_req->op);
+
+	/* Fill time_out cycles */
+	user_req->time_out = rte_get_timer_cycles() +
+			DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
+	user_req->extra_time = 0;
+
+	/* Default mode of software queue */
+	mark_cpt_inst(instance);
+
+	pqueue->rid_queue[pqueue->enq_tail].rid =
+		(uintptr_t)user_req;
+	/* We will use soft queue length here to limit
+	 * requests
+	 */
+	MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);
+	pqueue->pending_count += 1;
+
+	CPT_LOG_DP_DEBUG("Submitted NB cmd with request: %p "
+			 "op: %p", user_req, user_req->op);
+
+	return ret;
+}
+
 static __rte_always_inline int __hot
 cpt_pmd_crypto_operation(struct cpt_instance *instance,
 		struct rte_crypto_op *op, struct pending_queue *pqueue,
@@ -45,7 +87,6 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 	int ret = 0;
 	uint64_t cpt_op;
 	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
-	RTE_SET_USED(pqueue);
 
 	if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 		int sess_len;
@@ -83,6 +124,9 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 		goto req_fail;
 	}
 
+	/* Enqueue prepared instruction to HW */
+	ret = cpt_enqueue_req(instance, pqueue, prep_req);
+
 	if (unlikely(ret)) {
 		if (unlikely(ret == -EAGAIN))
 			goto req_fail;
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index affbba1..6f4d6e1 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -187,6 +187,15 @@ otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
 	return vqx_dbell.s.dbell_cnt;
 }
 
+static __rte_always_inline void
+otx_cpt_ring_dbell(struct cpt_instance *instance, uint16_t count)
+{
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	/* Memory barrier to flush pending writes */
+	rte_smp_wmb();
+	otx_cpt_write_vq_doorbell(cptvf, count);
+}
+
 static __rte_always_inline void *
 get_cpt_inst(struct command_queue *cqueue)
 {
@@ -237,7 +246,16 @@ mark_cpt_inst(struct cpt_instance *instance)
 		queue->idx = 0;
 		queue->cchunk = cchunk;
 	}
+}
 
+static __rte_always_inline uint8_t
+check_nb_command_id(struct cpt_request_info *user_req,
+		struct cpt_instance *instance)
+{
+	/* Required for dequeue operation. Adding a dummy routine for now */
+	RTE_SET_USED(user_req);
+	RTE_SET_USED(instance);
+	return 0;
 }
 
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 16fad49..4240051 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -341,6 +341,31 @@ otx_cpt_session_clear(struct rte_cryptodev *dev,
 	}
 }
 
+static uint16_t
+otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	struct cpt_instance *instance = (struct cpt_instance *)qptr;
+	uint16_t count = 0;
+	int ret;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct pending_queue *pqueue = &cptvf->pqueue;
+
+	count = DEFAULT_CMD_QLEN - pqueue->pending_count;
+	if (nb_ops > count)
+		nb_ops = count;
+
+	count = 0;
+	while (likely(count < nb_ops)) {
+		ret = cpt_pmd_crypto_operation(instance, ops[count], pqueue,
+						otx_cryptodev_driver_id);
+		if (unlikely(ret))
+			break;
+		count++;
+	}
+	otx_cpt_ring_dbell(instance, count);
+	return count;
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -432,7 +457,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 
 	c_dev->dev_ops = &cptvf_ops;
 
-	c_dev->enqueue_burst = NULL;
+	c_dev->enqueue_burst = otx_cpt_pkt_enqueue;
 	c_dev->dequeue_burst = NULL;
 
 	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
-- 
2.7.4

[dpdk-dev] [PATCH v4 21/23] crypto/octeontx: add dequeue burst op

[Anoob Joseph]

From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 drivers/common/cpt/cpt_common.h                   |  2 +
 drivers/common/cpt/cpt_mcode_defines.h            | 15 +++++
 drivers/common/cpt/cpt_request_mgr.h              | 39 +++++++++++++
 drivers/common/cpt/cpt_ucode.h                    | 26 +++++++++
 drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 69 +++++++++++++++++++++--
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 47 ++++++++++++++-
 6 files changed, 192 insertions(+), 6 deletions(-)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 1823939..8461cd6 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -15,6 +15,8 @@
  */
 #define CRYPTO_OCTEONTX		0x1
 
+#define TIME_IN_RESET_COUNT	5
+
 /* Default command timeout in seconds */
 #define DEFAULT_COMMAND_TIMEOUT	4
 
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 60be8b3..becc14f 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -175,6 +175,21 @@ typedef enum {
 	ERR_ENODEV,
 } mc_error_code_t;
 
+/**
+ * Enumeration cpt_comp_e
+ *
+ * CPT Completion Enumeration
+ * Enumerates the values of CPT_RES_S[COMPCODE].
+ */
+typedef enum {
+	CPT_8X_COMP_E_NOTDONE    = (0x00),
+	CPT_8X_COMP_E_GOOD       = (0x01),
+	CPT_8X_COMP_E_FAULT      = (0x02),
+	CPT_8X_COMP_E_SWERR      = (0x03),
+	CPT_8X_COMP_E_HWERR      = (0x04),
+	CPT_8X_COMP_E_LAST_ENTRY = (0xFF)
+} cpt_comp_e_t;
+
 typedef struct sglist_comp {
 	union {
 		uint64_t len;
diff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h
index dea89f8..4463cfb 100644
--- a/drivers/common/cpt/cpt_request_mgr.h
+++ b/drivers/common/cpt/cpt_request_mgr.h
@@ -143,4 +143,43 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,
 	return ret;
 }
 
+static __rte_always_inline int32_t __hot
+cpt_dequeue_burst(struct cpt_instance *instance, uint16_t cnt,
+		  void *resp[], uint8_t cc[], struct pending_queue *pqueue)
+{
+	struct cpt_request_info *user_req;
+	struct rid *rid_e;
+	int i, count, pcount;
+	uint8_t ret;
+
+	pcount = pqueue->pending_count;
+	count = (cnt > pcount) ? pcount : cnt;
+
+	for (i = 0; i < count; i++) {
+		rid_e = &pqueue->rid_queue[pqueue->deq_head];
+		user_req = (struct cpt_request_info *)(rid_e->rid);
+
+		if (likely((i+1) < count))
+			rte_prefetch_non_temporal((void *)rid_e[1].rid);
+
+		ret = check_nb_command_id(user_req, instance);
+
+		if (unlikely(ret == ERR_REQ_PENDING)) {
+			/* Stop checking for completions */
+			break;
+		}
+
+		/* Return completion code and op handle */
+		cc[i] = (uint8_t)ret;
+		resp[i] = user_req->op;
+		CPT_LOG_DP_DEBUG("Request %p Op %p completed with code %d",
+			   user_req, user_req->op, ret);
+
+		MOD_INC(pqueue->deq_head, DEFAULT_CMD_QLEN);
+		pqueue->pending_count -= 1;
+	}
+
+	return i;
+}
+
 #endif /* _CPT_REQUEST_MGR_H_ */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 4d892f2..c5a9f34 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -3373,6 +3373,32 @@ fill_fc_params(struct rte_crypto_op *cop,
 	return prep_req;
 }
 
+static __rte_always_inline void
+compl_auth_verify(struct rte_crypto_op *op,
+		      uint8_t *gen_mac,
+		      uint64_t mac_len)
+{
+	uint8_t *mac;
+	struct rte_crypto_sym_op *sym_op = op->sym;
+
+	if (sym_op->auth.digest.data)
+		mac = sym_op->auth.digest.data;
+	else
+		mac = rte_pktmbuf_mtod_offset(sym_op->m_src,
+					      uint8_t *,
+					      sym_op->auth.data.length +
+					      sym_op->auth.data.offset);
+	if (!mac) {
+		op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		return;
+	}
+
+	if (memcmp(mac, gen_mac, mac_len))
+		op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+	else
+		op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+}
+
 static __rte_always_inline int
 instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
 {
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 6f4d6e1..82b15ee 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -1,19 +1,20 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2018 Cavium, Inc
  */
-
 #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
 #define _OTX_CRYPTODEV_HW_ACCESS_H_
 
 #include <stdbool.h>
 
 #include <rte_branch_prediction.h>
+#include <rte_cycles.h>
 #include <rte_io.h>
 #include <rte_memory.h>
 #include <rte_prefetch.h>
 
 #include "cpt_common.h"
 #include "cpt_hw_types.h"
+#include "cpt_mcode_defines.h"
 #include "cpt_pmd_logs.h"
 
 #define CPT_INTR_POLL_INTERVAL_MS	(50)
@@ -252,10 +253,68 @@ static __rte_always_inline uint8_t
 check_nb_command_id(struct cpt_request_info *user_req,
 		struct cpt_instance *instance)
 {
-	/* Required for dequeue operation. Adding a dummy routine for now */
-	RTE_SET_USED(user_req);
-	RTE_SET_USED(instance);
-	return 0;
+	uint8_t ret = ERR_REQ_PENDING;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	volatile cpt_res_s_t *cptres;
+
+	cptres = (volatile cpt_res_s_t *)user_req->completion_addr;
+
+	if (unlikely(cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE)) {
+		/*
+		 * Wait for some time for this command to get completed
+		 * before timing out
+		 */
+		if (rte_get_timer_cycles() < user_req->time_out)
+			return ret;
+		/*
+		 * TODO: See if alternate caddr can be used to not loop
+		 * longer than needed.
+		 */
+		if ((cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE) &&
+		    (user_req->extra_time < TIME_IN_RESET_COUNT)) {
+			user_req->extra_time++;
+			return ret;
+		}
+
+		if (cptres->s8x.compcode != CPT_8X_COMP_E_NOTDONE)
+			goto complete;
+
+		ret = ERR_REQ_TIMEOUT;
+		CPT_LOG_DP_ERR("Request %p timedout", user_req);
+		otx_cpt_poll_misc(cptvf);
+		goto exit;
+	}
+
+complete:
+	if (likely(cptres->s8x.compcode == CPT_8X_COMP_E_GOOD)) {
+		ret = 0; /* success */
+		if (unlikely((uint8_t)*user_req->alternate_caddr)) {
+			ret = (uint8_t)*user_req->alternate_caddr;
+			CPT_LOG_DP_ERR("Request %p : failed with microcode"
+				" error, MC completion code : 0x%x", user_req,
+				ret);
+		}
+		CPT_LOG_DP_DEBUG("MC status %.8x\n",
+			   *((volatile uint32_t *)user_req->alternate_caddr));
+		CPT_LOG_DP_DEBUG("HW status %.8x\n",
+			   *((volatile uint32_t *)user_req->completion_addr));
+	} else if ((cptres->s8x.compcode == CPT_8X_COMP_E_SWERR) ||
+		   (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT)) {
+		ret = (uint8_t)*user_req->alternate_caddr;
+		if (!ret)
+			ret = ERR_BAD_ALT_CCODE;
+		CPT_LOG_DP_DEBUG("Request %p : failed with %s : err code :%x",
+			   user_req,
+			   (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT) ?
+			   "DMA Fault" : "Software error", ret);
+	} else {
+		CPT_LOG_DP_ERR("Request %p : unexpected completion code %d",
+			   user_req, cptres->s8x.compcode);
+		ret = (uint8_t)*user_req->alternate_caddr;
+	}
+
+exit:
+	return ret;
 }
 
 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 4240051..23f9659 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -366,6 +366,51 @@ otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 	return count;
 }
 
+static uint16_t
+otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+	struct cpt_instance *instance = (struct cpt_instance *)qptr;
+	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
+	struct pending_queue *pqueue = &cptvf->pqueue;
+	uint16_t nb_completed, i = 0;
+	uint8_t compcode[nb_ops];
+
+	nb_completed = cpt_dequeue_burst(instance, nb_ops,
+					 (void **)ops, compcode, pqueue);
+	while (likely(i < nb_completed)) {
+		struct rte_crypto_op *cop;
+		void *metabuf;
+		uintptr_t *rsp;
+		uint8_t status;
+
+		rsp = (void *)ops[i];
+		status = compcode[i];
+		if (likely((i + 1) < nb_completed))
+			rte_prefetch0(ops[i+1]);
+		metabuf = (void *)rsp[0];
+		cop = (void *)rsp[1];
+
+		ops[i] = cop;
+
+		if (likely(status == 0)) {
+			if (likely(!rsp[2]))
+				cop->status =
+					RTE_CRYPTO_OP_STATUS_SUCCESS;
+			else
+				compl_auth_verify(cop, (uint8_t *)rsp[2],
+						  rsp[3]);
+		} else if (status == ERR_GC_ICV_MISCOMPARE) {
+			/*auth data mismatch */
+			cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+		} else {
+			cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+		}
+		free_op_meta(metabuf, cptvf->meta_info.cptvf_meta_pool);
+		i++;
+	}
+	return nb_completed;
+}
+
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
 	.dev_configure = otx_cpt_dev_config,
@@ -458,7 +503,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)
 	c_dev->dev_ops = &cptvf_ops;
 
 	c_dev->enqueue_burst = otx_cpt_pkt_enqueue;
-	c_dev->dequeue_burst = NULL;
+	c_dev->dequeue_burst = otx_cpt_pkt_dequeue;
 
 	c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
 			RTE_CRYPTODEV_FF_HW_ACCELERATED |
-- 
2.7.4

[dpdk-dev] [PATCH v4 22/23] test/crypto: add OCTEON TX unit tests

[Anoob Joseph]

From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>

Adding validation tests for OCTEON TX crypto device.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 test/test/meson.build                        |   1 +
 test/test/test_cryptodev.c                   | 318 +++++++++++++++++++++++++++
 test/test/test_cryptodev.h                   |   1 +
 test/test/test_cryptodev_aes_test_vectors.h  | 114 ++++++----
 test/test/test_cryptodev_blockcipher.c       |   9 +-
 test/test/test_cryptodev_blockcipher.h       |   1 +
 test/test/test_cryptodev_des_test_vectors.h  |  12 +-
 test/test/test_cryptodev_hash_test_vectors.h |  78 ++++---
 8 files changed, 465 insertions(+), 69 deletions(-)

diff --git a/test/test/meson.build b/test/test/meson.build
index bacb5b1..31e4732 100644
--- a/test/test/meson.build
+++ b/test/test/meson.build
@@ -145,6 +145,7 @@ test_names = [
 	'cryptodev_sw_mvsam_autotest',
 	'cryptodev_dpaa2_sec_autotest',
 	'cryptodev_dpaa_sec_autotest',
+	'cryptodev_octeontx_autotest',
 	'cycles_autotest',
 	'debug_autotest',
 	'devargs_autotest',
diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
index c63662d..e9f2c8f 100644
--- a/test/test/test_cryptodev.c
+++ b/test/test/test_cryptodev.c
@@ -2142,6 +2142,96 @@ test_3DES_cipheronly_mrvl_all(void)
 	return TEST_SUCCESS;
 }
 
+static int
+test_AES_chain_octeontx_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_AES_CHAIN_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_AES_cipheronly_octeontx_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_AES_CIPHERONLY_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_3DES_chain_octeontx_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_3DES_CHAIN_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_3DES_cipheronly_octeontx_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_3DES_CIPHERONLY_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
+static int
+test_authonly_octeontx_all(void)
+{
+	struct crypto_testsuite_params *ts_params = &testsuite_params;
+	int status;
+
+	status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+		ts_params->op_mpool, ts_params->session_mpool,
+		ts_params->valid_devs[0],
+		rte_cryptodev_driver_id_get(
+		RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)),
+		BLKCIPHER_AUTHONLY_TYPE);
+
+	TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+	return TEST_SUCCESS;
+}
+
 /* ***** SNOW 3G Tests ***** */
 static int
 create_wireless_algo_hash_session(uint8_t dev_id,
@@ -9951,6 +10041,218 @@ static struct unit_test_suite cryptodev_ccp_testsuite  = {
 	}
 };
 
+static struct unit_test_suite cryptodev_octeontx_testsuite  = {
+	.suite_name = "Crypto Device OCTEONTX Unit Test Suite",
+	.setup = testsuite_setup,
+	.teardown = testsuite_teardown,
+	.unit_test_cases = {
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_chain_octeontx_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_cipheronly_octeontx_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_3DES_chain_octeontx_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_3DES_cipheronly_octeontx_all),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_authonly_octeontx_all),
+
+		/** AES GCM Authenticated Encryption */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_6),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_encryption_test_case_7),
+
+		/** AES GCM Authenticated Decryption */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_6),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GCM_authenticated_decryption_test_case_7),
+		/** AES GMAC Authentication */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_verify_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_verify_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_AES_GMAC_authentication_verify_test_case_3),
+
+		/** SNOW 3G encrypt only (UEA2) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_5),
+
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_1_oop),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_1_oop),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_encryption_test_case_1_oop_sgl),
+
+		/** SNOW 3G decrypt only (UEA2) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_decryption_test_case_5),
+
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_generate_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_generate_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_generate_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_verify_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_verify_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_snow3g_hash_verify_test_case_3),
+
+		/** ZUC encrypt only (EEA3) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_hash_generate_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_zuc_encryption_test_case_6_sgl),
+
+		/** KASUMI encrypt only (UEA1) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1_sgl),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1_oop_sgl),
+		/** KASUMI decrypt only (UEA1) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_5),
+
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_encryption_test_case_1_oop),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_decryption_test_case_1_oop),
+
+		/** KASUMI hash only (UIA1) */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_5),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_generate_test_case_6),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_1),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_2),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_3),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_4),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_kasumi_hash_verify_test_case_5),
+
+		/** NULL tests */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_cipher_only_operation),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_auth_only_operation),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_cipher_auth_operation),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			test_null_auth_cipher_operation),
+
+		/** Negative tests */
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_HMAC_SHA1_fail_data_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_HMAC_SHA1_fail_tag_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_AES128_GMAC_fail_data_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			authentication_verify_AES128_GMAC_fail_tag_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			auth_decryption_AES128CBC_HMAC_SHA1_fail_data_corrupt),
+		TEST_CASE_ST(ut_setup, ut_teardown,
+			auth_decryption_AES128CBC_HMAC_SHA1_fail_tag_corrupt),
+		TEST_CASES_END() /**< NULL terminate unit test array */
+	}
+};
+
 static int
 test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
 {
@@ -10203,6 +10505,21 @@ test_cryptodev_ccp(void)
 	return unit_test_suite_runner(&cryptodev_ccp_testsuite);
 }
 
+static int
+test_cryptodev_octeontx(void)
+{
+	gbl_driver_id =	rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+	if (gbl_driver_id == -1) {
+		RTE_LOG(ERR, USER1, "OCTEONTX PMD must be loaded. Check if "
+				"CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO is "
+				"enabled in config file to run this "
+				"testsuite.\n");
+		return TEST_FAILED;
+	}
+	return unit_test_suite_runner(&cryptodev_octeontx_testsuite);
+}
+
 REGISTER_TEST_COMMAND(cryptodev_qat_autotest, test_cryptodev_qat);
 REGISTER_TEST_COMMAND(cryptodev_aesni_mb_autotest, test_cryptodev_aesni_mb);
 REGISTER_TEST_COMMAND(cryptodev_openssl_autotest, test_cryptodev_openssl);
@@ -10217,3 +10534,4 @@ REGISTER_TEST_COMMAND(cryptodev_dpaa2_sec_autotest, test_cryptodev_dpaa2_sec);
 REGISTER_TEST_COMMAND(cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec);
 REGISTER_TEST_COMMAND(cryptodev_ccp_autotest, test_cryptodev_ccp);
 REGISTER_TEST_COMMAND(cryptodev_virtio_autotest, test_cryptodev_virtio);
+REGISTER_TEST_COMMAND(cryptodev_octeontx_autotest, test_cryptodev_octeontx);
diff --git a/test/test/test_cryptodev.h b/test/test/test_cryptodev.h
index 1bd44dc..f2d41ae 100644
--- a/test/test/test_cryptodev.h
+++ b/test/test/test_cryptodev.h
@@ -64,6 +64,7 @@
 #define CRYPTODEV_NAME_MVSAM_PMD		crypto_mvsam
 #define CRYPTODEV_NAME_CCP_PMD		crypto_ccp
 #define CRYPTODEV_NAME_VIRTIO_PMD	crypto_virtio
+#define CRYPTODEV_NAME_OCTEONTX_SYM_PMD	crypto_octeontx
 
 /**
  * Write (spread) data from buffer to mbuf data
diff --git a/test/test/test_cryptodev_aes_test_vectors.h b/test/test/test_cryptodev_aes_test_vectors.h
index 1c4dc66..5db46f4 100644
--- a/test/test/test_cryptodev_aes_test_vectors.h
+++ b/test/test/test_cryptodev_aes_test_vectors.h
@@ -1254,7 +1254,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1262,7 +1263,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_13,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENC_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1276,7 +1278,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1291,7 +1294,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1300,7 +1304,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SG,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1308,7 +1313,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_13,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest",
@@ -1322,7 +1328,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest "
@@ -1330,7 +1337,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_12,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENC_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1345,7 +1353,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1353,7 +1362,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.test_data = &aes_test_data_12,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest",
@@ -1366,7 +1376,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1376,7 +1387,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SESSIONLESS,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1387,7 +1399,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_FEATURE_SG |
 			BLOCKCIPHER_TEST_FEATURE_OOP,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
-			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL
+			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest "
@@ -1401,7 +1414,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest "
@@ -1415,7 +1429,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER
+			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC XCBC Encryption Digest",
@@ -1443,7 +1458,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1455,7 +1471,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA224 Encryption Digest",
@@ -1467,7 +1484,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
@@ -1480,7 +1498,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
@@ -1517,7 +1536,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SESSIONLESS,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr =
@@ -1528,7 +1548,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SESSIONLESS,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
 			BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 };
 
@@ -1545,7 +1566,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CBC Decryption",
@@ -1559,7 +1581,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Encryption",
@@ -1572,7 +1595,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Encryption Scater gather",
@@ -1582,7 +1606,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_FEATURE_OOP,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Decryption",
@@ -1595,7 +1620,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CBC Decryption Scatter Gather",
@@ -1603,7 +1629,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_DECRYPT,
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SG,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CBC Encryption",
@@ -1617,7 +1644,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CBC Decryption",
@@ -1631,7 +1659,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO
+			BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CBC OOP Encryption",
@@ -1668,7 +1697,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CTR Decryption",
@@ -1681,7 +1711,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CTR Encryption",
@@ -1693,7 +1724,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CTR Decryption",
@@ -1705,7 +1737,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CTR Encryption",
@@ -1718,7 +1751,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CTR Decryption",
@@ -1731,25 +1765,29 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-128-CTR Encryption (12-byte IV)",
 		.test_data = &aes_test_data_1_IV_12_bytes,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
-		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-192-CTR Encryption (12-byte IV)",
 		.test_data = &aes_test_data_2_IV_12_bytes,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
-		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "AES-256-CTR Encryption (12-byte IV)",
 		.test_data = &aes_test_data_3_IV_12_bytes,
 		.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
-		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	}
 };
 
diff --git a/test/test/test_cryptodev_blockcipher.c b/test/test/test_cryptodev_blockcipher.c
index f2701f8..6df1321 100644
--- a/test/test/test_cryptodev_blockcipher.c
+++ b/test/test/test_cryptodev_blockcipher.c
@@ -72,6 +72,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
 			RTE_STR(CRYPTODEV_NAME_MVSAM_PMD));
 	int virtio_pmd = rte_cryptodev_driver_id_get(
 			RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
+	int octeontx_pmd = rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
 
 	int nb_segs = 1;
 
@@ -114,7 +116,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
 			driver_id == armv8_pmd ||
 			driver_id == mrvl_pmd ||
 			driver_id == ccp_pmd ||
-			driver_id == virtio_pmd) { /* Fall through */
+			driver_id == virtio_pmd ||
+			driver_id == octeontx_pmd) { /* Fall through */
 		digest_len = tdata->digest.len;
 	} else if (driver_id == aesni_mb_pmd ||
 			driver_id == scheduler_pmd) {
@@ -640,6 +643,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
 			RTE_STR(CRYPTODEV_NAME_MVSAM_PMD));
 	int virtio_pmd = rte_cryptodev_driver_id_get(
 			RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
+	int octeontx_pmd = rte_cryptodev_driver_id_get(
+			RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
 
 	switch (test_type) {
 	case BLKCIPHER_AES_CHAIN_TYPE:
@@ -706,6 +711,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
 		target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MVSAM;
 	else if (driver_id == virtio_pmd)
 		target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO;
+	else if (driver_id == octeontx_pmd)
+		target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX;
 	else
 		TEST_ASSERT(0, "Unrecognized cryptodev type");
 
diff --git a/test/test/test_cryptodev_blockcipher.h b/test/test/test_cryptodev_blockcipher.h
index 6f7c892..57e678f 100644
--- a/test/test/test_cryptodev_blockcipher.h
+++ b/test/test/test_cryptodev_blockcipher.h
@@ -29,6 +29,7 @@
 #define BLOCKCIPHER_TEST_TARGET_PMD_MVSAM	0x0080 /* Marvell flag */
 #define BLOCKCIPHER_TEST_TARGET_PMD_CCP		0x0040 /* CCP flag */
 #define BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO	0x0200 /* VIRTIO flag */
+#define BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX	0x0100 /* OCTEON TX flag */
 
 #define BLOCKCIPHER_TEST_OP_CIPHER	(BLOCKCIPHER_TEST_OP_ENCRYPT | \
 					BLOCKCIPHER_TEST_OP_DECRYPT)
diff --git a/test/test/test_cryptodev_des_test_vectors.h b/test/test/test_cryptodev_des_test_vectors.h
index 1033456..0789881 100644
--- a/test/test/test_cryptodev_des_test_vectors.h
+++ b/test/test/test_cryptodev_des_test_vectors.h
@@ -1104,7 +1104,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-192-CBC HMAC-SHA1 Decryption Digest Verify",
@@ -1115,7 +1116,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-			BLOCKCIPHER_TEST_TARGET_PMD_CCP
+			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-192-CBC SHA1 Encryption Digest",
@@ -1276,7 +1278,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MB
+			BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-192-CBC Decryption",
@@ -1288,7 +1291,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MB
+			BLOCKCIPHER_TEST_TARGET_PMD_MB |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "3DES-128-CTR Encryption",
diff --git a/test/test/test_cryptodev_hash_test_vectors.h b/test/test/test_cryptodev_hash_test_vectors.h
index cf86dbb..c430409 100644
--- a/test/test/test_cryptodev_hash_test_vectors.h
+++ b/test/test/test_cryptodev_hash_test_vectors.h
@@ -373,14 +373,16 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.test_data = &md5_test_vector,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "MD5 Digest Verify",
 		.test_data = &md5_test_vector,
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-MD5 Digest",
@@ -392,7 +394,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-MD5 Digest Verify",
@@ -404,7 +407,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA1 Digest",
@@ -412,7 +416,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA1 Digest Verify",
@@ -420,7 +425,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest",
@@ -433,7 +439,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest Scatter Gather",
@@ -441,7 +448,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SG,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest Verify",
@@ -454,7 +462,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA1 Digest Verify Scatter Gather",
@@ -462,7 +471,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.feature_mask = BLOCKCIPHER_TEST_FEATURE_SG,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
-			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC
+			    BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA224 Digest",
@@ -470,7 +480,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA224 Digest Verify",
@@ -478,7 +489,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA224 Digest",
@@ -490,7 +502,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_QAT
+			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA224 Digest Verify",
@@ -502,7 +515,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_QAT
+			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA256 Digest",
@@ -510,7 +524,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA256 Digest Verify",
@@ -518,7 +533,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA256 Digest",
@@ -531,7 +547,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA256 Digest Verify",
@@ -544,7 +561,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA384 Digest",
@@ -552,7 +570,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA384 Digest Verify",
@@ -560,7 +579,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA384 Digest",
@@ -573,7 +593,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA384 Digest Verify",
@@ -586,7 +607,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA512 Digest",
@@ -594,7 +616,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "SHA512 Digest Verify",
@@ -602,7 +625,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 		.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
 		.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
 			    BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			    BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			    BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA512 Digest",
@@ -615,7 +639,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "HMAC-SHA512 Digest Verify",
@@ -628,7 +653,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
 			BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
 			BLOCKCIPHER_TEST_TARGET_PMD_QAT |
 			BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM
+			BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
+			BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
 	},
 	{
 		.test_descr = "CMAC Digest 12B",
-- 
2.7.4

[dpdk-dev] [PATCH v4 23/23] doc: add documentation for OCTEON TX crypto

[Anoob Joseph]

Adding feature file and guide for OCTEON TX crypto PMD

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
 MAINTAINERS                                 |   2 +
 doc/guides/cryptodevs/features/octeontx.ini |  62 ++++++++++++++
 doc/guides/cryptodevs/index.rst             |   1 +
 doc/guides/cryptodevs/octeontx.rst          | 128 ++++++++++++++++++++++++++++
 4 files changed, 193 insertions(+)
 create mode 100644 doc/guides/cryptodevs/features/octeontx.ini
 create mode 100644 doc/guides/cryptodevs/octeontx.rst

diff --git a/MAINTAINERS b/MAINTAINERS
index 001bae9..afa0e56 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -783,6 +783,8 @@ Cavium OCTEON TX crypto
 M: Anoob Joseph <anoob.joseph@caviumnetworks.com>
 F: drivers/common/cpt/
 F: drivers/crypto/octeontx/
+F: doc/guides/cryptodevs/octeontx.rst
+F: doc/guides/cryptodevs/features/octeontx.ini
 
 Crypto Scheduler
 M: Fan Zhang <roy.fan.zhang@intel.com>
diff --git a/doc/guides/cryptodevs/features/octeontx.ini b/doc/guides/cryptodevs/features/octeontx.ini
new file mode 100644
index 0000000..307ab88
--- /dev/null
+++ b/doc/guides/cryptodevs/features/octeontx.ini
@@ -0,0 +1,62 @@
+;
+; Supported features of the 'octeontx' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto       = Y
+Sym operation chaining = Y
+HW Accelerated         = Y
+In Place SGL           = Y
+OOP SGL In LB  Out     = Y
+OOP SGL In SGL Out     = Y
+
+;
+; Supported crypto algorithms of 'octeontx' crypto driver.
+;
+[Cipher]
+NULL           = Y
+3DES CBC       = Y
+3DES ECB       = Y
+AES CBC (128)  = Y
+AES CBC (192)  = Y
+AES CBC (256)  = Y
+AES CTR (128)  = Y
+AES CTR (192)  = Y
+AES CTR (256)  = Y
+AES XTS (128)  = Y
+AES XTS (256)  = Y
+DES CBC        = Y
+KASUMI F8      = Y
+SNOW3G UEA2    = Y
+ZUC EEA3       = Y
+
+;
+; Supported authentication algorithms of 'octeontx' crypto driver.
+;
+[Auth]
+NULL         = Y
+AES GMAC     = Y
+KASUMI F9    = Y
+MD5          = Y
+MD5 HMAC     = Y
+SHA1         = Y
+SHA1 HMAC    = Y
+SHA224       = Y
+SHA224 HMAC  = Y
+SHA256       = Y
+SHA256 HMAC  = Y
+SHA384       = Y
+SHA384 HMAC  = Y
+SHA512       = Y
+SHA512 HMAC  = Y
+SNOW3G UIA2  = Y
+ZUC EIA3     = Y
+
+;
+; Supported AEAD algorithms of 'octeontx' crypto driver.
+;
+[AEAD]
+AES GCM (128) = Y
+AES GCM (192) = Y
+AES GCM (256) = Y
diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst
index e9928a4..bd15885 100644
--- a/doc/guides/cryptodevs/index.rst
+++ b/doc/guides/cryptodevs/index.rst
@@ -17,6 +17,7 @@ Crypto Device Drivers
     dpaa2_sec
     dpaa_sec
     kasumi
+    octeontx
     openssl
     mvsam
     null
diff --git a/doc/guides/cryptodevs/octeontx.rst b/doc/guides/cryptodevs/octeontx.rst
new file mode 100644
index 0000000..1054446
--- /dev/null
+++ b/doc/guides/cryptodevs/octeontx.rst
@@ -0,0 +1,128 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+   Copyright(c) 2018 Cavium, Inc
+
+Cavium OCTEON TX Crypto Poll Mode Driver
+========================================
+
+The OCTEON TX crypto poll mode driver provides support for offloading
+cryptographic operations to cryptographic accelerator units on
+**OCTEON TX** :sup:`®` family of processors (CN8XXX). The OCTEON TX crypto
+poll mode driver enqueues the crypto request to this accelerator and dequeues
+the response once the operation is completed.
+
+Supported Algorithms
+--------------------
+
+Cipher Algorithms
+~~~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_CIPHER_NULL``
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_3DES_ECB``
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_CTR``
+* ``RTE_CRYPTO_CIPHER_AES_XTS``
+* ``RTE_CRYPTO_CIPHER_DES_CBC``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
+
+Hash Algorithms
+~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_AES_GMAC``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
+* ``RTE_CRYPTO_AUTH_MD5``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA1``
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+
+AEAD Algorithms
+~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_AEAD_AES_GCM``
+
+Compilation
+-----------
+
+The **OCTEON TX** :sup:`®` board must be running the linux kernel based on
+sdk-6.2.0 patch 3. In this, the OCTEON TX crypto PF driver is already built in.
+
+For compiling the OCTEON TX crypto poll mode driver, please check if the
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO setting is set to `y` in
+config/common_base file.
+
+* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y``
+
+The following are the steps to compile the OCTEON TX crypto poll mode driver:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        make config T=arm64-thunderx-linuxapp-gcc
+        make
+
+The example applications can be compiled using the following:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        export RTE_SDK=$PWD
+        export RTE_TARGET=build
+        cd examples/<application>
+        make
+
+Execution
+---------
+
+The number of crypto VFs to be enabled can be controlled by setting sysfs entry,
+`sriov_numvfs`, for the corresponding PF driver.
+
+.. code-block:: console
+
+        echo <num_vfs> > /sys/bus/pci/devices/<dev_bus_id>/sriov_numvfs
+
+The device bus ID, `dev_bus_id`, to be used in the above step can be found out
+by using dpdk-devbind.py script. The OCTEON TX crypto PF device need to be
+identified and the corresponding device number can be used to tune various PF
+properties.
+
+
+Once the required VFs are enabled, dpdk-devbind.py script can be used to
+identify the VFs. To be accessible from DPDK, VFs need to be bound to vfio-pci
+driver:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        ./usertools/dpdk-devbind.py -u <vf device no>
+        ./usertools/dpdk-devbind.py -b vfio-pci <vf device no>
+
+Appropriate huge page need to be setup in order to run the DPDK example
+applications.
+
+.. code-block:: console
+
+        echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
+        mkdir /mnt/huge
+        mount -t hugetlbfs nodev /mnt/huge
+
+Example applications can now be executed with crypto operations offloaded to
+OCTEON TX crypto PMD.
+
+.. code-block:: console
+
+        ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
+        "(1,0,0),(0,0,0)" -f ep1.cfg
+
-- 
2.7.4

Re: [dpdk-dev] [PATCH v4 00/23] Adding Cavium's OCTEON TX crypto PMD

[Thomas Monjalon]

09/10/2018 11:07, Anoob Joseph:
> v4:
> * Marged the following v3 patches (Akhil & Thomas),
>     - 01/32 & 02/32
>     - 03/32, 04/32 & 05/32
>     - 06/32 & 07/32
>     - 13/32 & 14/32
>     - 15/32 & 16/32
>     - 17/32 & 18/32
>     - 27/32 & 28/32
>     - 29/32 & 30/32
> * Replaced usages OCTEONTX with OCTEON TX (Thomas & Jerin)
> * Fixed commit logs in v3 02/32 (Thomas)
> * Replaced references to cpt with octeontx in v3 31/32 (Akhil)
> * Fixed commit logs in v3 31/32 (Akhil)

I guess it is ready to be pushed in the tree now.
Thanks

Re: [dpdk-dev] [PATCH v4 00/23] Adding Cavium's OCTEON TX crypto PMD

[Akhil Goyal]

On 10/9/2018 3:26 PM, Thomas Monjalon wrote:
> 09/10/2018 11:07, Anoob Joseph:
>> v4:
>> * Marged the following v3 patches (Akhil & Thomas),
>>      - 01/32 & 02/32
>>      - 03/32, 04/32 & 05/32
>>      - 06/32 & 07/32
>>      - 13/32 & 14/32
>>      - 15/32 & 16/32
>>      - 17/32 & 18/32
>>      - 27/32 & 28/32
>>      - 29/32 & 30/32
>> * Replaced usages OCTEONTX with OCTEON TX (Thomas & Jerin)
>> * Fixed commit logs in v3 02/32 (Thomas)
>> * Replaced references to cpt with octeontx in v3 31/32 (Akhil)
>> * Fixed commit logs in v3 31/32 (Akhil)
> I guess it is ready to be pushed in the tree now.
> Thanks
>
Applied to dpdk-next-crypto

Thanks
>