From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0082.outbound.protection.outlook.com [104.47.32.82]) by dpdk.org (Postfix) with ESMTP id 1669D1BE0 for ; Tue, 4 Sep 2018 06:03:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zffidsJdIglPqNa0czCLcYnIblhmYIkdVSexEPuh2j4=; b=bF2lKk7hCSYs2f/NN3ElaVDaKGcPyM9gT0PHkpx1PZMcAC74iUzZ7HtVZhCO6HuIdSkXJUvKWJujTPd9fBSc+/YavTfH/3CZrnvtLlIU7RpUxj8ZFme/0ifQDHunTEKTf3NRNvXeSPag4BQ4jRgYVRhpw3vGw5hPA2ZGB1uKbfo= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Anoob.Joseph@cavium.com; Received: from ajoseph83.caveonetworks.com.com (115.113.156.2) by BYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1101.15; Tue, 4 Sep 2018 04:02:12 +0000 From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon Cc: Anoob Joseph , Jerin Jacob , Narayana Prasad , dev@dpdk.org, Ankur Dwivedi , Murthy NSSR , Nithin Dabilpuram , Ragothaman Jayaraman , Srisivasubramanian S , Tejasree Kondoj Date: Tue, 4 Sep 2018 09:28:54 +0530 Message-Id: <1536033560-21541-8-git-send-email-ajoseph@caviumnetworks.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com> References: <1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com> <1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [115.113.156.2] X-ClientProxiedBy: BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::33) To BYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 15eeb741-99d3-43a0-2201-08d6121b33d8 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BYAPR07MB4902; X-Microsoft-Exchange-Diagnostics: 1; BYAPR07MB4902; 3:jpIda1rDnD+VPTKXaExDBNl+jZY8vOp30gK4gt4h3DhFuZ4s+gyiWDgkJwFxoHXZ5Y3jxMhsivG7j3JdUP/AUAqdVYArQfw9DDLKnU05fATZsj1PRbWetEiCi17ro8vcdoxiRCQVFWW9HKon9XuraoyONdMhlu/c51VsDRdER5epYj/EAR7BvKKDXT6d3aT50JgUwMdpH993grM+/UYH6vZXmDiStipbyeX9c2nkSTepruQg5r6sTqofspZoUpPs; 25:fbTXQuxFzKPnu4cQebYPWxQnFN9QW0QuCyTYJpKHOxmYySWZ89gPLPIM1fpYS9/vXnp1+JkCsi6l3vJGRxHZUyUpKTdsGRgBg8Ye1pCE6hh3oOKUOV/TqvFam76WR4cSVBWebdinZ+/+w9lbnt22ighnurIMGym4LZldjbQ9kFT71HZIX8ctnLvovwdWHTFrXYQveQtwofkMTAcignpXOgapTrxASsyKZZ7iiWKTpbqJVnKDPK8bXAjq6ypv3h1SpuYrHTXhyms79IogJvVEON0u/HIAuBOsziTy/MLdcjXbkwIsPVD0q+LDptsaPVEbutP0enxbKL/WgG6AjROclg==; 31:Ldn+bgJPhUzRYDZgrmvMCQOetQ8lrYWlLWldPpWLW5d5be0FRG0UjL5pIZ/nL0GDlMoLrQmfKHBEok5+genlM6BzCp4yIWDzEVB3CANKSjKBJ57mZAftG2dmDwAOBLXOw6bkxnuqrp3ZxrDpr8ZkGhveQHsq1khD3VuJ31fEZmi36P1CvzoNy79fliyJTlhr09gXA+w2xjL+Jwkn6T8lXGGDTJbAek0PppGD0fYisXM= X-MS-TrafficTypeDiagnostic: BYAPR07MB4902: X-Microsoft-Exchange-Diagnostics: 1; BYAPR07MB4902; 20:y2pPpCKADicnxC7Hkt2YTsarjDe2yTrNqQiBlRHWJotlID9Ka99kX//HPEPEBLlkvWfSwnyp+FY/aDluCx5fImUfFEMwqFFOBAGYrIKtjbLe12tSP+LKgB+R09h/g/mPY4ypla097uLPplQH4+mb/yUfZY2iMzxlEGHnMO854/Q0a8Pi6H+g+Te7IRT/ocUDdawyhN8VDgDAWUwacocqv+BIcPXAs4XOK/6xZTB5MyCtf1RxTEEye3GUC09rueVieKP4KgvMsBIL5ukqpQfTwe8xbhOfx5dLqH3EVkppbCQfbm7gUmVO9Gy3gudhH3Z+/+WUfNLyN9mx7+RzvqlEGHrh2gA0GRfotecqGvUYPBcYX+ZqljQqLLrk0iWp7BGdBSOaP1JB+pBgKpxzauAVGWNe8vJeSgbXXDxrVBFu0X1bTjBy3WkD1OVMaAv43p6oKGseRJ4qDTjkg5L2uN/TeN4qzlYt30VC441rmxprZwhUzgAQCdMfVPgT1vmoXP/5oC1mhpf+Wiq7NGrThBshinWkjZOhgkJzUl9QP2pPVdHM095bXp4mS1giwcAn927gFk00UXSshQ/uaVZhUFk2l3ZvYZBzUdltRwUBU62oSJs=; 4:yA/m5duexsTKrsmwg7fp1a75dMeylibDvfjptx3OppnfkhftdrktiGXUFvg0ZI6PDBrEY2T/ExCi+b4K+/DFNN4eZQTLUGVluJ16XWXN2cP0C/XM41pgI33rf+9wd0WT3nrNE0xUNUc+JGMuZlIE9ozYJGwtw/TmzX6cSdinF+/dOMwqjNfDypeJzwasWc5TGyPO2fzEhLphs1FOfeE+ESvLRX46d59zYX1kBYBLObjFe0f7RD+TUWrc+Ca4pnMTxtwonkSSXRJHGqEnSS8CgQ== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(10201501046)(93006095)(3231311)(944501410)(52105095)(3002001)(149027)(150027)(6041310)(20161123562045)(20161123564045)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699016); SRVR:BYAPR07MB4902; BCL:0; PCL:0; RULEID:; SRVR:BYAPR07MB4902; X-Forefront-PRVS: 0785459C39 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(366004)(396003)(136003)(346002)(376002)(39860400002)(199004)(189003)(26005)(51416003)(52116002)(76176011)(81166006)(305945005)(81156014)(7736002)(105586002)(316002)(6506007)(106356001)(6512007)(8936002)(446003)(54906003)(25786009)(6666003)(68736007)(50226002)(110136005)(53936002)(16586007)(42882007)(386003)(5660300001)(2906002)(72206003)(50466002)(6486002)(36756003)(6116002)(107886003)(2616005)(14444005)(186003)(3846002)(478600001)(66066001)(476003)(8676002)(47776003)(486006)(956004)(48376002)(11346002)(4326008)(97736004)(16526019); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR07MB4902; H:ajoseph83.caveonetworks.com.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BYAPR07MB4902; 23:HCrthRwlEY3h6LJbtpHl24tO2Nw2/dk9kNWtvXHYN?= =?us-ascii?Q?mJrVndjGuMwrG85GXjiwBZJLV/oEU6JGMIQd84AvptA1eouJAkq3Gg4VafQ2?= =?us-ascii?Q?4ON06onyGAvNi8IZTHieJWUeOC8+w+13JxEBsFvoNjsQjHv1cH0aSyDAzfZ+?= =?us-ascii?Q?sp4kxT5jjP+Ro6NDBulaxnsHx/7szfplFSuvIkk2RHzENlfdyskx6JrFJ+rh?= =?us-ascii?Q?BxRHlJu3cRCjvnp3IpvG3sttfAom5vHhVV20OtnztkkuPRR/10uR9OagPeTP?= =?us-ascii?Q?zv/bZSlo2+0k78yKtuZQvOBPagxfYgj/SBj4Aaui3hO7538keie2mim57ANf?= =?us-ascii?Q?pNXvtohlAcgA6ehIUbjdcIwlU/Hp4Tkikva0oIVDHLCmIqZsgGxufXRqWyZT?= =?us-ascii?Q?qvC8j38ur6rjtNlrBi5XuZ2iIzAdvy6fN0IcBMEvg61nqqa08tIPdib+YERG?= =?us-ascii?Q?5NLQGeHNQ5sv5TXEpfEwNb1LTK/g7jnOQ0lRgMKS9mxy6moc3VXrYvXbsmN8?= =?us-ascii?Q?yIYK1/HGVJzhUAVgGSI8DsFk4I0s+jI5K2vl/RzFYHOn1kBpEzFP2Zc6SQjc?= =?us-ascii?Q?PSAkcj6tY0UgbCoH+F9h+krT6eMjiLmWzNNbJiyDrTd0Fs3kLSTbb252NtUO?= =?us-ascii?Q?zVjS6iWGG6cscqM7dF+cUyUVTTW5eno9g/yAr5kVUVASsdeJjdv9XhmcdFks?= =?us-ascii?Q?2dv5KgLGWx2sOVpSL0EvQp6TffiaW6QnHWyAcWxbOX2yx+88Gn6ozkcYMIv8?= =?us-ascii?Q?nKBH+ite6PIqcOg7ttF4jwKxKUluWEaoJAGSMZaLvU2YzBJxEu9oKMIySv/k?= =?us-ascii?Q?qH0cee8GNASOzCcffh/7/LKv690hE7Mss2/zo8dM2938VWQ116+2BVYVGguF?= =?us-ascii?Q?hJSetX4tBfSuyalfMF40UfYYuRwqNPZap0dSaz626N800LhX/roD3uEtTPqA?= =?us-ascii?Q?5uXA4PuwXTJI3rlQ6Ixs53CRegYkU1BB2uWhP+o3fGpb5ukPgxnnEmXLAOqm?= =?us-ascii?Q?sc7Hn/F1lLd3FiwRlT+X/LGvC2Oe4V9u9WW/47hyNJHWhVZQU1bl6hhYXQwP?= =?us-ascii?Q?RCrwGGx1ZvurmY4Gi4nJCnb7H3rJHpJ4+pVsx45LhHe3XoFt4P/6kMAwq7RC?= =?us-ascii?Q?CniQ+leWV9pittesid1is2SY6V2NMbMriyPGX+tf5pcUj+YpF2RpVz4BMP21?= =?us-ascii?Q?Ycpa+9jKBUQATd9X6Zv+Gk7djJ+0Y6/fzKCs0/Rcq9yDmEntrwwU+MYQFq19?= =?us-ascii?Q?6YKZxBnyN2WHbeQNLE=3D?= X-Microsoft-Antispam-Message-Info: wOlxmI/EEjgRvHZ3sq4cMlaFXdIRdlxgeTeJvWyfsC/PhXSY78Wy/bjk0btxHf8PMxCZ9vqVm9DDCLYeQB3XHSKeZ/Kj4+m2sYtipoEhpNYchpx7CqRKNjQ4kyEzp2HuzjPfWj/1Dm6SphSie0vqjo/0Erdx/cNqPFbBY8OEkONuyz4Nhwv1PoEm+PR+4/mTv2ckxAzl/aiN2FbfIVdtYygWUgHRy2WEWHt77XkayraL3qEx6Guc4YpuM3I/plO5KJ3E3ZhYPQkobP1Zd8Y3MHTjT7u7c9eZuHwtypJg3lWXhgZodGW5xJSmTdbZbw93lWGvkw4I6XUoK/G2aeXr1633dNdOs2o9XJswG12GNK4= X-Microsoft-Exchange-Diagnostics: 1; BYAPR07MB4902; 6:uRai0f9YOHoHgkmZo7IQns8BVHqnyfIOdIEinRZKZyLkwRon1HkLULdjlJIbZVocsLxPLxeoW5PcUZKx1kv7UiVS3I4a90hAdIosYt4W5fOkC4GYCES8LR5Jn4sx62GVkVwKekQhpEqGZxmIDzyeSotB51gp5M/WzK6nmWNLQ3t0sfDoBu74aIE2/AU3Xti6wRjv5UgQ9zKOkUakdvC86ICuAbWtXxBCN4ljuLxDTX4AKRoAsG+NMuEfvw0arEy0gA2ELg1zU60E+4g95NdugBo6j3vaMjEGXCRInToXzn2Uol7GxFFgmvhCG6ueFb6TusiDVoBQM9C4JGASMyQigOg/qE8pUuMry49gfQl8NPp3tRFVLZMgoJDo2Bct4TJZrq2ZNdrQdYpcweqqXT5S8oAy/admeTFcW271fZGZLGm6XyBOPeYtqBrld5x8+PSf/fN9Ie43xQSDjlUuezYspg==; 5:zfoBDHihcCb5RzRR1L+64/bQ6XuYes3D9n5BKLN/izUr9nDj4w4qAz8V9oZb3x9TWzfuT0qvsTNvjKg+NryTkxLLUgvJbG6WNyU31JbgmKE2oCNoojDxHdy17pcZnCjnGx1JMn0XGvajEBrLutHfN/BhAh86pNwQ4RoKzm794Bs=; 7:yW/6vZ6mWQb9vKrJy1meWaouSw1ALNRwNRQVQNNAiAiiGJTTtI+6AKv+ROlZwOfQdhKfF2Joag3pavhXIOCBUVAo5IUHg+c7llrl/R41IuAA8HjFL1L1x+FPPIrFKNLEX+cXzhe8HXwpqOLkiKj3N6fGEovTy+z8n3X62lgu6O44sJ767mg0GNrAWPGsz3qgShPallgx8OsWkwa2c3PjmK8mMFIE3nvwGBzSjGYD7fnZVcFAPcxgF7k+iHXrsqEf SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2018 04:02:12.4441 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15eeb741-99d3-43a0-2201-08d6121b33d8 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB4902 Subject: [dpdk-dev] [PATCH v2 07/33] common/cpt: add hardware register defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Sep 2018 04:03:07 -0000 From: Anoob Joseph Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian S Signed-off-by: Tejasree Kondoj --- drivers/common/cpt/cpt_hw_types.h | 517 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 517 insertions(+) create mode 100644 drivers/common/cpt/cpt_hw_types.h diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h new file mode 100644 index 0000000..8cd1bf8 --- /dev/null +++ b/drivers/common/cpt/cpt_hw_types.h @@ -0,0 +1,517 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Cavium, Inc + */ + +#ifndef _CPT_HW_TYPES_H_ +#define _CPT_HW_TYPES_H_ + +#include + +/* + * This file defines HRM specific structs. + * + */ + +#define CPT_VF_INTR_MBOX_MASK (1<<0) +#define CPT_VF_INTR_DOVF_MASK (1<<1) +#define CPT_VF_INTR_IRDE_MASK (1<<2) +#define CPT_VF_INTR_NWRP_MASK (1<<3) +#define CPT_VF_INTR_SWERR_MASK (1<<4) +#define CPT_VF_INTR_HWERR_MASK (1<<5) +#define CPT_VF_INTR_FAULT_MASK (1<<6) + +/* + * CPT_INST_S software command definitions + * Words EI (0-3) + */ +typedef union { + uint64_t u64; + struct { + uint16_t opcode; + uint16_t param1; + uint16_t param2; + uint16_t dlen; + } s; +} vq_cmd_word0_t; + +typedef union { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t grp : 3; + uint64_t cptr : 61; +#else + uint64_t cptr : 61; + uint64_t grp : 3; +#endif + } s; +} vq_cmd_word3_t; + +typedef struct cpt_vq_command { + vq_cmd_word0_t cmd; + uint64_t dptr; + uint64_t rptr; + vq_cmd_word3_t cptr; +} cpt_vq_cmd_t; + +/** + * Structure cpt_inst_s + * + * CPT Instruction Structure + * This structure specifies the instruction layout. + * Instructions are stored in memory as little-endian unless + * CPT()_PF_Q()_CTL[INST_BE] is set. + */ +typedef union cpt_inst_s { + uint64_t u[8]; + struct cpt_inst_s_8s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_17_63 : 47; + uint64_t doneint : 1; + /*< [ 16: 16] Done interrupt. + * 0 = No interrupts related to this instruction. + * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE] + * will be incremented, and based on the rules described + * there an interrupt may occur. + */ + uint64_t reserved_0_15 : 16; +#else /* Word 0 - Little Endian */ + uint64_t reserved_0_15 : 16; + uint64_t doneint : 1; + uint64_t reserved_17_63 : 47; +#endif /* Word 0 - End */ +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */ + uint64_t res_addr : 64; + /*< [127: 64] Result IOVA. + * If nonzero, specifies where to write CPT_RES_S. + * If zero, no result structure will be written. + * Address must be 16-byte aligned. + + * Bits <63:49> are ignored by hardware; software should + *use a sign-extended bit <48> for forward compatibility. + */ +#else /* Word 1 - Little Endian */ + uint64_t res_addr : 64; +#endif /* Word 1 - End */ +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */ + uint64_t reserved_172_191 : 20; + uint64_t grp : 10; + /*< [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to + * use when CPT submits work to SSO. + * For the SSO to not discard the add-work request, FPA_PF_MAP() + * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid. + */ + uint64_t tt : 2; + /*< [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use + * when CPT submits work to SSO. + */ + uint64_t tag : 32; + /*< [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when + * CPT submits work to SSO. + */ +#else /* Word 2 - Little Endian */ + uint64_t tag : 32; + uint64_t tt : 2; + uint64_t grp : 10; + uint64_t reserved_172_191 : 20; +#endif /* Word 2 - End */ +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */ + uint64_t wq_ptr : 64; + /**< [255:192] If [WQ_PTR] is nonzero, it is a pointer to a + * work-queue entry that CPT submits work to SSO after all + * context, output data, and result write operations are + * visible to other CNXXXX units and the cores. + * Bits <2:0> must be zero. + * Bits <63:49> are ignored by hardware; software should use a + * sign-extended bit <48> for forward compatibility. + * Internal:Bits <63:49>, <2:0> are ignored by hardware, + * treated as always 0x0. + **/ +#else /* Word 3 - Little Endian */ + uint64_t wq_ptr : 64; +#endif /* Word 3 - End */ +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 4 - Big Endian */ + union { + uint64_t ei0 : 64; + /**< [319:256] Engine instruction word 0. Passed to the + * AE/SE. + **/ + vq_cmd_word0_t vq_cmd_w0; + }; +#else /* Word 4 - Little Endian */ + union { + uint64_t ei0 : 64; + vq_cmd_word0_t vq_cmd_w0; + }; +#endif /* Word 4 - End */ +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 5 - Big Endian */ + union { + uint64_t ei1 : 64; + /**< [383:320] Engine instruction word 1. Passed to the + * AE/SE. + **/ + uint64_t dptr; + }; +#else /* Word 5 - Little Endian */ + union { + uint64_t ei1 : 64; + uint64_t dptr; + }; +#endif /* Word 5 - End */ +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 6 - Big Endian */ + union { + uint64_t ei2 : 64; + /**< [447:384] Engine instruction word 2. Passed to the + * AE/SE. + **/ + uint64_t rptr; + }; +#else /* Word 6 - Little Endian */ + union { + uint64_t ei2 : 64; + uint64_t rptr; + }; +#endif /* Word 6 - End */ +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 7 - Big Endian */ + union { + uint64_t ei3 : 64; + /**< [511:448] Engine instruction word 3. Passed to the + * AE/SE. + **/ + vq_cmd_word3_t vq_cmd_w3; + }; +#else /* Word 7 - Little Endian */ + union { + uint64_t ei3 : 64; + vq_cmd_word3_t vq_cmd_w3; + }; +#endif /* Word 7 - End */ + } s8x; +} cpt_inst_s_t; + +/** + * Structure cpt_res_s + * + * CPT Result Structure + * The CPT coprocessor writes the result structure after it completes a + * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each + * instruction completion produces exactly one result structure. + * + * This structure is stored in memory as little-endian unless + * CPT()_PF_Q()_CTL[INST_BE] is set. + */ +typedef union cpt_res_s { + uint64_t u[2]; + struct cpt_res_s_8s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_17_63 : 47; + uint64_t doneint : 1; + /**< [ 16: 16] Done interrupt. This bit is copied from the + * corresponding instruction's CPT_INST_S[DONEINT]. + **/ + uint64_t reserved_8_15 : 8; + uint64_t compcode : 8; + /**< [ 7: 0] Indicates completion/error status of the CPT + * coprocessor for the associated instruction, as enumerated by + * CPT_COMP_E. Core software may write the memory location + * containing [COMPCODE] to 0x0 before ringing the doorbell, and + * then poll for completion by checking for a nonzero value. + + Once the core observes a nonzero [COMPCODE] value in this case, + the CPT coprocessor will have also completed L2/DRAM write + operations. + */ +#else /* Word 0 - Little Endian */ + uint64_t compcode : 8; + uint64_t reserved_8_15 : 8; + uint64_t doneint : 1; + uint64_t reserved_17_63 : 47; +#endif /* Word 0 - End */ +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */ + uint64_t reserved_64_127 : 64; +#else /* Word 1 - Little Endian */ + uint64_t reserved_64_127 : 64; +#endif /* Word 1 - End */ + } s8x; +} cpt_res_s_t; + +/** + * Register (NCB) cpt#_vq#_ctl + * + * CPT VF Queue Control Registers + * This register configures queues. This register should be changed (other than + * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]). + */ +typedef union { + uint64_t u; + struct cptx_vqx_ctl_s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_1_63 : 63; + uint64_t ena : 1; + /**< [ 0: 0](R/W/H) Enables the logical instruction queue. + * See also CPT()_PF_Q()_CTL[CONT_ERR] and + * CPT()_VQ()_INPROG[INFLIGHT]. + * 1 = Queue is enabled. + * 0 = Queue is disabled. + **/ +#else /* Word 0 - Little Endian */ + uint64_t ena : 1; + uint64_t reserved_1_63 : 63; +#endif /* Word 0 - End */ + } s; +} cptx_vqx_ctl_t; + +/** + * Register (NCB) cpt#_vq#_done + * + * CPT Queue Done Count Registers + * These registers contain the per-queue instruction done count. + */ +typedef union { + uint64_t u; + struct cptx_vqx_done_s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_20_63 : 44; + uint64_t done : 20; + /**< [ 19: 0](R/W/H) Done count. When CPT_INST_S[DONEINT] set + * and that instruction completes,CPT()_VQ()_DONE[DONE] is + * incremented when the instruction finishes. Write to this + * field are for diagnostic use only; instead software writes + * CPT()_VQ()_DONE_ACK with the number of decrements for this + * field. + + Interrupts are sent as follows: + + * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending, + * the interrupt coalescing timer is held to zero, and an + * interrupt is not sent. + + * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt + * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE + * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ() + * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough + * results have arrived, then the interrupt is sent. Otherwise, + * it is not sent due to coalescing. + + * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is + * written but this is not typical), the interrupt coalescing + * timer restarts. Note after decrementing this interrupt + * equation is recomputed, for example if CPT()_VQ()_DONE[DONE] + * >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is + * zero, the interrupt will be resent immediately. (This covers + * the race case between software acknowledging an interrupt and + * a result returning.) + + * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not + * sent, but the counting described above still occurs. + + Since CPT instructions complete out-of-order, if software is + using completion interrupts the suggested scheme is to request a + DONEINT on each request, and when an interrupt arrives perform a + "greedy" scan for completions; even if a later command is + acknowledged first this will not result in missing a completion. + + Software is responsible for making sure [DONE] does not overflow + ; for example by insuring there are not more than 2^20-1 + instructions in flight that may request interrupts. + */ +#else /* Word 0 - Little Endian */ + uint64_t done : 20; + uint64_t reserved_20_63 : 44; +#endif /* Word 0 - End */ + } s; +} cptx_vqx_done_t; + +/** + * Register (NCB) cpt#_vq#_done_ack + * + * CPT Queue Done Count Ack Registers + * This register is written by software to acknowledge interrupts. + */ +typedef union { + uint64_t u; + struct cptx_vqx_done_ack_s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_20_63 : 44; + uint64_t done_ack : 20; + /**< [ 19: 0](R/W/H) Number of decrements to CPT()_VQ()_DONE + * [DONE]. Reads CPT()_VQ()_DONE[DONE]. + + Written by software to acknowledge interrupts. If CPT()_VQ()_ + DONE[DONE] is still nonzero the interrupt will be re-sent if the + conditions described in CPT()_VQ()_DONE[DONE] are satisfied. + */ +#else /* Word 0 - Little Endian */ + uint64_t done_ack : 20; + uint64_t reserved_20_63 : 44; +#endif /* Word 0 - End */ + } s; +} cptx_vqx_done_ack_t; + +/** + * Register (NCB) cpt#_vq#_done_wait + * + * CPT Queue Done Interrupt Coalescing Wait Registers + * Specifies the per queue interrupt coalescing settings. + */ +typedef union { + uint64_t u; + struct cptx_vqx_done_wait_s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_48_63 : 16; + uint64_t time_wait : 16; + /**< [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] = + * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When + * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing + * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is + * disabled. + **/ + uint64_t reserved_20_31 : 12; + uint64_t num_wait : 20; + /**< [ 19: 0](R/W) Number of messages hold-off. When + * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing + * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as + * 0x1. + **/ +#else /* Word 0 - Little Endian */ + uint64_t num_wait : 20; + uint64_t reserved_20_31 : 12; + uint64_t time_wait : 16; + uint64_t reserved_48_63 : 16; +#endif /* Word 0 - End */ + } s; +} cptx_vqx_done_wait_t; + +/** + * Register (NCB) cpt#_vq#_doorbell + * + * CPT Queue Doorbell Registers + * Doorbells for the CPT instruction queues. + */ +typedef union { + uint64_t u; + struct cptx_vqx_doorbell_s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_20_63 : 44; + uint64_t dbell_cnt : 20; + /**< [ 19: 0](R/W/H) Number of instruction queue 64-bit words + * to add to the CPT instruction doorbell count. Readback value + * is the the current number of pending doorbell requests. + + If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set. + + To reset the count back to zero, write one to clear + CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value of + 2^20 minus the read [DBELL_CNT], then write one to + CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and + CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF]. + + Must be a multiple of 8. All CPT instructions are 8 words and + require a doorbell count of multiple of 8. + */ +#else /* Word 0 - Little Endian */ + uint64_t dbell_cnt : 20; + uint64_t reserved_20_63 : 44; +#endif /* Word 0 - End */ + } s; +} cptx_vqx_doorbell_t; + +/** + * Register (NCB) cpt#_vq#_inprog + * + * CPT Queue In Progress Count Registers + * These registers contain the per-queue instruction in flight registers. + */ +typedef union { + uint64_t u; + struct cptx_vqx_inprog_s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_8_63 : 56; + uint64_t inflight : 8; + /**< [ 7: 0](RO/H) Inflight count. Counts the number of + * instructions for the VF for which CPT is fetching, executing + * or responding to instructions. However this does not include + * any interrupts that are awaiting software handling + * (CPT()_VQ()_DONE[DONE] != 0x0). + + A queue may not be reconfigured until: + 1. CPT()_VQ()_CTL[ENA] is cleared by software. + 2. [INFLIGHT] is polled until equals to zero. + */ +#else /* Word 0 - Little Endian */ + uint64_t inflight : 8; + uint64_t reserved_8_63 : 56; +#endif /* Word 0 - End */ + } s; +} cptx_vqx_inprog_t; + +/** + * Register (NCB) cpt#_vq#_misc_int + * + * CPT Queue Misc Interrupt Register + * These registers contain the per-queue miscellaneous interrupts. + */ +typedef union { + uint64_t u; + struct cptx_vqx_misc_int_s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_7_63 : 57; + uint64_t fault : 1; + /**< [ 6: 6](R/W1C/H) Translation fault detected. */ + uint64_t hwerr : 1; + /**< [ 5: 5](R/W1C/H) Hardware error from engines. */ + uint64_t swerr : 1; + /**< [ 4: 4](R/W1C/H) Software error from engines. */ + uint64_t nwrp : 1; + /**< [ 3: 3](R/W1C/H) NCB result write response error. */ + uint64_t irde : 1; + /**< [ 2: 2](R/W1C/H) Instruction NCB read response error. */ + uint64_t dovf : 1; + /**< [ 1: 1](R/W1C/H) Doorbell overflow. */ + uint64_t mbox : 1; + /**< [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when + * CPT()_VF()_PF_MBOX(0) is written. + **/ +#else /* Word 0 - Little Endian */ + uint64_t mbox : 1; + uint64_t dovf : 1; + uint64_t irde : 1; + uint64_t nwrp : 1; + uint64_t swerr : 1; + uint64_t hwerr : 1; + uint64_t fault : 1; + uint64_t reserved_5_63 : 59; +#endif /* Word 0 - End */ + } s; +} cptx_vqx_misc_int_t; + +/** + * Register (NCB) cpt#_vq#_saddr + * + * CPT Queue Starting Buffer Address Registers + * These registers set the instruction buffer starting address. + */ +typedef union { + uint64_t u; + struct cptx_vqx_saddr_s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_49_63 : 15; + uint64_t ptr : 43; + /**< [ 48: 6](R/W/H) Instruction buffer IOVA <48:6> + * (64-byte aligned). When written, it is the initial buffer + * starting address; when read, it is the next read pointer to + * be requested from L2C. The PTR field is overwritten with the + * next pointer each time that the command buffer segment is + * exhausted. New commands will then be read from the newly + * specified command buffer pointer. + **/ + uint64_t reserved_0_5 : 6; +#else /* Word 0 - Little Endian */ + uint64_t reserved_0_5 : 6; + uint64_t ptr : 43; + uint64_t reserved_49_63 : 15; +#endif /* Word 0 - End */ + } s; +} cptx_vqx_saddr_t; + +#endif /*_CPT_HW_TYPES_H_ */ -- 2.7.4