* [dpdk-dev] [PATCH 2/5] net/bnx2x: update link/PHY management
2018-09-19 21:59 [dpdk-dev] [PATCH 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
@ 2018-09-19 21:59 ` Mody, Rasesh
2018-09-21 18:10 ` Ferruh Yigit
2018-09-19 21:59 ` [dpdk-dev] [PATCH 3/5] net/bnx2x: fix to disable further interrupts Mody, Rasesh
` (7 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-19 21:59 UTC (permalink / raw)
To: dev; +Cc: Mody, Rasesh, ferruh.yigit, Dept-Eng DPDK Dev
This patch has changes to update the link/PHY management (elink) code
to the latest.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x.h | 3 +
drivers/net/bnx2x/ecore_hsi.h | 20 +-
drivers/net/bnx2x/elink.c | 7951 ++++++++++++++++++++++++++---------------
drivers/net/bnx2x/elink.h | 234 +-
4 files changed, 5231 insertions(+), 2977 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 2d545f5..1cc5a6b 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -824,6 +824,7 @@ struct bnx2x_devinfo {
#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
/* device ids */
+#define CHIP_NUM_57710 0x164e
#define CHIP_NUM_57711 0x164f
#define CHIP_NUM_57711E 0x1650
#define CHIP_NUM_57712 0x1662
@@ -865,6 +866,8 @@ struct bnx2x_devinfo {
#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
+#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
+#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h
index 57085eb..1192e5d 100644
--- a/drivers/net/bnx2x/ecore_hsi.h
+++ b/drivers/net/bnx2x/ecore_hsi.h
@@ -500,6 +500,18 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
+ /* Set non-default values for TXFIR in SFP mode. */
+ #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
+ #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
+
+ /* Set non-default values for IPREDRIVER in SFP mode. */
+ #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
+ #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24
+
+ /* Set non-default values for POST2 in SFP mode. */
+ #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
+ #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28
+
uint32_t reserved0[5]; /* 0x17c */
uint32_t aeu_int_mask; /* 0x190 */
@@ -783,6 +795,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722 0x00000f00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616 0x00001000
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834 0x00001100
+ #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858 0x00001200
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
@@ -2532,7 +2545,12 @@ struct shmem2_region {
uint32_t drv_func_info_addr; /* Offset 0x14C */
uint32_t drv_func_info_size; /* Offset 0x150 */
uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */
- #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0)
+ #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
+ #define LINK_ATTR_84858 0x00000002
+ #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
+ #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
+
+ uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
};
diff --git a/drivers/net/bnx2x/elink.c b/drivers/net/bnx2x/elink.c
index 1f94476..930b425 100644
--- a/drivers/net/bnx2x/elink.c
+++ b/drivers/net/bnx2x/elink.c
@@ -18,166 +18,159 @@
#include "ecore_hsi.h"
#include "ecore_reg.h"
-static elink_status_t elink_link_reset(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t reset_ext_phy);
-static elink_status_t elink_check_half_open_conn(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t notify);
-static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
- struct elink_params *params);
#define MDIO_REG_BANK_CL73_IEEEB0 0x0
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
+ #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
+ #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
+ #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
+ #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
#define MDIO_REG_BANK_CL73_IEEEB1 0x10
-#define MDIO_CL73_IEEEB1_AN_ADV1 0x00
-#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
-#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
-#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
-#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
-#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
-#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
+ #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
+ #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
+ #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
+ #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
+ #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
+ #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
+ #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
+ #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
+ #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
+ #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
#define MDIO_REG_BANK_RX0 0x80b0
-#define MDIO_RX0_RX_STATUS 0x10
-#define MDIO_RX0_RX_STATUS_SIGDET 0x8000
-#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
-#define MDIO_RX0_RX_EQ_BOOST 0x1c
-#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX0_RX_STATUS 0x10
+ #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
+ #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
+ #define MDIO_RX0_RX_EQ_BOOST 0x1c
+ #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_RX1 0x80c0
-#define MDIO_RX1_RX_EQ_BOOST 0x1c
-#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX1_RX_EQ_BOOST 0x1c
+ #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_RX2 0x80d0
-#define MDIO_RX2_RX_EQ_BOOST 0x1c
-#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX2_RX_EQ_BOOST 0x1c
+ #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_RX3 0x80e0
-#define MDIO_RX3_RX_EQ_BOOST 0x1c
-#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX3_RX_EQ_BOOST 0x1c
+ #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_RX_ALL 0x80f0
-#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
-#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
+ #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_TX0 0x8060
-#define MDIO_TX0_TX_DRIVER 0x17
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+ #define MDIO_TX0_TX_DRIVER 0x17
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+ #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
#define MDIO_REG_BANK_TX1 0x8070
-#define MDIO_TX1_TX_DRIVER 0x17
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+ #define MDIO_TX1_TX_DRIVER 0x17
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+ #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
#define MDIO_REG_BANK_TX2 0x8080
-#define MDIO_TX2_TX_DRIVER 0x17
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+ #define MDIO_TX2_TX_DRIVER 0x17
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+ #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
#define MDIO_REG_BANK_TX3 0x8090
-#define MDIO_TX3_TX_DRIVER 0x17
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+ #define MDIO_TX3_TX_DRIVER 0x17
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+ #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
-#define MDIO_BLOCK0_XGXS_CONTROL 0x10
+ #define MDIO_BLOCK0_XGXS_CONTROL 0x10
#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
-#define MDIO_BLOCK1_LANE_CTRL0 0x15
-#define MDIO_BLOCK1_LANE_CTRL1 0x16
-#define MDIO_BLOCK1_LANE_CTRL2 0x17
-#define MDIO_BLOCK1_LANE_PRBS 0x19
+ #define MDIO_BLOCK1_LANE_CTRL0 0x15
+ #define MDIO_BLOCK1_LANE_CTRL1 0x16
+ #define MDIO_BLOCK1_LANE_CTRL2 0x17
+ #define MDIO_BLOCK1_LANE_PRBS 0x19
#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
-#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
-#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
-#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
-#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
-#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
-#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
-#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
-#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
-#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
+ #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
+ #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
+ #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
+ #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
+ #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
+ #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
+ #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
+ #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
+ #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
#define MDIO_REG_BANK_GP_STATUS 0x8120
#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
+
#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
@@ -320,6 +313,7 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
Theotherbitsarereservedandshouldbezero*/
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
+
#define MDIO_PMA_DEVAD 0x1
/*ieee*/
#define MDIO_PMA_REG_CTRL 0x0
@@ -328,7 +322,7 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PMA_REG_TX_DISABLE 0x0009
#define MDIO_PMA_REG_RX_SD 0xa
/*bnx2x*/
-#define MDIO_PMA_REG_BNX2X_CTRL 0x0096
+#define MDIO_PMA_REG_BCM_CTRL 0x0096
#define MDIO_PMA_REG_FEC_CTRL 0x00ab
#define MDIO_PMA_LASI_RXCTRL 0x9000
#define MDIO_PMA_LASI_TXCTRL 0x9001
@@ -343,8 +337,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
#define MDIO_PMA_REG_MISC_CTRL 0xca0a
#define MDIO_PMA_REG_GEN_CTRL 0xca10
-#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
-#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
+ #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
+ #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
#define MDIO_PMA_REG_ROM_VER1 0xca19
@@ -358,21 +352,21 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PMA_REG_MISC_CTRL1 0xca85
#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
-#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
-#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
+ #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
-#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
+ #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
#define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
@@ -404,6 +398,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
+
+
#define MDIO_WIS_DEVAD 0x2
/*bnx2x*/
#define MDIO_WIS_REG_LASI_CNTL 0x9002
@@ -415,13 +411,15 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
-#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
+ #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
-#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
-#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
-#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
+ #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
+ #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
+ #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
+
+
#define MDIO_XS_DEVAD 0x4
#define MDIO_XS_REG_STATUS 0x0001
#define MDIO_XS_PLL_SEQUENCER 0x8000
@@ -439,12 +437,12 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
/*ieee*/
#define MDIO_AN_REG_CTRL 0x0000
#define MDIO_AN_REG_STATUS 0x0001
-#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
+ #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
#define MDIO_AN_REG_ADV_PAUSE 0x0010
-#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
-#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
-#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
-#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
+ #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
+ #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
+ #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
+ #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
#define MDIO_AN_REG_ADV 0x0011
#define MDIO_AN_REG_ADV2 0x0012
#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
@@ -465,13 +463,16 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
-#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
+ #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
+#define MDIO_AN_REG_848xx_ID_MSB 0xffe2
+ #define BNX2X84858_PHY_ID 0x600d
+#define MDIO_AN_REG_848xx_ID_LSB 0xffe3
#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
-#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
+ #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
@@ -480,62 +481,62 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
/* BNX2X84823 only */
#define MDIO_CTL_DEVAD 0x1e
#define MDIO_CTL_REG_84823_MEDIA 0x401a
-#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
+ #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
/* These pins configure the BNX2X84823 interface to MAC after reset. */
-#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
-#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
+ #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
+ #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
/* These pins configure the BNX2X84823 interface to Line after reset. */
-#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
-#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
-#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
+ #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
+ #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
+ #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
/* When this pin is active high during reset, 10GBASE-T core is power
* down, When it is active low the 10GBASE-T is power up
*/
-#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
-#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
-#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
-#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
-#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
+ #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
+ #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
+ #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
+ #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
+ #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
-#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
+ #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
-#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
+ #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
-#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
+ #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
/* BNX2X84833 only */
#define MDIO_84833_TOP_CFG_FW_REV 0x400f
-#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
-#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
+#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
+#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
-#define MDIO_84833_SUPER_ISOLATE 0x8000
-/* These are mailbox register set used by 84833. */
-#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
-#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
-#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
-#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
-#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
-#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
-#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
-#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
-#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
-#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
-#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
-#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
-#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
-#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
-#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
-#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
-#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
-#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
-
-/* Mailbox command set used by 84833. */
-#define PHY84833_CMD_SET_PAIR_SWAP 0x8001
-#define PHY84833_CMD_GET_EEE_MODE 0x8008
-#define PHY84833_CMD_SET_EEE_MODE 0x8009
-#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
-/* Mailbox status set used by 84833. */
+#define MDIO_84833_SUPER_ISOLATE 0x8000
+/* These are mailbox register set used by 84833/84858. */
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
+#define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)
+#define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)
+#define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)
+#define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)
+#define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)
+#define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)
+#define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)
+
+/* Mailbox command set used by 84833/84858 */
+#define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
+#define PHY848xx_CMD_GET_EEE_MODE 0x8008
+#define PHY848xx_CMD_SET_EEE_MODE 0x8009
+#define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031
+/* Mailbox status set used by 84833 only */
#define PHY84833_STATUS_CMD_RECEIVED 0x0001
#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
@@ -545,6 +546,19 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
+/* Mailbox Process */
+#define PHY84833_MB_PROCESS1 1
+#define PHY84833_MB_PROCESS2 2
+#define PHY84833_MB_PROCESS3 3
+
+
+/* Mailbox status set used by 84858 only */
+#define PHY84858_STATUS_CMD_RECEIVED 0x0001
+#define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
+#define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
+#define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
+#define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
+
/* Warpcore clause 45 addressing */
#define MDIO_WC_DEVAD 0x3
@@ -553,8 +567,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
-#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
-#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
+ #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
+ #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
#define MDIO_WC_REG_PCS_STATUS2 0x0021
#define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
@@ -570,6 +584,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
@@ -585,7 +601,9 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
+#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
+#define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a
#define MDIO_WC_REG_XGXS_STATUS3 0x8129
#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
@@ -599,35 +617,35 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
+ #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
+ #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
+ #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
+ #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
#define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
#define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
#define MDIO_WC_REG_DSC_SMC 0x8213
#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
#define MDIO_WC_REG_TX_FIR_TAP 0x82e2
-#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
-#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
-#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
-#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
-#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
-#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
-#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
+ #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
+ #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
+ #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
+ #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
+ #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
+ #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
+ #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
@@ -689,8 +707,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
-#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
-#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
+#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
+#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
@@ -700,33 +718,31 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_REG_GPHY_MII_STATUS 0x1
#define MDIO_REG_GPHY_PHYID_LSB 0x3
#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
-#define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
-#define MDIO_REG_GPHY_CL45_REG_READ 0xc000
+ #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
+ #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
-#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
+ #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
#define MDIO_REG_GPHY_EXP_ACCESS 0x17
-#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
-#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
+ #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
+ #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
#define MDIO_REG_GPHY_AUX_STATUS 0x19
#define MDIO_REG_INTR_STATUS 0x1a
#define MDIO_REG_INTR_MASK 0x1b
-#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
+ #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
#define MDIO_REG_GPHY_SHADOW 0x1c
-#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
-#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
-#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
-#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
-#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
-
-typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
- struct elink_params *
- params,
- uint8_t dev_addr,
- uint16_t addr,
- uint8_t byte_cnt,
- uint8_t * o_buf,
- uint8_t);
+ #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
+ #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
+ #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
+ #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
+ #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
+
+
+typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
+ struct elink_params *params,
+ uint8_t dev_addr, uint16_t addr,
+ uint8_t byte_cnt,
+ uint8_t *o_buf, uint8_t);
/********************************************************/
#define ELINK_ETH_HLEN 14
/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
@@ -850,21 +866,29 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
#define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
-#define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
-#define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
-#define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
+ #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
+ #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
+ #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
+ #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
+
+
+#define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR 0x3
+ #define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK (1 << 4)
+ #define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK (1 << 5)
+ #define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1 << 6)
-#define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
-#define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
-#define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
-#define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
+#define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR 0x6
+ #define ELINK_SFP_EEPROM_1G_COMP_CODE_SX (1 << 0)
+ #define ELINK_SFP_EEPROM_1G_COMP_CODE_LX (1 << 1)
+ #define ELINK_SFP_EEPROM_1G_COMP_CODE_CX (1 << 2)
+ #define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T (1 << 3)
#define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
-#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
-#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
+ #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
+ #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
#define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
-#define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
+ #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
#define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
#define ELINK_EDC_MODE_LINEAR 0x0022
@@ -883,6 +907,10 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
#define ELINK_MAX_PACKET_SIZE (9700)
#define MAX_KR_LINK_RETRY 4
+#define DEFAULT_TX_DRV_BRDCT 2
+#define DEFAULT_TX_DRV_IFIR 0
+#define DEFAULT_TX_DRV_POST2 3
+#define DEFAULT_TX_DRV_IPRE_DRIVER 6
/**********************************************************/
/* INTERFACE */
@@ -900,6 +928,11 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
(_bank + (_addr & 0xf)), \
_val)
+static elink_status_t elink_check_half_open_conn(struct elink_params *params,
+ struct elink_vars *vars, uint8_t notify);
+static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
+ struct elink_params *params);
+
static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits)
{
uint32_t val = REG_RD(sc, reg);
@@ -935,16 +968,16 @@ static int elink_check_lfa(struct elink_params *params)
struct bnx2x_softc *sc = params->sc;
additional_config =
- REG_RD(sc, params->lfa_base +
- offsetof(struct shmem_lfa, additional_config));
+ REG_RD(sc, params->lfa_base +
+ offsetof(struct shmem_lfa, additional_config));
/* NOTE: must be first condition checked -
- * to verify DCC bit is cleared in any case!
- */
+ * to verify DCC bit is cleared in any case!
+ */
if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
- PMD_DRV_LOG(DEBUG, sc, "No LFA due to DCC flap after clp exit");
+ ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit");
REG_WR(sc, params->lfa_base +
- offsetof(struct shmem_lfa, additional_config),
+ offsetof(struct shmem_lfa, additional_config),
additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
return LFA_DCC_LFA_DISABLED;
}
@@ -983,8 +1016,8 @@ static int elink_check_lfa(struct elink_params *params)
offsetof(struct shmem_lfa, req_duplex));
req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
- PMD_DRV_LOG(INFO, sc, "Duplex mismatch %x vs. %x",
- (saved_val & lfa_mask), (req_val & lfa_mask));
+ ELINK_DEBUG_P2(sc, "Duplex mismatch %x vs. %x",
+ (saved_val & lfa_mask), (req_val & lfa_mask));
return LFA_DUPLEX_MISMATCH;
}
/* Compare Flow Control */
@@ -992,8 +1025,8 @@ static int elink_check_lfa(struct elink_params *params)
offsetof(struct shmem_lfa, req_flow_ctrl));
req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
- PMD_DRV_LOG(DEBUG, sc, "Flow control mismatch %x vs. %x",
- (saved_val & lfa_mask), (req_val & lfa_mask));
+ ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x",
+ (saved_val & lfa_mask), (req_val & lfa_mask));
return LFA_FLOW_CTRL_MISMATCH;
}
/* Compare Link Speed */
@@ -1001,8 +1034,8 @@ static int elink_check_lfa(struct elink_params *params)
offsetof(struct shmem_lfa, req_line_speed));
req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
- PMD_DRV_LOG(DEBUG, sc, "Link speed mismatch %x vs. %x",
- (saved_val & lfa_mask), (req_val & lfa_mask));
+ ELINK_DEBUG_P2(sc, "Link speed mismatch %x vs. %x",
+ (saved_val & lfa_mask), (req_val & lfa_mask));
return LFA_LINK_SPEED_MISMATCH;
}
@@ -1012,21 +1045,21 @@ static int elink_check_lfa(struct elink_params *params)
speed_cap_mask[cfg_idx]));
if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
- PMD_DRV_LOG(DEBUG, sc, "Speed Cap mismatch %x vs. %x",
- cur_speed_cap_mask,
- params->speed_cap_mask[cfg_idx]);
+ ELINK_DEBUG_P2(sc, "Speed Cap mismatch %x vs. %x",
+ cur_speed_cap_mask,
+ params->speed_cap_mask[cfg_idx]);
return LFA_SPEED_CAP_MISMATCH;
}
}
cur_req_fc_auto_adv =
- REG_RD(sc, params->lfa_base +
- offsetof(struct shmem_lfa, additional_config)) &
- REQ_FC_AUTO_ADV_MASK;
+ REG_RD(sc, params->lfa_base +
+ offsetof(struct shmem_lfa, additional_config)) &
+ REQ_FC_AUTO_ADV_MASK;
- if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {
- PMD_DRV_LOG(DEBUG, sc, "Flow Ctrl AN mismatch %x vs. %x",
- cur_req_fc_auto_adv, params->req_fc_auto_adv);
+ if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
+ ELINK_DEBUG_P2(sc, "Flow Ctrl AN mismatch %x vs. %x",
+ cur_req_fc_auto_adv, params->req_fc_auto_adv);
return LFA_FLOW_CTRL_MISMATCH;
}
@@ -1038,27 +1071,25 @@ static int elink_check_lfa(struct elink_params *params)
(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
(params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
- PMD_DRV_LOG(DEBUG, sc,
- "EEE mismatch %x vs. %x", params->eee_mode,
- eee_status);
+ ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x", params->eee_mode,
+ eee_status);
return LFA_EEE_MISMATCH;
}
/* LFA conditions are met */
return 0;
}
-
/******************************************************************/
/* EPIO/GPIO section */
/******************************************************************/
static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
- uint32_t * en)
+ uint32_t *en)
{
uint32_t epio_mask, gp_oenable;
*en = 0;
/* Sanity check */
if (epio_pin > 31) {
- PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to get", epio_pin);
+ ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to get", epio_pin);
return;
}
@@ -1069,17 +1100,16 @@ static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
*en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
}
-
static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en)
{
uint32_t epio_mask, gp_output, gp_oenable;
/* Sanity check */
if (epio_pin > 31) {
- PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to set", epio_pin);
+ ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to set", epio_pin);
return;
}
- PMD_DRV_LOG(DEBUG, sc, "Setting EPIO pin %d to %d", epio_pin, en);
+ ELINK_DEBUG_P2(sc, "Setting EPIO pin %d to %d", epio_pin, en);
epio_mask = 1 << epio_pin;
/* Set this EPIO to output */
gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
@@ -1105,12 +1135,12 @@ static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
} else {
uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
- elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port);
+ elink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port);
}
}
static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
- uint32_t * val)
+ uint32_t *val)
{
if (pin_cfg == PIN_CFG_NA)
return ELINK_STATUS_ERROR;
@@ -1122,14 +1152,939 @@ static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
*val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
}
return ELINK_STATUS_OK;
+}
+
+/******************************************************************/
+/* ETS section */
+/******************************************************************/
+static void elink_ets_e2e3a0_disabled(struct elink_params *params)
+{
+ /* ETS disabled configuration*/
+ struct bnx2x_softc *sc = params->sc;
+
+ ELINK_DEBUG_P0(sc, "ETS E2E3 disabled configuration");
+
+ /* mapping between entry priority to client number (0,1,2 -debug and
+ * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
+ * 3bits client num.
+ * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
+ * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
+ */
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ * as strict. Bits 0,1,2 - debug and management entries, 3 -
+ * COS0 entry, 4 - COS1 entry.
+ * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
+ * bit4 bit3 bit2 bit1 bit0
+ * MCP and debug are strict
+ */
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
+ /* defines which entries (clients) are subjected to WFQ arbitration */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
+ /* For strict priority entries defines the number of consecutive
+ * slots for the highest priority.
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
+ /* mapping between the CREDIT_WEIGHT registers and actual client
+ * numbers
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
+ REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
+ /* ETS mode disable */
+ REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
+ /* If ETS mode is enabled (there is no strict priority) defines a WFQ
+ * weight for COS0/COS1.
+ */
+ REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);
+ REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);
+ /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
+ REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);
+ REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);
+ /* Defines the number of consecutive slots for the strict priority */
+ REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
+}
+/******************************************************************************
+ * Description:
+ * Getting min_w_val will be set according to line speed .
+ *.
+ ******************************************************************************/
+static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars)
+{
+ uint32_t min_w_val = 0;
+ /* Calculate min_w_val.*/
+ if (vars->link_up) {
+ if (vars->line_speed == ELINK_SPEED_20000)
+ min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
+ else
+ min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
+ } else {
+ min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
+ }
+ /* If the link isn't up (static configuration for example ) The
+ * link will be according to 20GBPS.
+ */
+ return min_w_val;
+}
+/******************************************************************************
+ * Description:
+ * Getting credit upper bound form min_w_val.
+ *.
+ ******************************************************************************/
+static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val)
+{
+ const uint32_t credit_upper_bound = (uint32_t)
+ ELINK_MAXVAL((150 * min_w_val),
+ ELINK_MAX_PACKET_SIZE);
+ return credit_upper_bound;
+}
+/******************************************************************************
+ * Description:
+ * Set credit upper bound for NIG.
+ *.
+ ******************************************************************************/
+static void elink_ets_e3b0_set_credit_upper_bound_nig(
+ const struct elink_params *params,
+ const uint32_t min_w_val)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint32_t credit_upper_bound =
+ elink_ets_get_credit_upper_bound(min_w_val);
+
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
+
+ if (!port) {
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
+ credit_upper_bound);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
+ credit_upper_bound);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
+ credit_upper_bound);
+ }
+}
+/******************************************************************************
+ * Description:
+ * Will return the NIG ETS registers to init values.Except
+ * credit_upper_bound.
+ * That isn't used in this configuration (No WFQ is enabled) and will be
+ * configured according to spec
+ *.
+ ******************************************************************************/
+static void elink_ets_e3b0_nig_disabled(const struct elink_params *params,
+ const struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars);
+ /* Mapping between entry priority to client number (0,1,2 -debug and
+ * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
+ * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
+ * reset value or init tool
+ */
+ if (port) {
+ REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
+ REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
+ } else {
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
+ }
+ /* For strict priority entries defines the number of consecutive
+ * slots for the highest priority.
+ */
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
+ NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
+ /* Mapping between the CREDIT_WEIGHT registers and actual client
+ * numbers
+ */
+ if (port) {
+ /*Port 1 has 6 COS*/
+ REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
+ REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
+ } else {
+ /*Port 0 has 9 COS*/
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
+ 0x43210876);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
+ }
+
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ * as strict. Bits 0,1,2 - debug and management entries, 3 -
+ * COS0 entry, 4 - COS1 entry.
+ * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
+ * bit4 bit3 bit2 bit1 bit0
+ * MCP and debug are strict
+ */
+ if (port)
+ REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
+ else
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
+ /* defines which entries (clients) are subjected to WFQ arbitration */
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
+ NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
+
+ /* Please notice the register address are note continuous and a
+ * for here is note appropriate.In 2 port mode port0 only COS0-5
+ * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
+ * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
+ * are never used for WFQ
+ */
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
+ if (!port) {
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
+ }
+
+ elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
+}
+/******************************************************************************
+ * Description:
+ * Set credit upper bound for PBF.
+ *.
+ ******************************************************************************/
+static void elink_ets_e3b0_set_credit_upper_bound_pbf(
+ const struct elink_params *params,
+ const uint32_t min_w_val)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint32_t credit_upper_bound =
+ elink_ets_get_credit_upper_bound(min_w_val);
+ const uint8_t port = params->port;
+ uint32_t base_upper_bound = 0;
+ uint8_t max_cos = 0;
+ uint8_t i = 0;
+ /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
+ * port mode port1 has COS0-2 that can be used for WFQ.
+ */
+ if (!port) {
+ base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
+ max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+ } else {
+ base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
+ max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
+ }
+
+ for (i = 0; i < max_cos; i++)
+ REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound);
+}
+
+/******************************************************************************
+ * Description:
+ * Will return the PBF ETS registers to init values.Except
+ * credit_upper_bound.
+ * That isn't used in this configuration (No WFQ is enabled) and will be
+ * configured according to spec
+ *.
+ ******************************************************************************/
+static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
+ uint8_t i = 0;
+ uint32_t base_weight = 0;
+ uint8_t max_cos = 0;
+
+ /* Mapping between entry priority to client number 0 - COS0
+ * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
+ * TODO_ETS - Should be done by reset value or init tool
+ */
+ if (port)
+ /* 0x688 (|011|0 10|00 1|000) */
+ REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1, 0x688);
+ else
+ /* (10 1|100 |011|0 10|00 1|000) */
+ REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0, 0x2C688);
+
+ /* TODO_ETS - Should be done by reset value or init tool */
+ if (port)
+ /* 0x688 (|011|0 10|00 1|000)*/
+ REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
+ else
+ /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
+ REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
+ PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0, 0x100);
+
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
+ PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0, 0);
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
+ PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 0);
+ /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
+ * In 4 port mode port1 has COS0-2 that can be used for WFQ.
+ */
+ if (!port) {
+ base_weight = PBF_REG_COS0_WEIGHT_P0;
+ max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+ } else {
+ base_weight = PBF_REG_COS0_WEIGHT_P1;
+ max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
+ }
+
+ for (i = 0; i < max_cos; i++)
+ REG_WR(sc, base_weight + (0x4 * i), 0);
+
+ elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
+}
+/******************************************************************************
+ * Description:
+ * E3B0 disable will return basicly the values to init values.
+ *.
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params,
+ const struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+
+ if (!CHIP_IS_E3B0(sc)) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_disabled the chip isn't E3B0");
+ return ELINK_STATUS_ERROR;
+ }
+
+ elink_ets_e3b0_nig_disabled(params, vars);
+
+ elink_ets_e3b0_pbf_disabled(params);
+
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * Disable will return basicly the values to init values.
+ *
+ ******************************************************************************/
+elink_status_t elink_ets_disabled(struct elink_params *params,
+ struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+ elink_status_t elink_status = ELINK_STATUS_OK;
+
+ if ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc))) {
+ elink_ets_e2e3a0_disabled(params);
+ } else if (CHIP_IS_E3B0(sc)) {
+ elink_status = elink_ets_e3b0_disabled(params, vars);
+ } else {
+ ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported");
+ return ELINK_STATUS_ERROR;
+ }
+
+ return elink_status;
+}
+
+/******************************************************************************
+ * Description
+ * Set the COS mappimg to SP and BW until this point all the COS are not
+ * set as SP or BW.
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params,
+ __rte_unused const struct elink_ets_params *ets_params,
+ const uint8_t cos_sp_bitmap,
+ const uint8_t cos_bw_bitmap)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
+ const uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap;
+ const uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
+ const uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
+
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
+ NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
+ PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0, pbf_cli_sp_bitmap);
+
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
+ NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
+ nig_cli_subject2wfq_bitmap);
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
+ PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
+ pbf_cli_subject2wfq_bitmap);
+
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
+ * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_set_cos_bw(struct bnx2x_softc *sc,
+ const uint8_t cos_entry,
+ const uint32_t min_w_val_nig,
+ const uint32_t min_w_val_pbf,
+ const uint16_t total_bw,
+ const uint8_t bw,
+ const uint8_t port)
+{
+ uint32_t nig_reg_address_crd_weight = 0;
+ uint32_t pbf_reg_address_crd_weight = 0;
+ /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
+ const uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
+ const uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
+
+ switch (cos_entry) {
+ case 0:
+ nig_reg_address_crd_weight =
+ (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
+ pbf_reg_address_crd_weight = (port) ?
+ PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
+ break;
+ case 1:
+ nig_reg_address_crd_weight = (port) ?
+ NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
+ pbf_reg_address_crd_weight = (port) ?
+ PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
+ break;
+ case 2:
+ nig_reg_address_crd_weight = (port) ?
+ NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
+
+ pbf_reg_address_crd_weight = (port) ?
+ PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
+ break;
+ case 3:
+ if (port)
+ return ELINK_STATUS_ERROR;
+ nig_reg_address_crd_weight =
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
+ pbf_reg_address_crd_weight =
+ PBF_REG_COS3_WEIGHT_P0;
+ break;
+ case 4:
+ if (port)
+ return ELINK_STATUS_ERROR;
+ nig_reg_address_crd_weight =
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
+ pbf_reg_address_crd_weight = PBF_REG_COS4_WEIGHT_P0;
+ break;
+ case 5:
+ if (port)
+ return ELINK_STATUS_ERROR;
+ nig_reg_address_crd_weight =
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
+ pbf_reg_address_crd_weight = PBF_REG_COS5_WEIGHT_P0;
+ break;
+ }
+
+ REG_WR(sc, nig_reg_address_crd_weight, cos_bw_nig);
+
+ REG_WR(sc, pbf_reg_address_crd_weight, cos_bw_pbf);
+
+ return ELINK_STATUS_OK;
+}
+/******************************************************************************
+ * Description:
+ * Calculate the total BW.A value of 0 isn't legal.
+ *
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_get_total_bw(
+ const struct elink_params *params,
+ struct elink_ets_params *ets_params,
+ uint16_t *total_bw)
+{
+ struct bnx2x_softc *sc = params->sc;
+ uint8_t cos_idx = 0;
+ uint8_t is_bw_cos_exist = 0;
+
+ *total_bw = 0;
+ /* Calculate total BW requested */
+ for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
+ if (ets_params->cos[cos_idx].state == elink_cos_state_bw) {
+ is_bw_cos_exist = 1;
+ if (!ets_params->cos[cos_idx].params.bw_params.bw) {
+ ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config BW"
+ " was set to 0");
+ /* This is to prevent a state when ramrods
+ * can't be sent
+ */
+ ets_params->cos[cos_idx].params.bw_params.bw
+ = 1;
+ }
+ *total_bw +=
+ ets_params->cos[cos_idx].params.bw_params.bw;
+ }
+ }
+
+ /* Check total BW is valid */
+ if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
+ if (*total_bw == 0) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_E3B0_config total BW shouldn't be 0");
+ return ELINK_STATUS_ERROR;
+ }
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_E3B0_config total BW should be 100");
+ /* We can handle a case whre the BW isn't 100 this can happen
+ * if the TC are joined.
+ */
+ }
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * Invalidate all the sp_pri_to_cos.
+ *
+ ******************************************************************************/
+static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos)
+{
+ uint8_t pri = 0;
+ for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)
+ sp_pri_to_cos[pri] = DCBX_INVALID_COS;
+}
+/******************************************************************************
+ * Description:
+ * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
+ * according to sp_pri_to_cos.
+ *
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(
+ const struct elink_params *params,
+ uint8_t *sp_pri_to_cos,
+ const uint8_t pri,
+ const uint8_t cos_entry)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint8_t max_num_of_cos = (port) ?
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+
+ if (pri >= max_num_of_cos) {
+ ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
+ "parameter Illegal strict priority");
+ return ELINK_STATUS_ERROR;
+ }
+
+ if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
+ ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
+ "parameter There can't be two COS's with "
+ "the same strict pri");
+ return ELINK_STATUS_ERROR;
+ }
+
+ sp_pri_to_cos[pri] = cos_entry;
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * Returns the correct value according to COS and priority in
+ * the sp_pri_cli register.
+ *
+ ******************************************************************************/
+static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos,
+ const uint8_t cos_offset,
+ const uint8_t pri_set,
+ const uint8_t pri_offset,
+ const uint8_t entry_size)
+{
+ uint64_t pri_cli_nig = 0;
+ pri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size *
+ (pri_set + pri_offset));
+
+ return pri_cli_nig;
+}
+/******************************************************************************
+ * Description:
+ * Returns the correct value according to COS and priority in the
+ * sp_pri_cli register for NIG.
+ *
+ ******************************************************************************/
+static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos,
+ const uint8_t pri_set)
+{
+ /* MCP Dbg0 and dbg1 are always with higher strict pri*/
+ const uint8_t nig_cos_offset = 3;
+ const uint8_t nig_pri_offset = 3;
+
+ return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
+ nig_pri_offset, 4);
+}
+
+/******************************************************************************
+ * Description:
+ * Returns the correct value according to COS and priority in the
+ * sp_pri_cli register for PBF.
+ *
+ ******************************************************************************/
+static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos,
+ const uint8_t pri_set)
+{
+ const uint8_t pbf_cos_offset = 0;
+ const uint8_t pbf_pri_offset = 0;
+
+ return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
+ pbf_pri_offset, 3);
+}
+
+/******************************************************************************
+ * Description:
+ * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
+ * according to sp_pri_to_cos.(which COS has higher priority)
+ *
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(
+ const struct elink_params *params,
+ uint8_t *sp_pri_to_cos)
+{
+ struct bnx2x_softc *sc = params->sc;
+ uint8_t i = 0;
+ const uint8_t port = params->port;
+ /* MCP Dbg0 and dbg1 are always with higher strict pri*/
+ uint64_t pri_cli_nig = 0x210;
+ uint32_t pri_cli_pbf = 0x0;
+ uint8_t pri_set = 0;
+ uint8_t pri_bitmask = 0;
+ const uint8_t max_num_of_cos = (port) ?
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+
+ uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1;
+
+ /* Set all the strict priority first */
+ for (i = 0; i < max_num_of_cos; i++) {
+ if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
+ if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_sp_set_pri_cli_reg "
+ "invalid cos entry");
+ return ELINK_STATUS_ERROR;
+ }
+
+ pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
+ sp_pri_to_cos[i], pri_set);
+
+ pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
+ sp_pri_to_cos[i], pri_set);
+ pri_bitmask = 1 << sp_pri_to_cos[i];
+ /* COS is used remove it from bitmap.*/
+ if (!(pri_bitmask & cos_bit_to_set)) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_sp_set_pri_cli_reg "
+ "invalid There can't be two COS's with"
+ " the same strict pri");
+ return ELINK_STATUS_ERROR;
+ }
+ cos_bit_to_set &= ~pri_bitmask;
+ pri_set++;
+ }
+ }
+
+ /* Set all the Non strict priority i= COS*/
+ for (i = 0; i < max_num_of_cos; i++) {
+ pri_bitmask = 1 << i;
+ /* Check if COS was already used for SP */
+ if (pri_bitmask & cos_bit_to_set) {
+ /* COS wasn't used for SP */
+ pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
+ i, pri_set);
+
+ pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
+ i, pri_set);
+ /* COS is used remove it from bitmap.*/
+ cos_bit_to_set &= ~pri_bitmask;
+ pri_set++;
+ }
+ }
+
+ if (pri_set != max_num_of_cos) {
+ ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_set_pri_cli_reg not all "
+ "entries were set");
+ return ELINK_STATUS_ERROR;
+ }
+
+ if (port) {
+ /* Only 6 usable clients*/
+ REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
+ (uint32_t)pri_cli_nig);
+
+ REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1, pri_cli_pbf);
+ } else {
+ /* Only 9 usable clients*/
+ const uint32_t pri_cli_nig_lsb = (uint32_t)(pri_cli_nig);
+ const uint32_t pri_cli_nig_msb = (uint32_t)
+ ((pri_cli_nig >> 32) & 0xF);
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
+ pri_cli_nig_lsb);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
+ pri_cli_nig_msb);
+
+ REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0, pri_cli_pbf);
+ }
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * Configure the COS to ETS according to BW and SP settings.
+ ******************************************************************************/
+elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
+ const struct elink_vars *vars,
+ struct elink_ets_params *ets_params)
+{
+ struct bnx2x_softc *sc = params->sc;
+ elink_status_t elink_status = ELINK_STATUS_OK;
+ const uint8_t port = params->port;
+ uint16_t total_bw = 0;
+ const uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars);
+ const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
+ uint8_t cos_bw_bitmap = 0;
+ uint8_t cos_sp_bitmap = 0;
+ uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};
+ const uint8_t max_num_of_cos = (port) ?
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+ uint8_t cos_entry = 0;
+
+ if (!CHIP_IS_E3B0(sc)) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_disabled the chip isn't E3B0");
+ return ELINK_STATUS_ERROR;
+ }
+
+ if (ets_params->num_of_cos > max_num_of_cos) {
+ ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config the number of COS "
+ "isn't supported");
+ return ELINK_STATUS_ERROR;
+ }
+
+ /* Prepare sp strict priority parameters*/
+ elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
+
+ /* Prepare BW parameters*/
+ elink_status = elink_ets_e3b0_get_total_bw(params, ets_params,
+ &total_bw);
+ if (elink_status != ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_E3B0_config get_total_bw failed");
+ return ELINK_STATUS_ERROR;
+ }
+
+ /* Upper bound is set according to current link speed (min_w_val
+ * should be the same for upper bound and COS credit val).
+ */
+ elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
+ elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
+
+
+ for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
+ if (elink_cos_state_bw == ets_params->cos[cos_entry].state) {
+ cos_bw_bitmap |= (1 << cos_entry);
+ /* The function also sets the BW in HW(not the mappin
+ * yet)
+ */
+ elink_status = elink_ets_e3b0_set_cos_bw(
+ sc, cos_entry, min_w_val_nig, min_w_val_pbf,
+ total_bw,
+ ets_params->cos[cos_entry].params.bw_params.bw,
+ port);
+ } else if (elink_cos_state_strict ==
+ ets_params->cos[cos_entry].state){
+ cos_sp_bitmap |= (1 << cos_entry);
+
+ elink_status = elink_ets_e3b0_sp_pri_to_cos_set(
+ params,
+ sp_pri_to_cos,
+ ets_params->cos[cos_entry].params.sp_params.pri,
+ cos_entry);
+
+ } else {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_config cos state not valid");
+ return ELINK_STATUS_ERROR;
+ }
+ if (elink_status != ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_config set cos bw failed");
+ return elink_status;
+ }
+ }
+
+ /* Set SP register (which COS has higher priority) */
+ elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params,
+ sp_pri_to_cos);
+
+ if (elink_status != ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_E3B0_config set_pri_cli_reg failed");
+ return elink_status;
+ }
+
+ /* Set client mapping of BW and strict */
+ elink_status = elink_ets_e3b0_cli_map(params, ets_params,
+ cos_sp_bitmap,
+ cos_bw_bitmap);
+
+ if (elink_status != ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config SP failed");
+ return elink_status;
+ }
+ return ELINK_STATUS_OK;
+}
+static void elink_ets_bw_limit_common(const struct elink_params *params)
+{
+ /* ETS disabled configuration */
+ struct bnx2x_softc *sc = params->sc;
+ ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration");
+ /* Defines which entries (clients) are subjected to WFQ arbitration
+ * COS0 0x8
+ * COS1 0x10
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
+ /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
+ * client numbers (WEIGHT_0 does not actually have to represent
+ * client 0)
+ * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
+ * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
+ ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
+ ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+
+ /* ETS mode enabled*/
+ REG_WR(sc, PBF_REG_ETS_ENABLED, 1);
+
+ /* Defines the number of consecutive slots for the strict priority */
+ REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
+ * entry, 4 - COS1 entry.
+ * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
+ * bit4 bit3 bit2 bit1 bit0
+ * MCP and debug are strict
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
+
+ /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
+ REG_WR(sc, PBF_REG_COS0_UPPER_BOUND,
+ ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+ REG_WR(sc, PBF_REG_COS1_UPPER_BOUND,
+ ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+}
+
+void elink_ets_bw_limit(const struct elink_params *params,
+ const uint32_t cos0_bw,
+ const uint32_t cos1_bw)
+{
+ /* ETS disabled configuration*/
+ struct bnx2x_softc *sc = params->sc;
+ const uint32_t total_bw = cos0_bw + cos1_bw;
+ uint32_t cos0_credit_weight = 0;
+ uint32_t cos1_credit_weight = 0;
+
+ ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration");
+ if ((!total_bw) ||
+ (!cos0_bw) ||
+ (!cos1_bw)) {
+ ELINK_DEBUG_P0(sc, "Total BW can't be zero");
+ return;
+ }
+
+ cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT) /
+ total_bw;
+ cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT) /
+ total_bw;
+
+ elink_ets_bw_limit_common(params);
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
+
+ REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
+ REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
+}
+
+elink_status_t elink_ets_strict(const struct elink_params *params,
+ const uint8_t strict_cos)
+{
+ /* ETS disabled configuration*/
+ struct bnx2x_softc *sc = params->sc;
+ uint32_t val = 0;
+
+ ELINK_DEBUG_P0(sc, "ETS enabled strict configuration");
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ * as strict. Bits 0,1,2 - debug and management entries,
+ * 3 - COS0 entry, 4 - COS1 entry.
+ * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
+ * bit4 bit3 bit2 bit1 bit0
+ * MCP and debug are strict
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
+ /* For strict priority entries defines the number of consecutive slots
+ * for the highest priority.
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
+ /* ETS mode disable */
+ REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
+ /* Defines the number of consecutive slots for the strict priority */
+ REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
+
+ /* Defines the number of consecutive slots for the strict priority */
+ REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
+
+ /* Mapping between entry priority to client number (0,1,2 -debug and
+ * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
+ * 3bits client num.
+ * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
+ * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
+ * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
+ */
+ val = (!strict_cos) ? 0x2318 : 0x22E0;
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
+
+ return ELINK_STATUS_OK;
}
/******************************************************************/
/* PFC section */
/******************************************************************/
static void elink_update_pfc_xmac(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars,
+ __rte_unused uint8_t is_lb)
{
struct bnx2x_softc *sc = params->sc;
uint32_t xmac_base;
@@ -1144,7 +2099,8 @@ static void elink_update_pfc_xmac(struct elink_params *params,
pfc1_val = 0x2;
/* No PFC support */
- if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
/* RX flow control - Process pause frame in receive direction
*/
@@ -1154,12 +2110,12 @@ static void elink_update_pfc_xmac(struct elink_params *params,
/* TX flow control - Send pause packet when buffer is full */
if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
- } else { /* PFC support */
+ } else {/* PFC support */
pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
- XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
- XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
- XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
- XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
+ XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
+ XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
+ XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
+ XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
/* Write pause and PFC registers */
REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
@@ -1173,21 +2129,76 @@ static void elink_update_pfc_xmac(struct elink_params *params,
REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
+
/* Set MAC address for source TX Pause/PFC frames */
REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
((params->mac_addr[2] << 24) |
(params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | (params->mac_addr[5])));
+ (params->mac_addr[4] << 8) |
+ (params->mac_addr[5])));
REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
- ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
+ ((params->mac_addr[0] << 8) |
+ (params->mac_addr[1])));
DELAY(30);
}
+static void elink_emac_get_pfc_stat(struct elink_params *params,
+ uint32_t pfc_frames_sent[2],
+ uint32_t pfc_frames_received[2])
+{
+ /* Read pfc statistic */
+ struct bnx2x_softc *sc = params->sc;
+ uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+ uint32_t val_xon = 0;
+ uint32_t val_xoff = 0;
+
+ ELINK_DEBUG_P0(sc, "pfc statistic read from EMAC");
+
+ /* PFC received frames */
+ val_xoff = REG_RD(sc, emac_base +
+ EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
+ val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
+ val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
+ val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
+
+ pfc_frames_received[0] = val_xon + val_xoff;
+
+ /* PFC received sent */
+ val_xoff = REG_RD(sc, emac_base +
+ EMAC_REG_RX_PFC_STATS_XOFF_SENT);
+ val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
+ val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
+ val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
+
+ pfc_frames_sent[0] = val_xon + val_xoff;
+}
+
+/* Read pfc statistic*/
+void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
+ uint32_t pfc_frames_sent[2],
+ uint32_t pfc_frames_received[2])
+{
+ /* Read pfc statistic */
+ struct bnx2x_softc *sc = params->sc;
+
+ ELINK_DEBUG_P0(sc, "pfc statistic");
+
+ if (!vars->link_up)
+ return;
+
+ if (vars->mac_type == ELINK_MAC_TYPE_EMAC) {
+ ELINK_DEBUG_P0(sc, "About to read PFC stats from EMAC");
+ elink_emac_get_pfc_stat(params, pfc_frames_sent,
+ pfc_frames_received);
+ }
+}
/******************************************************************/
/* MAC/PBF section */
/******************************************************************/
-static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
+static void elink_set_mdio_clk(struct bnx2x_softc *sc,
+ __rte_unused uint32_t chip_id,
+ uint32_t emac_base)
{
uint32_t new_mode, cur_mode;
uint32_t clc_cnt;
@@ -1206,26 +2217,16 @@ static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
return;
new_mode = cur_mode &
- ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
+ ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
new_mode |= clc_cnt;
new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
- PMD_DRV_LOG(DEBUG, sc, "Changing emac_mode from 0x%x to 0x%x",
- cur_mode, new_mode);
+ ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x",
+ cur_mode, new_mode);
REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
DELAY(40);
}
-static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,
- struct elink_params *params)
-{
- uint8_t phy_index;
- /* Set mdio clock per phy */
- for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
- phy_index++)
- elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl);
-}
-
static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)
{
uint32_t port4mode_ovwr_val;
@@ -1233,13 +2234,26 @@ static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)
port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
if (port4mode_ovwr_val & (1 << 0)) {
/* Return 4-port mode override value */
- return (port4mode_ovwr_val & (1 << 1)) == (1 << 1);
+ return ((port4mode_ovwr_val & (1 << 1)) == (1 << 1));
}
/* Return 4-port mode from input pin */
- return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN);
+ return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);
}
-static void elink_emac_init(struct elink_params *params)
+static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,
+ struct elink_params *params)
+{
+ uint8_t phy_index;
+
+ /* Set mdio clock per phy */
+ for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
+ phy_index++)
+ elink_set_mdio_clk(sc, params->chip_id,
+ params->phy[phy_index].mdio_ctrl);
+}
+
+static void elink_emac_init(struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
/* reset and unreset the emac core */
struct bnx2x_softc *sc = params->sc;
@@ -1263,9 +2277,9 @@ static void elink_emac_init(struct elink_params *params)
timeout = 200;
do {
val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
- PMD_DRV_LOG(DEBUG, sc, "EMAC reset reg is %u", val);
+ ELINK_DEBUG_P1(sc, "EMAC reset reg is %u", val);
if (!timeout) {
- PMD_DRV_LOG(DEBUG, sc, "EMAC timeout!");
+ ELINK_DEBUG_P0(sc, "EMAC timeout!");
return;
}
timeout--;
@@ -1273,17 +2287,20 @@ static void elink_emac_init(struct elink_params *params)
elink_set_mdio_emac_per_phy(sc, params);
/* Set mac address */
- val = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
+ val = ((params->mac_addr[0] << 8) |
+ params->mac_addr[1]);
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
val = ((params->mac_addr[2] << 24) |
(params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | params->mac_addr[5]);
+ (params->mac_addr[4] << 8) |
+ params->mac_addr[5]);
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
}
static void elink_set_xumac_nig(struct elink_params *params,
- uint16_t tx_pause_en, uint8_t enable)
+ uint16_t tx_pause_en,
+ uint8_t enable)
{
struct bnx2x_softc *sc = params->sc;
@@ -1301,7 +2318,7 @@ static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
uint32_t val;
struct bnx2x_softc *sc = params->sc;
if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
- (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
+ (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
return;
val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
if (en)
@@ -1315,7 +2332,7 @@ static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
}
static void elink_umac_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t lb)
+ struct elink_vars *vars, uint8_t lb)
{
uint32_t val;
uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
@@ -1328,15 +2345,15 @@ static void elink_umac_enable(struct elink_params *params,
REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
(MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
- PMD_DRV_LOG(DEBUG, sc, "enabling UMAC");
+ ELINK_DEBUG_P0(sc, "enabling UMAC");
/* This register opens the gate for the UMAC despite its name */
REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
- UMAC_COMMAND_CONFIG_REG_PAD_EN |
- UMAC_COMMAND_CONFIG_REG_SW_RESET |
- UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
+ UMAC_COMMAND_CONFIG_REG_PAD_EN |
+ UMAC_COMMAND_CONFIG_REG_SW_RESET |
+ UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
switch (vars->line_speed) {
case ELINK_SPEED_10:
val |= (0 << 2);
@@ -1351,8 +2368,8 @@ static void elink_umac_enable(struct elink_params *params,
val |= (3 << 2);
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Invalid speed for UMAC %d",
- vars->line_speed);
+ ELINK_DEBUG_P1(sc, "Invalid speed for UMAC %d",
+ vars->line_speed);
break;
}
if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
@@ -1369,7 +2386,7 @@ static void elink_umac_enable(struct elink_params *params,
/* Configure UMAC for EEE */
if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
- PMD_DRV_LOG(DEBUG, sc, "configured UMAC for EEE");
+ ELINK_DEBUG_P0(sc, "configured UMAC for EEE");
REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
@@ -1381,13 +2398,16 @@ static void elink_umac_enable(struct elink_params *params,
REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
((params->mac_addr[2] << 24) |
(params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | (params->mac_addr[5])));
+ (params->mac_addr[4] << 8) |
+ (params->mac_addr[5])));
REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
- ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
+ ((params->mac_addr[0] << 8) |
+ (params->mac_addr[1])));
/* Enable RX and TX */
val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
- val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA;
+ val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
+ UMAC_COMMAND_CONFIG_REG_RX_ENA;
REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
DELAY(50);
@@ -1427,7 +2447,8 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
is_port4mode &&
(REG_RD(sc, MISC_REG_RESET_REG_2) &
MISC_REGISTERS_RESET_REG_2_XMAC)) {
- PMD_DRV_LOG(DEBUG, sc, "XMAC already out of reset in 4-port mode");
+ ELINK_DEBUG_P0(sc,
+ "XMAC already out of reset in 4-port mode");
return;
}
@@ -1439,7 +2460,7 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
MISC_REGISTERS_RESET_REG_2_XMAC);
if (is_port4mode) {
- PMD_DRV_LOG(DEBUG, sc, "Init XMAC to 2 ports x 10G per path");
+ ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path");
/* Set the number of ports on the system side to up to 2 */
REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
@@ -1450,13 +2471,13 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
/* Set the number of ports on the system side to 1 */
REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
if (max_speed == ELINK_SPEED_10000) {
- PMD_DRV_LOG(DEBUG, sc,
- "Init XMAC to 10G x 1 port per path");
+ ELINK_DEBUG_P0(sc,
+ "Init XMAC to 10G x 1 port per path");
/* Set the number of ports on the Warp Core to 10G */
REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
} else {
- PMD_DRV_LOG(DEBUG, sc,
- "Init XMAC to 20G x 2 ports per path");
+ ELINK_DEBUG_P0(sc,
+ "Init XMAC to 20G x 2 ports per path");
/* Set the number of ports on the Warp Core to 20G */
REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
}
@@ -1478,7 +2499,8 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
uint32_t val;
- if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) {
+ if (REG_RD(sc, MISC_REG_RESET_REG_2) &
+ MISC_REGISTERS_RESET_REG_2_XMAC) {
/* Send an indication to change the state in the NIG back to XON
* Clearing this bit enables the next set of this bit to get
* rising edge
@@ -1488,7 +2510,7 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
(pfc_ctrl & ~(1 << 1)));
REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
(pfc_ctrl | (1 << 1)));
- PMD_DRV_LOG(DEBUG, sc, "Disable XMAC on port %x", port);
+ ELINK_DEBUG_P1(sc, "Disable XMAC on port %x", port);
val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
if (en)
val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
@@ -1499,11 +2521,11 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
}
static elink_status_t elink_xmac_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t lb)
+ struct elink_vars *vars, uint8_t lb)
{
uint32_t val, xmac_base;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "enabling XMAC");
+ ELINK_DEBUG_P0(sc, "enabling XMAC");
xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
@@ -1537,10 +2559,10 @@ static elink_status_t elink_xmac_enable(struct elink_params *params,
REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
/* update PFC */
- elink_update_pfc_xmac(params, vars);
+ elink_update_pfc_xmac(params, vars, 0);
if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
- PMD_DRV_LOG(DEBUG, sc, "Setting XMAC for EEE");
+ ELINK_DEBUG_P0(sc, "Setting XMAC for EEE");
REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
} else {
@@ -1569,14 +2591,14 @@ static elink_status_t elink_xmac_enable(struct elink_params *params,
}
static elink_status_t elink_emac_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t lb)
+ struct elink_vars *vars, uint8_t lb)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
uint32_t val;
- PMD_DRV_LOG(DEBUG, sc, "enabling EMAC");
+ ELINK_DEBUG_P0(sc, "enabling EMAC");
/* Disable BMAC */
REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
@@ -1585,19 +2607,39 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
/* enable emac and not bmac */
REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);
+#ifdef ELINK_INCLUDE_EMUL
+ /* for paladium */
+ if (CHIP_REV_IS_EMUL(sc)) {
+ /* Use lane 1 (of lanes 0-3) */
+ REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);
+ REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
+ }
+ /* for fpga */
+ else
+#endif
+#ifdef ELINK_INCLUDE_FPGA
+ if (CHIP_REV_IS_FPGA(sc)) {
+ /* Use lane 1 (of lanes 0-3) */
+ ELINK_DEBUG_P0(sc, "elink_emac_enable: Setting FPGA");
+
+ REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);
+ REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
+ } else
+#endif
+ /* ASIC */
if (vars->phy_flags & PHY_XGXS_FLAG) {
uint32_t ser_lane = ((params->lane_config &
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
- PMD_DRV_LOG(DEBUG, sc, "XGXS");
+ ELINK_DEBUG_P0(sc, "XGXS");
/* select the master lanes (out of 0-3) */
REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);
/* select XGXS */
REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
- } else { /* SerDes */
- PMD_DRV_LOG(DEBUG, sc, "SerDes");
+ } else { /* SerDes */
+ ELINK_DEBUG_P0(sc, "SerDes");
/* select SerDes */
REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
}
@@ -1607,28 +2649,39 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
EMAC_TX_MODE_RESET);
- /* pause enable/disable */
- elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
- EMAC_RX_MODE_FLOW_EN);
-
- elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
- (EMAC_TX_MODE_EXT_PAUSE_EN |
- EMAC_TX_MODE_FLOW_EN));
- if (!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
- if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
- elink_bits_en(sc, emac_base +
- EMAC_REG_EMAC_RX_MODE,
- EMAC_RX_MODE_FLOW_EN);
+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
+ if (CHIP_REV_IS_SLOW(sc)) {
+ /* config GMII mode */
+ val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
+ elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,
+ (val | EMAC_MODE_PORT_GMII));
+ } else { /* ASIC */
+#endif
+ /* pause enable/disable */
+ elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
+ EMAC_RX_MODE_FLOW_EN);
- if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
- elink_bits_en(sc, emac_base +
- EMAC_REG_EMAC_TX_MODE,
- (EMAC_TX_MODE_EXT_PAUSE_EN |
- EMAC_TX_MODE_FLOW_EN));
- } else
- elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
- EMAC_TX_MODE_FLOW_EN);
+ elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
+ (EMAC_TX_MODE_EXT_PAUSE_EN |
+ EMAC_TX_MODE_FLOW_EN));
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
+ if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
+ elink_bits_en(sc, emac_base +
+ EMAC_REG_EMAC_RX_MODE,
+ EMAC_RX_MODE_FLOW_EN);
+
+ if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
+ elink_bits_en(sc, emac_base +
+ EMAC_REG_EMAC_TX_MODE,
+ (EMAC_TX_MODE_EXT_PAUSE_EN |
+ EMAC_TX_MODE_FLOW_EN));
+ } else
+ elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
+ EMAC_TX_MODE_FLOW_EN);
+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
+ }
+#endif
/* KEEP_VLAN_TAG, promiscuous */
val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
@@ -1643,18 +2696,18 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
*/
elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
- PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
+ ELINK_DEBUG_P0(sc, "PFC is enabled");
/* Enable PFC again */
elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
- EMAC_REG_RX_PFC_MODE_RX_EN |
- EMAC_REG_RX_PFC_MODE_TX_EN |
- EMAC_REG_RX_PFC_MODE_PRIORITIES);
+ EMAC_REG_RX_PFC_MODE_RX_EN |
+ EMAC_REG_RX_PFC_MODE_TX_EN |
+ EMAC_REG_RX_PFC_MODE_PRIORITIES);
elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
- ((0x0101 <<
- EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
- (0x00ff <<
- EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
+ ((0x0101 <<
+ EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
+ (0x00ff <<
+ EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
}
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
@@ -1672,9 +2725,8 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
/* Enable emac for jumbo packets */
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
- (EMAC_RX_MTU_SIZE_JUMBO_ENA |
- (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
- ELINK_ETH_OVREHEAD)));
+ (EMAC_RX_MTU_SIZE_JUMBO_ENA |
+ (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD)));
/* Strip CRC */
REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);
@@ -1688,13 +2740,23 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);
val = 0;
if ((params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
+ ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
val = 1;
REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);
REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);
+#ifdef ELINK_INCLUDE_EMUL
+ if (CHIP_REV_IS_EMUL(sc)) {
+ /* Take the BigMac out of reset */
+ REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+ /* Enable access for bmac registers */
+ REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
+ } else
+#endif
REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
vars->mac_type = ELINK_MAC_TYPE_EMAC;
@@ -1706,13 +2768,13 @@ static void elink_update_pfc_bmac1(struct elink_params *params,
{
uint32_t wb_data[2];
struct bnx2x_softc *sc = params->sc;
- uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t val = 0x14;
if ((!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
- (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
+ ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
+ (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
/* Enable BigMAC to react on received Pause packets */
val |= (1 << 5);
wb_data[0] = val;
@@ -1723,7 +2785,7 @@ static void elink_update_pfc_bmac1(struct elink_params *params,
val = 0xc0;
if (!(params->feature_config_flags &
ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
- (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
+ (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
val |= 0x800000;
wb_data[0] = val;
wb_data[1] = 0;
@@ -1731,7 +2793,8 @@ static void elink_update_pfc_bmac1(struct elink_params *params,
}
static void elink_update_pfc_bmac2(struct elink_params *params,
- struct elink_vars *vars, uint8_t is_lb)
+ struct elink_vars *vars,
+ uint8_t is_lb)
{
/* Set rx control: Strip CRC and enable BigMAC to relay
* control packets to the system as well
@@ -1739,12 +2802,12 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
uint32_t wb_data[2];
struct bnx2x_softc *sc = params->sc;
uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t val = 0x14;
if ((!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
- (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
+ ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
+ (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
/* Enable BigMAC to react on received Pause packets */
val |= (1 << 5);
wb_data[0] = val;
@@ -1755,7 +2818,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
/* Tx control */
val = 0xc0;
if (!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
+ ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
val |= 0x800000;
wb_data[0] = val;
@@ -1763,21 +2826,21 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
- PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
+ ELINK_DEBUG_P0(sc, "PFC is enabled");
/* Enable PFC RX & TX & STATS and set 8 COS */
wb_data[0] = 0x0;
- wb_data[0] |= (1 << 0); /* RX */
- wb_data[0] |= (1 << 1); /* TX */
- wb_data[0] |= (1 << 2); /* Force initial Xon */
- wb_data[0] |= (1 << 3); /* 8 cos */
- wb_data[0] |= (1 << 5); /* STATS */
+ wb_data[0] |= (1 << 0); /* RX */
+ wb_data[0] |= (1 << 1); /* TX */
+ wb_data[0] |= (1 << 2); /* Force initial Xon */
+ wb_data[0] |= (1 << 3); /* 8 cos */
+ wb_data[0] |= (1 << 5); /* STATS */
wb_data[1] = 0;
REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
wb_data, 2);
/* Clear the force Xon */
wb_data[0] &= ~(1 << 2);
} else {
- PMD_DRV_LOG(DEBUG, sc, "PFC is disabled");
+ ELINK_DEBUG_P0(sc, "PFC is disabled");
/* Disable PFC RX & TX & STATS and set 8 COS */
wb_data[0] = 0x8;
wb_data[1] = 0;
@@ -1792,7 +2855,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
*/
val = 0x8000;
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
- val |= (1 << 16); /* enable automatic re-send */
+ val |= (1 << 16); /* enable automatic re-send */
wb_data[0] = val;
wb_data[1] = 0;
@@ -1800,10 +2863,10 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
wb_data, 2);
/* mac control */
- val = 0x3; /* Enable RX and TX */
+ val = 0x3; /* Enable RX and TX */
if (is_lb) {
- val |= 0x4; /* Local loopback */
- PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
+ val |= 0x4; /* Local loopback */
+ ELINK_DEBUG_P0(sc, "enable bmac loopback");
}
/* When PFC enabled, Pass pause frames towards the NIG. */
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
@@ -1815,47 +2878,46 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
}
/******************************************************************************
-* Description:
-* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
-* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
-******************************************************************************/
+ * Description:
+ * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
+ * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
+ ******************************************************************************/
static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,
- uint8_t cos_entry,
- uint32_t priority_mask,
- uint8_t port)
+ uint8_t cos_entry,
+ uint32_t priority_mask, uint8_t port)
{
uint32_t nig_reg_rx_priority_mask_add = 0;
switch (cos_entry) {
case 0:
- nig_reg_rx_priority_mask_add = (port) ?
- NIG_REG_P1_RX_COS0_PRIORITY_MASK :
- NIG_REG_P0_RX_COS0_PRIORITY_MASK;
+ nig_reg_rx_priority_mask_add = (port) ?
+ NIG_REG_P1_RX_COS0_PRIORITY_MASK :
+ NIG_REG_P0_RX_COS0_PRIORITY_MASK;
break;
case 1:
- nig_reg_rx_priority_mask_add = (port) ?
- NIG_REG_P1_RX_COS1_PRIORITY_MASK :
- NIG_REG_P0_RX_COS1_PRIORITY_MASK;
+ nig_reg_rx_priority_mask_add = (port) ?
+ NIG_REG_P1_RX_COS1_PRIORITY_MASK :
+ NIG_REG_P0_RX_COS1_PRIORITY_MASK;
break;
case 2:
- nig_reg_rx_priority_mask_add = (port) ?
- NIG_REG_P1_RX_COS2_PRIORITY_MASK :
- NIG_REG_P0_RX_COS2_PRIORITY_MASK;
+ nig_reg_rx_priority_mask_add = (port) ?
+ NIG_REG_P1_RX_COS2_PRIORITY_MASK :
+ NIG_REG_P0_RX_COS2_PRIORITY_MASK;
break;
case 3:
if (port)
- return ELINK_STATUS_ERROR;
- nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
+ return ELINK_STATUS_ERROR;
+ nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
break;
case 4:
if (port)
- return ELINK_STATUS_ERROR;
- nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
+ return ELINK_STATUS_ERROR;
+ nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
break;
case 5:
if (port)
- return ELINK_STATUS_ERROR;
- nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
+ return ELINK_STATUS_ERROR;
+ nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
break;
}
@@ -1863,7 +2925,6 @@ static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,
return ELINK_STATUS_OK;
}
-
static void elink_update_mng(struct elink_params *params, uint32_t link_status)
{
struct bnx2x_softc *sc = params->sc;
@@ -1873,31 +2934,20 @@ static void elink_update_mng(struct elink_params *params, uint32_t link_status)
port_mb[params->port].link_status), link_status);
}
-static void elink_update_link_attr(struct elink_params *params,
- uint32_t link_attr)
-{
- struct bnx2x_softc *sc = params->sc;
-
- if (SHMEM2_HAS(sc, link_attr_sync))
- REG_WR(sc, params->shmem2_base +
- offsetof(struct shmem2_region,
- link_attr_sync[params->port]), link_attr);
-}
-
static void elink_update_pfc_nig(struct elink_params *params,
- struct elink_nig_brb_pfc_port_params
- *nig_params)
+ __rte_unused struct elink_vars *vars,
+ struct elink_nig_brb_pfc_port_params *nig_params)
{
- uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en =
- 0;
+ uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0;
+ uint32_t llfc_out_en = 0;
uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
uint32_t pkt_priority_to_cos = 0;
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
int set_pfc = params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED;
- PMD_DRV_LOG(DEBUG, sc, "updating pfc nig parameters");
+ ELINK_FEATURE_CONFIG_PFC_ENABLED;
+ ELINK_DEBUG_P0(sc, "updating pfc nig parameters");
/* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
* MAC control frames (that are not pause packets)
@@ -1917,19 +2967,19 @@ static void elink_update_pfc_nig(struct elink_params *params,
else
ppp_enable = 1;
xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
- NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
+ NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
xcm_out_en = 0;
hwpfc_enable = 1;
- } else {
+ } else {
if (nig_params) {
llfc_out_en = nig_params->llfc_out_en;
llfc_enable = nig_params->llfc_enable;
pause_enable = nig_params->pause_enable;
- } else /* Default non PFC mode - PAUSE */
+ } else /* Default non PFC mode - PAUSE */
pause_enable = 1;
xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
- NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
+ NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
xcm_out_en = 1;
}
@@ -1966,9 +3016,7 @@ static void elink_update_pfc_nig(struct elink_params *params,
for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
elink_pfc_nig_rx_priority_mask(sc, i,
- nig_params->
- rx_cos_priority_mask[i],
- port);
+ nig_params->rx_cos_priority_mask[i], port);
REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
@@ -1979,13 +3027,13 @@ static void elink_update_pfc_nig(struct elink_params *params,
nig_params->llfc_low_priority_classes);
}
REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
- NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos);
+ NIG_REG_P0_PKT_PRIORITY_TO_COS,
+ pkt_priority_to_cos);
}
elink_status_t elink_update_pfc(struct elink_params *params,
- struct elink_vars *vars,
- struct elink_nig_brb_pfc_port_params
- *pfc_params)
+ struct elink_vars *vars,
+ struct elink_nig_brb_pfc_port_params *pfc_params)
{
/* The PFC and pause are orthogonal to one another, meaning when
* PFC is enabled, the pause are disabled, and when PFC is
@@ -1993,7 +3041,6 @@ elink_status_t elink_update_pfc(struct elink_params *params,
*/
uint32_t val;
struct bnx2x_softc *sc = params->sc;
- elink_status_t elink_status = ELINK_STATUS_OK;
uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
@@ -2004,24 +3051,24 @@ elink_status_t elink_update_pfc(struct elink_params *params,
elink_update_mng(params, vars->link_status);
/* Update NIG params */
- elink_update_pfc_nig(params, pfc_params);
+ elink_update_pfc_nig(params, vars, pfc_params);
if (!vars->link_up)
- return elink_status;
+ return ELINK_STATUS_OK;
- PMD_DRV_LOG(DEBUG, sc, "About to update PFC in BMAC");
+ ELINK_DEBUG_P0(sc, "About to update PFC in BMAC");
if (CHIP_IS_E3(sc)) {
if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
- elink_update_pfc_xmac(params, vars);
+ elink_update_pfc_xmac(params, vars, 0);
} else {
val = REG_RD(sc, MISC_REG_RESET_REG_2);
if ((val &
(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
== 0) {
- PMD_DRV_LOG(DEBUG, sc, "About to update PFC in EMAC");
+ ELINK_DEBUG_P0(sc, "About to update PFC in EMAC");
elink_emac_enable(params, vars, 0);
- return elink_status;
+ return ELINK_STATUS_OK;
}
if (CHIP_IS_E2(sc))
elink_update_pfc_bmac2(params, vars, bmac_loopback);
@@ -2035,20 +3082,21 @@ elink_status_t elink_update_pfc(struct elink_params *params,
val = 1;
REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val);
}
- return elink_status;
+ return ELINK_STATUS_OK;
}
static elink_status_t elink_bmac1_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t is_lb)
+ struct elink_vars *vars,
+ uint8_t is_lb)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t wb_data[2];
uint32_t val;
- PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC1");
+ ELINK_DEBUG_P0(sc, "Enabling BigMAC1");
/* XGXS control */
wb_data[0] = 0x3c;
@@ -2058,16 +3106,18 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params,
/* TX MAC SA */
wb_data[0] = ((params->mac_addr[2] << 24) |
- (params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | params->mac_addr[5]);
- wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
+ (params->mac_addr[3] << 16) |
+ (params->mac_addr[4] << 8) |
+ params->mac_addr[5]);
+ wb_data[1] = ((params->mac_addr[0] << 8) |
+ params->mac_addr[1]);
REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
/* MAC control */
val = 0x3;
if (is_lb) {
val |= 0x4;
- PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
+ ELINK_DEBUG_P0(sc, "enable bmac loopback");
}
wb_data[0] = val;
wb_data[1] = 0;
@@ -2095,20 +3145,30 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params,
wb_data[1] = 0;
REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
wb_data, 2);
+#ifdef ELINK_INCLUDE_EMUL
+ /* Fix for emulation */
+ if (CHIP_REV_IS_EMUL(sc)) {
+ wb_data[0] = 0xf000;
+ wb_data[1] = 0;
+ REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
+ wb_data, 2);
+ }
+#endif
return ELINK_STATUS_OK;
}
static elink_status_t elink_bmac2_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t is_lb)
+ struct elink_vars *vars,
+ uint8_t is_lb)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t wb_data[2];
- PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC2");
+ ELINK_DEBUG_P0(sc, "Enabling BigMAC2");
wb_data[0] = 0;
wb_data[1] = 0;
@@ -2125,9 +3185,11 @@ static elink_status_t elink_bmac2_enable(struct elink_params *params,
/* TX MAC SA */
wb_data[0] = ((params->mac_addr[2] << 24) |
- (params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | params->mac_addr[5]);
- wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
+ (params->mac_addr[3] << 16) |
+ (params->mac_addr[4] << 8) |
+ params->mac_addr[5]);
+ wb_data[1] = ((params->mac_addr[0] << 8) |
+ params->mac_addr[1]);
REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
wb_data, 2);
@@ -2162,8 +3224,8 @@ static elink_status_t elink_bmac2_enable(struct elink_params *params,
}
static elink_status_t elink_bmac_enable(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t is_lb, uint8_t reset_bmac)
+ struct elink_vars *vars,
+ uint8_t is_lb, uint8_t reset_bmac)
{
elink_status_t rc = ELINK_STATUS_OK;
uint8_t port = params->port;
@@ -2182,7 +3244,7 @@ static elink_status_t elink_bmac_enable(struct elink_params *params,
/* Enable access for bmac registers */
REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
- /* Enable BMAC according to BMAC type */
+ /* Enable BMAC according to BMAC type*/
if (CHIP_IS_E2(sc))
rc = elink_bmac2_enable(params, vars, is_lb);
else
@@ -2192,7 +3254,7 @@ static elink_status_t elink_bmac_enable(struct elink_params *params,
REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);
val = 0;
if ((params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
+ ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
val = 1;
REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);
@@ -2206,13 +3268,15 @@ static elink_status_t elink_bmac_enable(struct elink_params *params,
return rc;
}
-static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
+static void elink_set_bmac_rx(struct bnx2x_softc *sc,
+ __rte_unused uint32_t chip_id,
+ uint8_t port, uint8_t en)
{
uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t wb_data[2];
- uint32_t nig_bmac_enable =
- REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
+ uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN +
+ port * 4);
if (CHIP_IS_E2(sc))
bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
@@ -2220,7 +3284,8 @@ static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
/* Only if the bmac is out of reset */
if (REG_RD(sc, MISC_REG_RESET_REG_2) &
- (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {
+ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
+ nig_bmac_enable) {
/* Clear Rx Enable bit in BMAC_CONTROL register */
REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
if (en)
@@ -2233,7 +3298,8 @@ static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
}
static elink_status_t elink_pbf_update(struct elink_params *params,
- uint32_t flow_ctrl, uint32_t line_speed)
+ uint32_t flow_ctrl,
+ uint32_t line_speed)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
@@ -2246,7 +3312,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
/* Wait for init credit */
init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);
crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
- PMD_DRV_LOG(DEBUG, sc, "init_crd 0x%x crd 0x%x", init_crd, crd);
+ ELINK_DEBUG_P2(sc, "init_crd 0x%x crd 0x%x", init_crd, crd);
while ((init_crd != crd) && count) {
DELAY(1000 * 5);
@@ -2255,24 +3321,25 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
}
crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
if (init_crd != crd) {
- PMD_DRV_LOG(DEBUG, sc, "BUG! init_crd 0x%x != crd 0x%x",
- init_crd, crd);
+ ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x",
+ init_crd, crd);
return ELINK_STATUS_ERROR;
}
if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
line_speed == ELINK_SPEED_10 ||
line_speed == ELINK_SPEED_100 ||
- line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) {
+ line_speed == ELINK_SPEED_1000 ||
+ line_speed == ELINK_SPEED_2500) {
REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);
/* Update threshold */
REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);
/* Update init credit */
- init_crd = 778; /* (800-18-4) */
+ init_crd = 778; /* (800-18-4) */
} else {
uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
- ELINK_ETH_OVREHEAD) / 16;
+ ELINK_ETH_OVREHEAD) / 16;
REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
/* Update threshold */
REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);
@@ -2282,14 +3349,14 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
init_crd = thresh + 553 - 22;
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
- line_speed);
+ ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x",
+ line_speed);
return ELINK_STATUS_ERROR;
}
}
REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);
- PMD_DRV_LOG(DEBUG, sc, "PBF updated to speed %d credit %d",
- line_speed, init_crd);
+ ELINK_DEBUG_P2(sc, "PBF updated to speed %d credit %d",
+ line_speed, init_crd);
/* Probe the credit changes */
REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);
@@ -2317,7 +3384,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
* the emac_base for the CL45 read/writes operations
*/
static uint32_t elink_get_emac_base(struct bnx2x_softc *sc,
- uint32_t mdc_mdio_access, uint8_t port)
+ uint32_t mdc_mdio_access, uint8_t port)
{
uint32_t emac_base = 0;
switch (mdc_mdio_access) {
@@ -2365,7 +3432,8 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
/* Address */
tmp = ((phy->addr << 21) | (reg << 16) | val |
- EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY);
+ EMAC_MDIO_COMM_COMMAND_WRITE_22 |
+ EMAC_MDIO_COMM_START_BUSY);
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
for (i = 0; i < 50; i++) {
@@ -2378,7 +3446,7 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
}
}
if (tmp & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
+ ELINK_DEBUG_P0(sc, "write phy register failed");
rc = ELINK_STATUS_TIMEOUT;
}
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
@@ -2387,7 +3455,7 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
struct elink_phy *phy,
- uint16_t reg, uint16_t * ret_val)
+ uint16_t reg, uint16_t *ret_val)
{
uint32_t val, mode;
uint16_t i;
@@ -2400,7 +3468,8 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
/* Address */
val = ((phy->addr << 21) | (reg << 16) |
- EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY);
+ EMAC_MDIO_COMM_COMMAND_READ_22 |
+ EMAC_MDIO_COMM_START_BUSY);
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
for (i = 0; i < 50; i++) {
@@ -2408,13 +3477,13 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
- *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA);
+ *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
DELAY(5);
break;
}
}
if (val & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
+ ELINK_DEBUG_P0(sc, "read phy register failed");
*ret_val = 0;
rc = ELINK_STATUS_TIMEOUT;
@@ -2427,14 +3496,17 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
/* CL45 access functions */
/******************************************************************/
static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t devad,
- uint16_t reg, uint16_t * ret_val)
+ struct elink_phy *phy,
+ uint8_t devad, uint16_t reg, uint16_t *ret_val)
{
uint32_t val;
uint16_t i;
elink_status_t rc = ELINK_STATUS_OK;
+ uint32_t chip_id;
if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
- elink_set_mdio_clk(sc, phy->mdio_ctrl);
+ chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
+ ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
+ elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
}
if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
@@ -2442,7 +3514,8 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
EMAC_MDIO_STATUS_10MB);
/* Address */
val = ((phy->addr << 21) | (devad << 16) | reg |
- EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
+ EMAC_MDIO_COMM_COMMAND_ADDRESS |
+ EMAC_MDIO_COMM_START_BUSY);
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
for (i = 0; i < 50; i++) {
@@ -2455,8 +3528,9 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
}
}
if (val & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
- elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
+ ELINK_DEBUG_P0(sc, "read phy register failed");
+ elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);
+ /* "MDC/MDIO access timeout" */
*ret_val = 0;
rc = ELINK_STATUS_TIMEOUT;
@@ -2473,14 +3547,16 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
val = REG_RD(sc, phy->mdio_ctrl +
EMAC_REG_EMAC_MDIO_COMM);
if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
- *ret_val =
- (uint16_t) (val & EMAC_MDIO_COMM_DATA);
+ *ret_val = (uint16_t)
+ (val & EMAC_MDIO_COMM_DATA);
break;
}
}
if (val & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
- elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
+ ELINK_DEBUG_P0(sc, "read phy register failed");
+ elink_cb_event_log(sc,
+ ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);
+ /* "MDC/MDIO access timeout" */
*ret_val = 0;
rc = ELINK_STATUS_TIMEOUT;
@@ -2502,14 +3578,17 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
}
static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t devad,
- uint16_t reg, uint16_t val)
+ struct elink_phy *phy,
+ uint8_t devad, uint16_t reg, uint16_t val)
{
uint32_t tmp;
uint8_t i;
elink_status_t rc = ELINK_STATUS_OK;
+ uint32_t chip_id;
if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
- elink_set_mdio_clk(sc, phy->mdio_ctrl);
+ chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
+ ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
+ elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
}
if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
@@ -2518,7 +3597,8 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
/* Address */
tmp = ((phy->addr << 21) | (devad << 16) | reg |
- EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
+ EMAC_MDIO_COMM_COMMAND_ADDRESS |
+ EMAC_MDIO_COMM_START_BUSY);
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
for (i = 0; i < 50; i++) {
@@ -2531,8 +3611,9 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
}
}
if (tmp & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
- elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
+ ELINK_DEBUG_P0(sc, "write phy register failed");
+ elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);
+ /* "MDC/MDIO access timeout" */
rc = ELINK_STATUS_TIMEOUT;
} else {
@@ -2553,8 +3634,10 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
}
}
if (tmp & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
- elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
+ ELINK_DEBUG_P0(sc, "write phy register failed");
+ elink_cb_event_log(sc,
+ ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);
+ /* "MDC/MDIO access timeout" */
rc = ELINK_STATUS_TIMEOUT;
}
@@ -2581,14 +3664,14 @@ static uint8_t elink_eee_has_cap(struct elink_params *params)
struct bnx2x_softc *sc = params->sc;
if (REG_RD(sc, params->shmem2_base) <=
- offsetof(struct shmem2_region, eee_status[params->port]))
- return 0;
+ offsetof(struct shmem2_region, eee_status[params->port]))
+ return 0;
return 1;
}
static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,
- uint32_t * idle_timer)
+ uint32_t *idle_timer)
{
switch (nvram_mode) {
case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
@@ -2609,7 +3692,7 @@ static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,
}
static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer,
- uint32_t * nvram_mode)
+ uint32_t *nvram_mode)
{
switch (idle_timer) {
case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
@@ -2636,7 +3719,7 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params)
if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
- /* time value in eee_mode --> used directly */
+ /* time value in eee_mode --> used directly*/
eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
} else {
/* hsi value in eee_mode --> time */
@@ -2646,12 +3729,11 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params)
return 0;
}
} else {
- /* hsi values in nvram --> time */
+ /* hsi values in nvram --> time*/
eee_mode = ((REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config
- [params->
- port].eee_power_mode)) &
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].
+ eee_power_mode)) &
PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
@@ -2663,7 +3745,7 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params)
}
static elink_status_t elink_eee_set_timers(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
uint32_t eee_idle = 0, eee_mode;
struct bnx2x_softc *sc = params->sc;
@@ -2676,7 +3758,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,
} else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
(params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
(params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
- PMD_DRV_LOG(DEBUG, sc, "Error: Tx LPI is enabled with timer 0");
+ ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0");
return ELINK_STATUS_ERROR;
}
@@ -2685,7 +3767,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,
/* eee_idle in 1u --> eee_status in 16u */
eee_idle >>= 4;
vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
- SHMEM_EEE_TIME_OUTPUT_BIT;
+ SHMEM_EEE_TIME_OUTPUT_BIT;
} else {
if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
return ELINK_STATUS_ERROR;
@@ -2696,8 +3778,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,
}
static elink_status_t elink_eee_initial_config(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t mode)
+ struct elink_vars *vars, uint8_t mode)
{
vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
@@ -2716,8 +3797,8 @@ static elink_status_t elink_eee_initial_config(struct elink_params *params,
}
static elink_status_t elink_eee_disable(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
@@ -2732,9 +3813,8 @@ static elink_status_t elink_eee_disable(struct elink_phy *phy,
}
static elink_status_t elink_eee_advertise(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars,
- uint8_t modes)
+ struct elink_params *params,
+ struct elink_vars *vars, uint8_t modes)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val = 0;
@@ -2743,11 +3823,11 @@ static elink_status_t elink_eee_advertise(struct elink_phy *phy,
REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
if (modes & SHMEM_EEE_10G_ADV) {
- PMD_DRV_LOG(DEBUG, sc, "Advertise 10GBase-T EEE");
+ ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE");
val |= 0x8;
}
if (modes & SHMEM_EEE_1G_ADV) {
- PMD_DRV_LOG(DEBUG, sc, "Advertise 1GBase-T EEE");
+ ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE");
val |= 0x4;
}
@@ -2771,8 +3851,8 @@ static void elink_update_mng_eee(struct elink_params *params,
}
static void elink_eee_an_resolve(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t adv = 0, lp = 0;
@@ -2787,7 +3867,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
if (adv & 0x2) {
if (vars->line_speed == ELINK_SPEED_100)
neg = 1;
- PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 100M");
+ ELINK_DEBUG_P0(sc, "EEE negotiated - 100M");
}
}
if (lp & 0x14) {
@@ -2795,7 +3875,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
if (adv & 0x14) {
if (vars->line_speed == ELINK_SPEED_1000)
neg = 1;
- PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 1G");
+ ELINK_DEBUG_P0(sc, "EEE negotiated - 1G");
}
}
if (lp & 0x68) {
@@ -2803,7 +3883,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
if (adv & 0x68) {
if (vars->line_speed == ELINK_SPEED_10000)
neg = 1;
- PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 10G");
+ ELINK_DEBUG_P0(sc, "EEE negotiated - 10G");
}
}
@@ -2811,7 +3891,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
if (neg) {
- PMD_DRV_LOG(DEBUG, sc, "EEE is active");
+ ELINK_DEBUG_P0(sc, "EEE is active");
vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
}
}
@@ -2832,37 +3912,34 @@ static void elink_bsc_module_sel(struct elink_params *params)
dev_info.shared_hw_config.board));
i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
- SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
+ SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
/* Read I2C output value */
sfp_ctrl = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_cmn_pin_cfg));
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg));
i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
- PMD_DRV_LOG(DEBUG, sc, "Setting BSC switch");
+ ELINK_DEBUG_P0(sc, "Setting BSC switch");
for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
}
-static elink_status_t elink_bsc_read(struct elink_params *params,
- struct bnx2x_softc *sc,
- uint8_t sl_devid,
- uint16_t sl_addr,
- uint8_t lc_addr,
- uint8_t xfer_cnt, uint32_t * data_array)
+static elink_status_t elink_bsc_read(struct bnx2x_softc *sc,
+ uint8_t sl_devid,
+ uint16_t sl_addr,
+ uint8_t lc_addr,
+ uint8_t xfer_cnt,
+ uint32_t *data_array)
{
uint32_t val, i;
elink_status_t rc = ELINK_STATUS_OK;
if (xfer_cnt > 16) {
- PMD_DRV_LOG(DEBUG, sc, "invalid xfer_cnt %d. Max is 16 bytes",
- xfer_cnt);
+ ELINK_DEBUG_P1(sc, "invalid xfer_cnt %d. Max is 16 bytes",
+ xfer_cnt);
return ELINK_STATUS_ERROR;
}
- if (params)
- elink_bsc_module_sel(params);
xfer_cnt = 16 - lc_addr;
@@ -2875,11 +3952,11 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
val = (sl_devid << 16) | sl_addr;
REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
- /* Start xfer with 0 byte to update the address pointer ??? */
+ /* Start xfer with 0 byte to update the address pointer ???*/
val = (MCPR_IMC_COMMAND_ENABLE) |
- (MCPR_IMC_COMMAND_WRITE_OP <<
- MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
- (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
+ (MCPR_IMC_COMMAND_WRITE_OP <<
+ MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
+ (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
/* Poll for completion */
@@ -2889,8 +3966,8 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
DELAY(10);
val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
if (i++ > 1000) {
- PMD_DRV_LOG(DEBUG, sc, "wr 0 byte timed out after %d try",
- i);
+ ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try",
+ i);
rc = ELINK_STATUS_TIMEOUT;
break;
}
@@ -2900,10 +3977,10 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
/* Start xfer with read op */
val = (MCPR_IMC_COMMAND_ENABLE) |
- (MCPR_IMC_COMMAND_READ_OP <<
- MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
- (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
- (xfer_cnt);
+ (MCPR_IMC_COMMAND_READ_OP <<
+ MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
+ (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
+ (xfer_cnt);
REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
/* Poll for completion */
@@ -2913,8 +3990,7 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
DELAY(10);
val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
if (i++ > 1000) {
- PMD_DRV_LOG(DEBUG, sc,
- "rd op timed out after %d try", i);
+ ELINK_DEBUG_P1(sc, "rd op timed out after %d try", i);
rc = ELINK_STATUS_TIMEOUT;
break;
}
@@ -2926,17 +4002,18 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4));
#ifdef __BIG_ENDIAN
data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
- ((data_array[i] & 0x0000ff00) << 8) |
- ((data_array[i] & 0x00ff0000) >> 8) |
- ((data_array[i] & 0xff000000) >> 24);
+ ((data_array[i] & 0x0000ff00) << 8) |
+ ((data_array[i] & 0x00ff0000) >> 8) |
+ ((data_array[i] & 0xff000000) >> 24);
#endif
}
return rc;
}
static void elink_cl45_read_or_write(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t devad,
- uint16_t reg, uint16_t or_val)
+ struct elink_phy *phy,
+ uint8_t devad, uint16_t reg,
+ uint16_t or_val)
{
uint16_t val;
elink_cl45_read(sc, phy, devad, reg, &val);
@@ -2953,7 +4030,42 @@ static void elink_cl45_read_and_write(struct bnx2x_softc *sc,
elink_cl45_write(sc, phy, devad, reg, val & and_val);
}
-static uint8_t elink_get_warpcore_lane(struct elink_params *params)
+elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
+ uint8_t devad, uint16_t reg, uint16_t *ret_val)
+{
+ uint8_t phy_index;
+ /* Probe for the phy according to the given phy_addr, and execute
+ * the read request on it
+ */
+ for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
+ if (params->phy[phy_index].addr == phy_addr) {
+ return elink_cl45_read(params->sc,
+ ¶ms->phy[phy_index], devad,
+ reg, ret_val);
+ }
+ }
+ return ELINK_STATUS_ERROR;
+}
+
+elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
+ uint8_t devad, uint16_t reg, uint16_t val)
+{
+ uint8_t phy_index;
+ /* Probe for the phy according to the given phy_addr, and execute
+ * the write request on it
+ */
+ for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
+ if (params->phy[phy_index].addr == phy_addr) {
+ return elink_cl45_write(params->sc,
+ ¶ms->phy[phy_index], devad,
+ reg, val);
+ }
+ }
+ return ELINK_STATUS_ERROR;
+}
+
+static uint8_t elink_get_warpcore_lane(__rte_unused struct elink_phy *phy,
+ struct elink_params *params)
{
uint8_t lane = 0;
struct bnx2x_softc *sc = params->sc;
@@ -2987,14 +4099,16 @@ static uint8_t elink_get_warpcore_lane(struct elink_params *params)
port = port ^ 1;
lane = (port << 1) + path;
- } else { /* Two port mode - no port swap */
+ } else { /* Two port mode - no port swap */
/* Figure out path swap value */
- path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
+ path_swap_ovr =
+ REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
if (path_swap_ovr & 0x1) {
path_swap = (path_swap_ovr & 0x2);
} else {
- path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
+ path_swap =
+ REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
}
if (path_swap)
path = path ^ 1;
@@ -3004,6 +4118,7 @@ static uint8_t elink_get_warpcore_lane(struct elink_params *params)
return lane;
}
+
static void elink_set_aer_mmd(struct elink_params *params,
struct elink_phy *phy)
{
@@ -3012,13 +4127,13 @@ static void elink_set_aer_mmd(struct elink_params *params,
struct bnx2x_softc *sc = params->sc;
ser_lane = ((params->lane_config &
PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
- (phy->addr + ser_lane) : 0;
+ (phy->addr + ser_lane) : 0;
if (USES_WARPCORE(sc)) {
- aer_val = elink_get_warpcore_lane(params);
+ aer_val = elink_get_warpcore_lane(phy, params);
/* In Dual-lane mode, two lanes are joined together,
* so in order to configure them, the AER broadcast method is
* used here.
@@ -3051,7 +4166,7 @@ static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port)
DELAY(500);
REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
DELAY(500);
- /* Set Clause 45 */
+ /* Set Clause 45 */
REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0);
}
@@ -3059,7 +4174,7 @@ static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)
{
uint32_t val;
- PMD_DRV_LOG(DEBUG, sc, "elink_serdes_deassert");
+ ELINK_DEBUG_P0(sc, "elink_serdes_deassert");
val = ELINK_SERDES_RESET_BITS << (port * 16);
@@ -3094,7 +4209,7 @@ static void elink_xgxs_deassert(struct elink_params *params)
struct bnx2x_softc *sc = params->sc;
uint8_t port;
uint32_t val;
- PMD_DRV_LOG(DEBUG, sc, "elink_xgxs_deassert");
+ ELINK_DEBUG_P0(sc, "elink_xgxs_deassert");
port = params->port;
val = ELINK_XGXS_RESET_BITS << (port * 16);
@@ -3109,8 +4224,9 @@ static void elink_xgxs_deassert(struct elink_params *params)
static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
struct elink_params *params,
- uint16_t * ieee_fc)
+ uint16_t *ieee_fc)
{
+ struct bnx2x_softc *sc = params->sc;
*ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
/* Resolve pause mode and advertisement Please refer to Table
* 28B-3 of the 802.3ab-1999 spec
@@ -3120,12 +4236,12 @@ static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
case ELINK_FLOW_CTRL_AUTO:
switch (params->req_fc_auto_adv) {
case ELINK_FLOW_CTRL_BOTH:
+ case ELINK_FLOW_CTRL_RX:
*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
break;
- case ELINK_FLOW_CTRL_RX:
case ELINK_FLOW_CTRL_TX:
*ieee_fc |=
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
break;
default:
break;
@@ -3145,16 +4261,18 @@ static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
break;
}
- PMD_DRV_LOG(DEBUG, params->sc, "ieee_fc = 0x%x", *ieee_fc);
+ ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x", *ieee_fc);
}
-static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
+static void set_phy_vars(struct elink_params *params,
+ struct elink_vars *vars)
{
+ struct bnx2x_softc *sc = params->sc;
uint8_t actual_phy_idx, phy_index, link_cfg_idx;
uint8_t phy_config_swapped = params->multi_phy_config &
- PORT_HW_CFG_PHY_SWAPPED_ENABLED;
+ PORT_HW_CFG_PHY_SWAPPED_ENABLED;
for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
actual_phy_idx = phy_index;
if (phy_config_swapped) {
@@ -3164,26 +4282,26 @@ static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
actual_phy_idx = ELINK_EXT_PHY1;
}
params->phy[actual_phy_idx].req_flow_ctrl =
- params->req_flow_ctrl[link_cfg_idx];
+ params->req_flow_ctrl[link_cfg_idx];
params->phy[actual_phy_idx].req_line_speed =
- params->req_line_speed[link_cfg_idx];
+ params->req_line_speed[link_cfg_idx];
params->phy[actual_phy_idx].speed_cap_mask =
- params->speed_cap_mask[link_cfg_idx];
+ params->speed_cap_mask[link_cfg_idx];
params->phy[actual_phy_idx].req_duplex =
- params->req_duplex[link_cfg_idx];
+ params->req_duplex[link_cfg_idx];
if (params->req_line_speed[link_cfg_idx] ==
ELINK_SPEED_AUTO_NEG)
vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
- PMD_DRV_LOG(DEBUG, params->sc, "req_flow_ctrl %x, req_line_speed %x,"
- " speed_cap_mask %x",
- params->phy[actual_phy_idx].req_flow_ctrl,
- params->phy[actual_phy_idx].req_line_speed,
- params->phy[actual_phy_idx].speed_cap_mask);
+ ELINK_DEBUG_P3(sc, "req_flow_ctrl %x, req_line_speed %x,"
+ " speed_cap_mask %x",
+ params->phy[actual_phy_idx].req_flow_ctrl,
+ params->phy[actual_phy_idx].req_line_speed,
+ params->phy[actual_phy_idx].speed_cap_mask);
}
}
@@ -3201,38 +4319,57 @@ static void elink_ext_phy_set_pause(struct elink_params *params,
/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
}
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
}
- PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize 0x%x", val);
+ ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x", val);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
}
-static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
-{ /* LD LP */
- switch (pause_result) { /* ASYM P ASYM P */
- case 0xb: /* 1 0 1 1 */
+static void elink_pause_resolve(__rte_unused struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars,
+ uint32_t pause_result)
+{
+ struct bnx2x_softc *sc = params->sc;
+ /* LD LP */
+ switch (pause_result) { /* ASYM P ASYM P */
+ case 0xb: /* 1 0 1 1 */
+ ELINK_DEBUG_P0(sc, "Flow Control: TX only");
vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
break;
- case 0xe: /* 1 1 1 0 */
+ case 0xe: /* 1 1 1 0 */
+ ELINK_DEBUG_P0(sc, "Flow Control: RX only");
vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
break;
- case 0x5: /* 0 1 0 1 */
- case 0x7: /* 0 1 1 1 */
- case 0xd: /* 1 1 0 1 */
- case 0xf: /* 1 1 1 1 */
+ case 0x5: /* 0 1 0 1 */
+ case 0x7: /* 0 1 1 1 */
+ case 0xd: /* 1 1 0 1 */
+ case 0xf: /* 1 1 1 1 */
+ /* If the user selected to advertise RX ONLY,
+ * although we advertised both, need to enable
+ * RX only.
+ */
+
+ if (params->req_fc_auto_adv == ELINK_FLOW_CTRL_BOTH) {
+ ELINK_DEBUG_P0(sc, "Flow Control: RX & TX");
vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
+ } else {
+ ELINK_DEBUG_P0(sc, "Flow Control: RX only");
+ vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
+ }
break;
-
default:
+ ELINK_DEBUG_P0(sc, "Flow Control: None");
+ vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
break;
}
if (pause_result & (1 << 0))
@@ -3246,22 +4383,23 @@ static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
struct elink_params *params,
struct elink_vars *vars)
{
- uint16_t ld_pause; /* local */
- uint16_t lp_pause; /* link partner */
+ uint16_t ld_pause; /* local */
+ uint16_t lp_pause; /* link partner */
uint16_t pause_result;
struct bnx2x_softc *sc = params->sc;
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) {
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) {
elink_cl22_read(sc, phy, 0x4, &ld_pause);
elink_cl22_read(sc, phy, 0x5, &lp_pause);
- } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) {
- uint8_t lane = elink_get_warpcore_lane(params);
+ } else if (CHIP_IS_E3(sc) &&
+ ELINK_SINGLE_MEDIA_DIRECT(params)) {
+ uint8_t lane = elink_get_warpcore_lane(phy, params);
uint16_t gp_status, gp_mask;
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
&gp_status);
gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
- lane;
+ lane;
if ((gp_status & gp_mask) == gp_mask) {
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_ADV_PAUSE, &ld_pause);
@@ -3287,16 +4425,18 @@ static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
}
- pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
- pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
- PMD_DRV_LOG(DEBUG, sc, "Ext PHY pause result 0x%x", pause_result);
- elink_pause_resolve(vars, pause_result);
+ pause_result = (ld_pause &
+ MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
+ pause_result |= (lp_pause &
+ MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
+ ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x", pause_result);
+ elink_pause_resolve(phy, params, vars, pause_result);
}
static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint8_t ret = 0;
vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
@@ -3314,7 +4454,6 @@ static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
}
return ret;
}
-
/******************************************************************/
/* Warpcore section */
/******************************************************************/
@@ -3323,19 +4462,31 @@ static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
* init configuration, and set/clear SGMII flag. Internal
* phy init is done purely in phy_init stage.
*/
-#define WC_TX_DRIVER(post2, idriver, ipre) \
+#define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
(idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
- (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
+ (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
+ (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
#define WC_TX_FIR(post, main, pre) \
((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
(main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
(pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
+static void elink_update_link_attr(struct elink_params *params,
+ uint32_t link_attr)
+{
+ struct bnx2x_softc *sc = params->sc;
+
+ if (SHMEM2_HAS(sc, link_attr_sync))
+ REG_WR(sc, params->shmem2_base +
+ offsetof(struct shmem2_region,
+ link_attr_sync[params->port]), link_attr);
+}
+
static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars)
+ __rte_unused struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t i;
@@ -3358,7 +4509,7 @@ static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
};
- PMD_DRV_LOG(DEBUG, sc, "Enabling 20G-KR2");
+ ELINK_DEBUG_P0(sc, "Enabling 20G-KR2");
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));
@@ -3368,15 +4519,16 @@ static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
reg_set[i].val);
/* Start KR2 work-around timer which handles BNX2X8073 link-parner */
- vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
- elink_update_link_attr(params, vars->link_attr_sync);
+ params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
+ elink_update_link_attr(params, params->link_attr_sync);
}
static void elink_disable_kr2(struct elink_params *params,
- struct elink_vars *vars, struct elink_phy *phy)
+ struct elink_vars *vars,
+ struct elink_phy *phy)
{
struct bnx2x_softc *sc = params->sc;
- uint32_t i;
+ int i;
static struct elink_reg_set reg_set[] = {
/* Step 1 - Program the TX/RX alignment markers */
{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
@@ -3395,13 +4547,13 @@ static void elink_disable_kr2(struct elink_params *params,
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
};
- PMD_DRV_LOG(DEBUG, sc, "Disabling 20G-KR2");
+ ELINK_DEBUG_P0(sc, "Disabling 20G-KR2");
- for (i = 0; i < ARRAY_SIZE(reg_set); i++)
+ for (i = 0; i < (int)ARRAY_SIZE(reg_set); i++)
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
reg_set[i].val);
- vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
- elink_update_link_attr(params, vars->link_attr_sync);
+ params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
+ elink_update_link_attr(params, params->link_attr_sync);
vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
}
@@ -3411,7 +4563,7 @@ static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Configure WC for LPI pass through");
+ ELINK_DEBUG_P0(sc, "Configure WC for LPI pass through");
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
@@ -3423,7 +4575,7 @@ static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
{
/* Restart autoneg on the leading lane only */
struct bnx2x_softc *sc = params->sc;
- uint16_t lane = elink_get_warpcore_lane(params);
+ uint16_t lane = elink_get_warpcore_lane(phy, params);
CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
MDIO_AER_BLOCK_AER_REG, lane);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
@@ -3435,9 +4587,9 @@ static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars)
-{
- uint16_t lane, i, cl72_ctrl, an_adv = 0;
+ struct elink_vars *vars) {
+ uint16_t lane, i, cl72_ctrl, an_adv = 0, val;
+ uint32_t wc_lane_config;
struct bnx2x_softc *sc = params->sc;
static struct elink_reg_set reg_set[] = {
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
@@ -3449,7 +4601,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
{MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
};
- PMD_DRV_LOG(DEBUG, sc, "Enable Auto Negotiation for KR");
+ ELINK_DEBUG_P0(sc, "Enable Auto Negotiation for KR");
/* Set to default registers that may be overridden by 10G force */
for (i = 0; i < ARRAY_SIZE(reg_set); i++)
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
@@ -3471,11 +4623,11 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
/* Enable CL37 1G Parallel Detect */
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
- PMD_DRV_LOG(DEBUG, sc, "Advertize 1G");
+ ELINK_DEBUG_P0(sc, "Advertize 1G");
}
if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
- (vars->line_speed == ELINK_SPEED_10000)) {
+ (vars->line_speed == ELINK_SPEED_10000)) {
/* Check adding advertisement for 10G KR */
an_adv |= (1 << 7);
/* Enable 10G Parallel Detect */
@@ -3485,23 +4637,25 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
elink_set_aer_mmd(params, phy);
- PMD_DRV_LOG(DEBUG, sc, "Advertize 10G");
+ ELINK_DEBUG_P0(sc, "Advertize 10G");
}
/* Set Transmit PMD settings */
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
- WC_TX_DRIVER(0x02, 0x06, 0x09));
+ WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
/* Configure the next lane if dual mode */
if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1),
- WC_TX_DRIVER(0x02, 0x06, 0x09));
+ WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0);
+ MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
+ 0x03f0);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0);
+ MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
+ 0x03f0);
/* Advertised speeds */
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
@@ -3515,14 +4669,13 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
/* Enable CL37 BAM */
if (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- default_cfg)) &
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg)) &
PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
1);
- PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
+ ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR");
}
/* Advertise pause */
@@ -3533,7 +4686,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
/* Over 1G - AN local device user page 1 */
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
+ MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
@@ -3544,7 +4697,8 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_RX1_PCI_CTRL +
- (0x10 * lane), (1 << 11));
+ (0x10 * lane),
+ (1 << 11));
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
@@ -3552,6 +4706,31 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
elink_warpcore_enable_AN_KR2(phy, params, vars);
} else {
+ /* Enable Auto-Detect to support 1G over CL37 as well */
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
+ wc_lane_config = REG_RD(sc, params->shmem_base +
+ offsetof(struct shmem_region, dev_info.
+ shared_hw_config.wc_lane_config));
+ elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
+ /* Force cl48 sync_status LOW to avoid getting stuck in CL73
+ * parallel-detect loop when CL73 and CL37 are enabled.
+ */
+ val |= 1 << 11;
+
+ /* Restore Polarity settings in case it was run over by
+ * previous link owner
+ */
+ if (wc_lane_config &
+ (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
+ val |= 3 << 2;
+ else
+ val &= ~(3 << 2);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
+ val);
+
elink_disable_kr2(params, vars, phy);
}
@@ -3560,7 +4739,8 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
}
static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
- struct elink_params *params)
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val16, i, lane;
@@ -3568,7 +4748,7 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
/* Disable Autoneg */
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
- 0x3f00},
+ 0x3f00},
{MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
{MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
@@ -3581,7 +4761,7 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
reg_set[i].val);
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
/* Global registers */
CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
MDIO_AER_BLOCK_AER_REG, 0);
@@ -3611,7 +4791,8 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
/* Turn TX scramble payload only the 64/66 scrambler */
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_TX66_CONTROL, 0x9);
/* Turn RX scramble payload only the 64/66 scrambler */
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
@@ -3632,7 +4813,7 @@ static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
-
+ uint32_t ifir_val, ipost2_val, ipre_driver_val;
/* Hold rxSeqStart */
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
@@ -3677,38 +4858,59 @@ static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
if (is_xfi) {
misc1_val |= 0x5;
tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
- tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
+ tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
} else {
cfg_tap_val = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->
- port].sfi_tap_values));
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].
+ sfi_tap_values));
tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
- tx_drv_brdct = (cfg_tap_val &
- PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
- PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
-
misc1_val |= 0x9;
/* TAP values are controlled by nvram, if value there isn't 0 */
if (tx_equal)
- tap_val = (uint16_t) tx_equal;
+ tap_val = (uint16_t)tx_equal;
else
tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
- if (tx_drv_brdct)
- tx_driver_val =
- WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06);
- else
- tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
+ ifir_val = DEFAULT_TX_DRV_IFIR;
+ ipost2_val = DEFAULT_TX_DRV_POST2;
+ ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
+ tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
+
+ /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all
+ * configuration.
+ */
+ if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
+ PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
+ PORT_HW_CFG_TX_DRV_POST2_MASK)) {
+ ifir_val = (cfg_tap_val &
+ PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
+ PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
+ ipre_driver_val = (cfg_tap_val &
+ PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
+ >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
+ ipost2_val = (cfg_tap_val &
+ PORT_HW_CFG_TX_DRV_POST2_MASK) >>
+ PORT_HW_CFG_TX_DRV_POST2_SHIFT;
+ }
+
+ if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
+ tx_drv_brdct = (cfg_tap_val &
+ PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
+ PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
+ }
+
+ tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
+ ipre_driver_val, ifir_val);
}
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
/* Set Transmit PMD settings */
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX_FIR_TAP,
tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
@@ -3756,7 +4958,8 @@ static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1));
- elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
+ elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
+ MDIO_AN_REG_CTRL, 0);
/* Turn off CL73 */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_CL73_USERB0_CTRL, &val);
@@ -3792,7 +4995,8 @@ static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
}
static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint16_t lane)
+ struct elink_phy *phy,
+ uint16_t lane)
{
/* Rx0 anaRxControl1G */
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
@@ -3802,13 +5006,17 @@ static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX66_SCW0, 0xE070);
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX66_SCW1, 0xC0D0);
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX66_SCW2, 0xA0B0);
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX66_SCW3, 0x8090);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
@@ -3837,7 +5045,7 @@ static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
MDIO_WC_REG_TX_FIR_TAP_ENABLE));
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
- WC_TX_DRIVER(0x02, 0x02, 0x02));
+ WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
}
static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
@@ -3859,7 +5067,7 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
0x1000);
- PMD_DRV_LOG(DEBUG, sc, "set SGMII AUTONEG");
+ ELINK_DEBUG_P0(sc, "set SGMII AUTONEG");
} else {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
@@ -3874,9 +5082,8 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
val16 |= 0x0040;
break;
default:
- PMD_DRV_LOG(DEBUG, sc,
- "Speed not supported: 0x%x",
- phy->req_line_speed);
+ ELINK_DEBUG_P1(sc,
+ "Speed not supported: 0x%x", phy->req_line_speed);
return;
}
@@ -3884,13 +5091,13 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
val16 |= 0x0100;
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
+ MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
- PMD_DRV_LOG(DEBUG, sc, "set SGMII force speed %d",
- phy->req_line_speed);
+ ELINK_DEBUG_P1(sc, "set SGMII force speed %d",
+ phy->req_line_speed);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
- PMD_DRV_LOG(DEBUG, sc, " (readback) %x", val16);
+ ELINK_DEBUG_P1(sc, " (readback) %x", val16);
}
/* SGMII Slave mode and disable signal detect */
@@ -3902,28 +5109,31 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
digctrl_kx1 &= 0xff4a;
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1);
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
+ digctrl_kx1);
/* Turn off parallel detect */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
- (digctrl_kx2 & ~(1 << 2)));
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
+ (digctrl_kx2 & ~(1 << 2)));
/* Re-enable parallel detect */
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
- (digctrl_kx2 | (1 << 2)));
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
+ (digctrl_kx2 | (1 << 2)));
/* Enable autodet */
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
- (digctrl_kx1 | 0x10));
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
+ (digctrl_kx1 | 0x10));
}
+
static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t reset)
+ struct elink_phy *phy,
+ uint8_t reset)
{
uint16_t val;
/* Take lane out of reset after configuration is finished */
@@ -3936,7 +5146,7 @@ static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL5_MISC6, val);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_DIGITAL5_MISC6, &val);
+ MDIO_WC_REG_DIGITAL5_MISC6, &val);
}
/* Clear SFI/XFI link settings registers */
@@ -3952,11 +5162,11 @@ static void elink_warpcore_clear_regs(struct elink_phy *phy,
{MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
- 0x0195},
+ 0x0195},
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
- 0x0007},
+ 0x0007},
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
- 0x0002},
+ 0x0002},
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
{MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
{MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
@@ -3970,28 +5180,28 @@ static void elink_warpcore_clear_regs(struct elink_phy *phy,
elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
wc_regs[i].val);
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990);
}
static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
+ __rte_unused uint32_t chip_id,
uint32_t shmem_base,
uint8_t port,
- uint8_t * gpio_num,
- uint8_t * gpio_port)
+ uint8_t *gpio_num,
+ uint8_t *gpio_port)
{
uint32_t cfg_pin;
*gpio_num = 0;
*gpio_port = 0;
if (CHIP_IS_E3(sc)) {
cfg_pin = (REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_sfp_ctrl)) &
- PORT_HW_CFG_E3_MOD_ABS_MASK) >>
- PORT_HW_CFG_E3_MOD_ABS_SHIFT;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].e3_sfp_ctrl)) &
+ PORT_HW_CFG_E3_MOD_ABS_MASK) >>
+ PORT_HW_CFG_E3_MOD_ABS_SHIFT;
/* Should not happen. This function called upon interrupt
* triggered by GPIO ( since EPIO can only generate interrupts
@@ -4001,9 +5211,9 @@ static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
*/
if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
(cfg_pin > PIN_CFG_GPIO3_P1)) {
- PMD_DRV_LOG(DEBUG, sc,
- "No cfg pin %x for module detect indication",
- cfg_pin);
+ ELINK_DEBUG_P1(sc,
+ "No cfg pin %x for module detect indication",
+ cfg_pin);
return ELINK_STATUS_ERROR;
}
@@ -4017,12 +5227,13 @@ static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
return ELINK_STATUS_OK;
}
-static int elink_is_sfp_module_plugged(struct elink_params *params)
+static int elink_is_sfp_module_plugged(__rte_unused struct elink_phy *phy,
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint8_t gpio_num, gpio_port;
uint32_t gpio_val;
- if (elink_get_mod_abs_int_cfg(sc,
+ if (elink_get_mod_abs_int_cfg(sc, params->chip_id,
params->shmem_base, params->port,
&gpio_num, &gpio_port) != ELINK_STATUS_OK)
return 0;
@@ -4034,17 +5245,16 @@ static int elink_is_sfp_module_plugged(struct elink_params *params)
else
return 0;
}
-
static int elink_warpcore_get_sigdet(struct elink_phy *phy,
struct elink_params *params)
{
uint16_t gp2_status_reg0, lane;
struct bnx2x_softc *sc = params->sc;
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
- &gp2_status_reg0);
+ &gp2_status_reg0);
return (gp2_status_reg0 >> (8 + lane)) & 0x1;
}
@@ -4063,38 +5273,35 @@ static void elink_warpcore_config_runtime(struct elink_phy *phy,
return;
if (vars->rx_tx_asic_rst) {
- uint16_t lane = elink_get_warpcore_lane(params);
+ uint16_t lane = elink_get_warpcore_lane(phy, params);
serdes_net_if = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config
- [params->port].
- default_cfg)) &
- PORT_HW_CFG_NET_SERDES_IF_MASK);
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg)) &
+ PORT_HW_CFG_NET_SERDES_IF_MASK);
switch (serdes_net_if) {
case PORT_HW_CFG_NET_SERDES_IF_KR:
/* Do we get link yet? */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
&gp_status1);
- lnkup = (gp_status1 >> (8 + lane)) & 0x1; /* 1G */
- /*10G KR */
+ lnkup = (gp_status1 >> (8 + lane)) & 0x1;/* 1G */
+ /*10G KR*/
lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1;
if (lnkup_kr || lnkup) {
vars->rx_tx_asic_rst = 0;
} else {
- /* Reset the lane to see if link comes up. */
+ /* Reset the lane to see if link comes up.*/
elink_warpcore_reset_lane(sc, phy, 1);
elink_warpcore_reset_lane(sc, phy, 0);
/* Restart Autoneg */
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
- MDIO_WC_REG_IEEE0BLK_MIICNTL,
- 0x1200);
+ MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
vars->rx_tx_asic_rst--;
- PMD_DRV_LOG(DEBUG, sc, "0x%x retry left",
- vars->rx_tx_asic_rst);
+ ELINK_DEBUG_P1(sc, "0x%x retry left",
+ vars->rx_tx_asic_rst);
}
break;
@@ -4102,29 +5309,29 @@ static void elink_warpcore_config_runtime(struct elink_phy *phy,
break;
}
- }
- /*params->rx_tx_asic_rst */
+ } /*params->rx_tx_asic_rst*/
}
static void elink_warpcore_config_sfi(struct elink_phy *phy,
struct elink_params *params)
{
- uint16_t lane = elink_get_warpcore_lane(params);
-
+ uint16_t lane = elink_get_warpcore_lane(phy, params);
+ struct bnx2x_softc *sc = params->sc;
elink_warpcore_clear_regs(phy, params, lane);
if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
ELINK_SPEED_10000) &&
(phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
- PMD_DRV_LOG(DEBUG, params->sc, "Setting 10G SFI");
+ ELINK_DEBUG_P0(sc, "Setting 10G SFI");
elink_warpcore_set_10G_XFI(phy, params, 0);
} else {
- PMD_DRV_LOG(DEBUG, params->sc, "Setting 1G Fiber");
+ ELINK_DEBUG_P0(sc, "Setting 1G Fiber");
elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
}
}
static void elink_sfp_e3_set_transmitter(struct elink_params *params,
- struct elink_phy *phy, uint8_t tx_en)
+ struct elink_phy *phy,
+ uint8_t tx_en)
{
struct bnx2x_softc *sc = params->sc;
uint32_t cfg_pin;
@@ -4133,9 +5340,9 @@ static void elink_sfp_e3_set_transmitter(struct elink_params *params,
cfg_pin = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
dev_info.port_hw_config[port].e3_sfp_ctrl)) &
- PORT_HW_CFG_E3_TX_LASER_MASK;
+ PORT_HW_CFG_E3_TX_LASER_MASK;
/* Set the !tx_en since this pin is DISABLE_TX_LASER */
- PMD_DRV_LOG(DEBUG, sc, "Setting WC TX to %d", tx_en);
+ ELINK_DEBUG_P1(sc, "Setting WC TX to %d", tx_en);
/* For 20G, the expected pin to be used is 3 pins after the current */
elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
@@ -4143,22 +5350,21 @@ static void elink_sfp_e3_set_transmitter(struct elink_params *params,
elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
}
-static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static void elink_warpcore_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint32_t serdes_net_if;
uint8_t fiber_mode;
- uint16_t lane = elink_get_warpcore_lane(params);
+ uint16_t lane = elink_get_warpcore_lane(phy, params);
serdes_net_if = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- default_cfg)) &
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg)) &
PORT_HW_CFG_NET_SERDES_IF_MASK);
- PMD_DRV_LOG(DEBUG, sc,
- "Begin Warpcore init, link_speed %d, "
- "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if);
+ ELINK_DEBUG_P2(sc, "Begin Warpcore init, link_speed %d, "
+ "serdes_net_if = 0x%x",
+ vars->line_speed, serdes_net_if);
elink_set_aer_mmd(params, phy);
elink_warpcore_reset_lane(sc, phy, 1);
vars->phy_flags |= PHY_XGXS_FLAG;
@@ -4167,7 +5373,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
((phy->req_line_speed == ELINK_SPEED_100) ||
(phy->req_line_speed == ELINK_SPEED_10)))) {
vars->phy_flags |= PHY_SGMII_FLAG;
- PMD_DRV_LOG(DEBUG, sc, "Setting SGMII mode");
+ ELINK_DEBUG_P0(sc, "Setting SGMII mode");
elink_warpcore_clear_regs(phy, params, lane);
elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
} else {
@@ -4177,27 +5383,28 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
if (params->loopback_mode != ELINK_LOOPBACK_EXT)
elink_warpcore_enable_AN_KR(phy, params, vars);
else {
- PMD_DRV_LOG(DEBUG, sc, "Setting KR 10G-Force");
- elink_warpcore_set_10G_KR(phy, params);
+ ELINK_DEBUG_P0(sc, "Setting KR 10G-Force");
+ elink_warpcore_set_10G_KR(phy, params, vars);
}
break;
case PORT_HW_CFG_NET_SERDES_IF_XFI:
elink_warpcore_clear_regs(phy, params, lane);
if (vars->line_speed == ELINK_SPEED_10000) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 10G XFI");
+ ELINK_DEBUG_P0(sc, "Setting 10G XFI");
elink_warpcore_set_10G_XFI(phy, params, 1);
} else {
if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
- PMD_DRV_LOG(DEBUG, sc, "1G Fiber");
+ ELINK_DEBUG_P0(sc, "1G Fiber");
fiber_mode = 1;
} else {
- PMD_DRV_LOG(DEBUG, sc, "10/100/1G SGMII");
+ ELINK_DEBUG_P0(sc, "10/100/1G SGMII");
fiber_mode = 0;
}
elink_warpcore_set_sgmii_speed(phy,
- params,
- fiber_mode, 0);
+ params,
+ fiber_mode,
+ 0);
}
break;
@@ -4209,7 +5416,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
*/
if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
(params->loopback_mode == ELINK_LOOPBACK_EXT)) {
- if (elink_is_sfp_module_plugged(params))
+ if (elink_is_sfp_module_plugged(phy, params))
elink_sfp_module_detection(phy, params);
else
elink_sfp_e3_set_transmitter(params,
@@ -4221,10 +5428,10 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
if (vars->line_speed != ELINK_SPEED_20000) {
- PMD_DRV_LOG(DEBUG, sc, "Speed not supported yet");
- return 0;
+ ELINK_DEBUG_P0(sc, "Speed not supported yet");
+ return;
}
- PMD_DRV_LOG(DEBUG, sc, "Setting 20G DXGXS");
+ ELINK_DEBUG_P0(sc, "Setting 20G DXGXS");
elink_warpcore_set_20G_DXGXS(sc, phy, lane);
/* Issue Module detection */
@@ -4234,23 +5441,21 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
if (!params->loopback_mode) {
elink_warpcore_enable_AN_KR(phy, params, vars);
} else {
- PMD_DRV_LOG(DEBUG, sc, "Setting KR 20G-Force");
+ ELINK_DEBUG_P0(sc, "Setting KR 20G-Force");
elink_warpcore_set_20G_force_KR2(phy, params);
}
break;
default:
- PMD_DRV_LOG(DEBUG, sc,
- "Unsupported Serdes Net Interface 0x%x",
- serdes_net_if);
- return 0;
+ ELINK_DEBUG_P1(sc,
+ "Unsupported Serdes Net Interface 0x%x",
+ serdes_net_if);
+ return;
}
}
/* Take lane out of reset after configuration is finished */
elink_warpcore_reset_lane(sc, phy, 0);
- PMD_DRV_LOG(DEBUG, sc, "Exit config init");
-
- return 0;
+ ELINK_DEBUG_P0(sc, "Exit config init");
}
static void elink_warpcore_link_reset(struct elink_phy *phy,
@@ -4277,11 +5482,12 @@ static void elink_warpcore_link_reset(struct elink_phy *phy,
MDIO_AER_BLOCK_AER_REG, 0);
/* Enable 1G MDIO (1-copy) */
elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10);
+ MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
+ ~0x10);
elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
/* Disable CL36 PCS Tx */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
@@ -4313,8 +5519,8 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t val16;
uint32_t lane;
- PMD_DRV_LOG(DEBUG, sc, "Setting Warpcore loopback type %x, speed %d",
- params->loopback_mode, phy->req_line_speed);
+ ELINK_DEBUG_P2(sc, "Setting Warpcore loopback type %x, speed %d",
+ params->loopback_mode, phy->req_line_speed);
if (phy->req_line_speed < ELINK_SPEED_10000 ||
phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
@@ -4328,14 +5534,15 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,
MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
0x10);
/* Set 1G loopback based on lane (1-copy) */
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
val16 |= (1 << lane);
if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
val16 |= (2 << lane);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16);
+ MDIO_WC_REG_XGXSBLK1_LANECTRL2,
+ val16);
/* Switch back to 4-copy registers */
elink_set_aer_mmd(params, phy);
@@ -4349,8 +5556,10 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,
}
}
+
+
static void elink_sync_link(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t link_10g_plus;
@@ -4358,21 +5567,23 @@ static void elink_sync_link(struct elink_params *params,
vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
if (vars->link_up) {
- PMD_DRV_LOG(DEBUG, sc, "phy link up");
+ ELINK_DEBUG_P0(sc, "phy link up");
+ ELINK_DEBUG_P1(sc, "link status = %x", vars->link_status);
vars->phy_link_up = 1;
vars->duplex = DUPLEX_FULL;
- switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
+ switch (vars->link_status &
+ LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
case ELINK_LINK_10THD:
vars->duplex = DUPLEX_HALF;
- /* Fall through */
+ /* Fall thru */
case ELINK_LINK_10TFD:
vars->line_speed = ELINK_SPEED_10;
break;
case ELINK_LINK_100TXHD:
vars->duplex = DUPLEX_HALF;
- /* Fall through */
+ /* Fall thru */
case ELINK_LINK_100T4:
case ELINK_LINK_100TXFD:
vars->line_speed = ELINK_SPEED_100;
@@ -4380,14 +5591,14 @@ static void elink_sync_link(struct elink_params *params,
case ELINK_LINK_1000THD:
vars->duplex = DUPLEX_HALF;
- /* Fall through */
+ /* Fall thru */
case ELINK_LINK_1000TFD:
vars->line_speed = ELINK_SPEED_1000;
break;
case ELINK_LINK_2500THD:
vars->duplex = DUPLEX_HALF;
- /* Fall through */
+ /* Fall thru */
case ELINK_LINK_2500TFD:
vars->line_speed = ELINK_SPEED_2500;
break;
@@ -4419,7 +5630,8 @@ static void elink_sync_link(struct elink_params *params,
vars->phy_flags &= ~PHY_SGMII_FLAG;
}
if (vars->line_speed &&
- USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000))
+ USES_WARPCORE(sc) &&
+ (vars->line_speed == ELINK_SPEED_1000))
vars->phy_flags |= PHY_SGMII_FLAG;
/* Anything 10 and over uses the bmac */
link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
@@ -4435,8 +5647,8 @@ static void elink_sync_link(struct elink_params *params,
else
vars->mac_type = ELINK_MAC_TYPE_EMAC;
}
- } else { /* Link down */
- PMD_DRV_LOG(DEBUG, sc, "phy link down");
+ } else { /* Link down */
+ ELINK_DEBUG_P0(sc, "phy link down");
vars->phy_link_up = 0;
@@ -4480,44 +5692,44 @@ void elink_link_status_update(struct elink_params *params,
elink_sync_link(params, vars);
/* Sync media type */
sync_offset = params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].media_type);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].media_type);
media_types = REG_RD(sc, sync_offset);
params->phy[ELINK_INT_PHY].media_type =
- (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
- PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
+ (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
+ PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
params->phy[ELINK_EXT_PHY1].media_type =
- (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
- PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
+ (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
+ PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
params->phy[ELINK_EXT_PHY2].media_type =
- (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
- PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
- PMD_DRV_LOG(DEBUG, sc, "media_types = 0x%x", media_types);
+ (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
+ PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
+ ELINK_DEBUG_P1(sc, "media_types = 0x%x", media_types);
/* Sync AEU offset */
sync_offset = params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].aeu_int_mask);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].aeu_int_mask);
vars->aeu_int_mask = REG_RD(sc, sync_offset);
/* Sync PFC status */
if (vars->link_status & LINK_STATUS_PFC_ENABLED)
params->feature_config_flags |=
- ELINK_FEATURE_CONFIG_PFC_ENABLED;
+ ELINK_FEATURE_CONFIG_PFC_ENABLED;
else
params->feature_config_flags &=
- ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
+ ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
if (SHMEM2_HAS(sc, link_attr_sync))
- vars->link_attr_sync = SHMEM2_RD(sc,
+ params->link_attr_sync = SHMEM2_RD(sc,
link_attr_sync[params->port]);
- PMD_DRV_LOG(DEBUG, sc, "link_status 0x%x phy_link_up %x int_mask 0x%x",
- vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
- PMD_DRV_LOG(DEBUG, sc, "line_speed %x duplex %x flow_ctrl 0x%x",
- vars->line_speed, vars->duplex, vars->flow_ctrl);
+ ELINK_DEBUG_P3(sc, "link_status 0x%x phy_link_up %x int_mask 0x%x",
+ vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
+ ELINK_DEBUG_P3(sc, "line_speed %x duplex %x flow_ctrl 0x%x",
+ vars->line_speed, vars->duplex, vars->flow_ctrl);
}
static void elink_set_master_ln(struct elink_params *params,
@@ -4532,7 +5744,8 @@ static void elink_set_master_ln(struct elink_params *params,
/* Set the master_ln for AN */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_XGXS_BLOCK2,
- MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln);
+ MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
+ &new_master_ln);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_XGXS_BLOCK2,
@@ -4541,8 +5754,8 @@ static void elink_set_master_ln(struct elink_params *params,
}
static elink_status_t elink_reset_unicore(struct elink_params *params,
- struct elink_phy *phy,
- uint8_t set_serdes)
+ struct elink_phy *phy,
+ uint8_t set_serdes)
{
struct bnx2x_softc *sc = params->sc;
uint16_t mii_control;
@@ -4555,7 +5768,8 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
MDIO_COMBO_IEEE0_MII_CONTROL,
- (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
+ (mii_control |
+ MDIO_COMBO_IEEO_MII_CONTROL_RESET));
if (set_serdes)
elink_set_serdes_access(sc, params->port);
@@ -4566,7 +5780,8 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,
/* The reset erased the previous bank value */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
DELAY(5);
@@ -4574,10 +5789,12 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,
}
}
- elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
- // " Port %d",
+ elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port);
+ /* "Warning: PHY was not initialized,"
+ * " Port %d",
+ */
- PMD_DRV_LOG(DEBUG, sc, "BUG! XGXS is still in reset!");
+ ELINK_DEBUG_P0(sc, "BUG! XGXS is still in reset!");
return ELINK_STATUS_ERROR;
}
@@ -4631,31 +5848,35 @@ static void elink_set_parallel_detection(struct elink_phy *phy,
uint16_t control2;
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+ &control2);
if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
else
control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
- PMD_DRV_LOG(DEBUG, sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
- phy->speed_cap_mask, control2);
+ ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
+ phy->speed_cap_mask, control2);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+ control2);
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
- (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
- PMD_DRV_LOG(DEBUG, sc, "XGXS");
+ (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
+ ELINK_DEBUG_P0(sc, "XGXS");
CL22_WR_OVER_CL45(sc, phy,
- MDIO_REG_BANK_10G_PARALLEL_DETECT,
- MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
- MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
+ MDIO_REG_BANK_10G_PARALLEL_DETECT,
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_10G_PARALLEL_DETECT,
MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
&control2);
+
control2 |=
MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
@@ -4675,7 +5896,8 @@ static void elink_set_parallel_detection(struct elink_phy *phy,
static void elink_set_autoneg(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars, uint8_t enable_cl73)
+ struct elink_vars *vars,
+ uint8_t enable_cl73)
{
struct bnx2x_softc *sc = params->sc;
uint16_t reg_val;
@@ -4688,7 +5910,7 @@ static void elink_set_autoneg(struct elink_phy *phy,
/* CL37 Autoneg Enabled */
if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
- else /* CL37 Autoneg Disabled */
+ else /* CL37 Autoneg Disabled */
reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
@@ -4702,7 +5924,7 @@ static void elink_set_autoneg(struct elink_phy *phy,
MDIO_REG_BANK_SERDES_DIGITAL,
MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
@@ -4716,7 +5938,8 @@ static void elink_set_autoneg(struct elink_phy *phy,
/* Enable TetonII and BAM autoneg */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_BAM_NEXT_PAGE,
- MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val);
+ MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+ ®_val);
if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
/* Enable BAM aneg Mode and TetonII aneg Mode */
reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
@@ -4728,40 +5951,45 @@ static void elink_set_autoneg(struct elink_phy *phy,
}
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_BAM_NEXT_PAGE,
- MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val);
+ MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+ reg_val);
if (enable_cl73) {
/* Enable Cl73 FSM status bits */
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_USERB0,
- MDIO_CL73_USERB0_CL73_UCTRL, 0xe);
+ MDIO_CL73_USERB0_CL73_UCTRL,
+ 0xe);
- /* Enable BAM Station Manager */
+ /* Enable BAM Station Manager*/
CL22_WR_OVER_CL45(sc, phy,
- MDIO_REG_BANK_CL73_USERB0,
- MDIO_CL73_USERB0_CL73_BAM_CTRL1,
- MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
- MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
- |
- MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
+ MDIO_REG_BANK_CL73_USERB0,
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1,
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
/* Advertise CL73 link speeds */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB1,
- MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
- if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
+ MDIO_CL73_IEEEB1_AN_ADV2,
+ ®_val);
+ if (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
- if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
+ if (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB1,
- MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
+ MDIO_CL73_IEEEB1_AN_ADV2,
+ reg_val);
/* CL73 Autoneg Enabled */
reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
- } else /* CL73 Autoneg Disabled */
+ } else /* CL73 Autoneg Disabled */
reg_val = 0;
CL22_WR_OVER_CL45(sc, phy,
@@ -4777,7 +6005,7 @@ static void elink_program_serdes(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t reg_val;
- /* Program duplex, disable autoneg and sgmii */
+ /* Program duplex, disable autoneg and sgmii*/
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
@@ -4797,7 +6025,7 @@ static void elink_program_serdes(struct elink_phy *phy,
MDIO_REG_BANK_SERDES_DIGITAL,
MDIO_SERDES_DIGITAL_MISC1, ®_val);
/* Clearing the speed value before setting the right speed */
- PMD_DRV_LOG(DEBUG, sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
+ ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
@@ -4810,7 +6038,7 @@ static void elink_program_serdes(struct elink_phy *phy,
MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
if (vars->line_speed == ELINK_SPEED_10000)
reg_val |=
- MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
+ MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
}
CL22_WR_OVER_CL45(sc, phy,
@@ -4831,10 +6059,12 @@ static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
val |= MDIO_OVER_1G_UP1_10G;
CL22_WR_OVER_CL45(sc, phy,
- MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);
+ MDIO_REG_BANK_OVER_1G,
+ MDIO_OVER_1G_UP1, val);
CL22_WR_OVER_CL45(sc, phy,
- MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);
+ MDIO_REG_BANK_OVER_1G,
+ MDIO_OVER_1G_UP3, 0x400);
}
static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
@@ -4865,7 +6095,7 @@ static void elink_restart_autoneg(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t mii_control;
- PMD_DRV_LOG(DEBUG, sc, "elink_restart_autoneg");
+ ELINK_DEBUG_P0(sc, "elink_restart_autoneg");
/* Enable and restart BAM/CL37 aneg */
if (enable_cl73) {
@@ -4878,16 +6108,17 @@ static void elink_restart_autoneg(struct elink_phy *phy,
MDIO_REG_BANK_CL73_IEEEB0,
MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
(mii_control |
- MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
- MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
} else {
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
- PMD_DRV_LOG(DEBUG, sc,
- "elink_restart_autoneg mii_control before = 0x%x",
- mii_control);
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
+ ELINK_DEBUG_P1(sc,
+ "elink_restart_autoneg mii_control before = 0x%x",
+ mii_control);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
MDIO_COMBO_IEEE0_MII_CONTROL,
@@ -4908,7 +6139,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+ &control1);
control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
/* Set sgmii mode (and not fiber) */
control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
@@ -4916,7 +6148,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+ control1);
/* If forced speed */
if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
@@ -4925,7 +6158,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
@@ -4933,30 +6167,32 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
switch (vars->line_speed) {
case ELINK_SPEED_100:
mii_control |=
- MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
+ MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
break;
case ELINK_SPEED_1000:
mii_control |=
- MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
+ MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
break;
case ELINK_SPEED_10:
/* There is nothing to set for 10M */
break;
default:
/* Invalid speed for SGMII */
- PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
- vars->line_speed);
+ ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x",
+ vars->line_speed);
break;
}
/* Setting the full duplex */
if (phy->req_duplex == DUPLEX_FULL)
- mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
+ mii_control |=
+ MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL, mii_control);
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ mii_control);
- } else { /* AN mode */
+ } else { /* AN mode */
/* Enable and restart AN */
elink_restart_autoneg(phy, params, 0);
}
@@ -4965,8 +6201,7 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
/* Link management
*/
static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
- struct elink_params
- *params)
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint16_t pd_10g, status2_1000x;
@@ -4974,34 +6209,38 @@ static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
return ELINK_STATUS_OK;
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
+ MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
+ &status2_1000x);
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
+ MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
+ &status2_1000x);
if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
- PMD_DRV_LOG(DEBUG, sc, "1G parallel detect link on port %d",
- params->port);
- return ELINK_STATUS_ERROR;
+ ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d",
+ params->port);
+ return 1;
}
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_10G_PARALLEL_DETECT,
- MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
+ &pd_10g);
if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
- PMD_DRV_LOG(DEBUG, sc, "10G parallel detect link on port %d",
- params->port);
- return ELINK_STATUS_ERROR;
+ ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d",
+ params->port);
+ return 1;
}
return ELINK_STATUS_OK;
}
static void elink_update_adv_fc(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars, uint32_t gp_status)
+ struct elink_vars *vars,
+ uint32_t gp_status)
{
- uint16_t ld_pause; /* local driver */
- uint16_t lp_pause; /* link partner */
+ uint16_t ld_pause; /* local driver */
+ uint16_t lp_pause; /* link partner */
uint16_t pause_result;
struct bnx2x_softc *sc = params->sc;
if ((gp_status &
@@ -5012,37 +6251,42 @@ static void elink_update_adv_fc(struct elink_phy *phy,
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB1,
- MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause);
+ MDIO_CL73_IEEEB1_AN_ADV1,
+ &ld_pause);
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB1,
- MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);
+ MDIO_CL73_IEEEB1_AN_LP_ADV1,
+ &lp_pause);
pause_result = (ld_pause &
MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
pause_result |= (lp_pause &
MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
- PMD_DRV_LOG(DEBUG, sc, "pause_result CL73 0x%x", pause_result);
+ ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x", pause_result);
} else {
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
+ &ld_pause);
CL22_RD_OVER_CL45(sc, phy,
- MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
- &lp_pause);
+ MDIO_REG_BANK_COMBO_IEEE0,
+ MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
+ &lp_pause);
pause_result = (ld_pause &
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;
pause_result |= (lp_pause &
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;
- PMD_DRV_LOG(DEBUG, sc, "pause_result CL37 0x%x", pause_result);
+ ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x", pause_result);
}
- elink_pause_resolve(vars, pause_result);
+ elink_pause_resolve(phy, params, vars, pause_result);
}
static void elink_flow_ctrl_resolve(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars, uint32_t gp_status)
+ struct elink_vars *vars,
+ uint32_t gp_status)
{
+ struct bnx2x_softc *sc = params->sc;
vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
/* Resolve from gp_status in case of AN complete and not sgmii */
@@ -5062,7 +6306,7 @@ static void elink_flow_ctrl_resolve(struct elink_phy *phy,
}
elink_update_adv_fc(phy, params, vars, gp_status);
}
- PMD_DRV_LOG(DEBUG, params->sc, "flow_ctrl 0x%x", vars->flow_ctrl);
+ ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x", vars->flow_ctrl);
}
static void elink_check_fallback_to_cl37(struct elink_phy *phy,
@@ -5070,14 +6314,16 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
{
struct bnx2x_softc *sc = params->sc;
uint16_t rx_status, ustat_val, cl37_fsm_received;
- PMD_DRV_LOG(DEBUG, sc, "elink_check_fallback_to_cl37");
+ ELINK_DEBUG_P0(sc, "elink_check_fallback_to_cl37");
/* Step 1: Make sure signal is detected */
CL22_RD_OVER_CL45(sc, phy,
- MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);
+ MDIO_REG_BANK_RX0,
+ MDIO_RX0_RX_STATUS,
+ &rx_status);
if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
(MDIO_RX0_RX_STATUS_SIGDET)) {
- PMD_DRV_LOG(DEBUG, sc, "Signal is not detected. Restoring CL73."
- "rx_status(0x80b0) = 0x%x", rx_status);
+ ELINK_DEBUG_P1(sc, "Signal is not detected. Restoring CL73."
+ "rx_status(0x80b0) = 0x%x", rx_status);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB0,
MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
@@ -5087,14 +6333,15 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
/* Step 2: Check CL73 state machine */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_USERB0,
- MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val);
+ MDIO_CL73_USERB0_CL73_USTAT1,
+ &ustat_val);
if ((ustat_val &
(MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
(MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
- MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
- PMD_DRV_LOG(DEBUG, sc, "CL73 state-machine is not stable. "
- "ustat_val(0x8371) = 0x%x", ustat_val);
+ MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
+ ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. "
+ "ustat_val(0x8371) = 0x%x", ustat_val);
return;
}
/* Step 3: Check CL37 Message Pages received to indicate LP
@@ -5102,14 +6349,16 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
*/
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_REMOTE_PHY,
- MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received);
+ MDIO_REMOTE_PHY_MISC_RX_STATUS,
+ &cl37_fsm_received);
if ((cl37_fsm_received &
(MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
- MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
+ MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
(MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
- MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
- PMD_DRV_LOG(DEBUG, sc, "No CL37 FSM were received. "
- "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received);
+ MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
+ ELINK_DEBUG_P1(sc, "No CL37 FSM were received. "
+ "misc_rx_status(0x8330) = 0x%x",
+ cl37_fsm_received);
return;
}
/* The combined cl37/cl73 fsm state information indicating that
@@ -5121,34 +6370,38 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
/* Disable CL73 */
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB0,
- MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+ 0);
/* Restart CL37 autoneg */
elink_restart_autoneg(phy, params, 0);
- PMD_DRV_LOG(DEBUG, sc, "Disabling CL73, and restarting CL37 autoneg");
+ ELINK_DEBUG_P0(sc, "Disabling CL73, and restarting CL37 autoneg");
}
static void elink_xgxs_an_resolve(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars, uint32_t gp_status)
+ struct elink_vars *vars,
+ uint32_t gp_status)
{
if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
- vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+ vars->link_status |=
+ LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
if (elink_direct_parallel_detect_used(phy, params))
- vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
+ vars->link_status |=
+ LINK_STATUS_PARALLEL_DETECTION_USED;
}
-
static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
- struct elink_params *params __rte_unused,
- struct elink_vars *vars,
- uint16_t is_link_up,
- uint16_t speed_mask,
- uint16_t is_duplex)
+ struct elink_params *params,
+ struct elink_vars *vars,
+ uint16_t is_link_up,
+ uint16_t speed_mask,
+ uint16_t is_duplex)
{
+ struct bnx2x_softc *sc = params->sc;
if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
if (is_link_up) {
- PMD_DRV_LOG(DEBUG, params->sc, "phy link up");
+ ELINK_DEBUG_P0(sc, "phy link up");
vars->phy_link_up = 1;
vars->link_status |= LINK_STATUS_LINK_UP;
@@ -5189,9 +6442,9 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
case ELINK_GP_STATUS_5G:
case ELINK_GP_STATUS_6G:
- PMD_DRV_LOG(DEBUG, params->sc,
- "link speed unsupported gp_status 0x%x",
- speed_mask);
+ ELINK_DEBUG_P1(sc,
+ "link speed unsupported gp_status 0x%x",
+ speed_mask);
return ELINK_STATUS_ERROR;
case ELINK_GP_STATUS_10G_KX4:
@@ -5209,13 +6462,13 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
vars->link_status |= ELINK_LINK_20GTFD;
break;
default:
- PMD_DRV_LOG(DEBUG, params->sc,
- "link speed unsupported gp_status 0x%x",
- speed_mask);
+ ELINK_DEBUG_P1(sc,
+ "link speed unsupported gp_status 0x%x",
+ speed_mask);
return ELINK_STATUS_ERROR;
}
- } else { /* link_down */
- PMD_DRV_LOG(DEBUG, params->sc, "phy link down");
+ } else { /* link_down */
+ ELINK_DEBUG_P0(sc, "phy link down");
vars->phy_link_up = 0;
@@ -5223,14 +6476,16 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
vars->mac_type = ELINK_MAC_TYPE_NONE;
}
- PMD_DRV_LOG(DEBUG, params->sc, " phy_link_up %x line_speed %d",
+ ELINK_DEBUG_P2(sc, " in elink_get_link_speed_duplex vars->link_status = %x, vars->duplex = %x",
+ vars->link_status, vars->duplex);
+ ELINK_DEBUG_P2(sc, " phy_link_up %x line_speed %d",
vars->phy_link_up, vars->line_speed);
return ELINK_STATUS_OK;
}
-static uint8_t elink_link_settings_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static elink_status_t elink_link_settings_status(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
@@ -5240,14 +6495,23 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
/* Read gp_status */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_GP_STATUS,
- MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);
- if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
+ MDIO_GP_STATUS_TOP_AN_STATUS1,
+ &gp_status);
+ if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) {
duplex = DUPLEX_FULL;
+ ELINK_DEBUG_P1(sc, "duplex status read from phy is = %x",
+ duplex);
+ } else {
+ ELINK_DEBUG_P1(sc, "phy status does not allow interface to be FULL_DUPLEX : %x",
+ gp_status);
+ }
+
+
if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
link_up = 1;
speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
- PMD_DRV_LOG(DEBUG, sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
- gp_status, link_up, speed_mask);
+ ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
+ gp_status, link_up, speed_mask);
rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
duplex);
if (rc == ELINK_STATUS_ERROR)
@@ -5261,7 +6525,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
elink_xgxs_an_resolve(phy, params, vars,
gp_status);
}
- } else { /* Link_down */
+ } else { /* Link_down */
if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
ELINK_SINGLE_MEDIA_DIRECT(params)) {
/* Check signal is detected */
@@ -5269,7 +6533,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
}
}
- /* Read LP advertised speeds */
+ /* Read LP advertised speeds*/
if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
(vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
uint16_t val;
@@ -5279,61 +6543,69 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
MDIO_OVER_1G_LP_UP1, &val);
if (val & MDIO_OVER_1G_UP1_2_5G)
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
}
- PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
- vars->duplex, vars->flow_ctrl, vars->link_status);
+ ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
+ vars->duplex, vars->flow_ctrl, vars->link_status);
return rc;
}
-static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t lane;
uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
elink_status_t rc = ELINK_STATUS_OK;
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
/* Read gp_status */
- if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
+ if ((params->loopback_mode) &&
+ (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
link_up &= 0x1;
+ ELINK_DEBUG_P1(sc, "params->loopback_mode link_up read = %x",
+ link_up);
} else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
- (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
+ (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
uint16_t temp_link_up;
- elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);
- elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);
- PMD_DRV_LOG(DEBUG, sc, "PCS RX link status = 0x%x-->0x%x",
- temp_link_up, link_up);
+ elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
+ 1, &temp_link_up);
+ elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
+ 1, &link_up);
+ ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x",
+ temp_link_up, link_up);
link_up &= (1 << 2);
if (link_up)
elink_ext_phy_resolve_fc(phy, params, vars);
} else {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
- PMD_DRV_LOG(DEBUG, sc, "0x81d1 = 0x%x", gp_status1);
+ MDIO_WC_REG_GP2_STATUS_GP_2_1,
+ &gp_status1);
+ ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x", gp_status1);
/* Check for either KR, 1G, or AN up. */
link_up = ((gp_status1 >> 8) |
- (gp_status1 >> 12) | (gp_status1)) & (1 << lane);
+ (gp_status1 >> 12) |
+ (gp_status1)) &
+ (1 << lane);
if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
uint16_t an_link;
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
@@ -5341,6 +6613,8 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_STATUS, &an_link);
link_up |= (an_link & (1 << 2));
+ ELINK_DEBUG_P2(sc, "an_link = %x, link_up = %x",
+ an_link, link_up);
}
if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
uint16_t pd, gp_status4;
@@ -5351,7 +6625,7 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
&gp_status4);
if (gp_status4 & ((1 << 12) << lane))
vars->link_status |=
- LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+ LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
/* Check parallel detect used */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
@@ -5359,13 +6633,19 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
&pd);
if (pd & (1 << 15))
vars->link_status |=
- LINK_STATUS_PARALLEL_DETECTION_USED;
+ LINK_STATUS_PARALLEL_DETECTION_USED;
+ ELINK_DEBUG_P2(sc, "pd = %x, link_status = %x",
+ pd, vars->link_status);
}
elink_ext_phy_resolve_fc(phy, params, vars);
vars->duplex = duplex;
+ ELINK_DEBUG_P3(sc, " ELINK_SINGLE_MEDIA_DIRECT duplex %x flow_ctrl 0x%x link_status 0x%x",
+ vars->duplex, vars->flow_ctrl,
+ vars->link_status);
}
}
-
+ ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
+ vars->duplex, vars->flow_ctrl, vars->link_status);
if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
ELINK_SINGLE_MEDIA_DIRECT(params)) {
uint16_t val;
@@ -5375,24 +6655,28 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
-
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ ELINK_DEBUG_P2(sc, "val = %x, link_status = %x",
+ val, vars->link_status);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
if (val & MDIO_OVER_1G_UP1_2_5G)
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ ELINK_DEBUG_P2(sc, "val = %x, link_status = %x",
+ val, vars->link_status);
}
+
if (lane < 2) {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
@@ -5400,12 +6684,12 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
}
- PMD_DRV_LOG(DEBUG, sc, "lane %d gp_speed 0x%x", lane, gp_speed);
+ ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x", lane, gp_speed);
if ((lane & 1) == 0)
gp_speed <<= 8;
gp_speed &= 0x3f00;
- link_up = ! !link_up;
+ link_up = !!link_up;
/* Reset the TX FIFO to fix SGMII issue */
rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
@@ -5416,11 +6700,10 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
(!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
- PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
- vars->duplex, vars->flow_ctrl, vars->link_status);
+ ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
+ vars->duplex, vars->flow_ctrl, vars->link_status);
return rc;
}
-
static void elink_set_gmii_tx_driver(struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
@@ -5431,7 +6714,8 @@ static void elink_set_gmii_tx_driver(struct elink_params *params)
/* Read precomp */
CL22_RD_OVER_CL45(sc, phy,
- MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);
+ MDIO_REG_BANK_OVER_1G,
+ MDIO_OVER_1G_LP_UP2, &lp_up2);
/* Bits [10:7] at lp_up2, positioned at [15:12] */
lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
@@ -5442,32 +6726,36 @@ static void elink_set_gmii_tx_driver(struct elink_params *params)
return;
for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
- bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
+ bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
CL22_RD_OVER_CL45(sc, phy,
- bank, MDIO_TX0_TX_DRIVER, &tx_driver);
+ bank,
+ MDIO_TX0_TX_DRIVER, &tx_driver);
/* Replace tx_driver bits [15:12] */
- if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
+ if (lp_up2 !=
+ (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
tx_driver |= lp_up2;
CL22_WR_OVER_CL45(sc, phy,
- bank, MDIO_TX0_TX_DRIVER, tx_driver);
+ bank,
+ MDIO_TX0_TX_DRIVER, tx_driver);
}
}
}
static elink_status_t elink_emac_program(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
uint16_t mode = 0;
- PMD_DRV_LOG(DEBUG, sc, "setting link speed & duplex");
+ ELINK_DEBUG_P0(sc, "setting link speed & duplex");
elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +
EMAC_REG_EMAC_MODE,
(EMAC_MODE_25G_MODE |
- EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX));
+ EMAC_MODE_PORT_MII_10M |
+ EMAC_MODE_HALF_DUPLEX));
switch (vars->line_speed) {
case ELINK_SPEED_10:
mode |= EMAC_MODE_PORT_MII_10M;
@@ -5487,15 +6775,16 @@ static elink_status_t elink_emac_program(struct elink_params *params,
default:
/* 10G not valid for EMAC */
- PMD_DRV_LOG(DEBUG, sc,
- "Invalid line_speed 0x%x", vars->line_speed);
+ ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x",
+ vars->line_speed);
return ELINK_STATUS_ERROR;
}
if (vars->duplex == DUPLEX_HALF)
mode |= EMAC_MODE_HALF_DUPLEX;
elink_bits_en(sc,
- GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode);
+ GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE,
+ mode);
elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
return ELINK_STATUS_OK;
@@ -5512,24 +6801,26 @@ static void elink_set_preemphasis(struct elink_phy *phy,
bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) {
CL22_WR_OVER_CL45(sc, phy,
bank,
- MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]);
+ MDIO_RX0_RX_EQ_BOOST,
+ phy->rx_preemphasis[i]);
}
for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
CL22_WR_OVER_CL45(sc, phy,
bank,
- MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]);
+ MDIO_TX0_TX_DRIVER,
+ phy->tx_preemphasis[i]);
}
}
-static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static void elink_xgxs_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
+ struct bnx2x_softc *sc = params->sc;
uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
- (params->loopback_mode == ELINK_LOOPBACK_XGXS));
-
+ (params->loopback_mode == ELINK_LOOPBACK_XGXS));
if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
(params->feature_config_flags &
@@ -5540,7 +6831,7 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
(ELINK_SINGLE_MEDIA_DIRECT(params) &&
params->loopback_mode == ELINK_LOOPBACK_EXT)) {
- PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, no AN");
+ ELINK_DEBUG_P0(sc, "not SGMII, no AN");
/* Disable autoneg */
elink_set_autoneg(phy, params, vars, 0);
@@ -5548,8 +6839,8 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
/* Program speed and duplex */
elink_program_serdes(phy, params, vars);
- } else { /* AN_mode */
- PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, AN");
+ } else { /* AN_mode */
+ ELINK_DEBUG_P0(sc, "not SGMII, AN");
/* AN enabled */
elink_set_brcm_cl37_advertisement(phy, params);
@@ -5565,18 +6856,16 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
elink_restart_autoneg(phy, params, enable_cl73);
}
- } else { /* SGMII mode */
- PMD_DRV_LOG(DEBUG, params->sc, "SGMII");
+ } else { /* SGMII mode */
+ ELINK_DEBUG_P0(sc, "SGMII");
elink_initialize_sgmii_process(phy, params, vars);
}
-
- return 0;
}
static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
elink_status_t rc;
vars->phy_flags |= PHY_XGXS_FLAG;
@@ -5614,28 +6903,32 @@ static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
}
static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- struct elink_params *params)
+ struct elink_phy *phy,
+ struct elink_params *params)
{
uint16_t cnt, ctrl;
/* Wait for soft reset to get cleared up to 1 sec */
for (cnt = 0; cnt < 1000; cnt++) {
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
- elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl);
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE)
+ elink_cl22_read(sc, phy,
+ MDIO_PMA_REG_CTRL, &ctrl);
else
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_CTRL, &ctrl);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL, &ctrl);
if (!(ctrl & (1 << 15)))
break;
DELAY(1000 * 1);
}
if (cnt == 1000)
- elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
- // " Port %d",
+ elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED,
+ params->port);
+ /* "Warning: PHY was not initialized,"
+ * " Port %d",
+ */
- PMD_DRV_LOG(DEBUG, sc, "control reg 0x%x (after %d ms)", ctrl, cnt);
+ ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)", ctrl, cnt);
return cnt;
}
@@ -5653,37 +6946,38 @@ static void elink_link_int_enable(struct elink_params *params)
} else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
ELINK_NIG_MASK_XGXS0_LINK_STATUS);
- PMD_DRV_LOG(DEBUG, sc, "enabled XGXS interrupt");
+ ELINK_DEBUG_P0(sc, "enabled XGXS interrupt");
if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
- params->phy[ELINK_INT_PHY].type !=
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
+ params->phy[ELINK_INT_PHY].type !=
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
mask |= ELINK_NIG_MASK_MI_INT;
- PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
+ ELINK_DEBUG_P0(sc, "enabled external phy int");
}
- } else { /* SerDes */
+ } else { /* SerDes */
mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
- PMD_DRV_LOG(DEBUG, sc, "enabled SerDes interrupt");
+ ELINK_DEBUG_P0(sc, "enabled SerDes interrupt");
if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
- params->phy[ELINK_INT_PHY].type !=
- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
+ params->phy[ELINK_INT_PHY].type !=
+ PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
mask |= ELINK_NIG_MASK_MI_INT;
- PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
+ ELINK_DEBUG_P0(sc, "enabled external phy int");
}
}
- elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);
+ elink_bits_en(sc,
+ NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
+ mask);
- PMD_DRV_LOG(DEBUG, sc, "port %x, is_xgxs %x, int_status 0x%x", port,
- (params->switch_cfg == ELINK_SWITCH_CFG_10G),
- REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
- PMD_DRV_LOG(DEBUG, sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
- REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
- REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
- REG_RD(sc,
- NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
- PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
- REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
- REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
+ ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x", port,
+ (params->switch_cfg == ELINK_SWITCH_CFG_10G),
+ REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
+ ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
+ REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
+ REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
+ REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
+ ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x",
+ REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
+ REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
}
static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
@@ -5696,17 +6990,20 @@ static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
* so in this case we need to write the status to clear the XOR
*/
/* Read Latched signals */
- latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);
- PMD_DRV_LOG(DEBUG, sc, "latch_status = 0x%x", latch_status);
- /* Handle only those with latched-signal=up. */
+ latch_status = REG_RD(sc,
+ NIG_REG_LATCH_STATUS_0 + port * 8);
+ ELINK_DEBUG_P1(sc, "latch_status = 0x%x", latch_status);
+ /* Handle only those with latched-signal=up.*/
if (exp_mi_int)
elink_bits_en(sc,
NIG_REG_STATUS_INTERRUPT_PORT0
- + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
+ + port * 4,
+ ELINK_NIG_STATUS_EMAC0_MI_INT);
else
elink_bits_dis(sc,
NIG_REG_STATUS_INTERRUPT_PORT0
- + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
+ + port * 4,
+ ELINK_NIG_STATUS_EMAC0_MI_INT);
if (latch_status & 1) {
@@ -5741,23 +7038,24 @@ static void elink_link_int_ack(struct elink_params *params,
* the relevant lane in the status register
*/
uint32_t ser_lane =
- ((params->lane_config &
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+ ((params->lane_config &
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
mask = ((1 << ser_lane) <<
- ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
+ ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
} else
mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
}
- PMD_DRV_LOG(DEBUG, sc, "Ack link up interrupt with mask 0x%x",
- mask);
+ ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x",
+ mask);
elink_bits_en(sc,
- NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);
+ NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,
+ mask);
}
}
-static uint8_t elink_format_ver(uint32_t num, uint8_t * str,
- uint16_t * len)
+static elink_status_t elink_format_ver(uint32_t num, uint8_t *str,
+ uint16_t *len)
{
uint8_t *str_ptr = str;
uint32_t mask = 0xf0000000;
@@ -5795,14 +7093,57 @@ static uint8_t elink_format_ver(uint32_t num, uint8_t * str,
return ELINK_STATUS_OK;
}
-static uint8_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
- uint8_t * str, uint16_t * len)
+
+static elink_status_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
+ uint8_t *str,
+ uint16_t *len)
{
str[0] = '\0';
(*len)--;
return ELINK_STATUS_OK;
}
+elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params,
+ uint8_t *version,
+ uint16_t len)
+{
+ struct bnx2x_softc *sc;
+ uint32_t spirom_ver = 0;
+ elink_status_t status = ELINK_STATUS_OK;
+ uint8_t *ver_p = version;
+ uint16_t remain_len = len;
+ if (version == NULL || params == NULL)
+ return ELINK_STATUS_ERROR;
+ sc = params->sc;
+
+ /* Extract first external phy*/
+ version[0] = '\0';
+ spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);
+
+ if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {
+ status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,
+ ver_p,
+ &remain_len);
+ ver_p += (len - remain_len);
+ }
+ if ((params->num_phys == ELINK_MAX_PHYS) &&
+ (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {
+ spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);
+ if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {
+ *ver_p = '/';
+ ver_p++;
+ remain_len--;
+ status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(
+ spirom_ver,
+ ver_p,
+ &remain_len);
+ ver_p = version + (len - remain_len);
+ }
+ }
+ *ver_p = '\0';
+ return status;
+}
+
static void elink_set_xgxs_loopback(struct elink_phy *phy,
struct elink_params *params)
{
@@ -5812,7 +7153,7 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,
if (phy->req_line_speed != ELINK_SPEED_1000) {
uint32_t md_devad = 0;
- PMD_DRV_LOG(DEBUG, sc, "XGXS 10G loopback enable");
+ ELINK_DEBUG_P0(sc, "XGXS 10G loopback enable");
if (!CHIP_IS_E3(sc)) {
/* Change the uni_phy_addr in the nig */
@@ -5826,7 +7167,8 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,
elink_cl45_write(sc, phy,
5,
(MDIO_REG_BANK_AER_BLOCK +
- (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800);
+ (MDIO_AER_BLOCK_AER_REG & 0xf)),
+ 0x2800);
elink_cl45_write(sc, phy,
5,
@@ -5844,22 +7186,21 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,
}
} else {
uint16_t mii_ctrl;
- PMD_DRV_LOG(DEBUG, sc, "XGXS 1G loopback enable");
+ ELINK_DEBUG_P0(sc, "XGXS 1G loopback enable");
elink_cl45_read(sc, phy, 5,
(MDIO_REG_BANK_COMBO_IEEE0 +
- (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
+ (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
&mii_ctrl);
elink_cl45_write(sc, phy, 5,
(MDIO_REG_BANK_COMBO_IEEE0 +
- (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
+ (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
mii_ctrl |
MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
}
}
elink_status_t elink_set_led(struct elink_params *params,
- struct elink_vars *vars, uint8_t mode,
- uint32_t speed)
+ struct elink_vars *vars, uint8_t mode, uint32_t speed)
{
uint8_t port = params->port;
uint16_t hw_led_mode = params->hw_led_mode;
@@ -5868,16 +7209,21 @@ elink_status_t elink_set_led(struct elink_params *params,
uint32_t tmp;
uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "elink_set_led: port %x, mode %d", port, mode);
- PMD_DRV_LOG(DEBUG, sc,
- "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode);
+ ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d", port, mode);
+ ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x",
+ speed, hw_led_mode);
/* In case */
for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
if (params->phy[phy_idx].set_link_led) {
- params->phy[phy_idx].set_link_led(¶ms->phy[phy_idx],
- params, mode);
+ params->phy[phy_idx].set_link_led(
+ ¶ms->phy[phy_idx], params, mode);
}
}
+#ifdef ELINK_INCLUDE_EMUL
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)
+ return rc;
+#endif
switch (mode) {
case ELINK_LED_MODE_FRONT_PANEL_OFF:
@@ -5888,10 +7234,10 @@ elink_status_t elink_set_led(struct elink_params *params,
tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
if (params->phy[ELINK_EXT_PHY1].type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
+ PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE)
tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
- EMAC_LED_100MB_OVERRIDE |
- EMAC_LED_10MB_OVERRIDE);
+ EMAC_LED_100MB_OVERRIDE |
+ EMAC_LED_10MB_OVERRIDE);
else
tmp |= EMAC_LED_OVERRIDE;
@@ -5904,25 +7250,21 @@ elink_status_t elink_set_led(struct elink_params *params,
*/
if (!vars->link_up)
break;
- /* fall-through */
case ELINK_LED_MODE_ON:
if (((params->phy[ELINK_EXT_PHY1].type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||
- (params->phy[ELINK_EXT_PHY1].type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||
+ (params->phy[ELINK_EXT_PHY1].type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&
CHIP_IS_E2(sc) && params->num_phys == 2) {
- /* This is a work-around for E2+8727 Configurations */
+ /* This is a work-around for E2 + 8727 Configurations */
if (mode == ELINK_LED_MODE_ON ||
- speed == ELINK_SPEED_10000) {
+ speed == ELINK_SPEED_10000){
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
- tmp =
- elink_cb_reg_read(sc,
- emac_base +
- EMAC_REG_EMAC_LED);
- elink_cb_reg_write(sc,
- emac_base +
+ tmp = elink_cb_reg_read(sc, emac_base +
+ EMAC_REG_EMAC_LED);
+ elink_cb_reg_write(sc, emac_base +
EMAC_REG_EMAC_LED,
(tmp | EMAC_LED_OVERRIDE));
/* Return here without enabling traffic
@@ -5938,22 +7280,23 @@ elink_status_t elink_set_led(struct elink_params *params,
* is up in CL73
*/
if ((!CHIP_IS_E3(sc)) ||
- (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON))
+ (CHIP_IS_E3(sc) &&
+ mode == ELINK_LED_MODE_ON))
REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
if (CHIP_IS_E1x(sc) ||
- CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON))
+ CHIP_IS_E2(sc) ||
+ (mode == ELINK_LED_MODE_ON))
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
else
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
hw_led_mode);
} else if ((params->phy[ELINK_EXT_PHY1].type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) &&
+ PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) &&
(mode == ELINK_LED_MODE_ON)) {
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
- tmp =
- elink_cb_reg_read(sc,
- emac_base + EMAC_REG_EMAC_LED);
+ tmp = elink_cb_reg_read(sc, emac_base +
+ EMAC_REG_EMAC_LED);
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
tmp | EMAC_LED_OVERRIDE |
EMAC_LED_1000MB_OVERRIDE);
@@ -5963,11 +7306,10 @@ elink_status_t elink_set_led(struct elink_params *params,
break;
} else {
uint32_t nig_led_mode = ((params->hw_led_mode <<
- SHARED_HW_CFG_LED_MODE_SHIFT)
- ==
- SHARED_HW_CFG_LED_EXTPHY2)
- ? (SHARED_HW_CFG_LED_PHY1 >>
- SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
+ SHARED_HW_CFG_LED_MODE_SHIFT) ==
+ SHARED_HW_CFG_LED_EXTPHY2) ?
+ (SHARED_HW_CFG_LED_PHY1 >>
+ SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
nig_led_mode);
}
@@ -5981,27 +7323,133 @@ elink_status_t elink_set_led(struct elink_params *params,
else
REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
LED_BLINK_RATE_VAL_E1X_E2);
- REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);
+ REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
+ port * 4, 1);
tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
- (tmp & (~EMAC_LED_OVERRIDE)));
+ (tmp & (~EMAC_LED_OVERRIDE)));
+ if (CHIP_IS_E1(sc) &&
+ ((speed == ELINK_SPEED_2500) ||
+ (speed == ELINK_SPEED_1000) ||
+ (speed == ELINK_SPEED_100) ||
+ (speed == ELINK_SPEED_10))) {
+ /* For speeds less than 10G LED scheme is different */
+ REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+ + port * 4, 1);
+ REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
+ port * 4, 0);
+ REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
+ port * 4, 1);
+ }
break;
default:
rc = ELINK_STATUS_ERROR;
- PMD_DRV_LOG(DEBUG, sc,
- "elink_set_led: Invalid led mode %d", mode);
+ ELINK_DEBUG_P1(sc, "elink_set_led: Invalid led mode %d",
+ mode);
break;
}
return rc;
}
+/* This function comes to reflect the actual link state read DIRECTLY from the
+ * HW
+ */
+elink_status_t elink_test_link(struct elink_params *params,
+ __rte_unused struct elink_vars *vars,
+ uint8_t is_serdes)
+{
+ struct bnx2x_softc *sc = params->sc;
+ uint16_t gp_status = 0, phy_index = 0;
+ uint8_t ext_phy_link_up = 0, serdes_phy_type;
+ struct elink_vars temp_vars;
+ struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
+#ifdef ELINK_INCLUDE_FPGA
+ if (CHIP_REV_IS_FPGA(sc))
+ return ELINK_STATUS_OK;
+#endif
+#ifdef ELINK_INCLUDE_EMUL
+ if (CHIP_REV_IS_EMUL(sc))
+ return ELINK_STATUS_OK;
+#endif
+
+ if (CHIP_IS_E3(sc)) {
+ uint16_t link_up;
+ if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)]
+ > ELINK_SPEED_10000) {
+ /* Check 20G link */
+ elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
+ 1, &link_up);
+ elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
+ 1, &link_up);
+ link_up &= (1 << 2);
+ } else {
+ /* Check 10G link and below*/
+ uint8_t lane = elink_get_warpcore_lane(int_phy, params);
+ elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_GP2_STATUS_GP_2_1,
+ &gp_status);
+ gp_status = ((gp_status >> 8) & 0xf) |
+ ((gp_status >> 12) & 0xf);
+ link_up = gp_status & (1 << lane);
+ }
+ if (!link_up)
+ return ELINK_STATUS_NO_LINK;
+ } else {
+ CL22_RD_OVER_CL45(sc, int_phy,
+ MDIO_REG_BANK_GP_STATUS,
+ MDIO_GP_STATUS_TOP_AN_STATUS1,
+ &gp_status);
+ /* Link is up only if both local phy and external phy are up */
+ if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
+ return ELINK_STATUS_NO_LINK;
+ }
+ /* In XGXS loopback mode, do not check external PHY */
+ if (params->loopback_mode == ELINK_LOOPBACK_XGXS)
+ return ELINK_STATUS_OK;
+
+ switch (params->num_phys) {
+ case 1:
+ /* No external PHY */
+ return ELINK_STATUS_OK;
+ case 2:
+ ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(
+ ¶ms->phy[ELINK_EXT_PHY1],
+ params, &temp_vars);
+ break;
+ case 3: /* Dual Media */
+ for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
+ phy_index++) {
+ serdes_phy_type = ((params->phy[phy_index].media_type ==
+ ELINK_ETH_PHY_SFPP_10G_FIBER) ||
+ (params->phy[phy_index].media_type ==
+ ELINK_ETH_PHY_SFP_1G_FIBER) ||
+ (params->phy[phy_index].media_type ==
+ ELINK_ETH_PHY_XFP_FIBER) ||
+ (params->phy[phy_index].media_type ==
+ ELINK_ETH_PHY_DA_TWINAX));
+
+ if (is_serdes != serdes_phy_type)
+ continue;
+ if (params->phy[phy_index].read_status) {
+ ext_phy_link_up |=
+ params->phy[phy_index].read_status(
+ ¶ms->phy[phy_index],
+ params, &temp_vars);
+ }
+ }
+ break;
+ }
+ if (ext_phy_link_up)
+ return ELINK_STATUS_OK;
+ return ELINK_STATUS_NO_LINK;
+}
+
static elink_status_t elink_link_initialize(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
- elink_status_t rc = ELINK_STATUS_OK;
uint8_t phy_index, non_ext_phy;
struct bnx2x_softc *sc = params->sc;
/* In case of external phy existence, the line speed would be the
@@ -6026,11 +7474,12 @@ static elink_status_t elink_link_initialize(struct elink_params *params,
(params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
- (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)))
+ (CHIP_IS_E1x(sc) ||
+ CHIP_IS_E2(sc)))
elink_set_parallel_detection(phy, params);
if (params->phy[ELINK_INT_PHY].config_init)
- params->phy[ELINK_INT_PHY].config_init(phy,
- params, vars);
+ params->phy[ELINK_INT_PHY].config_init(phy, params,
+ vars);
}
/* Re-read this value in case it was changed inside config_init due to
@@ -6038,14 +7487,14 @@ static elink_status_t elink_link_initialize(struct elink_params *params,
*/
vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
- /* Init external phy */
+ /* Init external phy*/
if (non_ext_phy) {
if (params->phy[ELINK_INT_PHY].supported &
ELINK_SUPPORTED_FIBRE)
vars->link_status |= LINK_STATUS_SERDES_LINK;
} else {
for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
/* No need to initialize second phy in case of first
* phy only selection. In case of second phy, we do
* need to initialize the first phy, since they are
@@ -6058,13 +7507,13 @@ static elink_status_t elink_link_initialize(struct elink_params *params,
if (phy_index == ELINK_EXT_PHY2 &&
(elink_phy_selection(params) ==
PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
- PMD_DRV_LOG(DEBUG, sc,
- "Not initializing second phy");
+ ELINK_DEBUG_P0(sc,
+ "Not initializing second phy");
continue;
}
- params->phy[phy_index].config_init(¶ms->
- phy[phy_index],
- params, vars);
+ params->phy[phy_index].config_init(
+ ¶ms->phy[phy_index],
+ params, vars);
}
}
/* Reset the interrupt indication after phy was initialized */
@@ -6074,7 +7523,7 @@ static elink_status_t elink_link_initialize(struct elink_params *params,
ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
ELINK_NIG_MASK_MI_INT));
- return rc;
+ return ELINK_STATUS_OK;
}
static void elink_int_link_reset(__rte_unused struct elink_phy *phy,
@@ -6096,19 +7545,21 @@ static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,
else
gpio_port = params->port;
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ gpio_port);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
- PMD_DRV_LOG(DEBUG, sc, "reset external PHY");
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ gpio_port);
+ ELINK_DEBUG_P0(sc, "reset external PHY");
}
static elink_status_t elink_update_link_down(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
- PMD_DRV_LOG(DEBUG, sc, "Port %x: Link is down", port);
+ ELINK_DEBUG_P1(sc, "Port %x: Link is down", port);
elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
/* Indicate no mac active */
@@ -6128,8 +7579,9 @@ static elink_status_t elink_update_link_down(struct elink_params *params,
DELAY(1000 * 10);
/* Reset BigMac/Xmac */
- if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))
- elink_set_bmac_rx(sc, params->port, 0);
+ if (CHIP_IS_E1x(sc) ||
+ CHIP_IS_E2(sc))
+ elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
if (CHIP_IS_E3(sc)) {
/* Prevent LPI Generation by chip */
@@ -6149,8 +7601,8 @@ static elink_status_t elink_update_link_down(struct elink_params *params,
}
static elink_status_t elink_update_link_up(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t link_10g)
+ struct elink_vars *vars,
+ uint8_t link_10g)
{
struct bnx2x_softc *sc = params->sc;
uint8_t phy_idx, port = params->port;
@@ -6161,15 +7613,17 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
- vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
+ vars->link_status |=
+ LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
- vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
+ vars->link_status |=
+ LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
if (USES_WARPCORE(sc)) {
if (link_10g) {
if (elink_xmac_enable(params, vars, 0) ==
ELINK_STATUS_NO_LINK) {
- PMD_DRV_LOG(DEBUG, sc, "Found errors on XMAC");
+ ELINK_DEBUG_P0(sc, "Found errors on XMAC");
vars->link_up = 0;
vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
vars->link_status &= ~LINK_STATUS_LINK_UP;
@@ -6181,7 +7635,7 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
(vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
- PMD_DRV_LOG(DEBUG, sc, "Enabling LPI assertion");
+ ELINK_DEBUG_P0(sc, "Enabling LPI assertion");
REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
(params->port << 2), 1);
REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
@@ -6189,11 +7643,12 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
(params->port << 2), 0xfc20);
}
}
- if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) {
+ if ((CHIP_IS_E1x(sc) ||
+ CHIP_IS_E2(sc))) {
if (link_10g) {
if (elink_bmac_enable(params, vars, 0, 1) ==
ELINK_STATUS_NO_LINK) {
- PMD_DRV_LOG(DEBUG, sc, "Found errors on BMAC");
+ ELINK_DEBUG_P0(sc, "Found errors on BMAC");
vars->link_up = 0;
vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
vars->link_status &= ~LINK_STATUS_LINK_UP;
@@ -6236,6 +7691,24 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
return rc;
}
+static void elink_chng_link_count(struct elink_params *params, uint8_t clear)
+{
+ struct bnx2x_softc *sc = params->sc;
+ uint32_t addr, val;
+
+ /* Verify the link_change_count is supported by the MFW */
+ if (!(SHMEM2_HAS(sc, link_change_count)))
+ return;
+
+ addr = params->shmem2_base +
+ offsetof(struct shmem2_region, link_change_count[params->port]);
+ if (clear)
+ val = 0;
+ else
+ val = REG_RD(sc, addr) + 1;
+ REG_WR(sc, addr, val);
+}
+
/* The elink_link_update function should be called upon link
* interrupt.
* Link is considered up as follows:
@@ -6248,24 +7721,24 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
* external phy needs to be up, and at least one of the 2
* external phy link must be up.
*/
-elink_status_t elink_link_update(struct elink_params * params,
- struct elink_vars * vars)
+elink_status_t elink_link_update(struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
struct elink_vars phy_vars[ELINK_MAX_PHYS];
uint8_t port = params->port;
uint8_t link_10g_plus, phy_index;
+ uint32_t prev_link_status = vars->link_status;
uint8_t ext_phy_link_up = 0, cur_link_up;
elink_status_t rc = ELINK_STATUS_OK;
- __rte_unused uint8_t is_mi_int = 0;
uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
uint8_t active_external_phy = ELINK_INT_PHY;
vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
phy_vars[phy_index].flow_ctrl = 0;
- phy_vars[phy_index].link_status = ETH_LINK_DOWN;
+ phy_vars[phy_index].link_status = 0;
phy_vars[phy_index].line_speed = 0;
phy_vars[phy_index].duplex = DUPLEX_FULL;
phy_vars[phy_index].phy_link_up = 0;
@@ -6278,21 +7751,18 @@ elink_status_t elink_link_update(struct elink_params * params,
if (USES_WARPCORE(sc))
elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
- PMD_DRV_LOG(DEBUG, sc, "port %x, XGXS?%x, int_status 0x%x",
- port, (vars->phy_flags & PHY_XGXS_FLAG),
- REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
+ ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x",
+ port, (vars->phy_flags & PHY_XGXS_FLAG),
+ REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
- is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
- port * 0x18) > 0);
- PMD_DRV_LOG(DEBUG, sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
- REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
- is_mi_int,
- REG_RD(sc,
- NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
+ ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
+ REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
+ REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18) > 0,
+ REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
- PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
- REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
- REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
+ ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x",
+ REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
+ REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
/* Disable emac */
if (!CHIP_IS_E3(sc))
@@ -6306,7 +7776,7 @@ elink_status_t elink_link_update(struct elink_params * params,
* speed/duplex result
*/
for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
struct elink_phy *phy = ¶ms->phy[phy_index];
if (!phy->read_status)
continue;
@@ -6314,11 +7784,11 @@ elink_status_t elink_link_update(struct elink_params * params,
cur_link_up = phy->read_status(phy, params,
&phy_vars[phy_index]);
if (cur_link_up) {
- PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is up",
- phy_index);
+ ELINK_DEBUG_P1(sc, "phy in index %d link is up",
+ phy_index);
} else {
- PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is down",
- phy_index);
+ ELINK_DEBUG_P1(sc, "phy in index %d link is down",
+ phy_index);
continue;
}
@@ -6329,30 +7799,30 @@ elink_status_t elink_link_update(struct elink_params * params,
switch (elink_phy_selection(params)) {
case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
- /* In this option, the first PHY makes sure to pass the
- * traffic through itself only.
- * Its not clear how to reset the link on the second phy
- */
+ /* In this option, the first PHY makes sure to pass the
+ * traffic through itself only.
+ * Its not clear how to reset the link on the second phy
+ */
active_external_phy = ELINK_EXT_PHY1;
break;
case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
- /* In this option, the first PHY makes sure to pass the
- * traffic through the second PHY.
- */
+ /* In this option, the first PHY makes sure to pass the
+ * traffic through the second PHY.
+ */
active_external_phy = ELINK_EXT_PHY2;
break;
default:
- /* Link indication on both PHYs with the following cases
- * is invalid:
- * - FIRST_PHY means that second phy wasn't initialized,
- * hence its link is expected to be down
- * - SECOND_PHY means that first phy should not be able
- * to link up by itself (using configuration)
- * - DEFAULT should be overridden during initialization
- */
- PMD_DRV_LOG(DEBUG, sc, "Invalid link indication"
- "mpc=0x%x. DISABLING LINK !!!",
- params->multi_phy_config);
+ /* Link indication on both PHYs with the following cases
+ * is invalid:
+ * - FIRST_PHY means that second phy wasn't initialized,
+ * hence its link is expected to be down
+ * - SECOND_PHY means that first phy should not be able
+ * to link up by itself (using configuration)
+ * - DEFAULT should be overridden during initialiazation
+ */
+ ELINK_DEBUG_P1(sc, "Invalid link indication"
+ " mpc=0x%x. DISABLING LINK !!!",
+ params->multi_phy_config);
ext_phy_link_up = 0;
break;
}
@@ -6366,9 +7836,9 @@ elink_status_t elink_link_update(struct elink_params * params,
* external phy
*/
if (params->phy[ELINK_INT_PHY].read_status)
- params->phy[ELINK_INT_PHY].read_status(¶ms->
- phy[ELINK_INT_PHY],
- params, vars);
+ params->phy[ELINK_INT_PHY].read_status(
+ ¶ms->phy[ELINK_INT_PHY],
+ params, vars);
/* The INT_PHY flow control reside in the vars. This include the
* case where the speed or flow control are not set to AUTO.
* Otherwise, the active external phy flow control result is set
@@ -6388,11 +7858,11 @@ elink_status_t elink_link_update(struct elink_params * params,
*/
if (active_external_phy == ELINK_EXT_PHY1) {
if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
- PMD_DRV_LOG(DEBUG, sc, "Disabling TX on EXT_PHY2");
- params->phy[ELINK_EXT_PHY2].
- phy_specific_func(¶ms->
- phy[ELINK_EXT_PHY2],
- params, ELINK_DISABLE_TX);
+ ELINK_DEBUG_P0(sc,
+ "Disabling TX on EXT_PHY2");
+ params->phy[ELINK_EXT_PHY2].phy_specific_func(
+ ¶ms->phy[ELINK_EXT_PHY2],
+ params, ELINK_DISABLE_TX);
}
}
@@ -6406,12 +7876,27 @@ elink_status_t elink_link_update(struct elink_params * params,
vars->eee_status = phy_vars[active_external_phy].eee_status;
- PMD_DRV_LOG(DEBUG, sc, "Active external phy selected: %x",
- active_external_phy);
- }
+ ELINK_DEBUG_P1(sc, "Active external phy selected: %x",
+ active_external_phy);
+ }
+
+ ELINK_DEBUG_P3(sc, "vars : phy_flags = %x, mac_type = %x, phy_link_up = %x",
+ vars->phy_flags, vars->mac_type, vars->phy_link_up);
+ ELINK_DEBUG_P3(sc, "vars : link_up = %x, line_speed = %x, duplex = %x",
+ vars->link_up, vars->line_speed, vars->duplex);
+ ELINK_DEBUG_P3(sc, "vars : flow_ctrl = %x, ieee_fc = %x, link_status = %x",
+ vars->flow_ctrl, vars->ieee_fc, vars->link_status);
+ ELINK_DEBUG_P3(sc, "vars : eee_status = %x, fault_detected = %x, check_kr2_recovery_cnt = %x",
+ vars->eee_status, vars->fault_detected,
+ vars->check_kr2_recovery_cnt);
+ ELINK_DEBUG_P3(sc, "vars : periodic_flags = %x, aeu_int_mask = %x, rx_tx_asic_rst = %x",
+ vars->periodic_flags, vars->aeu_int_mask,
+ vars->rx_tx_asic_rst);
+ ELINK_DEBUG_P2(sc, "vars : turn_to_run_wc_rt = %x, rsrv2 = %x",
+ vars->turn_to_run_wc_rt, vars->rsrv2);
for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
if (params->phy[phy_index].flags &
ELINK_FLAGS_REARM_LATCH_SIGNAL) {
elink_rearm_latch_signal(sc, port,
@@ -6420,9 +7905,9 @@ elink_status_t elink_link_update(struct elink_params * params,
break;
}
}
- PMD_DRV_LOG(DEBUG, sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
- " ext_phy_line_speed = %d", vars->flow_ctrl,
- vars->link_status, ext_phy_line_speed);
+ ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
+ " ext_phy_line_speed = %d", vars->flow_ctrl,
+ vars->link_status, ext_phy_line_speed);
/* Upon link speed change set the NIG into drain mode. Comes to
* deals with possible FIFO glitch due to clk change when speed
* is decreased without link down indicator
@@ -6431,15 +7916,15 @@ elink_status_t elink_link_update(struct elink_params * params,
if (vars->phy_link_up) {
if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
(ext_phy_line_speed != vars->line_speed)) {
- PMD_DRV_LOG(DEBUG, sc, "Internal link speed %d is"
- " different than the external"
- " link speed %d", vars->line_speed,
- ext_phy_line_speed);
+ ELINK_DEBUG_P2(sc, "Internal link speed %d is"
+ " different than the external"
+ " link speed %d", vars->line_speed,
+ ext_phy_line_speed);
vars->phy_link_up = 0;
+ ELINK_DEBUG_P0(sc, "phy_link_up set to 0");
} else if (prev_line_speed != vars->line_speed) {
- REG_WR(sc,
- NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4,
- 0);
+ REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE +
+ params->port * 4, 0);
DELAY(1000 * 1);
}
}
@@ -6457,11 +7942,11 @@ elink_status_t elink_link_update(struct elink_params * params,
* initialize it
*/
if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
- PMD_DRV_LOG(DEBUG, sc, "ext_phy_link_up = %d, int_link_up = %d,"
- " init_preceding = %d", ext_phy_link_up,
- vars->phy_link_up,
- params->phy[ELINK_EXT_PHY1].flags &
- ELINK_FLAGS_INIT_XGXS_FIRST);
+ ELINK_DEBUG_P3(sc, "ext_phy_link_up = %d, int_link_up = %d,"
+ " init_preceding = %d", ext_phy_link_up,
+ vars->phy_link_up,
+ params->phy[ELINK_EXT_PHY1].flags &
+ ELINK_FLAGS_INIT_XGXS_FIRST);
if (!(params->phy[ELINK_EXT_PHY1].flags &
ELINK_FLAGS_INIT_XGXS_FIRST)
&& ext_phy_link_up && !vars->phy_link_up) {
@@ -6472,11 +7957,9 @@ elink_status_t elink_link_update(struct elink_params * params,
vars->phy_flags &= ~PHY_SGMII_FLAG;
if (params->phy[ELINK_INT_PHY].config_init)
- params->phy[ELINK_INT_PHY].config_init(¶ms->
- phy
- [ELINK_INT_PHY],
- params,
- vars);
+ params->phy[ELINK_INT_PHY].config_init(
+ ¶ms->phy[ELINK_INT_PHY], params,
+ vars);
}
}
/* Link is up only if both local phy and external phy (in case of
@@ -6487,6 +7970,11 @@ elink_status_t elink_link_update(struct elink_params * params,
ELINK_SINGLE_MEDIA_DIRECT(params)) &&
(phy_vars[active_external_phy].fault_detected == 0));
+ if (vars->link_up)
+ ELINK_DEBUG_P0(sc, "local phy and external phy are up");
+ else
+ ELINK_DEBUG_P0(sc, "either local phy or external phy or both are down");
+
/* Update the PFC configuration in case it was changed */
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
vars->link_status |= LINK_STATUS_PFC_ENABLED;
@@ -6498,9 +7986,12 @@ elink_status_t elink_link_update(struct elink_params * params,
else
rc = elink_update_link_down(params, vars);
+ if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
+ elink_chng_link_count(params, 0);
+
/* Update MCP link status was changed */
- if (params->
- feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
return rc;
@@ -6509,28 +8000,28 @@ elink_status_t elink_link_update(struct elink_params * params,
/*****************************************************************************/
/* External Phy section */
/*****************************************************************************/
-static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)
+void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)
{
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
DELAY(1000 * 1);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
}
-static void elink_save_spirom_version(struct bnx2x_softc *sc,
- __rte_unused uint8_t port,
+static void elink_save_spirom_version(struct bnx2x_softc *sc, uint8_t port,
uint32_t spirom_ver, uint32_t ver_addr)
{
- PMD_DRV_LOG(DEBUG, sc, "FW version 0x%x:0x%x for port %d",
- (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);
+ ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d",
+ (uint16_t)(spirom_ver >> 16), (uint16_t)spirom_ver, port);
if (ver_addr)
REG_WR(sc, ver_addr, spirom_ver);
}
static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t port)
+ struct elink_phy *phy,
+ uint8_t port)
{
uint16_t fw_ver1, fw_ver2;
@@ -6538,18 +8029,21 @@ static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,
MDIO_PMA_REG_ROM_VER1, &fw_ver1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
MDIO_PMA_REG_ROM_VER2, &fw_ver2);
- elink_save_spirom_version(sc, port,
- (uint32_t) (fw_ver1 << 16 | fw_ver2),
+ elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1 << 16 | fw_ver2),
phy->ver_addr);
}
static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- struct elink_vars *vars)
+ struct elink_phy *phy,
+ struct elink_vars *vars)
{
uint16_t val;
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_STATUS, &val);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_STATUS, &val);
if (val & (1 << 5))
vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
if ((val & (1 << 0)) == 0)
@@ -6573,8 +8067,8 @@ static void elink_8073_resolve_fc(struct elink_phy *phy,
if (elink_ext_phy_resolve_fc(phy, params, vars) &&
(vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
uint16_t pause_result;
- uint16_t ld_pause; /* local */
- uint16_t lp_pause; /* link partner */
+ uint16_t ld_pause; /* local */
+ uint16_t lp_pause; /* link partner */
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_CL37_FC_LD, &ld_pause);
@@ -6587,31 +8081,35 @@ static void elink_8073_resolve_fc(struct elink_phy *phy,
pause_result |= (lp_pause &
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
- elink_pause_resolve(vars, pause_result);
- PMD_DRV_LOG(DEBUG, sc, "Ext PHY CL37 pause result 0x%x",
- pause_result);
+ elink_pause_resolve(phy, params, vars, pause_result);
+ ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x",
+ pause_result);
}
}
-
static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- uint8_t port)
+ struct elink_phy *phy,
+ uint8_t port)
{
uint32_t count = 0;
- uint16_t fw_ver1 = 0, fw_msgout;
+ uint16_t fw_ver1, fw_msgout;
elink_status_t rc = ELINK_STATUS_OK;
/* Boot port from external ROM */
/* EDC grst */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_GEN_CTRL,
+ 0x0001);
/* Ucode reboot and rst */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_GEN_CTRL,
+ 0x008c);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_MISC_CTRL1, 0x0001);
/* Reset internal microprocessor */
elink_cl45_write(sc, phy,
@@ -6632,10 +8130,10 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
do {
count++;
if (count > 300) {
- PMD_DRV_LOG(DEBUG, sc,
- "elink_8073_8727_external_rom_boot port %x:"
- "Download failed. fw version = 0x%x",
- port, fw_ver1);
+ ELINK_DEBUG_P2(sc,
+ "elink_8073_8727_external_rom_boot port %x:"
+ "Download failed. fw version = 0x%x",
+ port, fw_ver1);
rc = ELINK_STATUS_ERROR;
break;
}
@@ -6649,17 +8147,19 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
DELAY(1000 * 1);
} while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
- ((fw_msgout & 0xff) != 0x03 && (phy->type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));
+ ((fw_msgout & 0xff) != 0x03 && (phy->type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));
/* Clear ser_boot_ctl bit */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_MISC_CTRL1, 0x0000);
elink_save_bnx2x_spirom_ver(sc, phy, port);
- PMD_DRV_LOG(DEBUG, sc,
- "elink_8073_8727_external_rom_boot port %x:"
- "Download complete. fw version = 0x%x", port, fw_ver1);
+ ELINK_DEBUG_P2(sc,
+ "elink_8073_8727_external_rom_boot port %x:"
+ "Download complete. fw version = 0x%x",
+ port, fw_ver1);
return rc;
}
@@ -6673,22 +8173,25 @@ static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc,
/* This is only required for 8073A1, version 102 only */
uint16_t val;
- /* Read 8073 HW revision */
+ /* Read 8073 HW revision*/
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8073_CHIP_REV, &val);
if (val != 1) {
/* No need to workaround in 8073 A1 */
return ELINK_STATUS_OK;
}
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_ROM_VER2, &val);
/* SNR should be applied only for version 0x102 */
if (val != 0x102)
return ELINK_STATUS_OK;
- return ELINK_STATUS_ERROR;
+ return 1;
}
static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
@@ -6697,7 +8200,8 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
uint16_t val, cnt, cnt1;
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8073_CHIP_REV, &val);
if (val > 0) {
/* No need to workaround in 8073 A1 */
@@ -6712,16 +8216,17 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
for (cnt = 0; cnt < 1000; cnt++) {
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);
- /* If bit [14] = 0 or bit [13] = 0, continue on with
- * system initialization (XAUI work-around not required, as
- * these bits indicate 2.5G or 1G link up).
- */
+ MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
+ &val);
+ /* If bit [14] = 0 or bit [13] = 0, continue on with
+ * system initialization (XAUI work-around not required, as
+ * these bits indicate 2.5G or 1G link up).
+ */
if (!(val & (1 << 14)) || !(val & (1 << 13))) {
- PMD_DRV_LOG(DEBUG, sc, "XAUI work-around not required");
+ ELINK_DEBUG_P0(sc, "XAUI work-around not required");
return ELINK_STATUS_OK;
} else if (!(val & (1 << 15))) {
- PMD_DRV_LOG(DEBUG, sc, "bit 15 went off");
+ ELINK_DEBUG_P0(sc, "bit 15 went off");
/* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
* MSB (bit15) goes to 1 (indicating that the XAUI
* workaround has completed), then continue on with
@@ -6729,12 +8234,11 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
*/
for (cnt1 = 0; cnt1 < 1000; cnt1++) {
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8073_XAUI_WA,
- &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8073_XAUI_WA, &val);
if (val & (1 << 15)) {
- PMD_DRV_LOG(DEBUG, sc,
- "XAUI workaround has completed");
+ ELINK_DEBUG_P0(sc,
+ "XAUI workaround has completed");
return ELINK_STATUS_OK;
}
DELAY(1000 * 3);
@@ -6743,19 +8247,21 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
}
DELAY(1000 * 3);
}
- PMD_DRV_LOG(DEBUG, sc, "Warning: XAUI work-around timeout !!!");
+ ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!");
return ELINK_STATUS_ERROR;
}
static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy)
{
/* Force KR or KX */
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000);
- elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
+ elink_cl45_write(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
}
static void elink_8073_set_pause_cl37(struct elink_params *params,
@@ -6771,21 +8277,22 @@ static void elink_8073_set_pause_cl37(struct elink_params *params,
/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
- cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
+ cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
}
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
- cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+ cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
}
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
}
- PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize cl37 0x%x", cl37_val);
+ ELINK_DEBUG_P1(sc,
+ "Ext phy AN advertize cl37 0x%x", cl37_val);
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
@@ -6803,31 +8310,31 @@ static void elink_8073_specific_func(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
(1 << 2));
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
- 0x0004);
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
break;
}
}
-static uint8_t elink_8073_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static elink_status_t elink_8073_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val = 0, tmp1;
uint8_t gpio_port;
- PMD_DRV_LOG(DEBUG, sc, "Init 8073");
+ ELINK_DEBUG_P0(sc, "Init 8073");
if (CHIP_IS_E2(sc))
gpio_port = SC_PATH(sc);
else
gpio_port = params->port;
- /* Restore normal power mode */
+ /* Restore normal power mode*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
elink_8073_set_pause_cl37(params, phy, vars);
@@ -6835,14 +8342,15 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
- PMD_DRV_LOG(DEBUG, sc, "Before rom RX_ALARM(port1): 0x%x", tmp1);
+ ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x", tmp1);
/* Swap polarity if required - Must be done only in non-1G mode */
if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
/* Configure the 8073 to swap _P and _N of the KR lines */
- PMD_DRV_LOG(DEBUG, sc, "Swapping polarity for the 8073");
+ ELINK_DEBUG_P0(sc, "Swapping polarity for the 8073");
/* 10G Rx/Tx and 1G Tx signal polarity swap */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
@@ -6853,31 +8361,33 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
(val | (3 << 9)));
}
+
/* Enable CL37 BAM */
if (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- default_cfg)) &
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg)) &
PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
elink_cl45_read(sc, phy,
- MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8073_BAM, &val);
elink_cl45_write(sc, phy,
- MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);
- PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8073_BAM, val | 1);
+ ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR");
}
if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
elink_807x_force_10G(sc, phy);
- PMD_DRV_LOG(DEBUG, sc, "Forced speed 10G on 807X");
+ ELINK_DEBUG_P0(sc, "Forced speed 10G on 807X");
return ELINK_STATUS_OK;
} else {
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
}
if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
if (phy->req_line_speed == ELINK_SPEED_10000) {
val = (1 << 7);
- } else if (phy->req_line_speed == ELINK_SPEED_2500) {
+ } else if (phy->req_line_speed == ELINK_SPEED_2500) {
val = (1 << 5);
/* Note that 2.5G works only when used with 1G
* advertisement
@@ -6886,15 +8396,16 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
val = (1 << 5);
} else {
val = 0;
- if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
+ if (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
val |= (1 << 7);
/* Note that 2.5G works only when used with 1G advertisement */
if (phy->speed_cap_mask &
- (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
- PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
+ (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
val |= (1 << 5);
- PMD_DRV_LOG(DEBUG, sc, "807x autoneg val = 0x%x", val);
+ ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x", val);
}
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
@@ -6908,13 +8419,13 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
&phy_ver);
- PMD_DRV_LOG(DEBUG, sc, "Add 2.5G");
+ ELINK_DEBUG_P0(sc, "Add 2.5G");
if (phy_ver > 0)
tmp1 |= 1;
else
tmp1 &= 0xfffe;
} else {
- PMD_DRV_LOG(DEBUG, sc, "Disable 2.5G");
+ ELINK_DEBUG_P0(sc, "Disable 2.5G");
tmp1 &= 0xfffe;
}
@@ -6948,14 +8459,14 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
/* Restart autoneg */
DELAY(1000 * 500);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
- PMD_DRV_LOG(DEBUG, sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
- ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
+ ELINK_DEBUG_P2(sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
+ ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
return ELINK_STATUS_OK;
}
static uint8_t elink_8073_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t link_up = 0;
@@ -6963,33 +8474,41 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
uint16_t link_status = 0;
uint16_t an1000_status = 0;
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8703 LASI status 0x%x", val1);
+ ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x", val1);
/* Clear the interrupt LASI status register */
- elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "807x PCS status 0x%x->0x%x", val2, val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
+ ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x", val2, val1);
/* Clear MSG-OUT */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
/* Check the LASI */
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
- PMD_DRV_LOG(DEBUG, sc, "KR 0x9003 0x%x", val2);
+ ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x", val2);
/* Check the link status */
- elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
- PMD_DRV_LOG(DEBUG, sc, "KR PCS status 0x%x", val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
+ ELINK_DEBUG_P1(sc, "KR PCS status 0x%x", val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
link_up = ((val1 & 4) == 4);
- PMD_DRV_LOG(DEBUG, sc, "PMA_REG_STATUS=0x%x", val1);
+ ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x", val1);
- if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {
+ if (link_up &&
+ ((phy->req_line_speed != ELINK_SPEED_10000))) {
if (elink_8073_xaui_wa(sc, phy) != 0)
return 0;
}
@@ -6999,10 +8518,12 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
/* Check the link status on 1.1.2 */
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "KR PMA status 0x%x->0x%x,"
- "an_link_status=0x%x", val2, val1, an1000_status);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
+ ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x,"
+ "an_link_status=0x%x", val2, val1, an1000_status);
link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));
if (link_up && elink_8073_is_snr_needed(sc, phy)) {
@@ -7027,27 +8548,28 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_10000;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 10G",
+ params->port);
} else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_2500;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 2.5G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G",
+ params->port);
} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_1000;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 1G",
+ params->port);
} else {
link_up = 0;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link is down",
+ params->port);
}
if (link_up) {
/* Swap polarity if required */
- if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
+ if (params->lane_config &
+ PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
/* Configure the 8073 to swap P and N of the KR lines */
elink_cl45_read(sc, phy,
MDIO_XS_DEVAD,
@@ -7056,15 +8578,16 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
* when it`s in 10G mode.
*/
if (vars->line_speed == ELINK_SPEED_1000) {
- PMD_DRV_LOG(DEBUG, sc, "Swapping 1G polarity for"
- "the 8073");
+ ELINK_DEBUG_P0(sc, "Swapping 1G polarity for"
+ " the 8073");
val1 |= (1 << 3);
} else
val1 &= ~(1 << 3);
elink_cl45_write(sc, phy,
MDIO_XS_DEVAD,
- MDIO_XS_REG_8073_RX_CTRL_PCIE, val1);
+ MDIO_XS_REG_8073_RX_CTRL_PCIE,
+ val1);
}
elink_ext_phy_10G_an_resolve(sc, phy, vars);
elink_8073_resolve_fc(phy, params, vars);
@@ -7077,10 +8600,10 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
if (val1 & (1 << 5))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
if (val1 & (1 << 7))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
}
return link_up;
@@ -7095,25 +8618,25 @@ static void elink_8073_link_reset(__rte_unused struct elink_phy *phy,
gpio_port = SC_PATH(sc);
else
gpio_port = params->port;
- PMD_DRV_LOG(DEBUG, sc, "Setting 8073 port %d into low power mode",
- gpio_port);
+ ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode",
+ gpio_port);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ gpio_port);
}
/******************************************************************/
/* BNX2X8705 PHY SECTION */
/******************************************************************/
-static uint8_t elink_8705_config_init(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars
- *vars)
+static elink_status_t elink_8705_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "init 8705");
- /* Restore normal power mode */
+ ELINK_DEBUG_P0(sc, "init 8705");
+ /* Restore normal power mode*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
/* HW reset */
elink_ext_phy_hw_reset(sc, params->port);
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
@@ -7125,36 +8648,40 @@ static uint8_t elink_8705_config_init(struct elink_phy *phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
- elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
+ elink_cl45_write(sc, phy,
+ MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
/* BNX2X8705 doesn't have microcode, hence the 0 */
elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
return ELINK_STATUS_OK;
}
static uint8_t elink_8705_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint8_t link_up = 0;
uint16_t val1, rx_sd;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "read status 8705");
+ ELINK_DEBUG_P0(sc, "read status 8705");
elink_cl45_read(sc, phy,
- MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
+ MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
+ ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x", val1);
elink_cl45_read(sc, phy,
- MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
+ MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
+ ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x", val1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, 0xc809, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, 0xc809, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8705 1.c809 val=0x%x", val1);
- link_up = ((rx_sd & 0x1) && (val1 & (1 << 9))
- && ((val1 & (1 << 8)) == 0));
+ ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x", val1);
+ link_up = ((rx_sd & 0x1) && (val1 & (1 << 9)) &&
+ ((val1 & (1 << 8)) == 0));
if (link_up) {
vars->line_speed = ELINK_SPEED_10000;
elink_ext_phy_resolve_fc(phy, params, vars);
@@ -7175,17 +8702,17 @@ static void elink_set_disable_pmd_transmit(struct elink_params *params,
*/
if (pmd_dis) {
if (params->feature_config_flags &
- ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
- PMD_DRV_LOG(DEBUG, sc, "Disabling PMD transmitter");
+ ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
+ ELINK_DEBUG_P0(sc, "Disabling PMD transmitter");
} else {
- PMD_DRV_LOG(DEBUG, sc, "NOT disabling PMD transmitter");
+ ELINK_DEBUG_P0(sc, "NOT disabling PMD transmitter");
return;
}
- } else {
- PMD_DRV_LOG(DEBUG, sc, "Enabling PMD transmitter");
- }
+ } else
+ ELINK_DEBUG_P0(sc, "Enabling PMD transmitter");
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_TX_DISABLE, pmd_dis);
}
static uint8_t elink_get_gpio_port(struct elink_params *params)
@@ -7193,37 +8720,38 @@ static uint8_t elink_get_gpio_port(struct elink_params *params)
uint8_t gpio_port;
uint32_t swap_val, swap_override;
struct bnx2x_softc *sc = params->sc;
- if (CHIP_IS_E2(sc)) {
+ if (CHIP_IS_E2(sc))
gpio_port = SC_PATH(sc);
- } else {
+ else
gpio_port = params->port;
- }
swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
return gpio_port ^ (swap_val && swap_override);
}
static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
- struct elink_phy *phy, uint8_t tx_en)
+ struct elink_phy *phy,
+ uint8_t tx_en)
{
uint16_t val;
uint8_t port = params->port;
struct bnx2x_softc *sc = params->sc;
uint32_t tx_en_mode;
- /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */
+ /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
tx_en_mode = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
dev_info.port_hw_config[port].sfp_ctrl)) &
- PORT_HW_CFG_TX_LASER_MASK;
- PMD_DRV_LOG(DEBUG, sc, "Setting transmitter tx_en=%x for port %x "
- "mode = %x", tx_en, port, tx_en_mode);
+ PORT_HW_CFG_TX_LASER_MASK;
+ ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x "
+ "mode = %x", tx_en, port, tx_en_mode);
switch (tx_en_mode) {
case PORT_HW_CFG_TX_LASER_MDIO:
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, &val);
+ MDIO_PMA_REG_PHY_IDENTIFIER,
+ &val);
if (tx_en)
val &= ~(1 << 15);
@@ -7232,37 +8760,38 @@ static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, val);
- break;
+ MDIO_PMA_REG_PHY_IDENTIFIER,
+ val);
+ break;
case PORT_HW_CFG_TX_LASER_GPIO0:
case PORT_HW_CFG_TX_LASER_GPIO1:
case PORT_HW_CFG_TX_LASER_GPIO2:
case PORT_HW_CFG_TX_LASER_GPIO3:
- {
- uint16_t gpio_pin;
- uint8_t gpio_port, gpio_mode;
- if (tx_en)
- gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
- else
- gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
+ {
+ uint16_t gpio_pin;
+ uint8_t gpio_port, gpio_mode;
+ if (tx_en)
+ gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
+ else
+ gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
- gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
- gpio_port = elink_get_gpio_port(params);
- elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
- break;
- }
+ gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
+ gpio_port = elink_get_gpio_port(params);
+ elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
+ break;
+ }
default:
- PMD_DRV_LOG(DEBUG, sc,
- "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
+ ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
break;
}
}
static void elink_sfp_set_transmitter(struct elink_params *params,
- struct elink_phy *phy, uint8_t tx_en)
+ struct elink_phy *phy,
+ uint8_t tx_en)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ transmitter to %d", tx_en);
+ ELINK_DEBUG_P1(sc, "Setting SFP+ transmitter to %d", tx_en);
if (CHIP_IS_E3(sc))
elink_sfp_e3_set_transmitter(params, phy, tx_en);
else
@@ -7270,20 +8799,17 @@ static void elink_sfp_set_transmitter(struct elink_params *params,
}
static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
- struct elink_params
- *params,
- uint8_t dev_addr,
- uint16_t addr,
- uint8_t byte_cnt,
- uint8_t * o_buf,
- __rte_unused uint8_t
- is_init)
+ struct elink_params *params,
+ uint8_t dev_addr, uint16_t addr,
+ uint8_t byte_cnt,
+ uint8_t *o_buf, __rte_unused uint8_t is_init)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val = 0;
uint16_t i;
if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
- PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
+ ELINK_DEBUG_P0(sc,
+ "Reading from eeprom is limited to 0xf");
return ELINK_STATUS_ERROR;
}
/* Set the read command byte count */
@@ -7313,10 +8839,10 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
}
if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
- MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
- PMD_DRV_LOG(DEBUG, sc,
- "Got bad status 0x%x when reading from SFP+ EEPROM",
- (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
+ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
+ ELINK_DEBUG_P1(sc,
+ "Got bad status 0x%x when reading from SFP+ EEPROM",
+ (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
return ELINK_STATUS_ERROR;
}
@@ -7325,8 +8851,8 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
- o_buf[i] =
- (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
+ o_buf[i] = (uint8_t)
+ (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
}
for (i = 0; i < 100; i++) {
@@ -7349,29 +8875,27 @@ static void elink_warpcore_power_module(struct elink_params *params,
pin_cfg = (REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK)
- >> PORT_HW_CFG_E3_PWR_DIS_SHIFT;
+ dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
+ PORT_HW_CFG_E3_PWR_DIS_MASK) >>
+ PORT_HW_CFG_E3_PWR_DIS_SHIFT;
if (pin_cfg == PIN_CFG_NA)
return;
- PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ module power to %d using pin cfg %d",
- power, pin_cfg);
+ ELINK_DEBUG_P2(sc, "Setting SFP+ module power to %d using pin cfg %d",
+ power, pin_cfg);
/* Low ==> corresponding SFP+ module is powered
* high ==> the SFP+ module is powered down
*/
elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
}
-
-static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
- elink_phy *phy,
- struct elink_params
- *params,
- uint8_t dev_addr,
- uint16_t addr,
- uint8_t byte_cnt,
- uint8_t * o_buf,
- uint8_t is_init)
+static elink_status_t elink_warpcore_read_sfp_module_eeprom(
+ __rte_unused struct elink_phy *phy,
+ struct elink_params *params,
+ uint8_t dev_addr,
+ uint16_t addr,
+ uint8_t byte_cnt,
+ uint8_t *o_buf,
+ uint8_t is_init)
{
elink_status_t rc = ELINK_STATUS_OK;
uint8_t i, j = 0, cnt = 0;
@@ -7380,8 +8904,8 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
struct bnx2x_softc *sc = params->sc;
if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
- PMD_DRV_LOG(DEBUG, sc,
- "Reading from eeprom is limited to 16 bytes");
+ ELINK_DEBUG_P0(sc,
+ "Reading from eeprom is limited to 16 bytes");
return ELINK_STATUS_ERROR;
}
@@ -7394,13 +8918,15 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
DELAY(1000 * 1);
elink_warpcore_power_module(params, 1);
}
- rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
+
+ elink_bsc_module_sel(params);
+ rc = elink_bsc_read(sc, dev_addr, addr32, 0, byte_cnt,
data_array);
} while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
if (rc == ELINK_STATUS_OK) {
for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
- o_buf[j] = *((uint8_t *) data_array + i);
+ o_buf[j] = *((uint8_t *)data_array + i);
j++;
}
}
@@ -7409,20 +8935,18 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
}
static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
- struct elink_params
- *params,
- uint8_t dev_addr,
- uint16_t addr,
- uint8_t byte_cnt,
- uint8_t * o_buf,
- __rte_unused uint8_t
- is_init)
+ struct elink_params *params,
+ uint8_t dev_addr, uint16_t addr,
+ uint8_t byte_cnt,
+ uint8_t *o_buf,
+ __rte_unused uint8_t is_init)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val, i;
if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
- PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
+ ELINK_DEBUG_P0(sc,
+ "Reading from eeprom is limited to 0xf");
return ELINK_STATUS_ERROR;
}
@@ -7437,7 +8961,9 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
/* Need to read from 1.8000 to clear it */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
+ &val);
/* Set the read command byte count */
elink_cl45_write(sc, phy,
@@ -7448,16 +8974,19 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
/* Set the read command address */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);
+ MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
+ addr);
/* Set the destination address */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
+ 0x8004,
+ MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
/* Activate read command */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);
+ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
+ 0x8002);
/* Wait appropriate time for two-wire command to finish before
* polling the status register
*/
@@ -7475,10 +9004,10 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
}
if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
- MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
- PMD_DRV_LOG(DEBUG, sc,
- "Got bad status 0x%x when reading from SFP+ EEPROM",
- (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
+ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
+ ELINK_DEBUG_P1(sc,
+ "Got bad status 0x%x when reading from SFP+ EEPROM",
+ (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
return ELINK_STATUS_TIMEOUT;
}
@@ -7487,8 +9016,8 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
- o_buf[i] =
- (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
+ o_buf[i] = (uint8_t)
+ (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
}
for (i = 0; i < 100; i++) {
@@ -7503,22 +9032,18 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
return ELINK_STATUS_ERROR;
}
-
-static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
- struct elink_params *params,
- uint8_t dev_addr,
- uint16_t addr,
- uint16_t byte_cnt,
- uint8_t * o_buf)
+elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
+ struct elink_params *params, uint8_t dev_addr,
+ uint16_t addr, uint16_t byte_cnt,
+ uint8_t *o_buf)
{
- elink_status_t rc = ELINK_STATUS_OK;
+ elink_status_t rc = 0;
+ struct bnx2x_softc *sc = params->sc;
uint8_t xfer_size;
uint8_t *user_data = o_buf;
read_sfp_module_eeprom_func_p read_func;
-
if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
- PMD_DRV_LOG(DEBUG, params->sc,
- "invalid dev_addr 0x%x", dev_addr);
+ ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x", dev_addr);
return ELINK_STATUS_ERROR;
}
@@ -7539,7 +9064,7 @@ static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
while (!rc && (byte_cnt > 0)) {
xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
- ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
+ ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
rc = read_func(phy, params, dev_addr, addr, xfer_size,
user_data, 0);
byte_cnt -= xfer_size;
@@ -7550,91 +9075,105 @@ static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
}
static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
- struct elink_params *params,
- uint16_t * edc_mode)
+ struct elink_params *params,
+ uint16_t *edc_mode)
{
struct bnx2x_softc *sc = params->sc;
uint32_t sync_offset = 0, phy_idx, media_types;
- uint8_t gport, val[2], check_limiting_mode = 0;
+ uint8_t val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1];
+ uint8_t check_limiting_mode = 0;
*edc_mode = ELINK_EDC_MODE_LIMITING;
phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
/* First check for copper cable */
if (elink_read_sfp_module_eeprom(phy,
params,
ELINK_I2C_DEV_ADDR_A0,
- ELINK_SFP_EEPROM_CON_TYPE_ADDR,
- 2, (uint8_t *) val) != 0) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to read from SFP+ module EEPROM");
+ 0,
+ ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1,
+ (uint8_t *)val) != 0) {
+ ELINK_DEBUG_P0(sc, "Failed to read from SFP+ module EEPROM");
return ELINK_STATUS_ERROR;
}
-
- switch (val[0]) {
+ params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
+ params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] <<
+ LINK_SFP_EEPROM_COMP_CODE_SHIFT;
+ elink_update_link_attr(params, params->link_attr_sync);
+ switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) {
case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
- {
- uint8_t copper_module_type;
- phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
- /* Check if its active cable (includes SFP+ module)
- * of passive cable
+ {
+ uint8_t copper_module_type;
+ phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
+ /* Check if its active cable (includes SFP+ module)
+ * of passive cable
+ */
+ copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR];
+ if (copper_module_type &
+ ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
+ ELINK_DEBUG_P0(sc, "Active Copper cable detected");
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
+ *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
+ else
+ check_limiting_mode = 1;
+ } else {
+ *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
+ /* Even in case PASSIVE_DAC indication is not set,
+ * treat it as a passive DAC cable, since some cables
+ * don't have this indication.
*/
- if (elink_read_sfp_module_eeprom(phy,
- params,
- ELINK_I2C_DEV_ADDR_A0,
- ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
- 1,
- &copper_module_type) !=
- 0) {
- PMD_DRV_LOG(DEBUG, sc,
- "Failed to read copper-cable-type"
- " from SFP+ EEPROM");
- return ELINK_STATUS_ERROR;
- }
-
if (copper_module_type &
- ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
- PMD_DRV_LOG(DEBUG, sc,
- "Active Copper cable detected");
- if (phy->type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
- *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
- else
- check_limiting_mode = 1;
- } else if (copper_module_type &
- ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)
- {
- PMD_DRV_LOG(DEBUG, sc,
- "Passive Copper cable detected");
- *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
+ ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
+ ELINK_DEBUG_P0(sc,
+ "Passive Copper cable detected");
} else {
- PMD_DRV_LOG(DEBUG, sc,
- "Unknown copper-cable-type 0x%x !!!",
- copper_module_type);
- return ELINK_STATUS_ERROR;
+ ELINK_DEBUG_P0(sc,
+ "Unknown copper-cable-type");
}
- break;
}
+ break;
+ }
+ case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
check_limiting_mode = 1;
- if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
- ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
- ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
- PMD_DRV_LOG(DEBUG, sc, "1G SFP module detected");
- gport = params->port;
+ /* Module is considered as 1G in case it's NOT compliant with
+ * any 10G ethernet protocol, but is 1G Ethernet compliant.
+ */
+ if (((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] &
+ (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK |
+ ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK |
+ ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
+ (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
+ ELINK_DEBUG_P0(sc, "1G SFP module detected");
phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
if (phy->req_line_speed != ELINK_SPEED_1000) {
+ uint8_t gport = params->port;
phy->req_line_speed = ELINK_SPEED_1000;
if (!CHIP_IS_E1x(sc)) {
gport = SC_PATH(sc) +
- (params->port << 1);
+ (params->port << 1);
}
- elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
- // " Current SFP module in port %d is not"
- // " compliant with 10G Ethernet",
+ elink_cb_event_log(sc,
+ ELINK_LOG_ID_NON_10G_MODULE,
+ gport);
+ /*"Warning: Link speed was forced to 1000Mbps."
+ *" Current SFP module in port %d is not"
+ *" compliant with 10G Ethernet",
+ */
+ }
+ if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] &
+ ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) {
+ /* Some 1G-baseT modules will not link up,
+ * unless TX_EN is toggled with long delay in
+ * between.
+ */
+ elink_sfp_set_transmitter(params, phy, 0);
+ DELAY(1000 * 40);
+ elink_sfp_set_transmitter(params, phy, 1);
}
} else {
int idx, cfg_idx = 0;
- PMD_DRV_LOG(DEBUG, sc, "10G Optic module detected");
+ ELINK_DEBUG_P0(sc, "10G Optic module detected");
for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
if (params->phy[idx].type == phy->type) {
cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
@@ -7646,24 +9185,22 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
}
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Unable to determine module type 0x%x !!!",
- val[0]);
+ ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!",
+ val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]);
return ELINK_STATUS_ERROR;
}
sync_offset = params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].media_type);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[params->port].media_type);
media_types = REG_RD(sc, sync_offset);
/* Update media type for non-PMF sync */
for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
if (&(params->phy[phy_idx]) == phy) {
media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
- (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
- phy_idx));
- media_types |=
- ((phy->
- media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
- (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
+ (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
+ media_types |= ((phy->media_type &
+ PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
+ (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
break;
}
}
@@ -7676,8 +9213,8 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
ELINK_SFP_EEPROM_OPTIONS_ADDR,
ELINK_SFP_EEPROM_OPTIONS_SIZE,
options) != 0) {
- PMD_DRV_LOG(DEBUG, sc,
- "Failed to read Option field from module EEPROM");
+ ELINK_DEBUG_P0(sc,
+ "Failed to read Option field from module EEPROM");
return ELINK_STATUS_ERROR;
}
if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
@@ -7685,15 +9222,14 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
else
*edc_mode = ELINK_EDC_MODE_LIMITING;
}
- PMD_DRV_LOG(DEBUG, sc, "EDC mode is set to 0x%x", *edc_mode);
+ ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x", *edc_mode);
return ELINK_STATUS_OK;
}
-
/* This function read the relevant field from the module (SFP+), and verify it
* is compliant with this board
*/
static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
- struct elink_params *params)
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint32_t val, cmd;
@@ -7702,12 +9238,11 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1];
phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
val = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config[params->port].
- config));
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].config));
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
- PMD_DRV_LOG(DEBUG, sc, "NOT enforcing module verification");
+ ELINK_DEBUG_P0(sc, "NOT enforcing module verification");
return ELINK_STATUS_OK;
}
@@ -7717,23 +9252,24 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
} else if (params->feature_config_flags &
ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
- /* Use first phy request only in case of non-dual media */
+ /* Use first phy request only in case of non-dual media*/
if (ELINK_DUAL_MEDIA(params)) {
- PMD_DRV_LOG(DEBUG, sc,
- "FW does not support OPT MDL verification");
+ ELINK_DEBUG_P0(sc,
+ "FW does not support OPT MDL verification");
return ELINK_STATUS_ERROR;
}
cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
} else {
/* No support in OPT MDL detection */
- PMD_DRV_LOG(DEBUG, sc, "FW does not support OPT MDL verification");
+ ELINK_DEBUG_P0(sc,
+ "FW does not support OPT MDL verification");
return ELINK_STATUS_ERROR;
}
fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
- PMD_DRV_LOG(DEBUG, sc, "Approved module");
+ ELINK_DEBUG_P0(sc, "Approved module");
return ELINK_STATUS_OK;
}
@@ -7743,7 +9279,7 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
ELINK_I2C_DEV_ADDR_A0,
ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
- (uint8_t *) vendor_name))
+ (uint8_t *)vendor_name))
vendor_name[0] = '\0';
else
vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
@@ -7752,13 +9288,16 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
ELINK_I2C_DEV_ADDR_A0,
ELINK_SFP_EEPROM_PART_NO_ADDR,
ELINK_SFP_EEPROM_PART_NO_SIZE,
- (uint8_t *) vendor_pn))
+ (uint8_t *)vendor_pn))
vendor_pn[0] = '\0';
else
vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
- elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
- // " Port %d from %s part number %s",
+ elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port,
+ vendor_name, vendor_pn);
+ /* "Warning: Unqualified SFP+ module detected,"
+ * " Port %d from %s part number %s",
+ */
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
@@ -7766,13 +9305,14 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
return ELINK_STATUS_ERROR;
}
-static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
- *phy,
- struct elink_params
- *params)
+static elink_status_t elink_wait_for_sfp_module_initialized(
+ struct elink_phy *phy,
+ struct elink_params *params)
+
{
uint8_t val;
elink_status_t rc;
+ struct bnx2x_softc *sc = params->sc;
uint16_t timeout;
/* Initialization time after hot-plug may take up to 300ms for
* some phys type ( e.g. JDSU )
@@ -7780,18 +9320,17 @@ static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
for (timeout = 0; timeout < 60; timeout++) {
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
- rc = elink_warpcore_read_sfp_module_eeprom(phy, params,
- ELINK_I2C_DEV_ADDR_A0,
- 1, 1, &val,
- 1);
+ rc = elink_warpcore_read_sfp_module_eeprom(
+ phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,
+ 1);
else
rc = elink_read_sfp_module_eeprom(phy, params,
ELINK_I2C_DEV_ADDR_A0,
1, 1, &val);
if (rc == 0) {
- PMD_DRV_LOG(DEBUG, params->sc,
- "SFP+ module initialization took %d ms",
- timeout * 5);
+ ELINK_DEBUG_P1(sc,
+ "SFP+ module initialization took %d ms",
+ timeout * 5);
return ELINK_STATUS_OK;
}
DELAY(1000 * 5);
@@ -7802,8 +9341,8 @@ static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
}
static void elink_8727_power_module(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t is_power_up)
-{
+ struct elink_phy *phy,
+ uint8_t is_power_up) {
/* Make sure GPIOs are not using for LED mode */
uint16_t val;
/* In the GPIO register, bit 4 is use to determine if the GPIOs are
@@ -7828,30 +9367,33 @@ static void elink_8727_power_module(struct bnx2x_softc *sc,
val = (1 << 1);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_GPIO_CTRL,
+ val);
}
static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- uint16_t edc_mode)
+ struct elink_phy *phy,
+ uint16_t edc_mode)
{
uint16_t cur_limiting_mode;
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);
- PMD_DRV_LOG(DEBUG, sc,
- "Current Limiting mode is 0x%x", cur_limiting_mode);
+ MDIO_PMA_REG_ROM_VER2,
+ &cur_limiting_mode);
+ ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x",
+ cur_limiting_mode);
if (edc_mode == ELINK_EDC_MODE_LIMITING) {
- PMD_DRV_LOG(DEBUG, sc, "Setting LIMITING MODE");
+ ELINK_DEBUG_P0(sc, "Setting LIMITING MODE");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_ROM_VER2,
ELINK_EDC_MODE_LIMITING);
- } else { /* LRM mode ( default ) */
+ } else { /* LRM mode ( default )*/
- PMD_DRV_LOG(DEBUG, sc, "Setting LRM MODE");
+ ELINK_DEBUG_P0(sc, "Setting LRM MODE");
/* Changing to LRM mode takes quite few seconds. So do it only
* if current mode is limiting (default is LRM)
@@ -7860,27 +9402,35 @@ static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
return ELINK_STATUS_OK;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_LRM_MODE,
+ 0);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_ROM_VER2,
+ 0x128);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_MISC_CTRL0, 0x4008);
+ MDIO_PMA_REG_MISC_CTRL0,
+ 0x4008);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_LRM_MODE,
+ 0xaaaa);
}
return ELINK_STATUS_OK;
}
static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- uint16_t edc_mode)
+ struct elink_phy *phy,
+ uint16_t edc_mode)
{
uint16_t phy_identifier;
uint16_t rom_ver2_val;
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier);
+ MDIO_PMA_REG_PHY_IDENTIFIER,
+ &phy_identifier);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -7888,7 +9438,9 @@ static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,
(phy_identifier & ~(1 << 9)));
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_ROM_VER2,
+ &rom_ver2_val);
/* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -7922,12 +9474,14 @@ static void elink_8727_specific_func(struct elink_phy *phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
(1 << 2) | (1 << 5));
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
+ 0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
/* Make MOD_ABS give interrupt on change */
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
+ MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+ &val);
val |= (1 << 12);
if (phy->flags & ELINK_FLAGS_NOC)
val |= (3 << 5);
@@ -7935,29 +9489,27 @@ static void elink_8727_specific_func(struct elink_phy *phy,
* status which reflect SFP+ module over-current
*/
if (!(phy->flags & ELINK_FLAGS_NOC))
- val &= 0xff8f; /* Reset bits 4-6 */
+ val &= 0xff8f; /* Reset bits 4-6 */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
val);
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Function 0x%x not supported by 8727",
- action);
+ ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727",
+ action);
return;
}
}
static void elink_set_e1e2_module_fault_led(struct elink_params *params,
- uint8_t gpio_mode)
+ uint8_t gpio_mode)
{
struct bnx2x_softc *sc = params->sc;
uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[params->port].
- sfp_ctrl)) &
- PORT_HW_CFG_FAULT_MODULE_LED_MASK;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[params->port].sfp_ctrl)) &
+ PORT_HW_CFG_FAULT_MODULE_LED_MASK;
switch (fault_led_gpio) {
case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
return;
@@ -7965,19 +9517,19 @@ static void elink_set_e1e2_module_fault_led(struct elink_params *params,
case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
- {
- uint8_t gpio_port = elink_get_gpio_port(params);
- uint16_t gpio_pin = fault_led_gpio -
- PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
- PMD_DRV_LOG(DEBUG, sc, "Set fault module-detected led "
- "pin %x port %x mode %x",
- gpio_pin, gpio_port, gpio_mode);
- elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
- }
- break;
+ {
+ uint8_t gpio_port = elink_get_gpio_port(params);
+ uint16_t gpio_pin = fault_led_gpio -
+ PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
+ ELINK_DEBUG_P3(sc, "Set fault module-detected led "
+ "pin %x port %x mode %x",
+ gpio_pin, gpio_port, gpio_mode);
+ elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
+ }
+ break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Error: Invalid fault led mode 0x%x",
- fault_led_gpio);
+ ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x",
+ fault_led_gpio);
}
}
@@ -7988,12 +9540,12 @@ static void elink_set_e3_module_fault_led(struct elink_params *params,
uint8_t port = params->port;
struct bnx2x_softc *sc = params->sc;
pin_cfg = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].e3_sfp_ctrl)) &
- PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
- PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
- PMD_DRV_LOG(DEBUG, sc, "Setting Fault LED to %d using pin cfg %d",
- gpio_mode, pin_cfg);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].e3_sfp_ctrl)) &
+ PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
+ PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
+ ELINK_DEBUG_P2(sc, "Setting Fault LED to %d using pin cfg %d",
+ gpio_mode, pin_cfg);
elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
}
@@ -8001,8 +9553,7 @@ static void elink_set_sfp_module_fault_led(struct elink_params *params,
uint8_t gpio_mode)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc,
- "Setting SFP+ module fault LED to %d", gpio_mode);
+ ELINK_DEBUG_P1(sc, "Setting SFP+ module fault LED to %d", gpio_mode);
if (CHIP_IS_E3(sc)) {
/* Low ==> if SFP+ module is supported otherwise
* High ==> if SFP+ module is not on the approved vendor list
@@ -8027,9 +9578,11 @@ static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,
}
static void elink_power_sfp_module(struct elink_params *params,
- struct elink_phy *phy, uint8_t power)
+ struct elink_phy *phy,
+ uint8_t power)
{
- PMD_DRV_LOG(DEBUG, params->sc, "Setting SFP+ power to %x", power);
+ struct bnx2x_softc *sc = params->sc;
+ ELINK_DEBUG_P1(sc, "Setting SFP+ power to %x", power);
switch (phy->type) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
@@ -8043,7 +9596,6 @@ static void elink_power_sfp_module(struct elink_params *params,
break;
}
}
-
static void elink_warpcore_set_limiting_mode(struct elink_params *params,
struct elink_phy *phy,
uint16_t edc_mode)
@@ -8052,7 +9604,7 @@ static void elink_warpcore_set_limiting_mode(struct elink_params *params,
uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
struct bnx2x_softc *sc = params->sc;
- uint8_t lane = elink_get_warpcore_lane(params);
+ uint8_t lane = elink_get_warpcore_lane(phy, params);
/* This is a global register which controls all lanes */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
@@ -8085,7 +9637,8 @@ static void elink_warpcore_set_limiting_mode(struct elink_params *params,
}
static void elink_set_limiting_mode(struct elink_params *params,
- struct elink_phy *phy, uint16_t edc_mode)
+ struct elink_phy *phy,
+ uint16_t edc_mode)
{
switch (phy->type) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
@@ -8101,30 +9654,28 @@ static void elink_set_limiting_mode(struct elink_params *params,
}
}
-static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
- struct elink_params *params)
+elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint16_t edc_mode;
elink_status_t rc = ELINK_STATUS_OK;
uint32_t val = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config[params->
- port].
- config));
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].config));
/* Enabled transmitter by default */
elink_sfp_set_transmitter(params, phy, 1);
- PMD_DRV_LOG(DEBUG, sc, "SFP+ module plugged in/out detected on port %d",
- params->port);
+ ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d",
+ params->port);
/* Power up module */
elink_power_sfp_module(params, phy, 1);
if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to get valid module type");
+ ELINK_DEBUG_P0(sc, "Failed to get valid module type");
return ELINK_STATUS_ERROR;
} else if (elink_verify_sfp_module(phy, params) != 0) {
/* Check SFP+ module compatibility */
- PMD_DRV_LOG(DEBUG, sc, "Module verification failed!!");
+ ELINK_DEBUG_P0(sc, "Module verification failed!!");
rc = ELINK_STATUS_ERROR;
/* Turn on fault module-detected led */
elink_set_sfp_module_fault_led(params,
@@ -8132,8 +9683,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
/* Check if need to power down the SFP+ module */
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
- PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
- PMD_DRV_LOG(DEBUG, sc, "Shutdown SFP+ module!!");
+ PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
+ ELINK_DEBUG_P0(sc, "Shutdown SFP+ module!!");
elink_power_sfp_module(params, phy, 0);
return rc;
}
@@ -8166,22 +9717,22 @@ void elink_handle_module_detect_int(struct elink_params *params)
uint8_t gpio_num, gpio_port;
if (CHIP_IS_E3(sc)) {
phy = ¶ms->phy[ELINK_INT_PHY];
- /* Always enable TX laser,will be disabled in case of fault */
+ /* Always enable TX laser, will be disabled in case of fault */
elink_sfp_set_transmitter(params, phy, 1);
} else {
phy = ¶ms->phy[ELINK_EXT_PHY1];
}
- if (elink_get_mod_abs_int_cfg(sc, params->shmem_base,
+ if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base,
params->port, &gpio_num, &gpio_port) ==
ELINK_STATUS_ERROR) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to get MOD_ABS interrupt config");
+ ELINK_DEBUG_P0(sc, "Failed to get MOD_ABS interrupt config");
return;
}
/* Set valid module led off */
elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
- /* Get current gpio val reflecting module plugged in / out */
+ /* Get current gpio val reflecting module plugged in / out*/
gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
/* Call the handling function in case module is detected */
@@ -8191,8 +9742,8 @@ void elink_handle_module_detect_int(struct elink_params *params)
elink_power_sfp_module(params, phy, 1);
elink_cb_gpio_int_write(sc, gpio_num,
- MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
- gpio_port);
+ MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
+ gpio_port);
if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
elink_sfp_module_detection(phy, params);
if (CHIP_IS_E3(sc)) {
@@ -8214,12 +9765,12 @@ void elink_handle_module_detect_int(struct elink_params *params)
}
}
} else {
- PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
+ ELINK_DEBUG_P0(sc, "SFP+ module is not initialized");
}
} else {
elink_cb_gpio_int_write(sc, gpio_num,
- MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
- gpio_port);
+ MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
+ gpio_port);
/* Module was plugged out.
* Disable transmit for this module
*/
@@ -8237,9 +9788,11 @@ static void elink_sfp_mask_fault(struct bnx2x_softc *sc,
{
uint16_t alarm_status, val;
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
+ MDIO_PMA_DEVAD, alarm_status_offset,
+ &alarm_status);
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
+ MDIO_PMA_DEVAD, alarm_status_offset,
+ &alarm_status);
/* Mask or enable the fault event. */
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
if (alarm_status & (1 << 0))
@@ -8248,38 +9801,42 @@ static void elink_sfp_mask_fault(struct bnx2x_softc *sc,
val |= (1 << 0);
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
}
-
/******************************************************************/
/* common BNX2X8706/BNX2X8726 PHY SECTION */
/******************************************************************/
static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint8_t link_up = 0;
uint16_t val1, val2, rx_sd, pcs_status;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "XGXS 8706/8726");
- /* Clear RX Alarm */
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
+ ELINK_DEBUG_P0(sc, "XGXS 8706/8726");
+ /* Clear RX Alarm*/
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
MDIO_PMA_LASI_TXCTRL);
- /* Clear LASI indication */
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
- PMD_DRV_LOG(DEBUG, sc,
- "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
+ /* Clear LASI indication*/
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
+ ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
elink_cl45_read(sc, phy,
MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
- PMD_DRV_LOG(DEBUG, sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
- " link_status 0x%x", rx_sd, pcs_status, val2);
+ ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
+ " link_status 0x%x", rx_sd, pcs_status, val2);
/* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
* are set, or if the autoneg bit 1 is set
*/
@@ -8296,9 +9853,9 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
/* Capture 10G link fault. Read twice to clear stale value. */
if (vars->line_speed == ELINK_SPEED_10000) {
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_TXSTAT, &val1);
+ MDIO_PMA_LASI_TXSTAT, &val1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_TXSTAT, &val1);
+ MDIO_PMA_LASI_TXSTAT, &val1);
if (val1 & (1 << 0))
vars->fault_detected = 1;
}
@@ -8310,15 +9867,15 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
/* BNX2X8706 PHY SECTION */
/******************************************************************/
static uint8_t elink_8706_config_init(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars *vars)
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
uint32_t tx_en_mode;
uint16_t cnt, val, tmp1;
struct bnx2x_softc *sc = params->sc;
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
/* HW reset */
elink_ext_phy_hw_reset(sc, params->port);
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
@@ -8332,34 +9889,35 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
break;
DELAY(1000 * 10);
}
- PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 is initialized after %d ms", cnt);
+ ELINK_DEBUG_P1(sc, "XGXS 8706 is initialized after %d ms", cnt);
if ((params->feature_config_flags &
ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
uint8_t i;
uint16_t reg;
for (i = 0; i < 4; i++) {
reg = MDIO_XS_8706_REG_BANK_RX0 +
- i * (MDIO_XS_8706_REG_BANK_RX1 -
- MDIO_XS_8706_REG_BANK_RX0);
+ i * (MDIO_XS_8706_REG_BANK_RX1 -
+ MDIO_XS_8706_REG_BANK_RX0);
elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
/* Clear first 3 bits of the control */
val &= ~0x7;
/* Set control bits according to configuration */
val |= (phy->rx_preemphasis[i] & 0x7);
- PMD_DRV_LOG(DEBUG, sc, "Setting RX Equalizer to BNX2X8706"
- " reg 0x%x <-- val 0x%x", reg, val);
+ ELINK_DEBUG_P2(sc, "Setting RX Equalizer to BNX2X8706"
+ " reg 0x%x <-- val 0x%x", reg, val);
elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
}
}
/* Force speed */
if (phy->req_line_speed == ELINK_SPEED_10000) {
- PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 force 10Gbps");
+ ELINK_DEBUG_P0(sc, "XGXS 8706 force 10Gbps");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
+ 0);
/* Arm LASI for link and Tx fault. */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
@@ -8367,7 +9925,7 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
/* Force 1Gbps using autoneg with 1G advertisement */
/* Allow CL37 through CL73 */
- PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 AutoNeg");
+ ELINK_DEBUG_P0(sc, "XGXS 8706 AutoNeg");
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
@@ -8385,9 +9943,11 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
+ 0x0400);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
+ 0x0004);
}
elink_save_bnx2x_spirom_ver(sc, phy, params->port);
@@ -8397,27 +9957,24 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
tx_en_mode = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- sfp_ctrl))
- & PORT_HW_CFG_TX_LASER_MASK;
+ dev_info.port_hw_config[params->port].sfp_ctrl))
+ & PORT_HW_CFG_TX_LASER_MASK;
if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
- PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
+ ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS");
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
- &tmp1);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
tmp1 |= 0x1;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
- tmp1);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
}
return ELINK_STATUS_OK;
}
-static uint8_t elink_8706_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static elink_status_t elink_8706_read_status(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
return elink_8706_8726_read_status(phy, params, vars);
}
@@ -8429,7 +9986,7 @@ static void elink_8726_config_loopback(struct elink_phy *phy,
struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "PMA/PMD ext_phy_loopback: 8726");
+ ELINK_DEBUG_P0(sc, "PMA/PMD ext_phy_loopback: 8726");
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
}
@@ -8451,7 +10008,8 @@ static void elink_8726_external_rom_boot(struct elink_phy *phy,
MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_MISC_CTRL1, 0x0001);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -8463,15 +10021,16 @@ static void elink_8726_external_rom_boot(struct elink_phy *phy,
/* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_MISC_CTRL1, 0x0000);
DELAY(1000 * 200);
elink_save_bnx2x_spirom_ver(sc, phy, params->port);
}
static uint8_t elink_8726_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val1;
@@ -8481,7 +10040,7 @@ static uint8_t elink_8726_read_status(struct elink_phy *phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
&val1);
if (val1 & (1 << 15)) {
- PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
+ ELINK_DEBUG_P0(sc, "Tx is disabled");
link_up = 0;
vars->line_speed = 0;
}
@@ -8489,12 +10048,13 @@ static uint8_t elink_8726_read_status(struct elink_phy *phy,
return link_up;
}
-static uint8_t elink_8726_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+
+static elink_status_t elink_8726_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8726");
+ ELINK_DEBUG_P0(sc, "Initializing BNX2X8726");
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
elink_wait_reset_complete(sc, phy, params);
@@ -8509,7 +10069,7 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
elink_sfp_module_detection(phy, params);
if (phy->req_line_speed == ELINK_SPEED_1000) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
+ ELINK_DEBUG_P0(sc, "Setting 1G force");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
elink_cl45_write(sc, phy,
@@ -8517,17 +10077,19 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
+ 0x400);
} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
((phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
+ ELINK_DEBUG_P0(sc, "Setting 1G clause37");
/* Set Flow control */
elink_ext_phy_set_pause(params, phy, vars);
- elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
+ elink_cl45_write(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
elink_cl45_write(sc, phy,
@@ -8535,16 +10097,17 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
elink_cl45_write(sc, phy,
- MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
/* Enable RX-ALARM control to receive interrupt for 1G speed
* change
*/
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
+ 0x400);
- } else { /* Default 10G. Set only LASI control */
+ } else { /* Default 10G. Set only LASI control */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
}
@@ -8552,9 +10115,10 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
/* Set TX PreEmphasis if needed */
if ((params->feature_config_flags &
ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
- PMD_DRV_LOG(DEBUG, sc,
- "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
- phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
+ ELINK_DEBUG_P2(sc,
+ "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
+ phy->tx_preemphasis[0],
+ phy->tx_preemphasis[1]);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8726_TX_CTRL1,
@@ -8574,10 +10138,11 @@ static void elink_8726_link_reset(struct elink_phy *phy,
struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "elink_8726_link_reset port %d", params->port);
+ ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d", params->port);
/* Set serial boot control for external load */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_GEN_CTRL, 0x0001);
}
/******************************************************************/
@@ -8610,22 +10175,28 @@ static void elink_8727_set_link_led(struct elink_phy *phy,
break;
}
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+ &val);
val &= 0xff8f;
val |= led_mode_bitmask;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+ val);
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_GPIO_CTRL,
+ &val);
val &= 0xffe0;
val |= gpio_pins_bitmask;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_GPIO_CTRL,
+ val);
}
-
static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,
- struct elink_params *params)
-{
+ struct elink_params *params) {
uint32_t swap_val, swap_override;
uint8_t port;
/* The PHY reset is controlled by GPIO 1. Fake the port number
@@ -8636,7 +10207,7 @@ static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,
swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
port = (swap_val && swap_override) ^ 1;
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
}
static void elink_8727_config_speed(struct elink_phy *phy,
@@ -8647,14 +10218,14 @@ static void elink_8727_config_speed(struct elink_phy *phy,
/* Set option 1G speed */
if ((phy->req_line_speed == ELINK_SPEED_1000) ||
(phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
+ ELINK_DEBUG_P0(sc, "Setting 1G force");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
- PMD_DRV_LOG(DEBUG, sc, "1.7 = 0x%x", tmp1);
+ ELINK_DEBUG_P1(sc, "1.7 = 0x%x", tmp1);
/* Power down the XAUI until link is up in case of dual-media
* and 1G
*/
@@ -8671,10 +10242,10 @@ static void elink_8727_config_speed(struct elink_phy *phy,
((phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
((phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
+ ELINK_DEBUG_P0(sc, "Setting 1G clause37");
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
elink_cl45_write(sc, phy,
@@ -8696,10 +10267,9 @@ static void elink_8727_config_speed(struct elink_phy *phy,
}
}
-static uint8_t elink_8727_config_init(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars
- *vars)
+static elink_status_t elink_8727_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
uint32_t tx_en_mode;
uint16_t tmp1, mod_abs, tmp2;
@@ -8708,7 +10278,7 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,
elink_wait_reset_complete(sc, phy, params);
- PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8727");
+ ELINK_DEBUG_P0(sc, "Initializing BNX2X8727");
elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
/* Initially configure MOD_ABS to interrupt when module is
@@ -8734,15 +10304,18 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
elink_8727_config_speed(phy, params);
+
/* Set TX PreEmphasis if needed */
if ((params->feature_config_flags &
ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
- PMD_DRV_LOG(DEBUG, sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
- phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
+ ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
+ phy->tx_preemphasis[0],
+ phy->tx_preemphasis[1]);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
phy->tx_preemphasis[0]);
@@ -8757,25 +10330,24 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,
*/
tx_en_mode = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- sfp_ctrl))
- & PORT_HW_CFG_TX_LASER_MASK;
+ dev_info.port_hw_config[params->port].sfp_ctrl))
+ & PORT_HW_CFG_TX_LASER_MASK;
if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
- PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
+ ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS");
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
- &tmp2);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
tmp2 |= 0x1000;
tmp2 &= 0xFFEF;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
- tmp2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2);
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff));
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
+ &tmp2);
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
+ (tmp2 & 0x7fff));
}
return ELINK_STATUS_OK;
@@ -8787,15 +10359,17 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t mod_abs, rx_alarm_status;
uint32_t val = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config[params->
- port].config));
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
- &mod_abs);
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].
+ config));
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
if (mod_abs & (1 << 8)) {
/* Module is absent */
- PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is absent");
+ ELINK_DEBUG_P0(sc,
+ "MOD_ABS indication show module is absent");
phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
/* 1. Set mod_abs to detect next module
* presence event
@@ -8820,7 +10394,8 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,
} else {
/* Module is present */
- PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is present");
+ ELINK_DEBUG_P0(sc,
+ "MOD_ABS indication show module is present");
/* First disable transmitter, and if the module is ok, the
* module_detection will enable it
* 1. Set mod_abs to detect next module absent event ( bit 8)
@@ -8844,51 +10419,56 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,
MDIO_PMA_DEVAD,
MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
+
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
elink_sfp_set_transmitter(params, phy, 0);
- if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
+ if (elink_wait_for_sfp_module_initialized(phy, params) == 0)
elink_sfp_module_detection(phy, params);
- } else {
- PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
- }
+ else
+ ELINK_DEBUG_P0(sc, "SFP+ module is not initialized");
/* Reconfigure link speed based on module type limitations */
elink_8727_config_speed(phy, params);
}
- PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
+ ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x",
+ rx_alarm_status);
/* No need to check link status in case of module plugged in/out */
}
static uint8_t elink_8727_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
+
{
struct bnx2x_softc *sc = params->sc;
- uint8_t link_up = 0, oc_port = params->port;
+ uint8_t link_up = 0;
uint16_t link_status = 0;
uint16_t rx_alarm_status, lasi_ctrl, val1;
/* If PHY is not initialized, do not check link status */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
+ &lasi_ctrl);
if (!lasi_ctrl)
return 0;
/* Check the LASI on Rx */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
+ &rx_alarm_status);
vars->line_speed = 0;
- PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
+ ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
MDIO_PMA_LASI_TXCTRL);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8727 LASI status 0x%x", val1);
+ ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x", val1);
/* Clear MSG-OUT */
elink_cl45_read(sc, phy,
@@ -8898,24 +10478,28 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
* for over current
*/
if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) {
- /* Check over-current using 8727 GPIO0 input */
+ /* Check over-current using 8727 GPIO0 input*/
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
&val1);
if ((val1 & (1 << 8)) == 0) {
+ uint8_t oc_port = params->port;
if (!CHIP_IS_E1x(sc))
oc_port = SC_PATH(sc) + (params->port << 1);
- PMD_DRV_LOG(DEBUG, sc,
- "8727 Power fault has been detected on port %d",
- oc_port);
- elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
- // "been detected and the power to "
- // "that SFP+ module has been removed "
- // "to prevent failure of the card. "
- // "Please remove the SFP+ module and "
- // "restart the system to clear this "
- // "error.",
+ ELINK_DEBUG_P1(sc,
+ "8727 Power fault has been detected on port %d",
+ oc_port);
+ elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT,
+ oc_port);
+ /* "Error: Power fault on Port %d has "
+ * "been detected and the power to "
+ * "that SFP+ module has been removed "
+ * "to prevent failure of the card. "
+ * "Please remove the SFP+ module and "
+ * "restart the system to clear this "
+ * "error.",
+ */
/* Disable all RX_ALARMs except for mod_abs */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -8931,14 +10515,13 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
MDIO_PMA_REG_PHY_IDENTIFIER, val1);
/* Clear RX alarm */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
elink_8727_power_module(params->sc, phy, 0);
return 0;
}
- }
+ } /* Over current check */
- /* Over current check */
/* When module absent bit is set, check module */
if (rx_alarm_status & (1 << 5)) {
elink_8727_handle_mod_abs(phy, params);
@@ -8949,10 +10532,10 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
}
if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
- PMD_DRV_LOG(DEBUG, sc, "Enabling 8727 TX laser");
+ ELINK_DEBUG_P0(sc, "Enabling 8727 TX laser");
elink_sfp_set_transmitter(params, phy, 1);
} else {
- PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
+ ELINK_DEBUG_P0(sc, "Tx is disabled");
return 0;
}
@@ -8966,26 +10549,26 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_10000;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 10G",
+ params->port);
} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_1000;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 1G",
+ params->port);
} else {
link_up = 0;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link is down",
+ params->port);
}
/* Capture 10G link fault. */
if (vars->line_speed == ELINK_SPEED_10000) {
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_TXSTAT, &val1);
+ MDIO_PMA_LASI_TXSTAT, &val1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_TXSTAT, &val1);
+ MDIO_PMA_LASI_TXSTAT, &val1);
if (val1 & (1 << 0)) {
vars->fault_detected = 1;
@@ -8995,7 +10578,7 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
if (link_up) {
elink_ext_phy_resolve_fc(phy, params, vars);
vars->duplex = DUPLEX_FULL;
- PMD_DRV_LOG(DEBUG, sc, "duplex = 0x%x", vars->duplex);
+ ELINK_DEBUG_P1(sc, "duplex = 0x%x", vars->duplex);
}
if ((ELINK_DUAL_MEDIA(params)) &&
@@ -9035,8 +10618,16 @@ static void elink_8727_link_reset(struct elink_phy *phy,
/******************************************************************/
/* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */
/******************************************************************/
+static int elink_is_8483x_8485x(struct elink_phy *phy)
+{
+ return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
+ (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) ||
+ (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858));
+}
+
static void elink_save_848xx_spirom_version(struct elink_phy *phy,
- struct bnx2x_softc *sc, uint8_t port)
+ struct bnx2x_softc *sc,
+ uint8_t port)
{
uint16_t val, fw_ver2, cnt, i;
static struct elink_reg_set reg_set[] = {
@@ -9048,11 +10639,10 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
};
uint16_t fw_ver1;
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
+ if (elink_is_8483x_8485x(phy)) {
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
- phy->ver_addr);
+ phy->ver_addr);
} else {
/* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
/* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
@@ -9067,12 +10657,14 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
DELAY(5);
}
if (cnt == 100) {
- PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx "
- "phy fw version(1)");
- elink_save_spirom_version(sc, port, 0, phy->ver_addr);
+ ELINK_DEBUG_P0(sc, "Unable to read 848xx "
+ "phy fw version(1)");
+ elink_save_spirom_version(sc, port, 0,
+ phy->ver_addr);
return;
}
+
/* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
@@ -9084,9 +10676,10 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
DELAY(5);
}
if (cnt == 100) {
- PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx phy fw "
- "version(2)");
- elink_save_spirom_version(sc, port, 0, phy->ver_addr);
+ ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw "
+ "version(2)");
+ elink_save_spirom_version(sc, port, 0,
+ phy->ver_addr);
return;
}
@@ -9100,8 +10693,8 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
}
}
-
-static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)
+static void elink_848xx_set_led(struct bnx2x_softc *sc,
+ struct elink_phy *phy)
{
uint16_t val, offset, i;
static struct elink_reg_set reg_set[] = {
@@ -9110,29 +10703,30 @@ static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)
{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
{MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
- MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
+ MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
{MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
};
/* PHYC_CTL_LED_CTL */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
val &= 0xFE00;
val |= 0x0092;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LINK_SIGNAL, val);
for (i = 0; i < ARRAY_SIZE(reg_set); i++)
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
reg_set[i].val);
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
+ if (elink_is_8483x_8485x(phy))
offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
else
offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
- /* stretch_en for LED3 */
+ /* stretch_en for LED3*/
elink_cl45_read_or_write(sc, phy,
MDIO_PMA_DEVAD, offset,
MDIO_PMA_REG_84823_LED3_STRETCH_EN);
@@ -9145,8 +10739,7 @@ static void elink_848xx_specific_func(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
switch (action) {
case ELINK_PHY_INIT:
- if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
- (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
+ if (!elink_is_8483x_8485x(phy)) {
/* Save spirom version */
elink_save_848xx_spirom_version(phy, sc, params->port);
}
@@ -9163,14 +10756,15 @@ static void elink_848xx_specific_func(struct elink_phy *phy,
}
static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t autoneg_val, an_1000_val, an_10_100_val;
elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
/* set 1000 speed advertisement */
elink_cl45_read(sc, phy,
@@ -9180,24 +10774,25 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
elink_ext_phy_set_pause(params, phy, vars);
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val);
+ MDIO_AN_REG_8481_LEGACY_AN_ADV,
+ &an_10_100_val);
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
&autoneg_val);
/* Disable forced speed */
- autoneg_val &=
- ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
+ autoneg_val &= ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) |
+ (1 << 13));
an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));
if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
(phy->req_line_speed == ELINK_SPEED_1000)) {
an_1000_val |= (1 << 8);
autoneg_val |= (1 << 9 | 1 << 12);
if (phy->req_duplex == DUPLEX_FULL)
an_1000_val |= (1 << 9);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
+ ELINK_DEBUG_P0(sc, "Advertising 1G");
} else
an_1000_val &= ~((1 << 8) | (1 << 9));
@@ -9213,7 +10808,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
*/
autoneg_val |= (1 << 9 | 1 << 12);
an_10_100_val |= (1 << 8);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
+ ELINK_DEBUG_P0(sc, "Advertising 100M-FD");
}
if (phy->speed_cap_mask &
@@ -9222,7 +10817,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
*/
autoneg_val |= (1 << 9 | 1 << 12);
an_10_100_val |= (1 << 7);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
+ ELINK_DEBUG_P0(sc, "Advertising 100M-HD");
}
if ((phy->speed_cap_mask &
@@ -9230,7 +10825,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
an_10_100_val |= (1 << 6);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
+ ELINK_DEBUG_P0(sc, "Advertising 10M-FD");
}
if ((phy->speed_cap_mask &
@@ -9238,14 +10833,15 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
an_10_100_val |= (1 << 5);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
+ ELINK_DEBUG_P0(sc, "Advertising 10M-HD");
}
}
/* Only 10/100 are allowed to work in FORCE mode */
if ((phy->req_line_speed == ELINK_SPEED_100) &&
(phy->supported &
- (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) {
+ (ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full))) {
autoneg_val |= (1 << 13);
/* Enabled AUTO-MDIX when autoneg is disabled */
elink_cl45_write(sc, phy,
@@ -9253,16 +10849,17 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(1 << 15 | 1 << 9 | 7 << 0));
/* The PHY needs this set even for forced link. */
an_10_100_val |= (1 << 8) | (1 << 7);
- PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
+ ELINK_DEBUG_P0(sc, "Setting 100M force");
}
if ((phy->req_line_speed == ELINK_SPEED_10) &&
(phy->supported &
- (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) {
+ (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full))) {
/* Enabled AUTO-MDIX when autoneg is disabled */
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
(1 << 15 | 1 << 9 | 7 << 0));
- PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
+ ELINK_DEBUG_P0(sc, "Setting 10M force");
}
elink_cl45_write(sc, phy,
@@ -9275,42 +10872,44 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
/* Always write this if this is not 84833/4.
* For 84833/4, write it only when it's a forced speed.
*/
- if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
- (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) ||
+ if (!elink_is_8483x_8485x(phy) ||
((autoneg_val & (1 << 12)) == 0))
elink_cl45_write(sc, phy,
- MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
(phy->req_line_speed == ELINK_SPEED_10000)) {
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10G");
- /* Restart autoneg for 10G */
+ ELINK_DEBUG_P0(sc, "Advertising 10G");
+ /* Restart autoneg for 10G*/
- elink_cl45_read_or_write(sc, phy,
- MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
- 0x1000);
+ elink_cl45_read_or_write(
+ sc, phy,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
+ 0x1000);
elink_cl45_write(sc, phy,
- MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200);
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
+ 0x3200);
} else
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1);
+ MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
+ 1);
return ELINK_STATUS_OK;
}
-static uint8_t elink_8481_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static elink_status_t elink_8481_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
- /* Restore normal power mode */
+ /* Restore normal power mode*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
/* HW reset */
elink_ext_phy_hw_reset(sc, params->port);
@@ -9320,101 +10919,219 @@ static uint8_t elink_8481_config_init(struct elink_phy *phy,
return elink_848xx_cmn_config_init(phy, params, vars);
}
-#define PHY84833_CMDHDLR_WAIT 300
-#define PHY84833_CMDHDLR_MAX_ARGS 5
-static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
+#define PHY848xx_CMDHDLR_WAIT 300
+#define PHY848xx_CMDHDLR_MAX_ARGS 5
+
+static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy,
struct elink_params *params,
- uint16_t fw_cmd, uint16_t cmd_args[],
- int argc)
+ uint16_t fw_cmd,
+ uint16_t cmd_args[], int argc)
+{
+ int idx;
+ uint16_t val;
+ struct bnx2x_softc *sc = params->sc;
+
+ /* Step 1: Poll the STATUS register to see whether the previous command
+ * is in progress or the system is busy (CMD_IN_PROGRESS or
+ * SYSTEM_BUSY). If previous command is in progress or system is busy,
+ * check again until the previous command finishes execution and the
+ * system is available for taking command
+ */
+
+ for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
+ elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_STATUS, &val);
+ if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
+ (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
+ break;
+ DELAY(1000 * 1);
+ }
+ if (idx >= PHY848xx_CMDHDLR_WAIT) {
+ ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.");
+ return ELINK_STATUS_ERROR;
+ }
+
+ /* Step2: If any parameters are required for the function, write them
+ * to the required DATA registers
+ */
+
+ for (idx = 0; idx < argc; idx++) {
+ elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_DATA1 + idx,
+ cmd_args[idx]);
+ }
+
+ /* Step3: When the firmware is ready for commands, write the 'Command
+ * code' to the CMD register
+ */
+ elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
+
+ /* Step4: Once the command has been written, poll the STATUS register
+ * to check whether the command has completed (CMD_COMPLETED_PASS/
+ * CMD_FOR_CMDS or CMD_COMPLETED_ERROR).
+ */
+
+ for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
+ elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_STATUS, &val);
+ if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
+ (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
+ break;
+ DELAY(1000 * 1);
+ }
+ if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
+ (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
+ ELINK_DEBUG_P0(sc, "FW cmd failed.");
+ return ELINK_STATUS_ERROR;
+ }
+ /* Step5: Once the command has completed, read the specficied DATA
+ * registers for any saved results for the command, if applicable
+ */
+
+ /* Gather returning data */
+ for (idx = 0; idx < argc; idx++) {
+ elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_DATA1 + idx,
+ &cmd_args[idx]);
+ }
+
+ return ELINK_STATUS_OK;
+}
+
+static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
+ struct elink_params *params, uint16_t fw_cmd,
+ uint16_t cmd_args[], int argc, int process)
{
int idx;
uint16_t val;
struct bnx2x_softc *sc = params->sc;
+ elink_status_t rc = ELINK_STATUS_OK;
+
+ if (process == PHY84833_MB_PROCESS2) {
/* Write CMD_OPEN_OVERRIDE to STATUS reg */
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_STATUS,
- PHY84833_STATUS_CMD_OPEN_OVERRIDE);
- for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
+ MDIO_848xx_CMD_HDLR_STATUS,
+ PHY84833_STATUS_CMD_OPEN_OVERRIDE);
+ }
+
+ for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_STATUS, &val);
+ MDIO_848xx_CMD_HDLR_STATUS, &val);
if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
break;
DELAY(1000 * 1);
}
- if (idx >= PHY84833_CMDHDLR_WAIT) {
- PMD_DRV_LOG(DEBUG, sc, "FW cmd: FW not ready.");
+ if (idx >= PHY848xx_CMDHDLR_WAIT) {
+ ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.");
+ /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR
+ * clear the status to CMD_CLEAR_COMPLETE
+ */
+ if (val == PHY84833_STATUS_CMD_COMPLETE_PASS ||
+ val == PHY84833_STATUS_CMD_COMPLETE_ERROR) {
+ elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_STATUS,
+ PHY84833_STATUS_CMD_CLEAR_COMPLETE);
+ }
return ELINK_STATUS_ERROR;
}
-
- /* Prepare argument(s) and issue command */
+ if (process == PHY84833_MB_PROCESS1 ||
+ process == PHY84833_MB_PROCESS2) {
+ /* Prepare argument(s) */
for (idx = 0; idx < argc; idx++) {
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_DATA1 + idx,
- cmd_args[idx]);
+ MDIO_848xx_CMD_HDLR_DATA1 + idx,
+ cmd_args[idx]);
}
+ }
+
+ /* Issue command */
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
- for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
+ MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
+ for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_STATUS, &val);
+ MDIO_848xx_CMD_HDLR_STATUS, &val);
if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
- (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
+ (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
break;
DELAY(1000 * 1);
}
- if ((idx >= PHY84833_CMDHDLR_WAIT) ||
- (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
- PMD_DRV_LOG(DEBUG, sc, "FW cmd failed.");
- return ELINK_STATUS_ERROR;
+ if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
+ (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
+ ELINK_DEBUG_P0(sc, "FW cmd failed.");
+ rc = ELINK_STATUS_ERROR;
}
+ if (process == PHY84833_MB_PROCESS3 && rc == ELINK_STATUS_OK) {
/* Gather returning data */
for (idx = 0; idx < argc; idx++) {
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_DATA1 + idx,
+ MDIO_848xx_CMD_HDLR_DATA1 + idx,
&cmd_args[idx]);
}
+ }
+ if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR ||
+ val == PHY84833_STATUS_CMD_COMPLETE_PASS) {
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_STATUS,
- PHY84833_STATUS_CMD_CLEAR_COMPLETE);
- return ELINK_STATUS_OK;
+ MDIO_848xx_CMD_HDLR_STATUS,
+ PHY84833_STATUS_CMD_CLEAR_COMPLETE);
+ }
+ return rc;
}
-static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars
- *vars)
+static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy,
+ struct elink_params *params,
+ uint16_t fw_cmd,
+ uint16_t cmd_args[], int argc,
+ int process)
+{
+ struct bnx2x_softc *sc = params->sc;
+
+ if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858) ||
+ (REG_RD(sc, params->shmem2_base +
+ offsetof(struct shmem2_region,
+ link_attr_sync[params->port])) &
+ LINK_ATTR_84858)) {
+ return elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
+ argc);
+ } else {
+ return elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
+ argc, process);
+ }
+}
+
+static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy,
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
uint32_t pair_swap;
- uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
+ uint16_t data[PHY848xx_CMDHDLR_MAX_ARGS];
elink_status_t status;
struct bnx2x_softc *sc = params->sc;
/* Check for configuration. */
pair_swap = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- xgbt_phy_cfg)) &
- PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
+ dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
+ PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
if (pair_swap == 0)
return ELINK_STATUS_OK;
/* Only the second argument is used for this command */
- data[1] = (uint16_t) pair_swap;
+ data[1] = (uint16_t)pair_swap;
- status = elink_84833_cmd_hdlr(phy, params,
- PHY84833_CMD_SET_PAIR_SWAP, data,
- PHY84833_CMDHDLR_MAX_ARGS);
- if (status == ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Pairswap OK, val=0x%x", data[1]);
- }
+ status = elink_848xx_cmd_hdlr(phy, params,
+ PHY848xx_CMD_SET_PAIR_SWAP, data,
+ 2, PHY84833_MB_PROCESS2);
+ if (status == ELINK_STATUS_OK)
+ ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x", data[1]);
return status;
}
static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- __rte_unused uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ __rte_unused uint32_t chip_id)
{
uint32_t reset_pin[2];
uint32_t idx;
@@ -9424,54 +11141,50 @@ static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,
for (idx = 0; idx < 2; idx++) {
/* Map config param to register bit. */
reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[0].
- e3_cmn_pin_cfg));
- reset_pin[idx] =
- (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >>
- PORT_HW_CFG_E3_PHY_RESET_SHIFT;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[0].e3_cmn_pin_cfg));
+ reset_pin[idx] = (reset_pin[idx] &
+ PORT_HW_CFG_E3_PHY_RESET_MASK) >>
+ PORT_HW_CFG_E3_PHY_RESET_SHIFT;
reset_pin[idx] -= PIN_CFG_GPIO0_P0;
reset_pin[idx] = (1 << reset_pin[idx]);
}
- reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
+ reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
} else {
/* E2, look from diff place of shmem. */
for (idx = 0; idx < 2; idx++) {
reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[0].
- default_cfg));
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[0].default_cfg));
reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
reset_pin[idx] = (1 << reset_pin[idx]);
}
- reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
+ reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
}
return reset_gpios;
}
-static void elink_84833_hw_reset_phy(struct elink_phy *phy,
- struct elink_params *params)
+static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint8_t reset_gpios;
uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
- offsetof(struct shmem2_region,
- other_shmem_base_addr));
+ offsetof(struct shmem2_region,
+ other_shmem_base_addr));
uint32_t shmem_base_path[2];
/* Work around for 84833 LED failure inside RESET status */
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_LEGACY_MII_CTRL,
- MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
+ MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+ MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
- MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
+ MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
+ MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
shmem_base_path[0] = params->shmem_base;
shmem_base_path[1] = other_shmem_base_addr;
@@ -9482,24 +11195,27 @@ static void elink_84833_hw_reset_phy(struct elink_phy *phy,
elink_cb_gpio_mult_write(sc, reset_gpios,
MISC_REGISTERS_GPIO_OUTPUT_LOW);
DELAY(10);
- PMD_DRV_LOG(DEBUG, sc,
- "84833 hw reset on pin values 0x%x", reset_gpios);
+ ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x",
+ reset_gpios);
+
+ return ELINK_STATUS_OK;
}
static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
elink_status_t rc;
+ struct bnx2x_softc *sc = params->sc;
uint16_t cmd_args = 0;
- PMD_DRV_LOG(DEBUG, params->sc, "Don't Advertise 10GBase-T EEE");
+ ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE");
/* Prevent Phy from working in EEE and advertising it */
- rc = elink_84833_cmd_hdlr(phy, params,
- PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
+ rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
+ &cmd_args, 1, PHY84833_MB_PROCESS1);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, params->sc, "EEE disable failed.");
+ ELINK_DEBUG_P0(sc, "EEE disable failed.");
return rc;
}
@@ -9507,16 +11223,17 @@ static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
}
static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
elink_status_t rc;
+ struct bnx2x_softc *sc = params->sc;
uint16_t cmd_args = 1;
- rc = elink_84833_cmd_hdlr(phy, params,
- PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
+ rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
+ &cmd_args, 1, PHY84833_MB_PROCESS1);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, params->sc, "EEE enable failed.");
+ ELINK_DEBUG_P0(sc, "EEE enable failed.");
return rc;
}
@@ -9524,15 +11241,15 @@ static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
}
#define PHY84833_CONSTANT_LATENCY 1193
-static uint8_t elink_848x3_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static elink_status_t elink_848x3_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port, initialize = 1;
uint16_t val;
uint32_t actual_phy_selection;
- uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
+ uint16_t cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
elink_status_t rc = ELINK_STATUS_OK;
DELAY(1000 * 1);
@@ -9544,19 +11261,20 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+ port);
} else {
/* MDIO reset */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL, 0x8000);
}
elink_wait_reset_complete(sc, phy, params);
/* Wait for GPHY to come out of reset */
DELAY(1000 * 50);
- if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
- (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
+ if (!elink_is_8483x_8485x(phy)) {
/* BNX2X84823 requires that XGXS links up first @ 10G for normal
* behavior.
*/
@@ -9567,7 +11285,19 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
vars->line_speed = temp;
}
+ /* Check if this is actually BNX2X84858 */
+ if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858) {
+ uint16_t hw_rev;
+
+ elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
+ MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
+ if (hw_rev == BNX2X84858_PHY_ID) {
+ params->link_attr_sync |= LINK_ATTR_84858;
+ elink_update_link_attr(params, params->link_attr_sync);
+ }
+ }
+ /* Set dual-media configuration according to configuration */
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
MDIO_CTL_REG_84823_MEDIA, &val);
val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
@@ -9609,39 +11339,33 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
MDIO_CTL_REG_84823_MEDIA, val);
- PMD_DRV_LOG(DEBUG, sc, "Multi_phy config = 0x%x, Media control = 0x%x",
- params->multi_phy_config, val);
+ ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x",
+ params->multi_phy_config, val);
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
- elink_84833_pair_swap_cfg(phy, params, vars);
+ if (elink_is_8483x_8485x(phy)) {
+ elink_848xx_pair_swap_cfg(phy, params, vars);
/* Keep AutogrEEEn disabled. */
cmd_args[0] = 0x0;
cmd_args[1] = 0x0;
cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
cmd_args[3] = PHY84833_CONSTANT_LATENCY;
- rc = elink_84833_cmd_hdlr(phy, params,
- PHY84833_CMD_SET_EEE_MODE, cmd_args,
- PHY84833_CMDHDLR_MAX_ARGS);
- if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Cfg AutogrEEEn failed.");
- }
+ rc = elink_848xx_cmd_hdlr(phy, params,
+ PHY848xx_CMD_SET_EEE_MODE, cmd_args,
+ 4, PHY84833_MB_PROCESS1);
+ if (rc != ELINK_STATUS_OK)
+ ELINK_DEBUG_P0(sc, "Cfg AutogrEEEn failed.");
}
- if (initialize) {
+ if (initialize)
rc = elink_848xx_cmn_config_init(phy, params, vars);
- } else {
+ else
elink_save_848xx_spirom_version(phy, sc, params->port);
- }
/* 84833 PHY has a better feature and doesn't need to support this. */
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
uint32_t cms_enable = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[params->
- port].
- default_cfg)) &
- PORT_HW_CFG_ENABLE_CMS_MASK;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[params->port].default_cfg)) &
+ PORT_HW_CFG_ENABLE_CMS_MASK;
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
@@ -9662,7 +11386,7 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
elink_eee_has_cap(params)) {
rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
+ ELINK_DEBUG_P0(sc, "Failed to configure EEE timers");
elink_8483x_disable_eee(phy, params, vars);
return rc;
}
@@ -9675,39 +11399,40 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
else
rc = elink_8483x_disable_eee(phy, params, vars);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to set EEE advertisement");
+ ELINK_DEBUG_P0(sc, "Failed to set EEE advertisement");
return rc;
}
} else {
vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
}
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
+ if (elink_is_8483x_8485x(phy)) {
/* Bring PHY out of super isolate mode as the final step. */
elink_cl45_read_and_write(sc, phy,
MDIO_CTL_DEVAD,
MDIO_84833_TOP_CFG_XGPHY_STRAP1,
- (uint16_t) ~
- MDIO_84833_SUPER_ISOLATE);
+ (uint16_t)~MDIO_84833_SUPER_ISOLATE);
}
return rc;
}
static uint8_t elink_848xx_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val, val1, val2;
uint8_t link_up = 0;
+
/* Check 10G-BaseT link status */
/* Check PMD signal ok */
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);
- PMD_DRV_LOG(DEBUG, sc, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
+ MDIO_AN_DEVAD, 0xFFFA, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
+ &val2);
+ ELINK_DEBUG_P1(sc, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
/* Check link 10G */
if (val2 & (1 << 11)) {
@@ -9715,8 +11440,8 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
vars->duplex = DUPLEX_FULL;
link_up = 1;
elink_ext_phy_10G_an_resolve(sc, phy, vars);
- } else { /* Check Legacy speed link */
- uint16_t legacy_status, legacy_speed, mii_ctrl;
+ } else { /* Check Legacy speed link */
+ uint16_t legacy_status, legacy_speed;
/* Enable expansion register 0x42 (Operation mode status) */
elink_cl45_write(sc, phy,
@@ -9729,8 +11454,8 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
&legacy_status);
- PMD_DRV_LOG(DEBUG, sc,
- "Legacy speed status = 0x%x", legacy_status);
+ ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x",
+ legacy_status);
link_up = ((legacy_status & (1 << 11)) == (1 << 11));
legacy_speed = (legacy_status & (3 << 9));
if (legacy_speed == (0 << 9))
@@ -9739,13 +11464,15 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
vars->line_speed = ELINK_SPEED_100;
else if (legacy_speed == (2 << 9))
vars->line_speed = ELINK_SPEED_1000;
- else { /* Should not happen: Treat as link down */
+ else { /* Should not happen: Treat as link down */
vars->line_speed = 0;
link_up = 0;
}
if (params->feature_config_flags &
- ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
+ ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
+ uint16_t mii_ctrl;
+
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_8481_LEGACY_MII_CTRL,
@@ -9760,10 +11487,10 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
else
vars->duplex = DUPLEX_HALF;
- PMD_DRV_LOG(DEBUG, sc,
- "Link is up in %dMbps, is_duplex_full= %d",
- vars->line_speed,
- (vars->duplex == DUPLEX_FULL));
+ ELINK_DEBUG_P2(sc,
+ "Link is up in %dMbps, is_duplex_full= %d",
+ vars->line_speed,
+ (vars->duplex == DUPLEX_FULL));
/* Check legacy speed AN resolution */
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
@@ -9771,19 +11498,19 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
&val);
if (val & (1 << 5))
vars->link_status |=
- LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+ LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
&val);
if ((val & (1 << 0)) == 0)
vars->link_status |=
- LINK_STATUS_PARALLEL_DETECTION_USED;
+ LINK_STATUS_PARALLEL_DETECTION_USED;
}
}
if (link_up) {
- PMD_DRV_LOG(DEBUG, sc, "BNX2X848x3: link speed is %d",
- vars->line_speed);
+ ELINK_DEBUG_P1(sc, "BNX2X848x3: link speed is %d",
+ vars->line_speed);
elink_ext_phy_resolve_fc(phy, params, vars);
/* Read LP advertised speeds */
@@ -9791,48 +11518,47 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
MDIO_AN_REG_CL37_FC_LP, &val);
if (val & (1 << 5))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
if (val & (1 << 6))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
if (val & (1 << 7))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
if (val & (1 << 8))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
if (val & (1 << 9))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_1000T_STATUS, &val);
if (val & (1 << 10))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
if (val & (1 << 11))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_MASTER_STATUS, &val);
if (val & (1 << 11))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
/* Determine if EEE was negotiated */
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
+ if (elink_is_8483x_8485x(phy))
elink_eee_an_resolve(phy, params, vars);
}
return link_up;
}
-static uint8_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,
- uint16_t * len)
+static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str,
+ uint16_t *len)
{
elink_status_t status = ELINK_STATUS_OK;
uint32_t spirom_ver;
@@ -9845,17 +11571,18 @@ static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy,
struct elink_params *params)
{
elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
}
static void elink_8481_link_reset(struct elink_phy *phy,
- struct elink_params *params)
+ struct elink_params *params)
{
elink_cl45_write(params->sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
- elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
+ elink_cl45_write(params->sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
}
static void elink_848x3_link_reset(struct elink_phy *phy,
@@ -9872,7 +11599,8 @@ static void elink_848x3_link_reset(struct elink_phy *phy,
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ port);
} else {
elink_cl45_read(sc, phy,
MDIO_CTL_DEVAD,
@@ -9889,48 +11617,52 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
{
struct bnx2x_softc *sc = params->sc;
uint16_t val;
- __rte_unused uint8_t port;
+ uint8_t port;
if (!(CHIP_IS_E1x(sc)))
port = SC_PATH(sc);
else
port = params->port;
-
switch (mode) {
case ELINK_LED_MODE_OFF:
- PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OFF", port);
+ ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
/* Set LED masks */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED2_MASK, 0x0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED2_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED3_MASK, 0x0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED3_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED5_MASK, 0x0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED5_MASK,
+ 0x0);
} else {
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
}
break;
case ELINK_LED_MODE_FRONT_PANEL_OFF:
- PMD_DRV_LOG(DEBUG, sc,
- "Port 0x%x: LED MODE FRONT PANEL OFF", port);
+ ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF",
+ port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
@@ -9938,25 +11670,31 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
/* Set LED masks */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED2_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED2_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED3_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED3_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED5_MASK, 0x20);
+ MDIO_PMA_REG_8481_LED5_MASK,
+ 0x20);
} else {
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
+ if (phy->type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
/* Disable MI_INT interrupt before setting LED4
* source to constant off.
*/
@@ -9964,12 +11702,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
params->port * 4) &
ELINK_NIG_MASK_MI_INT) {
params->link_flags |=
- ELINK_LINK_FLAGS_INT_DISABLED;
+ ELINK_LINK_FLAGS_INT_DISABLED;
- elink_bits_dis(sc,
- NIG_REG_MASK_INTERRUPT_PORT0
- + params->port * 4,
- ELINK_NIG_MASK_MI_INT);
+ elink_bits_dis(
+ sc,
+ NIG_REG_MASK_INTERRUPT_PORT0 +
+ params->port * 4,
+ ELINK_NIG_MASK_MI_INT);
}
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -9980,42 +11719,50 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
break;
case ELINK_LED_MODE_ON:
- PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE ON", port);
+ ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
/* Set control reg */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ &val);
val &= 0x8000;
val |= 0x2492;
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, val);
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ val);
/* Set LED masks */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED2_MASK, 0x20);
+ MDIO_PMA_REG_8481_LED2_MASK,
+ 0x20);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED3_MASK, 0x20);
+ MDIO_PMA_REG_8481_LED3_MASK,
+ 0x20);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED5_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED5_MASK,
+ 0x0);
} else {
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x20);
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x20);
+ if (phy->type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
/* Disable MI_INT interrupt before setting LED4
* source to constant on.
*/
@@ -10023,12 +11770,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
params->port * 4) &
ELINK_NIG_MASK_MI_INT) {
params->link_flags |=
- ELINK_LINK_FLAGS_INT_DISABLED;
+ ELINK_LINK_FLAGS_INT_DISABLED;
- elink_bits_dis(sc,
- NIG_REG_MASK_INTERRUPT_PORT0
- + params->port * 4,
- ELINK_NIG_MASK_MI_INT);
+ elink_bits_dis(
+ sc,
+ NIG_REG_MASK_INTERRUPT_PORT0 +
+ params->port * 4,
+ ELINK_NIG_MASK_MI_INT);
}
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -10040,7 +11788,7 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
case ELINK_LED_MODE_OPER:
- PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OPER", port);
+ ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
@@ -10048,14 +11796,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
/* Set control reg */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ &val);
if (!((val &
MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
- >>
- MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))
- {
- PMD_DRV_LOG(DEBUG, sc, "Setting LINK_SIGNAL");
+ >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
+ ELINK_DEBUG_P0(sc, "Setting LINK_SIGNAL");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8481_LINK_SIGNAL,
@@ -10065,19 +11812,23 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
/* Set LED masks */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x10);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x10);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED2_MASK, 0x80);
+ MDIO_PMA_REG_8481_LED2_MASK,
+ 0x80);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED3_MASK, 0x98);
+ MDIO_PMA_REG_8481_LED3_MASK,
+ 0x98);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED5_MASK, 0x40);
+ MDIO_PMA_REG_8481_LED5_MASK,
+ 0x40);
} else {
/* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
@@ -10090,18 +11841,22 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, val);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ val);
/* Tell LED3 to blink on source */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ &val);
val &= ~(7 << 6);
- val |= (1 << 6); /* A83B[8:6]= 1 */
+ val |= (1 << 6); /* A83B[8:6]= 1 */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, val);
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ val);
+ if (phy->type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
/* Restore LED4 source to external link,
* and re-enable interrupts.
*/
@@ -10113,14 +11868,14 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
ELINK_LINK_FLAGS_INT_DISABLED) {
elink_link_int_enable(params);
params->link_flags &=
- ~ELINK_LINK_FLAGS_INT_DISABLED;
+ ~ELINK_LINK_FLAGS_INT_DISABLED;
}
}
}
break;
}
- /* This is a workaround for E3+84833 until autoneg
+ /* This is a workaround for E3 + 84833 until autoneg
* restart is fixed in f/w
*/
if (CHIP_IS_E3(sc)) {
@@ -10145,7 +11900,9 @@ static void elink_54618se_specific_func(struct elink_phy *phy,
elink_cl22_write(sc, phy,
MDIO_REG_GPHY_SHADOW,
MDIO_REG_GPHY_SHADOW_LED_SEL2);
- elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_GPHY_SHADOW,
+ &temp);
temp &= ~(0xf << 4);
temp |= (0x6 << 4);
elink_cl22_write(sc, phy,
@@ -10159,16 +11916,16 @@ static void elink_54618se_specific_func(struct elink_phy *phy,
}
}
-static uint8_t elink_54618se_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static elink_status_t elink_54618se_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port;
uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
uint32_t cfg_pin;
- PMD_DRV_LOG(DEBUG, sc, "54618SE cfg init");
+ ELINK_DEBUG_P0(sc, "54618SE cfg init");
DELAY(1000 * 1);
/* This works with E3 only, no need to check the chip
@@ -10177,11 +11934,10 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
port = params->port;
cfg_pin = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_cmn_pin_cfg)) &
- PORT_HW_CFG_E3_PHY_RESET_MASK) >>
- PORT_HW_CFG_E3_PHY_RESET_SHIFT;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
+ PORT_HW_CFG_E3_PHY_RESET_MASK) >>
+ PORT_HW_CFG_E3_PHY_RESET_SHIFT;
/* Drive pin high to bring the GPHY out of reset. */
elink_set_cfg_pin(sc, cfg_pin, 1);
@@ -10190,63 +11946,76 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
DELAY(1000 * 50);
/* reset phy */
- elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000);
+ elink_cl22_write(sc, phy,
+ MDIO_PMA_REG_CTRL, 0x8000);
elink_wait_reset_complete(sc, phy, params);
/* Wait for GPHY to reset */
DELAY(1000 * 50);
+
elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
/* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
elink_cl22_write(sc, phy,
- MDIO_REG_GPHY_SHADOW,
- MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
- elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
+ MDIO_REG_GPHY_SHADOW,
+ MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_GPHY_SHADOW,
+ &temp);
temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
elink_cl22_write(sc, phy,
- MDIO_REG_GPHY_SHADOW,
- MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
+ MDIO_REG_GPHY_SHADOW,
+ MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
/* Set up fc */
/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
fc_val = 0;
if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
/* Read all advertisement */
- elink_cl22_read(sc, phy, 0x09, &an_1000_val);
+ elink_cl22_read(sc, phy,
+ 0x09,
+ &an_1000_val);
- elink_cl22_read(sc, phy, 0x04, &an_10_100_val);
+ elink_cl22_read(sc, phy,
+ 0x04,
+ &an_10_100_val);
- elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val);
+ elink_cl22_read(sc, phy,
+ MDIO_PMA_REG_CTRL,
+ &autoneg_val);
/* Disable forced speed */
- autoneg_val &=
- ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
- an_10_100_val &=
- ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |
- (1 << 11));
+ autoneg_val &= ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) |
+ (1 << 13));
+ an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) |
+ (1 << 10) | (1 << 11));
if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
- (phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
- (phy->req_line_speed == ELINK_SPEED_1000)) {
+ (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
+ (phy->req_line_speed == ELINK_SPEED_1000)) {
an_1000_val |= (1 << 8);
autoneg_val |= (1 << 9 | 1 << 12);
if (phy->req_duplex == DUPLEX_FULL)
an_1000_val |= (1 << 9);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
+ ELINK_DEBUG_P0(sc, "Advertising 1G");
} else
an_1000_val &= ~((1 << 8) | (1 << 9));
- elink_cl22_write(sc, phy, 0x09, an_1000_val);
- elink_cl22_read(sc, phy, 0x09, &an_1000_val);
+ elink_cl22_write(sc, phy,
+ 0x09,
+ an_1000_val);
+ elink_cl22_read(sc, phy,
+ 0x09,
+ &an_1000_val);
/* Advertise 10/100 link speed */
if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
@@ -10254,25 +12023,25 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
an_10_100_val |= (1 << 5);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
+ ELINK_DEBUG_P0(sc, "Advertising 10M-HD");
}
if (phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
an_10_100_val |= (1 << 6);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
+ ELINK_DEBUG_P0(sc, "Advertising 10M-FD");
}
if (phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
an_10_100_val |= (1 << 7);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
+ ELINK_DEBUG_P0(sc, "Advertising 100M-HD");
}
if (phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
an_10_100_val |= (1 << 8);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
+ ELINK_DEBUG_P0(sc, "Advertising 100M-FD");
}
}
@@ -10280,13 +12049,17 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
if (phy->req_line_speed == ELINK_SPEED_100) {
autoneg_val |= (1 << 13);
/* Enabled AUTO-MDIX when autoneg is disabled */
- elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
- PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
+ elink_cl22_write(sc, phy,
+ 0x18,
+ (1 << 15 | 1 << 9 | 7 << 0));
+ ELINK_DEBUG_P0(sc, "Setting 100M force");
}
if (phy->req_line_speed == ELINK_SPEED_10) {
/* Enabled AUTO-MDIX when autoneg is disabled */
- elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
- PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
+ elink_cl22_write(sc, phy,
+ 0x18,
+ (1 << 15 | 1 << 9 | 7 << 0));
+ ELINK_DEBUG_P0(sc, "Setting 10M force");
}
if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
@@ -10301,7 +12074,7 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
+ ELINK_DEBUG_P0(sc, "Failed to configure EEE timers");
elink_eee_disable(phy, params, vars);
} else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
(phy->req_duplex == DUPLEX_FULL) &&
@@ -10315,38 +12088,42 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
elink_eee_advertise(phy, params, vars,
SHMEM_EEE_1G_ADV);
} else {
- PMD_DRV_LOG(DEBUG, sc, "Don't Advertise 1GBase-T EEE");
+ ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE");
elink_eee_disable(phy, params, vars);
}
} else {
- vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
- SHMEM_EEE_SUPPORTED_SHIFT;
+ vars->eee_status &= ((uint32_t)(~SHMEM_EEE_1G_ADV) <<
+ SHMEM_EEE_SUPPORTED_SHIFT);
if (phy->flags & ELINK_FLAGS_EEE) {
/* Handle legacy auto-grEEEn */
if (params->feature_config_flags &
ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
temp = 6;
- PMD_DRV_LOG(DEBUG, sc, "Enabling Auto-GrEEEn");
+ ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn");
} else {
temp = 0;
- PMD_DRV_LOG(DEBUG, sc, "Don't Adv. EEE");
+ ELINK_DEBUG_P0(sc, "Don't Adv. EEE");
}
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_EEE_ADV, temp);
}
}
- elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val);
+ elink_cl22_write(sc, phy,
+ 0x04,
+ an_10_100_val | fc_val);
if (phy->req_duplex == DUPLEX_FULL)
autoneg_val |= (1 << 8);
- elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val);
+ elink_cl22_write(sc, phy,
+ MDIO_PMA_REG_CTRL, autoneg_val);
return ELINK_STATUS_OK;
}
+
static void elink_5461x_set_link_led(struct elink_phy *phy,
struct elink_params *params, uint8_t mode)
{
@@ -10354,11 +12131,14 @@ static void elink_5461x_set_link_led(struct elink_phy *phy,
uint16_t temp;
elink_cl22_write(sc, phy,
- MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1);
- elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
+ MDIO_REG_GPHY_SHADOW,
+ MDIO_REG_GPHY_SHADOW_LED_SEL1);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_GPHY_SHADOW,
+ &temp);
temp &= 0xff00;
- PMD_DRV_LOG(DEBUG, sc, "54618x set link led (mode=%x)", mode);
+ ELINK_DEBUG_P1(sc, "54618x set link led (mode=%x)", mode);
switch (mode) {
case ELINK_LED_MODE_FRONT_PANEL_OFF:
case ELINK_LED_MODE_OFF:
@@ -10374,11 +12154,12 @@ static void elink_5461x_set_link_led(struct elink_phy *phy,
break;
}
elink_cl22_write(sc, phy,
- MDIO_REG_GPHY_SHADOW,
- MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
+ MDIO_REG_GPHY_SHADOW,
+ MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
return;
}
+
static void elink_54618se_link_reset(struct elink_phy *phy,
struct elink_params *params)
{
@@ -10395,19 +12176,18 @@ static void elink_54618se_link_reset(struct elink_phy *phy,
*/
port = params->port;
cfg_pin = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_cmn_pin_cfg)) &
- PORT_HW_CFG_E3_PHY_RESET_MASK) >>
- PORT_HW_CFG_E3_PHY_RESET_SHIFT;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
+ PORT_HW_CFG_E3_PHY_RESET_MASK) >>
+ PORT_HW_CFG_E3_PHY_RESET_SHIFT;
/* Drive pin low to put GPHY in reset. */
elink_set_cfg_pin(sc, cfg_pin, 0);
}
static uint8_t elink_54618se_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val;
@@ -10415,11 +12195,15 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,
uint16_t legacy_status, legacy_speed;
/* Get speed operation status */
- elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);
- PMD_DRV_LOG(DEBUG, sc, "54618SE read_status: 0x%x", legacy_status);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_GPHY_AUX_STATUS,
+ &legacy_status);
+ ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x", legacy_status);
/* Read status to clear the PHY interrupt. */
- elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_INTR_STATUS,
+ &val);
link_up = ((legacy_status & (1 << 2)) == (1 << 2));
@@ -10445,25 +12229,30 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,
} else if (legacy_speed == (1 << 8)) {
vars->line_speed = ELINK_SPEED_10;
vars->duplex = DUPLEX_HALF;
- } else /* Should not happen */
+ } else /* Should not happen */
vars->line_speed = 0;
- PMD_DRV_LOG(DEBUG, sc,
- "Link is up in %dMbps, is_duplex_full= %d",
- vars->line_speed, (vars->duplex == DUPLEX_FULL));
+ ELINK_DEBUG_P2(sc,
+ "Link is up in %dMbps, is_duplex_full= %d",
+ vars->line_speed,
+ (vars->duplex == DUPLEX_FULL));
/* Check legacy speed AN resolution */
- elink_cl22_read(sc, phy, 0x01, &val);
+ elink_cl22_read(sc, phy,
+ 0x01,
+ &val);
if (val & (1 << 5))
vars->link_status |=
- LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
- elink_cl22_read(sc, phy, 0x06, &val);
+ LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+ elink_cl22_read(sc, phy,
+ 0x06,
+ &val);
if ((val & (1 << 0)) == 0)
vars->link_status |=
- LINK_STATUS_PARALLEL_DETECTION_USED;
+ LINK_STATUS_PARALLEL_DETECTION_USED;
- PMD_DRV_LOG(DEBUG, sc, "BNX2X54618SE: link speed is %d",
- vars->line_speed);
+ ELINK_DEBUG_P1(sc, "BNX2X4618SE: link speed is %d",
+ vars->line_speed);
elink_ext_phy_resolve_fc(phy, params, vars);
@@ -10473,27 +12262,27 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,
if (val & (1 << 5))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
if (val & (1 << 6))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
if (val & (1 << 7))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
if (val & (1 << 8))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
if (val & (1 << 9))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
elink_cl22_read(sc, phy, 0xa, &val);
if (val & (1 << 10))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
if (val & (1 << 11))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
if ((phy->flags & ELINK_FLAGS_EEE) &&
elink_eee_has_cap(params))
@@ -10510,7 +12299,7 @@ static void elink_54618se_config_loopback(struct elink_phy *phy,
uint16_t val;
uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
- PMD_DRV_LOG(DEBUG, sc, "2PMA/PMD ext_phy_loopback: 54618se");
+ ELINK_DEBUG_P0(sc, "2PMA/PMD ext_phy_loopback: 54618se");
/* Enable master/slave manual mmode and set to master */
/* mii write 9 [bits set 11 12] */
@@ -10555,31 +12344,34 @@ static void elink_7101_config_loopback(struct elink_phy *phy,
MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
}
-static uint8_t elink_7101_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static elink_status_t elink_7101_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint16_t fw_ver1, fw_ver2, val;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LASI indication");
+ ELINK_DEBUG_P0(sc, "Setting the SFX7101 LASI indication");
- /* Restore normal power mode */
+ /* Restore normal power mode*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
/* HW reset */
elink_ext_phy_hw_reset(sc, params->port);
elink_wait_reset_complete(sc, phy, params);
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
- PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LED to blink on traffic");
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
+ ELINK_DEBUG_P0(sc, "Setting the SFX7101 LED to blink on traffic");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));
elink_ext_phy_set_pause(params, phy, vars);
/* Restart autoneg */
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
val |= 0x200;
- elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
+ elink_cl45_write(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
/* Save spirom version */
elink_cl45_read(sc, phy,
@@ -10588,24 +12380,30 @@ static uint8_t elink_7101_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
elink_save_spirom_version(sc, params->port,
- (uint32_t) (fw_ver1 << 16 | fw_ver2),
+ (uint32_t)(fw_ver1 << 16 | fw_ver2),
phy->ver_addr);
return ELINK_STATUS_OK;
}
static uint8_t elink_7101_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t link_up;
uint16_t val1, val2;
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- PMD_DRV_LOG(DEBUG, sc, "10G-base-T LASI status 0x%x->0x%x", val2, val1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "10G-base-T PMA status 0x%x->0x%x", val2, val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
+ ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x",
+ val2, val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
+ ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x",
+ val2, val1);
link_up = ((val1 & 4) == 4);
/* If link is up print the AN outcome of the SFX7101 PHY */
if (link_up) {
@@ -10614,21 +12412,21 @@ static uint8_t elink_7101_read_status(struct elink_phy *phy,
&val2);
vars->line_speed = ELINK_SPEED_10000;
vars->duplex = DUPLEX_FULL;
- PMD_DRV_LOG(DEBUG, sc, "SFX7101 AN status 0x%x->Master=%x",
- val2, (val2 & (1 << 14)));
+ ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x",
+ val2, (val2 & (1 << 14)));
elink_ext_phy_10G_an_resolve(sc, phy, vars);
elink_ext_phy_resolve_fc(phy, params, vars);
/* Read LP advertised speeds */
if (val2 & (1 << 11))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
}
return link_up;
}
-static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
- uint16_t * len)
+static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str,
+ uint16_t *len)
{
if (*len < 5)
return ELINK_STATUS_ERROR;
@@ -10641,15 +12439,39 @@ static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
return ELINK_STATUS_OK;
}
-static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,
- struct elink_params *params)
+void elink_sfx7101_sp_sw_reset(struct bnx2x_softc *sc, struct elink_phy *phy)
{
+ uint16_t val, cnt;
+
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_7101_RESET, &val);
+
+ for (cnt = 0; cnt < 10; cnt++) {
+ DELAY(1000 * 50);
+ /* Writes a self-clearing reset */
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_7101_RESET,
+ (val | (1 << 15)));
+ /* Wait for clear */
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_7101_RESET, &val);
+
+ if ((val & (1 << 15)) == 0)
+ break;
+ }
+}
+
+static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,
+ struct elink_params *params) {
/* Low power mode is controlled by GPIO 2 */
elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
/* The PHY reset is controlled by GPIO 1 */
elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
}
static void elink_7101_set_link_led(struct elink_phy *phy,
@@ -10670,7 +12492,9 @@ static void elink_7101_set_link_led(struct elink_phy *phy,
break;
}
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_7107_LINK_LED_CNTL,
+ val);
}
/******************************************************************/
@@ -10678,482 +12502,532 @@ static void elink_7101_set_link_led(struct elink_phy *phy,
/******************************************************************/
static const struct elink_phy phy_null = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
- .addr = 0,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = 0,
- .media_type = ELINK_ETH_PHY_NOT_PRESENT,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = NULL,
- .read_status = NULL,
- .link_reset = NULL,
- .config_loopback = NULL,
- .format_fw_ver = NULL,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
+ .addr = 0,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = 0,
+ .media_type = ELINK_ETH_PHY_NOT_PRESENT,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)NULL,
+ .read_status = (read_status_t)NULL,
+ .link_reset = (link_reset_t)NULL,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_serdes = {
- .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = 0,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_2500baseX_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_xgxs_config_init,
- .read_status = elink_link_settings_status,
- .link_reset = elink_int_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = NULL,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = 0,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_2500baseX_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_xgxs_config_init,
+ .read_status = (read_status_t)elink_link_settings_status,
+ .link_reset = (link_reset_t)elink_int_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_xgxs = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = 0,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_2500baseX_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_CX4,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_xgxs_config_init,
- .read_status = elink_link_settings_status,
- .link_reset = elink_int_link_reset,
- .config_loopback = elink_set_xgxs_loopback,
- .format_fw_ver = NULL,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = elink_xgxs_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = 0,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_2500baseX_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_CX4,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_xgxs_config_init,
+ .read_status = (read_status_t)elink_link_settings_status,
+ .link_reset = (link_reset_t)elink_int_link_reset,
+ .config_loopback = (config_loopback_t)elink_set_xgxs_loopback,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func
};
-
static const struct elink_phy phy_warpcore = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_TX_ERROR_CHECK,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_20000baseKR2_Full |
- ELINK_SUPPORTED_20000baseMLD2_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_UNSPECIFIED,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- /* req_duplex = */ 0,
- /* rsrv = */ 0,
- .config_init = elink_warpcore_config_init,
- .read_status = elink_warpcore_read_status,
- .link_reset = elink_warpcore_link_reset,
- .config_loopback = elink_set_warpcore_loopback,
- .format_fw_ver = NULL,
- .hw_reset = elink_warpcore_hw_reset,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_TX_ERROR_CHECK,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_1000baseKX_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_10000baseKR_Full |
+ ELINK_SUPPORTED_20000baseKR2_Full |
+ ELINK_SUPPORTED_20000baseMLD2_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_UNSPECIFIED,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ /* req_duplex = */0,
+ /* rsrv = */0,
+ .config_init = (config_init_t)elink_warpcore_config_init,
+ .read_status = (read_status_t)elink_warpcore_read_status,
+ .link_reset = (link_reset_t)elink_warpcore_link_reset,
+ .config_loopback = (config_loopback_t)elink_set_warpcore_loopback,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)elink_warpcore_hw_reset,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
+
static const struct elink_phy phy_7101 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_7101_config_init,
- .read_status = elink_7101_read_status,
- .link_reset = elink_common_ext_link_reset,
- .config_loopback = elink_7101_config_loopback,
- .format_fw_ver = elink_7101_format_ver,
- .hw_reset = elink_7101_hw_reset,
- .set_link_led = elink_7101_set_link_led,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_7101_config_init,
+ .read_status = (read_status_t)elink_7101_read_status,
+ .link_reset = (link_reset_t)elink_common_ext_link_reset,
+ .config_loopback = (config_loopback_t)elink_7101_config_loopback,
+ .format_fw_ver = (format_fw_ver_t)elink_7101_format_ver,
+ .hw_reset = (hw_reset_t)elink_7101_hw_reset,
+ .set_link_led = (set_link_led_t)elink_7101_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
-
static const struct elink_phy phy_8073 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = 0,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_2500baseX_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_KR,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8073_config_init,
- .read_status = elink_8073_read_status,
- .link_reset = elink_8073_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_format_ver,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = elink_8073_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = 0,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_2500baseX_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_KR,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8073_config_init,
+ .read_status = (read_status_t)elink_8073_read_status,
+ .link_reset = (link_reset_t)elink_8073_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)elink_8073_specific_func
};
-
static const struct elink_phy phy_8705 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_XFP_FIBER,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8705_config_init,
- .read_status = elink_8705_read_status,
- .link_reset = elink_common_ext_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_null_format_ver,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_XFP_FIBER,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8705_config_init,
+ .read_status = (read_status_t)elink_8705_read_status,
+ .link_reset = (link_reset_t)elink_common_ext_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_null_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
-
static const struct elink_phy phy_8706 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8706_config_init,
- .read_status = elink_8706_read_status,
- .link_reset = elink_common_ext_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_format_ver,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8706_config_init,
+ .read_status = (read_status_t)elink_8706_read_status,
+ .link_reset = (link_reset_t)elink_common_ext_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_8726 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK),
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_NOT_PRESENT,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8726_config_init,
- .read_status = elink_8726_read_status,
- .link_reset = elink_8726_link_reset,
- .config_loopback = elink_8726_config_loopback,
- .format_fw_ver = elink_format_ver,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = (ELINK_FLAGS_INIT_XGXS_FIRST |
+ ELINK_FLAGS_TX_ERROR_CHECK),
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_NOT_PRESENT,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8726_config_init,
+ .read_status = (read_status_t)elink_8726_read_status,
+ .link_reset = (link_reset_t)elink_8726_link_reset,
+ .config_loopback = (config_loopback_t)elink_8726_config_loopback,
+ .format_fw_ver = (format_fw_ver_t)elink_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_8727 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK),
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_NOT_PRESENT,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8727_config_init,
- .read_status = elink_8727_read_status,
- .link_reset = elink_8727_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_format_ver,
- .hw_reset = elink_8727_hw_reset,
- .set_link_led = elink_8727_set_link_led,
- .phy_specific_func = elink_8727_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_TX_ERROR_CHECK),
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_NOT_PRESENT,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8727_config_init,
+ .read_status = (read_status_t)elink_8727_read_status,
+ .link_reset = (link_reset_t)elink_8727_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_format_ver,
+ .hw_reset = (hw_reset_t)elink_8727_hw_reset,
+ .set_link_led = (set_link_led_t)elink_8727_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_8727_specific_func
};
-
static const struct elink_phy phy_8481 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
- ELINK_FLAGS_REARM_LATCH_SIGNAL,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8481_config_init,
- .read_status = elink_848xx_read_status,
- .link_reset = elink_8481_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_848xx_format_ver,
- .hw_reset = elink_8481_hw_reset,
- .set_link_led = elink_848xx_set_link_led,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8481_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_8481_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)elink_8481_hw_reset,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_84823 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
- ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK),
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_848x3_config_init,
- .read_status = elink_848xx_read_status,
- .link_reset = elink_848x3_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_848xx_format_ver,
- .hw_reset = NULL,
- .set_link_led = elink_848xx_set_link_led,
- .phy_specific_func = elink_848xx_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL |
+ ELINK_FLAGS_TX_ERROR_CHECK),
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_848x3_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_848x3_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
};
static const struct elink_phy phy_84833 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
- ELINK_FLAGS_REARM_LATCH_SIGNAL |
- ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE),
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_848x3_config_init,
- .read_status = elink_848xx_read_status,
- .link_reset = elink_848x3_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_848xx_format_ver,
- .hw_reset = elink_84833_hw_reset_phy,
- .set_link_led = elink_848xx_set_link_led,
- .phy_specific_func = elink_848xx_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL |
+ ELINK_FLAGS_TX_ERROR_CHECK |
+ ELINK_FLAGS_TEMPERATURE),
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_848x3_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_848x3_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
};
static const struct elink_phy phy_84834 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
- ELINK_FLAGS_REARM_LATCH_SIGNAL,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_848x3_config_init,
- .read_status = elink_848xx_read_status,
- .link_reset = elink_848x3_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_848xx_format_ver,
- .hw_reset = elink_84833_hw_reset_phy,
- .set_link_led = elink_848xx_set_link_led,
- .phy_specific_func = elink_848xx_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_848x3_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_848x3_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
};
-static const struct elink_phy phy_54618se = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- /* req_duplex = */ 0,
- /* rsrv = */ 0,
- .config_init = elink_54618se_config_init,
- .read_status = elink_54618se_read_status,
- .link_reset = elink_54618se_link_reset,
- .config_loopback = elink_54618se_config_loopback,
- .format_fw_ver = NULL,
- .hw_reset = NULL,
- .set_link_led = elink_5461x_set_link_led,
- .phy_specific_func = elink_54618se_specific_func
+static const struct elink_phy phy_84858 = {
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_848x3_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_848x3_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
};
+
+static const struct elink_phy phy_54618se = {
+ .type = PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ /* req_duplex = */0,
+ /* rsrv = */0,
+ .config_init = (config_init_t)elink_54618se_config_init,
+ .read_status = (read_status_t)elink_54618se_read_status,
+ .link_reset = (link_reset_t)elink_54618se_link_reset,
+ .config_loopback = (config_loopback_t)elink_54618se_config_loopback,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)elink_5461x_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func
+};
/*****************************************************************/
/* */
/* Populate the phy according. Main function: elink_populate_phy */
@@ -11161,9 +13035,9 @@ static void elink_7101_set_link_led(struct elink_phy *phy,
/*****************************************************************/
static void elink_populate_preemphasis(struct bnx2x_softc *sc,
- uint32_t shmem_base,
- struct elink_phy *phy, uint8_t port,
- uint8_t phy_index)
+ uint32_t shmem_base,
+ struct elink_phy *phy, uint8_t port,
+ uint8_t phy_index)
{
/* Get the 4 lanes xgxs config rx and tx */
uint32_t rx = 0, tx = 0, i;
@@ -11175,23 +13049,19 @@ static void elink_populate_preemphasis(struct bnx2x_softc *sc,
if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
rx = REG_RD(sc, shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- xgxs_config_rx[i << 1]));
+ dev_info.port_hw_config[port].xgxs_config_rx[i << 1]));
tx = REG_RD(sc, shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- xgxs_config_tx[i << 1]));
+ dev_info.port_hw_config[port].xgxs_config_tx[i << 1]));
} else {
rx = REG_RD(sc, shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- xgxs_config2_rx[i << 1]));
+ dev_info.port_hw_config[port].xgxs_config2_rx[i << 1]));
tx = REG_RD(sc, shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- xgxs_config2_rx[i << 1]));
+ dev_info.port_hw_config[port].xgxs_config2_rx[i << 1]));
}
phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff);
@@ -11199,65 +13069,62 @@ static void elink_populate_preemphasis(struct bnx2x_softc *sc,
phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff);
phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
+ ELINK_DEBUG_P2(sc, "phy->rx_preemphasis = %x, phy->tx_preemphasis = %x",
+ phy->rx_preemphasis[i << 1],
+ phy->tx_preemphasis[i << 1]);
}
}
static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,
- uint32_t shmem_base, uint8_t phy_index,
- uint8_t port)
+ uint32_t shmem_base,
+ uint8_t phy_index, uint8_t port)
{
uint32_t ext_phy_config = 0;
switch (phy_index) {
case ELINK_EXT_PHY1:
ext_phy_config = REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- external_phy_config));
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].external_phy_config));
break;
case ELINK_EXT_PHY2:
ext_phy_config = REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- external_phy_config2));
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].external_phy_config2));
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Invalid phy_index %d", phy_index);
+ ELINK_DEBUG_P1(sc, "Invalid phy_index %d", phy_index);
return ELINK_STATUS_ERROR;
}
return ext_phy_config;
}
-
static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base, uint8_t port,
- struct elink_phy *phy)
+ uint32_t shmem_base, uint8_t port,
+ struct elink_phy *phy)
{
uint32_t phy_addr;
- __rte_unused uint32_t chip_id;
+ uint32_t chip_id;
uint32_t switch_cfg = (REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.
- port_feature_config[port].
- link_config)) &
- PORT_FEATURE_CONNECTED_SWITCH_MASK);
- chip_id =
- (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
- ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
-
- PMD_DRV_LOG(DEBUG, sc, ":chip_id = 0x%x", chip_id);
+ offsetof(struct shmem_region,
+ dev_info.port_feature_config[port].link_config)) &
+ PORT_FEATURE_CONNECTED_SWITCH_MASK);
+ chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
+ ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
+
+ ELINK_DEBUG_P1(sc, ":chip_id = 0x%x", chip_id);
if (USES_WARPCORE(sc)) {
uint32_t serdes_net_if;
- phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
+ phy_addr = REG_RD(sc,
+ MISC_REG_WC0_CTRL_PHY_ADDR);
*phy = phy_warpcore;
if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
phy->flags |= ELINK_FLAGS_4_PORT_MODE;
else
phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
- /* Check Dual mode */
+ /* Check Dual mode */
serdes_net_if = (REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- default_cfg)) &
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[port].default_cfg)) &
PORT_HW_CFG_NET_SERDES_IF_MASK);
/* Set the appropriate supported and flags indications per
* interface type of the chip
@@ -11293,8 +13160,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
break;
case PORT_HW_CFG_NET_SERDES_IF_KR:
phy->media_type = ELINK_ETH_PHY_KR;
- phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
+ phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full |
+ ELINK_SUPPORTED_10000baseKR_Full |
ELINK_SUPPORTED_FIBRE |
ELINK_SUPPORTED_Autoneg |
ELINK_SUPPORTED_Pause |
@@ -11312,8 +13179,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
phy->media_type = ELINK_ETH_PHY_KR;
phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseKR_Full |
+ ELINK_SUPPORTED_1000baseKX_Full |
ELINK_SUPPORTED_Autoneg |
ELINK_SUPPORTED_FIBRE |
ELINK_SUPPORTED_Pause |
@@ -11321,8 +13188,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Unknown WC interface type 0x%x",
- serdes_net_if);
+ ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x",
+ serdes_net_if);
break;
}
@@ -11334,6 +13201,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
else
phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
+ ELINK_DEBUG_P3(sc, "media_type = %x, flags = %x, supported = %x",
+ phy->media_type, phy->flags, phy->supported);
} else {
switch (switch_cfg) {
case ELINK_SWITCH_CFG_1G:
@@ -11349,32 +13218,32 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
*phy = phy_xgxs;
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Invalid switch_cfg");
+ ELINK_DEBUG_P0(sc, "Invalid switch_cfg");
return ELINK_STATUS_ERROR;
}
}
- phy->addr = (uint8_t) phy_addr;
+ phy->addr = (uint8_t)phy_addr;
phy->mdio_ctrl = elink_get_emac_base(sc,
- SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
- port);
+ SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
+ port);
if (CHIP_IS_E2(sc))
phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
else
phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
- PMD_DRV_LOG(DEBUG, sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
- port, phy->addr, phy->mdio_ctrl);
+ ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
+ port, phy->addr, phy->mdio_ctrl);
elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
return ELINK_STATUS_OK;
}
static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
- uint8_t phy_index,
- uint32_t shmem_base,
- uint32_t shmem2_base,
- uint8_t port,
- struct elink_phy *phy)
+ uint8_t phy_index,
+ uint32_t shmem_base,
+ uint32_t shmem2_base,
+ uint8_t port,
+ struct elink_phy *phy)
{
uint32_t ext_phy_config, phy_type, config2;
uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
@@ -11420,10 +13289,13 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
*phy = phy_84834;
break;
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858:
+ *phy = phy_84858;
+ break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616:
- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE:
+ case PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE:
*phy = phy_54618se;
- if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
+ if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE)
phy->flags |= ELINK_FLAGS_EEE;
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
@@ -11449,21 +13321,20 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
* the address
*/
config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
- dev_info.shared_hw_config.
- config2));
+ dev_info.shared_hw_config.config2));
if (phy_index == ELINK_EXT_PHY1) {
phy->ver_addr = shmem_base + offsetof(struct shmem_region,
- port_mb[port].
- ext_phy_fw_version);
+ port_mb[port].ext_phy_fw_version);
/* Check specific mdc mdio settings */
if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
mdc_mdio_access = config2 &
- SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
+ SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
} else {
uint32_t size = REG_RD(sc, shmem2_base);
- if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) {
+ if (size >
+ offsetof(struct shmem2_region, ext_phy_fw_version2)) {
phy->ver_addr = shmem2_base +
offsetof(struct shmem2_region,
ext_phy_fw_version2[port]);
@@ -11471,35 +13342,34 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
/* Check specific mdc mdio settings */
if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
mdc_mdio_access = (config2 &
- SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
- >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
- SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
+ SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
+ (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
+ SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
}
phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
- if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) &&
- (phy->ver_addr)) {
+ if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) {
/* Remove 100Mb link supported for BNX2X84833/4 when phy fw
* version lower than or equal to 1.39
*/
uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
- if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1))
+ if (((raw_ver & 0x7F) <= 39) &&
+ (((raw_ver & 0xF80) >> 7) <= 1))
phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
ELINK_SUPPORTED_100baseT_Full);
}
- PMD_DRV_LOG(DEBUG, sc, "phy_type 0x%x port %d found in index %d",
- phy_type, port, phy_index);
- PMD_DRV_LOG(DEBUG, sc, " addr=0x%x, mdio_ctl=0x%x",
- phy->addr, phy->mdio_ctrl);
+ ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d",
+ phy_type, port, phy_index);
+ ELINK_DEBUG_P2(sc, " addr=0x%x, mdio_ctl=0x%x",
+ phy->addr, phy->mdio_ctrl);
return ELINK_STATUS_OK;
}
static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,
- uint8_t phy_index, uint32_t shmem_base,
- uint32_t shmem2_base, uint8_t port,
- struct elink_phy *phy)
+ uint8_t phy_index, uint32_t shmem_base,
+ uint32_t shmem2_base, uint8_t port,
+ struct elink_phy *phy)
{
elink_status_t status = ELINK_STATUS_OK;
phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
@@ -11511,50 +13381,42 @@ static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,
}
static void elink_phy_def_cfg(struct elink_params *params,
- struct elink_phy *phy, uint8_t phy_index)
+ struct elink_phy *phy,
+ uint8_t phy_index)
{
struct bnx2x_softc *sc = params->sc;
uint32_t link_config;
/* Populate the default phy configuration for MF mode */
if (phy_index == ELINK_EXT_PHY2) {
link_config = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config
- [params->port].link_config2));
- phy->speed_cap_mask =
- REG_RD(sc,
- params->shmem_base + offsetof(struct shmem_region,
- dev_info.port_hw_config
- [params->port].
- speed_capability_mask2));
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].link_config2));
+ phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
+ offsetof(struct shmem_region,
+ dev_info.
+ port_hw_config[params->port].speed_capability_mask2));
} else {
link_config = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config
- [params->port].link_config));
- phy->speed_cap_mask =
- REG_RD(sc,
- params->shmem_base + offsetof(struct shmem_region,
- dev_info.port_hw_config
- [params->port].
- speed_capability_mask));
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].link_config));
+ phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
+ offsetof(struct shmem_region,
+ dev_info.
+ port_hw_config[params->port].speed_capability_mask));
}
-
- PMD_DRV_LOG(DEBUG, sc,
- "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
- phy_index, link_config, phy->speed_cap_mask);
+ ELINK_DEBUG_P3(sc,
+ "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
+ phy_index, link_config, phy->speed_cap_mask);
phy->req_duplex = DUPLEX_FULL;
- switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
+ switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
case PORT_FEATURE_LINK_SPEED_10M_HALF:
phy->req_duplex = DUPLEX_HALF;
- /* fall-through */
case PORT_FEATURE_LINK_SPEED_10M_FULL:
phy->req_line_speed = ELINK_SPEED_10;
break;
case PORT_FEATURE_LINK_SPEED_100M_HALF:
phy->req_duplex = DUPLEX_HALF;
- /* fall-through */
case PORT_FEATURE_LINK_SPEED_100M_FULL:
phy->req_line_speed = ELINK_SPEED_100;
break;
@@ -11572,7 +13434,10 @@ static void elink_phy_def_cfg(struct elink_params *params,
break;
}
- switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
+ ELINK_DEBUG_P2(sc, "Default config phy idx %x, req_duplex config %x",
+ phy_index, phy->req_duplex);
+
+ switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
case PORT_FEATURE_FLOW_CONTROL_AUTO:
phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
break;
@@ -11589,6 +13454,9 @@ static void elink_phy_def_cfg(struct elink_params *params,
phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
break;
}
+ ELINK_DEBUG_P3(sc, "Requested Duplex = %x, line_speed = %x, flow_ctrl = %x",
+ phy->req_duplex, phy->req_line_speed,
+ phy->req_flow_ctrl);
}
uint32_t elink_phy_selection(struct elink_params *params)
@@ -11597,25 +13465,24 @@ uint32_t elink_phy_selection(struct elink_params *params)
uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
phy_config_swapped = params->multi_phy_config &
- PORT_HW_CFG_PHY_SWAPPED_ENABLED;
+ PORT_HW_CFG_PHY_SWAPPED_ENABLED;
- prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK;
+ prio_cfg = params->multi_phy_config &
+ PORT_HW_CFG_PHY_SELECTION_MASK;
if (phy_config_swapped) {
switch (prio_cfg) {
case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
- return_cfg =
- PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
+ return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
break;
case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
- return_cfg =
- PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
+ return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
break;
case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
- return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
+ return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
break;
case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
- return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
+ return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
break;
}
} else
@@ -11624,19 +13491,23 @@ uint32_t elink_phy_selection(struct elink_params *params)
return return_cfg;
}
-elink_status_t elink_phy_probe(struct elink_params * params)
+elink_status_t elink_phy_probe(struct elink_params *params)
{
uint8_t phy_index, actual_phy_idx;
uint32_t phy_config_swapped, sync_offset, media_types;
struct bnx2x_softc *sc = params->sc;
struct elink_phy *phy;
params->num_phys = 0;
- PMD_DRV_LOG(DEBUG, sc, "Begin phy probe");
-
+ ELINK_DEBUG_P0(sc, "Begin phy probe");
+#ifdef ELINK_INCLUDE_EMUL
+ if (CHIP_REV_IS_EMUL(sc))
+ return ELINK_STATUS_OK;
+#endif
phy_config_swapped = params->multi_phy_config &
- PORT_HW_CFG_PHY_SWAPPED_ENABLED;
+ PORT_HW_CFG_PHY_SWAPPED_ENABLED;
- for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
+ for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
+ phy_index++) {
actual_phy_idx = phy_index;
if (phy_config_swapped) {
if (phy_index == ELINK_EXT_PHY1)
@@ -11644,18 +13515,19 @@ elink_status_t elink_phy_probe(struct elink_params * params)
else if (phy_index == ELINK_EXT_PHY2)
actual_phy_idx = ELINK_EXT_PHY1;
}
- PMD_DRV_LOG(DEBUG, sc, "phy_config_swapped %x, phy_index %x,"
- " actual_phy_idx %x", phy_config_swapped,
- phy_index, actual_phy_idx);
+ ELINK_DEBUG_P3(sc, "phy_config_swapped %x, phy_index %x,"
+ " actual_phy_idx %x", phy_config_swapped,
+ phy_index, actual_phy_idx);
phy = ¶ms->phy[actual_phy_idx];
if (elink_populate_phy(sc, phy_index, params->shmem_base,
params->shmem2_base, params->port,
phy) != ELINK_STATUS_OK) {
params->num_phys = 0;
- PMD_DRV_LOG(DEBUG, sc, "phy probe failed in phy index %d",
- phy_index);
+ ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d",
+ phy_index);
for (phy_index = ELINK_INT_PHY;
- phy_index < ELINK_MAX_PHYS; phy_index++)
+ phy_index < ELINK_MAX_PHYS;
+ phy_index++)
*phy = phy_null;
return ELINK_STATUS_ERROR;
}
@@ -11671,8 +13543,8 @@ elink_status_t elink_phy_probe(struct elink_params * params)
phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
sync_offset = params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].media_type);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[params->port].media_type);
media_types = REG_RD(sc, sync_offset);
/* Update media type for non-PMF sync only for the first time
@@ -11683,9 +13555,9 @@ elink_status_t elink_phy_probe(struct elink_params * params)
(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
actual_phy_idx))) == 0) {
media_types |= ((phy->media_type &
- PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
- (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
- actual_phy_idx));
+ PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
+ (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
+ actual_phy_idx));
}
REG_WR(sc, sync_offset, media_types);
@@ -11693,48 +13565,231 @@ elink_status_t elink_phy_probe(struct elink_params * params)
params->num_phys++;
}
- PMD_DRV_LOG(DEBUG, sc,
- "End phy probe. #phys found %x", params->num_phys);
+ ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x", params->num_phys);
return ELINK_STATUS_OK;
}
-static void elink_init_bmac_loopback(struct elink_params *params,
- struct elink_vars *vars)
+#ifdef ELINK_INCLUDE_EMUL
+static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
+ struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+ vars->line_speed = params->req_line_speed[0];
+ /* In case link speed is auto, set speed the highest as possible */
+ if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)
+ vars->line_speed = ELINK_SPEED_2500;
+ else if (elink_is_4_port_mode(sc))
+ vars->line_speed = ELINK_SPEED_10000;
+ else
+ vars->line_speed = ELINK_SPEED_20000;
+ }
+ if (vars->line_speed < ELINK_SPEED_10000) {
+ if ((params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {
+ ELINK_DEBUG_P1(sc, "Invalid line speed %d while UMAC is"
+ " disabled!", params->req_line_speed[0]);
+ return ELINK_STATUS_ERROR;
+ }
+ switch (vars->line_speed) {
+ case ELINK_SPEED_10:
+ vars->link_status = ELINK_LINK_10TFD;
+ break;
+ case ELINK_SPEED_100:
+ vars->link_status = ELINK_LINK_100TXFD;
+ break;
+ case ELINK_SPEED_1000:
+ vars->link_status = ELINK_LINK_1000TFD;
+ break;
+ case ELINK_SPEED_2500:
+ vars->link_status = ELINK_LINK_2500TFD;
+ break;
+ default:
+ ELINK_DEBUG_P1(sc, "Invalid line speed %d for UMAC",
+ vars->line_speed);
+ return ELINK_STATUS_ERROR;
+ }
+ vars->link_status |= LINK_STATUS_LINK_UP;
+
+ if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
+ elink_umac_enable(params, vars, 1);
+ else
+ elink_umac_enable(params, vars, 0);
+ } else {
+ /* Link speed >= 10000 requires XMAC enabled */
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {
+ ELINK_DEBUG_P1(sc, "Invalid line speed %d while XMAC is"
+ " disabled!", params->req_line_speed[0]);
+ return ELINK_STATUS_ERROR;
+ }
+ /* Check link speed */
+ switch (vars->line_speed) {
+ case ELINK_SPEED_10000:
+ vars->link_status = ELINK_LINK_10GTFD;
+ break;
+ case ELINK_SPEED_20000:
+ vars->link_status = ELINK_LINK_20GTFD;
+ break;
+ default:
+ ELINK_DEBUG_P1(sc, "Invalid line speed %d for XMAC",
+ vars->line_speed);
+ return ELINK_STATUS_ERROR;
+ }
+ vars->link_status |= LINK_STATUS_LINK_UP;
+ if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
+ elink_xmac_enable(params, vars, 1);
+ else
+ elink_xmac_enable(params, vars, 0);
+ }
+ return ELINK_STATUS_OK;
+}
+
+static elink_status_t elink_init_emul(struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
+ if (CHIP_IS_E3(sc)) {
+ if (elink_init_e3_emul_mac(params, vars) !=
+ ELINK_STATUS_OK)
+ return ELINK_STATUS_ERROR;
+ } else {
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {
+ vars->line_speed = ELINK_SPEED_1000;
+ vars->link_status = (LINK_STATUS_LINK_UP |
+ ELINK_LINK_1000XFD);
+ if (params->loopback_mode ==
+ ELINK_LOOPBACK_EMAC)
+ elink_emac_enable(params, vars, 1);
+ else
+ elink_emac_enable(params, vars, 0);
+ } else {
+ vars->line_speed = ELINK_SPEED_10000;
+ vars->link_status = (LINK_STATUS_LINK_UP |
+ ELINK_LINK_10GTFD);
+ if (params->loopback_mode ==
+ ELINK_LOOPBACK_BMAC)
+ elink_bmac_enable(params, vars, 1, 1);
+ else
+ elink_bmac_enable(params, vars, 0, 1);
+ }
+ }
vars->link_up = 1;
- vars->line_speed = ELINK_SPEED_10000;
vars->duplex = DUPLEX_FULL;
vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
- vars->mac_type = ELINK_MAC_TYPE_BMAC;
-
- vars->phy_flags = PHY_XGXS_FLAG;
- elink_xgxs_deassert(params);
+ if (CHIP_IS_E1x(sc))
+ elink_pbf_update(params, vars->flow_ctrl,
+ vars->line_speed);
+ /* Disable drain */
+ REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
- /* Set bmac loopback */
- elink_bmac_enable(params, vars, 1, 1);
+ /* update shared memory */
+ elink_update_mng(params, vars->link_status);
+ return ELINK_STATUS_OK;
+}
+#endif
+#ifdef ELINK_INCLUDE_FPGA
+static elink_status_t elink_init_fpga(struct elink_params *params,
+ struct elink_vars *vars)
+{
+ /* Enable on E1.5 FPGA */
+ struct bnx2x_softc *sc = params->sc;
+ vars->duplex = DUPLEX_FULL;
+ vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
+ if (!(CHIP_IS_E1(sc))) {
+ vars->flow_ctrl = (ELINK_FLOW_CTRL_TX |
+ ELINK_FLOW_CTRL_RX);
+ vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
+ LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
+ }
+ if (CHIP_IS_E3(sc)) {
+ vars->line_speed = params->req_line_speed[0];
+ switch (vars->line_speed) {
+ case ELINK_SPEED_AUTO_NEG:
+ vars->line_speed = ELINK_SPEED_2500;
+ case ELINK_SPEED_2500:
+ vars->link_status = ELINK_LINK_2500TFD;
+ break;
+ case ELINK_SPEED_1000:
+ vars->link_status = ELINK_LINK_1000XFD;
+ break;
+ case ELINK_SPEED_100:
+ vars->link_status = ELINK_LINK_100TXFD;
+ break;
+ case ELINK_SPEED_10:
+ vars->link_status = ELINK_LINK_10TFD;
+ break;
+ default:
+ ELINK_DEBUG_P1(sc, "Invalid link speed %d",
+ params->req_line_speed[0]);
+ return ELINK_STATUS_ERROR;
+ }
+ vars->link_status |= LINK_STATUS_LINK_UP;
+ if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
+ elink_umac_enable(params, vars, 1);
+ else
+ elink_umac_enable(params, vars, 0);
+ } else {
+ vars->line_speed = ELINK_SPEED_10000;
+ vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
+ if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
+ elink_emac_enable(params, vars, 1);
+ else
+ elink_emac_enable(params, vars, 0);
+ }
+ vars->link_up = 1;
+ if (CHIP_IS_E1x(sc))
+ elink_pbf_update(params, vars->flow_ctrl,
+ vars->line_speed);
+ /* Disable drain */
REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
+
+ /* Update shared memory */
+ elink_update_mng(params, vars->link_status);
+ return ELINK_STATUS_OK;
+}
+#endif
+static void elink_init_bmac_loopback(struct elink_params *params,
+ struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+ vars->link_up = 1;
+ vars->line_speed = ELINK_SPEED_10000;
+ vars->duplex = DUPLEX_FULL;
+ vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
+ vars->mac_type = ELINK_MAC_TYPE_BMAC;
+
+ vars->phy_flags = PHY_XGXS_FLAG;
+
+ elink_xgxs_deassert(params);
+
+ /* Set bmac loopback */
+ elink_bmac_enable(params, vars, 1, 1);
+
+ REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
}
static void elink_init_emac_loopback(struct elink_params *params,
struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
- vars->link_up = 1;
- vars->line_speed = ELINK_SPEED_1000;
- vars->duplex = DUPLEX_FULL;
- vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
- vars->mac_type = ELINK_MAC_TYPE_EMAC;
+ vars->link_up = 1;
+ vars->line_speed = ELINK_SPEED_1000;
+ vars->duplex = DUPLEX_FULL;
+ vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
+ vars->mac_type = ELINK_MAC_TYPE_EMAC;
- vars->phy_flags = PHY_XGXS_FLAG;
+ vars->phy_flags = PHY_XGXS_FLAG;
- elink_xgxs_deassert(params);
- /* Set bmac loopback */
- elink_emac_enable(params, vars, 1);
- elink_emac_program(params, vars);
- REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
+ elink_xgxs_deassert(params);
+ /* Set bmac loopback */
+ elink_emac_enable(params, vars, 1);
+ elink_emac_program(params, vars);
+ REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
}
static void elink_init_xmac_loopback(struct elink_params *params,
@@ -11755,8 +13810,9 @@ static void elink_init_xmac_loopback(struct elink_params *params,
*/
elink_set_aer_mmd(params, ¶ms->phy[0]);
elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
- params->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY],
- params);
+ params->phy[ELINK_INT_PHY].config_loopback(
+ ¶ms->phy[ELINK_INT_PHY],
+ params);
elink_xmac_enable(params, vars, 1);
REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
@@ -11818,12 +13874,11 @@ static void elink_init_xgxs_loopback(struct elink_params *params,
/* Set external phy loopback */
uint8_t phy_index;
for (phy_index = ELINK_EXT_PHY1;
- phy_index < params->num_phys; phy_index++)
+ phy_index < params->num_phys; phy_index++)
if (params->phy[phy_index].config_loopback)
- params->phy[phy_index].config_loopback(¶ms->
- phy
- [phy_index],
- params);
+ params->phy[phy_index].config_loopback(
+ ¶ms->phy[phy_index],
+ params);
}
REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
@@ -11840,12 +13895,14 @@ void elink_set_rx_filter(struct elink_params *params, uint8_t en)
val |= en * 0x20;
REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val);
- REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3);
+ if (!CHIP_IS_E1(sc)) {
+ REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4,
+ en * 0x3);
+ }
REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
NIG_REG_LLH0_BRB1_NOT_MCP), en);
}
-
static elink_status_t elink_avoid_link_flap(struct elink_params *params,
struct elink_vars *vars)
{
@@ -11853,6 +13910,7 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,
uint32_t dont_clear_stat, lfa_sts;
struct bnx2x_softc *sc = params->sc;
+ elink_set_mdio_emac_per_phy(sc, params);
/* Sync the link parameters */
elink_link_status_update(params, vars);
@@ -11864,7 +13922,7 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,
for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
struct elink_phy *phy = ¶ms->phy[phy_idx];
if (phy->phy_specific_func) {
- PMD_DRV_LOG(DEBUG, sc, "Calling PHY specific func");
+ ELINK_DEBUG_P0(sc, "Calling PHY specific func");
phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
}
if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
@@ -11873,7 +13931,8 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,
elink_verify_sfp_module(phy, params);
}
lfa_sts = REG_RD(sc, params->lfa_base +
- offsetof(struct shmem_lfa, lfa_sts));
+ offsetof(struct shmem_lfa,
+ lfa_sts));
dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
@@ -11984,13 +14043,12 @@ elink_status_t elink_phy_init(struct elink_params *params,
{
int lfa_status;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Phy Initialization started");
- PMD_DRV_LOG(DEBUG, sc, "(1) req_speed %d, req_flowctrl %d",
- params->req_line_speed[0], params->req_flow_ctrl[0]);
- PMD_DRV_LOG(DEBUG, sc, "(2) req_speed %d, req_flowctrl %d",
- params->req_line_speed[1], params->req_flow_ctrl[1]);
- PMD_DRV_LOG(DEBUG, sc,
- "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
+ ELINK_DEBUG_P0(sc, "Phy Initialization started");
+ ELINK_DEBUG_P2(sc, "(1) req_speed %d, req_flowctrl %d",
+ params->req_line_speed[0], params->req_flow_ctrl[0]);
+ ELINK_DEBUG_P2(sc, "(2) req_speed %d, req_flowctrl %d",
+ params->req_line_speed[1], params->req_flow_ctrl[1]);
+ ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
vars->link_status = 0;
vars->phy_link_up = 0;
vars->link_up = 0;
@@ -12003,17 +14061,33 @@ elink_status_t elink_phy_init(struct elink_params *params,
params->link_flags = ELINK_PHY_INITIALIZED;
/* Driver opens NIG-BRB filters */
elink_set_rx_filter(params, 1);
+ elink_chng_link_count(params, 1);
/* Check if link flap can be avoided */
lfa_status = elink_check_lfa(params);
+ ELINK_DEBUG_P3(sc, " params : port = %x, loopback_mode = %x req_duplex = %x",
+ params->port, params->loopback_mode,
+ params->req_duplex[0]);
+ ELINK_DEBUG_P3(sc, " params : switch_cfg = %x, lane_config = %x req_duplex[1] = %x",
+ params->switch_cfg, params->lane_config,
+ params->req_duplex[1]);
+ ELINK_DEBUG_P3(sc, " params : chip_id = %x, feature_config_flags = %x, num_phys = %x",
+ params->chip_id, params->feature_config_flags,
+ params->num_phys);
+ ELINK_DEBUG_P3(sc, " params : rsrv = %x, eee_mode = %x, hw_led_mode = %x",
+ params->rsrv, params->eee_mode, params->hw_led_mode);
+ ELINK_DEBUG_P3(sc, " params : multi_phy = %x, req_fc_auto_adv = %x, link_flags = %x",
+ params->multi_phy_config, params->req_fc_auto_adv,
+ params->link_flags);
+ ELINK_DEBUG_P2(sc, " params : lfa_base = %x, link_attr = %x",
+ params->lfa_base, params->link_attr_sync);
if (lfa_status == 0) {
- PMD_DRV_LOG(DEBUG, sc,
- "Link Flap Avoidance in progress");
+ ELINK_DEBUG_P0(sc, "Link Flap Avoidance in progress");
return elink_avoid_link_flap(params, vars);
}
- PMD_DRV_LOG(DEBUG, sc,
- "Cannot avoid link flap lfa_sta=0x%x", lfa_status);
+ ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x",
+ lfa_status);
elink_cannot_avoid_link_flap(params, vars, lfa_status);
/* Disable attentions */
@@ -12022,20 +14096,34 @@ elink_status_t elink_phy_init(struct elink_params *params,
ELINK_NIG_MASK_XGXS0_LINK10G |
ELINK_NIG_MASK_SERDES0_LINK_STATUS |
ELINK_NIG_MASK_MI_INT));
+#ifdef ELINK_INCLUDE_EMUL
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))
+#endif
- elink_emac_init(params);
+ elink_emac_init(params, vars);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
vars->link_status |= LINK_STATUS_PFC_ENABLED;
- if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {
- PMD_DRV_LOG(DEBUG, sc, "No phy found for initialization !!");
+ if ((params->num_phys == 0) &&
+ !CHIP_REV_IS_SLOW(sc)) {
+ ELINK_DEBUG_P0(sc, "No phy found for initialization !!");
return ELINK_STATUS_ERROR;
}
set_phy_vars(params, vars);
- PMD_DRV_LOG(DEBUG, sc, "Num of phys on board: %d", params->num_phys);
-
+ ELINK_DEBUG_P1(sc, "Num of phys on board: %d", params->num_phys);
+#ifdef ELINK_INCLUDE_FPGA
+ if (CHIP_REV_IS_FPGA(sc)) {
+ return elink_init_fpga(params, vars);
+ } else
+#endif
+#ifdef ELINK_INCLUDE_EMUL
+ if (CHIP_REV_IS_EMUL(sc)) {
+ return elink_init_emul(params, vars);
+ } else
+#endif
switch (params->loopback_mode) {
case ELINK_LOOPBACK_BMAC:
elink_init_bmac_loopback(params, vars);
@@ -12071,15 +14159,16 @@ elink_status_t elink_phy_init(struct elink_params *params,
return ELINK_STATUS_OK;
}
-static elink_status_t elink_link_reset(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t reset_ext_phy)
+elink_status_t elink_link_reset(struct elink_params *params,
+ struct elink_vars *vars,
+ uint8_t reset_ext_phy)
{
struct bnx2x_softc *sc = params->sc;
uint8_t phy_index, port = params->port, clear_latch_ind = 0;
- PMD_DRV_LOG(DEBUG, sc, "Resetting the link of port %d", port);
+ ELINK_DEBUG_P1(sc, "Resetting the link of port %d", port);
/* Disable attentions */
vars->link_status = 0;
+ elink_chng_link_count(params, 1);
elink_update_mng(params, vars->link_status);
vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
SHMEM_EEE_ACTIVE_BIT);
@@ -12098,12 +14187,24 @@ static elink_status_t elink_link_reset(struct elink_params *params,
REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
}
- if (!CHIP_IS_E3(sc))
- elink_set_bmac_rx(sc, port, 0);
- if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {
- elink_set_xmac_rxtx(params, 0);
- elink_set_umac_rxtx(params, 0);
- }
+
+#ifdef ELINK_INCLUDE_EMUL
+ /* Stop BigMac rx */
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))
+#endif
+ if (!CHIP_IS_E3(sc))
+ elink_set_bmac_rx(sc, params->chip_id, port, 0);
+#ifdef ELINK_INCLUDE_EMUL
+ /* Stop XMAC/UMAC rx */
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))
+#endif
+ if (CHIP_IS_E3(sc) &&
+ !CHIP_REV_IS_FPGA(sc)) {
+ elink_set_xmac_rxtx(params, 0);
+ elink_set_umac_rxtx(params, 0);
+ }
/* Disable emac */
if (!CHIP_IS_E3(sc))
REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
@@ -12112,20 +14213,19 @@ static elink_status_t elink_link_reset(struct elink_params *params,
/* The PHY reset is controlled by GPIO 1
* Hold it as vars low
*/
- /* Clear link led */
+ /* Clear link led */
elink_set_mdio_emac_per_phy(sc, params);
elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
if (params->phy[phy_index].link_reset) {
elink_set_aer_mmd(params,
¶ms->phy[phy_index]);
- params->phy[phy_index].link_reset(¶ms->
- phy
- [phy_index],
- params);
+ params->phy[phy_index].link_reset(
+ ¶ms->phy[phy_index],
+ params);
}
if (params->phy[phy_index].flags &
ELINK_FLAGS_REARM_LATCH_SIGNAL)
@@ -12139,11 +14239,12 @@ static elink_status_t elink_link_reset(struct elink_params *params,
elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,
1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
}
+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
+ if (!CHIP_REV_IS_SLOW(sc))
+#endif
if (params->phy[ELINK_INT_PHY].link_reset)
- params->phy[ELINK_INT_PHY].link_reset(¶ms->
- phy
- [ELINK_INT_PHY],
- params);
+ params->phy[ELINK_INT_PHY].link_reset(
+ ¶ms->phy[ELINK_INT_PHY], params);
/* Disable nig ingress interface */
if (!CHIP_IS_E3(sc)) {
@@ -12153,8 +14254,8 @@ static elink_status_t elink_link_reset(struct elink_params *params,
REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);
REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);
} else {
- uint32_t xmac_base =
- (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
+ uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 :
+ GRCBASE_XMAC0;
elink_set_xumac_nig(params, 0, 0);
if (REG_RD(sc, MISC_REG_RESET_REG_2) &
MISC_REGISTERS_RESET_REG_2_XMAC)
@@ -12165,9 +14266,8 @@ static elink_status_t elink_link_reset(struct elink_params *params,
vars->phy_flags = 0;
return ELINK_STATUS_OK;
}
-
-elink_status_t elink_lfa_reset(struct elink_params * params,
- struct elink_vars * vars)
+elink_status_t elink_lfa_reset(struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
vars->link_up = 0;
@@ -12186,13 +14286,13 @@ elink_status_t elink_lfa_reset(struct elink_params * params,
* are passed.
*/
if (!CHIP_IS_E3(sc))
- elink_set_bmac_rx(sc, params->port, 0);
+ elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
if (CHIP_IS_E3(sc)) {
elink_set_xmac_rxtx(params, 0);
elink_set_umac_rxtx(params, 0);
}
- /* Wait 10ms for the pipe to clean up */
+ /* Wait 10ms for the pipe to clean up*/
DELAY(1000 * 10);
/* Clean the NIG-BRB using the network filters in a way that will
@@ -12207,7 +14307,7 @@ elink_status_t elink_lfa_reset(struct elink_params * params,
* minimum management protocol down time.
*/
if (!CHIP_IS_E3(sc))
- elink_set_bmac_rx(sc, params->port, 1);
+ elink_set_bmac_rx(sc, params->chip_id, params->port, 1);
if (CHIP_IS_E3(sc)) {
elink_set_xmac_rxtx(params, 1);
@@ -12222,10 +14322,10 @@ elink_status_t elink_lfa_reset(struct elink_params * params,
/* Common function */
/****************************************************************************/
static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint8_t phy_index,
- __rte_unused uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[],
+ uint8_t phy_index,
+ __rte_unused uint32_t chip_id)
{
struct elink_phy phy[PORT_MAX];
struct elink_phy *phy_blk[PORT_MAX];
@@ -12233,8 +14333,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
int8_t port = 0;
int8_t port_of_path = 0;
uint32_t swap_val, swap_override;
- swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
- swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
+ swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
+ swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
port ^= (swap_val && swap_override);
elink_ext_phy_hw_reset(sc, port);
/* PART1 - Reset both phys */
@@ -12255,7 +14355,7 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port_of_path, &phy[port]) !=
ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate_phy failed");
+ ELINK_DEBUG_P0(sc, "populate_phy failed");
return ELINK_STATUS_ERROR;
}
/* Disable attentions */
@@ -12270,11 +14370,14 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
* to write to access its registers
*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+ port);
/* Reset the phy */
elink_cl45_write(sc, &phy[port],
- MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL,
+ 1 << 15);
}
/* Add delay of 150ms after reset */
@@ -12295,8 +14398,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
else
port_of_path = 0;
- PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
- phy_blk[port]->addr);
+ ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x",
+ phy_blk[port]->addr);
if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
port_of_path))
return ELINK_STATUS_ERROR;
@@ -12309,7 +14412,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
/* Phase1 of TX_POWER_DOWN reset */
elink_cl45_write(sc, phy_blk[port],
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));
+ MDIO_PMA_REG_TX_POWER_DOWN,
+ (val | 1 << 10));
}
/* Toggle Transmitter: Power down and then up with 600ms delay
@@ -12326,9 +14430,9 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
MDIO_PMA_REG_TX_POWER_DOWN, &val);
elink_cl45_write(sc, phy_blk[port],
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_TX_POWER_DOWN,
- (val & (~(1 << 10))));
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_TX_POWER_DOWN,
+ (val & (~(1 << 10))));
DELAY(1000 * 15);
/* Read modify write the SPI-ROM version select register */
@@ -12341,16 +14445,15 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
/* set GPIO2 back to LOW */
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
}
return ELINK_STATUS_OK;
}
-
static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint8_t phy_index,
- __rte_unused uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[],
+ uint8_t phy_index,
+ __rte_unused uint32_t chip_id)
{
uint32_t val;
int8_t port;
@@ -12359,8 +14462,8 @@ static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
/* Enable the module detection interrupt */
val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
val |= ((1 << MISC_REGISTERS_GPIO_3) |
- (1 <<
- (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
+ (1 << (MISC_REGISTERS_GPIO_3 +
+ MISC_REGISTERS_GPIO_PORT_SHIFT)));
REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
elink_ext_phy_hw_reset(sc, 0);
@@ -12378,33 +14481,33 @@ static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
}
/* Extract the ext phy address for the port */
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
- port, &phy) != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
+ port, &phy) !=
+ ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc, "populate phy failed");
return ELINK_STATUS_ERROR;
}
- /* Reset phy */
+ /* Reset phy*/
elink_cl45_write(sc, &phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
+
/* Set fault module detected LED on */
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
- MISC_REGISTERS_GPIO_HIGH, port);
+ MISC_REGISTERS_GPIO_HIGH,
+ port);
}
return ELINK_STATUS_OK;
}
-
static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,
- uint32_t shmem_base, uint8_t * io_gpio,
- uint8_t * io_port)
+ uint32_t shmem_base,
+ uint8_t *io_gpio, uint8_t *io_port)
{
uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[PORT_0].
- default_cfg));
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[PORT_0].default_cfg));
switch (phy_gpio_reset) {
case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
*io_gpio = 0;
@@ -12445,10 +14548,10 @@ static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,
}
static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint8_t phy_index,
- __rte_unused uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[],
+ uint8_t phy_index,
+ __rte_unused uint32_t chip_id)
{
int8_t port, reset_gpio;
uint32_t swap_val, swap_override;
@@ -12465,18 +14568,17 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
* Default is GPIO1, PORT1
*/
elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
- (uint8_t *) & reset_gpio,
- (uint8_t *) & port);
+ (uint8_t *)&reset_gpio, (uint8_t *)&port);
/* Calculate the port based on port swap */
port ^= (swap_val && swap_override);
- /* Initiate PHY reset */
+ /* Initiate PHY reset*/
elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
- port);
+ port);
DELAY(1000 * 1);
elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
- port);
+ port);
DELAY(1000 * 5);
@@ -12498,8 +14600,8 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
/* Extract the ext phy address for the port */
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port_of_path, &phy[port]) !=
- ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
+ ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc, "populate phy failed");
return ELINK_STATUS_ERROR;
}
/* disable attentions */
@@ -12510,6 +14612,7 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
ELINK_NIG_MASK_SERDES0_LINK_STATUS |
ELINK_NIG_MASK_MI_INT));
+
/* Reset the phy */
elink_cl45_write(sc, &phy[port],
MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
@@ -12530,25 +14633,25 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
port_of_path = port;
else
port_of_path = 0;
- PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
- phy_blk[port]->addr);
+ ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x",
+ phy_blk[port]->addr);
if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
port_of_path))
return ELINK_STATUS_ERROR;
/* Disable PHY transmitter output */
elink_cl45_write(sc, phy_blk[port],
- MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_TX_DISABLE, 1);
}
return ELINK_STATUS_OK;
}
static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- __rte_unused uint32_t
- shmem2_base_path[],
- __rte_unused uint8_t
- phy_index, uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ __rte_unused uint32_t shmem2_base_path[],
+ __rte_unused uint8_t phy_index,
+ uint32_t chip_id)
{
uint8_t reset_gpios;
reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
@@ -12557,17 +14660,15 @@ static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
DELAY(10);
elink_cb_gpio_mult_write(sc, reset_gpios,
MISC_REGISTERS_GPIO_OUTPUT_HIGH);
- PMD_DRV_LOG(DEBUG, sc,
- "84833 reset pulse on pin values 0x%x", reset_gpios);
+ ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x",
+ reset_gpios);
return ELINK_STATUS_OK;
}
-
static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint8_t phy_index,
- uint32_t ext_phy_type,
- uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[],
+ uint8_t phy_index,
+ uint32_t ext_phy_type, uint32_t chip_id)
{
elink_status_t rc = ELINK_STATUS_OK;
@@ -12595,44 +14696,50 @@ static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858:
/* GPIO3's are linked, and so both need to be toggled
* to obtain required 2us pulse.
*/
rc = elink_84833_common_init_phy(sc, shmem_base_path,
- shmem2_base_path,
- phy_index, chip_id);
+ shmem2_base_path,
+ phy_index, chip_id);
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
rc = ELINK_STATUS_ERROR;
break;
default:
- PMD_DRV_LOG(DEBUG, sc,
- "ext_phy 0x%x common init not required",
- ext_phy_type);
+ ELINK_DEBUG_P1(sc,
+ "ext_phy 0x%x common init not required",
+ ext_phy_type);
break;
}
if (rc != ELINK_STATUS_OK)
- elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
- // " Port %d",
+ elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0);
+ /* "Warning: PHY was not initialized,"
+ * " Port %d",
+ */
return rc;
}
-elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint32_t chip_id,
- __rte_unused uint8_t one_port_enabled)
+elink_status_t elink_common_init_phy(struct bnx2x_softc *sc,
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[], uint32_t chip_id,
+ __rte_unused uint8_t one_port_enabled)
{
elink_status_t rc = ELINK_STATUS_OK;
uint32_t phy_ver, val;
uint8_t phy_index = 0;
uint32_t ext_phy_type, ext_phy_config;
+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
+ if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))
+ return ELINK_STATUS_OK;
+#endif
- elink_set_mdio_clk(sc, GRCBASE_EMAC0);
- elink_set_mdio_clk(sc, GRCBASE_EMAC1);
- PMD_DRV_LOG(DEBUG, sc, "Begin common phy init");
+ elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0);
+ elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1);
+ ELINK_DEBUG_P0(sc, "Begin common phy init");
if (CHIP_IS_E3(sc)) {
/* Enable EPIO */
val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
@@ -12643,14 +14750,14 @@ elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
offsetof(struct shmem_region,
port_mb[PORT_0].ext_phy_fw_version));
if (phy_ver) {
- PMD_DRV_LOG(DEBUG, sc, "Not doing common init; phy ver is 0x%x",
- phy_ver);
+ ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x",
+ phy_ver);
return ELINK_STATUS_OK;
}
/* Read the ext_phy_type for arbitrary port(0) */
for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
- phy_index++) {
+ phy_index++) {
ext_phy_config = elink_get_ext_phy_config(sc,
shmem_base_path[0],
phy_index, 0);
@@ -12673,10 +14780,9 @@ static void elink_check_over_curr(struct elink_params *params,
cfg_pin = (REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_cmn_pin_cfg1)) &
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
- PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
+ PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
/* Ignore check if no external input PIN available */
if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
@@ -12684,13 +14790,16 @@ static void elink_check_over_curr(struct elink_params *params,
if (!pin_val) {
if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
- elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
- // " been detected and the power to "
- // "that SFP+ module has been removed"
- // " to prevent failure of the card."
- // " Please remove the SFP+ module and"
- // " restart the system to clear this"
- // " error.",
+ elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT,
+ params->port);
+ /* "Error: Power fault on Port %d has"
+ * " been detected and the power to "
+ * "that SFP+ module has been removed"
+ * " to prevent failure of the card."
+ * " Please remove the SFP+ module and"
+ * " restart the system to clear this"
+ * " error.",
+ */
vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
elink_warpcore_power_module(params, 0);
}
@@ -12700,9 +14809,9 @@ static void elink_check_over_curr(struct elink_params *params,
/* Returns 0 if no change occurred since last check; 1 otherwise. */
static uint8_t elink_analyze_link_error(struct elink_params *params,
- struct elink_vars *vars,
- uint32_t status, uint32_t phy_flag,
- uint32_t link_flag, uint8_t notify)
+ struct elink_vars *vars, uint32_t status,
+ uint32_t phy_flag, uint32_t link_flag,
+ uint8_t notify)
{
struct bnx2x_softc *sc = params->sc;
/* Compare new value with previous value */
@@ -12715,16 +14824,20 @@ static uint8_t elink_analyze_link_error(struct elink_params *params,
/* If values differ */
switch (phy_flag) {
case PHY_HALF_OPEN_CONN_FLAG:
- PMD_DRV_LOG(DEBUG, sc, "Analyze Remote Fault");
+ ELINK_DEBUG_P0(sc, "Analyze Remote Fault");
break;
case PHY_SFP_TX_FAULT_FLAG:
- PMD_DRV_LOG(DEBUG, sc, "Analyze TX Fault");
+ ELINK_DEBUG_P0(sc, "Analyze TX Fault");
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Analyze UNKNOWN");
+ ELINK_DEBUG_P0(sc, "Analyze UNKNOWN");
}
- PMD_DRV_LOG(DEBUG, sc, "Link changed:[%x %x]->%x", vars->link_up,
- old_status, status);
+ ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x", vars->link_up,
+ old_status, status);
+
+ /* Do not touch the link in case physical link down */
+ if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
+ return 1;
/* a. Update shmem->link_status accordingly
* b. Update elink_vars->link_up
@@ -12767,17 +14880,18 @@ static uint8_t elink_analyze_link_error(struct elink_params *params,
}
/******************************************************************************
-* Description:
-* This function checks for half opened connection change indication.
-* When such change occurs, it calls the elink_analyze_link_error
-* to check if Remote Fault is set or cleared. Reception of remote fault
-* status message in the MAC indicates that the peer's MAC has detected
-* a fault, for example, due to break in the TX side of fiber.
-*
-******************************************************************************/
-static elink_status_t elink_check_half_open_conn(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t notify)
+ * Description:
+ * This function checks for half opened connection change indication.
+ * When such change occurs, it calls the elink_analyze_link_error
+ * to check if Remote Fault is set or cleared. Reception of remote fault
+ * status message in the MAC indicates that the peer's MAC has detected
+ * a fault, for example, due to break in the TX side of fiber.
+ *
+ ******************************************************************************/
+static
+elink_status_t elink_check_half_open_conn(struct elink_params *params,
+ struct elink_vars *vars,
+ uint8_t notify)
{
struct bnx2x_softc *sc = params->sc;
uint32_t lss_status = 0;
@@ -12789,7 +14903,7 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params,
if (CHIP_IS_E3(sc) &&
(REG_RD(sc, MISC_REG_RESET_REG_2) &
- (MISC_REGISTERS_RESET_REG_2_XMAC))) {
+ (MISC_REGISTERS_RESET_REG_2_XMAC))) {
/* Check E3 XMAC */
/* Note that link speed cannot be queried here, since it may be
* zero while link is down. In case UMAC is active, LSS will
@@ -12814,7 +14928,7 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params,
uint32_t lss_status_reg;
uint32_t wb_data[2];
mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
/* Read BIGMAC_REGISTER_RX_LSS_STATUS */
if (CHIP_IS_E2(sc))
lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
@@ -12830,7 +14944,6 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params,
}
return ELINK_STATUS_OK;
}
-
static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
struct elink_params *params,
struct elink_vars *vars)
@@ -12841,15 +14954,12 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
/* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
- dev_info.
- port_hw_config
- [port].
- e3_cmn_pin_cfg)) &
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
PORT_HW_CFG_E3_TX_FAULT_MASK) >>
- PORT_HW_CFG_E3_TX_FAULT_SHIFT;
+ PORT_HW_CFG_E3_TX_FAULT_SHIFT;
if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to read pin 0x%02x", cfg_pin);
+ ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x", cfg_pin);
return;
}
@@ -12871,24 +14981,25 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
/* If module is unapproved, led should be on regardless */
if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
- PMD_DRV_LOG(DEBUG, sc, "Change TX_Fault LED: ->%x",
- led_mode);
+ ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x",
+ led_mode);
elink_set_e3_module_fault_led(params, led_mode);
}
}
}
-
static void elink_kr2_recovery(struct elink_params *params,
- struct elink_vars *vars, struct elink_phy *phy)
+ struct elink_vars *vars,
+ struct elink_phy *phy)
{
- PMD_DRV_LOG(DEBUG, params->sc, "KR2 recovery");
-
+ struct bnx2x_softc *sc = params->sc;
+ ELINK_DEBUG_P0(sc, "KR2 recovery");
elink_warpcore_enable_AN_KR2(phy, params, vars);
elink_warpcore_restart_AN_KR(phy, params);
}
static void elink_check_kr2_wa(struct elink_params *params,
- struct elink_vars *vars, struct elink_phy *phy)
+ struct elink_vars *vars,
+ struct elink_phy *phy)
{
struct bnx2x_softc *sc = params->sc;
uint16_t base_page, next_page, not_kr2_device, lane;
@@ -12906,14 +15017,14 @@ static void elink_check_kr2_wa(struct elink_params *params,
sigdet = elink_warpcore_get_sigdet(phy, params);
if (!sigdet) {
- if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
+ if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
elink_kr2_recovery(params, vars, phy);
- PMD_DRV_LOG(DEBUG, sc, "No sigdet");
+ ELINK_DEBUG_P0(sc, "No sigdet");
}
return;
}
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
MDIO_AER_BLOCK_AER_REG, lane);
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
@@ -12924,9 +15035,9 @@ static void elink_check_kr2_wa(struct elink_params *params,
/* CL73 has not begun yet */
if (base_page == 0) {
- if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
+ if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
elink_kr2_recovery(params, vars, phy);
- PMD_DRV_LOG(DEBUG, sc, "No BP");
+ ELINK_DEBUG_P0(sc, "No BP");
}
return;
}
@@ -12940,10 +15051,10 @@ static void elink_check_kr2_wa(struct elink_params *params,
((next_page & 0xe0) == 0x20))));
/* In case KR2 is already disabled, check if we need to re-enable it */
- if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
+ if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
if (!not_kr2_device) {
- PMD_DRV_LOG(DEBUG, sc, "BP=0x%x, NP=0x%x", base_page,
- next_page);
+ ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x", base_page,
+ next_page);
elink_kr2_recovery(params, vars, phy);
}
return;
@@ -12951,8 +15062,7 @@ static void elink_check_kr2_wa(struct elink_params *params,
/* KR2 is enabled, but not KR2 device */
if (not_kr2_device) {
/* Disable KR2 on both lanes */
- PMD_DRV_LOG(DEBUG, sc,
- "BP=0x%x, NP=0x%x", base_page, next_page);
+ ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x", base_page, next_page);
elink_disable_kr2(params, vars, phy);
/* Restart AN on leading lane */
elink_warpcore_restart_AN_KR(phy, params);
@@ -12968,9 +15078,8 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)
if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
if (elink_check_half_open_conn(params, vars, 1) !=
- ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Fault detection failed");
- }
+ ELINK_STATUS_OK)
+ ELINK_DEBUG_P0(sc, "Fault detection failed");
break;
}
}
@@ -12978,22 +15087,24 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)
if (CHIP_IS_E3(sc)) {
struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
elink_set_aer_mmd(params, phy);
- if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
- (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
+ if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
+ (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
+ (phy->req_line_speed == ELINK_SPEED_20000))
elink_check_kr2_wa(params, vars, phy);
elink_check_over_curr(params, vars);
if (vars->rx_tx_asic_rst)
elink_warpcore_config_runtime(phy, params, vars);
if ((REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- default_cfg))
- & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg))
+ & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
PORT_HW_CFG_NET_SERDES_IF_SFI) {
- if (elink_is_sfp_module_plugged(params)) {
+ if (elink_is_sfp_module_plugged(phy, params)) {
elink_sfp_tx_fault_detection(phy, params, vars);
- } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) {
+ } else if (vars->link_status &
+ LINK_STATUS_SFP_TX_FAULT) {
/* Clean trail, interrupt corrects the leds */
vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
@@ -13005,17 +15116,18 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)
}
uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,
- uint32_t shmem_base,
- uint32_t shmem2_base, uint8_t port)
+ uint32_t shmem_base,
+ uint32_t shmem2_base,
+ uint8_t port)
{
uint8_t phy_index, fan_failure_det_req = 0;
struct elink_phy phy;
for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
- phy_index++) {
+ phy_index++) {
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port, &phy)
!= ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
+ ELINK_DEBUG_P0(sc, "populate phy failed");
return 0;
}
fan_failure_det_req |= (phy.flags &
@@ -13035,24 +15147,27 @@ void elink_hw_reset_phy(struct elink_params *params)
ELINK_NIG_MASK_SERDES0_LINK_STATUS |
ELINK_NIG_MASK_MI_INT));
- for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
+ for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
+ phy_index++) {
if (params->phy[phy_index].hw_reset) {
- params->phy[phy_index].hw_reset(¶ms->phy[phy_index],
- params);
+ params->phy[phy_index].hw_reset(
+ ¶ms->phy[phy_index],
+ params);
params->phy[phy_index] = phy_null;
}
}
}
void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
- __rte_unused uint32_t chip_id, uint32_t shmem_base,
- uint32_t shmem2_base, uint8_t port)
+ uint32_t chip_id, uint32_t shmem_base,
+ uint32_t shmem2_base,
+ uint8_t port)
{
uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
uint32_t val;
uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
if (CHIP_IS_E3(sc)) {
- if (elink_get_mod_abs_int_cfg(sc,
+ if (elink_get_mod_abs_int_cfg(sc, chip_id,
shmem_base,
port,
&gpio_num,
@@ -13061,11 +15176,11 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
} else {
struct elink_phy phy;
for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
- phy_index++) {
+ phy_index++) {
if (elink_populate_phy(sc, phy_index, shmem_base,
shmem2_base, port, &phy)
!= ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
+ ELINK_DEBUG_P0(sc, "populate phy failed");
return;
}
if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {
@@ -13088,15 +15203,15 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
gpio_port ^= (swap_val && swap_override);
vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
- (gpio_num + (gpio_port << 2));
+ (gpio_num + (gpio_port << 2));
sync_offset = shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].aeu_int_mask);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].aeu_int_mask);
REG_WR(sc, sync_offset, vars->aeu_int_mask);
- PMD_DRV_LOG(DEBUG, sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
- gpio_num, gpio_port, vars->aeu_int_mask);
+ ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
+ gpio_num, gpio_port, vars->aeu_int_mask);
if (port == 0)
offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
diff --git a/drivers/net/bnx2x/elink.h b/drivers/net/bnx2x/elink.h
index 40000c2..a375d52 100644
--- a/drivers/net/bnx2x/elink.h
+++ b/drivers/net/bnx2x/elink.h
@@ -14,7 +14,7 @@
#ifndef ELINK_H
#define ELINK_H
-#define ELINK_DEBUG
+#include "bnx2x_logs.h"
@@ -29,6 +29,11 @@
extern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr);
extern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val);
+/* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/
+extern void elink_cb_reg_wb_write(struct bnx2x_softc *sc, uint32_t offset,
+ uint32_t *wb_write, uint16_t len);
+extern void elink_cb_reg_wb_read(struct bnx2x_softc *sc, uint32_t offset,
+ uint32_t *wb_write, uint16_t len);
/* mode - 0( LOW ) /1(HIGH)*/
extern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc,
@@ -45,6 +50,9 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
extern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param);
+/* Delay */
+extern void elink_cb_udelay(struct bnx2x_softc *sc, uint32_t microsecond);
+
/* This function is called every 1024 bytes downloading of phy firmware.
Driver can use it to print to screen indication for download progress */
extern void elink_cb_download_progress(struct bnx2x_softc *sc, uint32_t cur, uint32_t total);
@@ -69,6 +77,8 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
extern void elink_cb_event_log(struct bnx2x_softc *sc, const elink_log_id_t log_id, ...);
extern void elink_cb_load_warpcore_microcode(void);
+extern uint8_t elink_cb_path_id(struct bnx2x_softc *sc);
+
extern void elink_cb_notify_link_changed(struct bnx2x_softc *sc);
#define ELINK_EVENT_LOG_LEVEL_ERROR 1
@@ -78,6 +88,32 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
/* Debug prints */
+#ifdef ELINK_DEBUG
+
+extern void elink_cb_dbg(struct bnx2x_softc *sc, const char *fmt);
+extern void elink_cb_dbg1(struct bnx2x_softc *sc, const char *fmt,
+ uint32_t arg1);
+extern void elink_cb_dbg2(struct bnx2x_softc *sc, const char *fmt,
+ uint32_t arg1, uint32_t arg2);
+extern void elink_cb_dbg3(struct bnx2x_softc *sc, const char *fmt,
+ uint32_t arg1, uint32_t arg2,
+ uint32_t arg3);
+
+#define ELINK_DEBUG_P0(sc, fmt) elink_cb_dbg(sc, fmt)
+#define ELINK_DEBUG_P1(sc, fmt, arg1) elink_cb_dbg1(sc, fmt, arg1)
+#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) \
+ elink_cb_dbg2(sc, fmt, arg1, arg2)
+#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \
+ elink_cb_dbg3(sc, fmt, arg1, arg2, arg3)
+#else
+#define ELINK_DEBUG_P0(sc, fmt) PMD_DRV_LOG(DEBUG, sc, fmt)
+#define ELINK_DEBUG_P1(sc, fmt, arg1) \
+ PMD_DRV_LOG(DEBUG, sc, fmt, arg1)
+#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) \
+ PMD_DRV_LOG(DEBUG, sc, fmt, arg1, arg2)
+#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \
+ PMD_DRV_LOG(DEBUG, sc, fmt, arg1, arg2, arg3)
+#endif
/***********************************************************/
/* Defines */
@@ -126,9 +162,12 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
#define ELINK_SFP_EEPROM_DATE_SIZE 6
#define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
#define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1
-#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2)
+#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1 << 2)
#define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
#define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1
+#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR 0x60
+#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE 16
+
#define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e
#define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f
@@ -219,23 +258,23 @@ struct elink_phy {
uint8_t def_md_devad;
uint16_t flags;
/* No Over-Current detection */
-#define ELINK_FLAGS_NOC (1<<1)
+#define ELINK_FLAGS_NOC (1 << 1)
/* Fan failure detection required */
-#define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2)
+#define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1 << 2)
/* Initialize first the XGXS and only then the phy itself */
-#define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3)
-#define ELINK_FLAGS_WC_DUAL_MODE (1<<4)
-#define ELINK_FLAGS_4_PORT_MODE (1<<5)
-#define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6)
-#define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7)
-#define ELINK_FLAGS_MDC_MDIO_WA (1<<8)
-#define ELINK_FLAGS_DUMMY_READ (1<<9)
-#define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10)
-#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11)
-#define ELINK_FLAGS_TX_ERROR_CHECK (1<<12)
-#define ELINK_FLAGS_EEE (1<<13)
-#define ELINK_FLAGS_TEMPERATURE (1<<14)
-#define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15)
+#define ELINK_FLAGS_INIT_XGXS_FIRST (1 << 3)
+#define ELINK_FLAGS_WC_DUAL_MODE (1 << 4)
+#define ELINK_FLAGS_4_PORT_MODE (1 << 5)
+#define ELINK_FLAGS_REARM_LATCH_SIGNAL (1 << 6)
+#define ELINK_FLAGS_SFP_NOT_APPROVED (1 << 7)
+#define ELINK_FLAGS_MDC_MDIO_WA (1 << 8)
+#define ELINK_FLAGS_DUMMY_READ (1 << 9)
+#define ELINK_FLAGS_MDC_MDIO_WA_B0 (1 << 10)
+#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1 << 11)
+#define ELINK_FLAGS_TX_ERROR_CHECK (1 << 12)
+#define ELINK_FLAGS_EEE (1 << 13)
+#define ELINK_FLAGS_TEMPERATURE (1 << 14)
+#define ELINK_FLAGS_MDC_MDIO_WA_G (1 << 15)
/* preemphasis values for the rx side */
uint16_t rx_preemphasis[4];
@@ -247,20 +286,22 @@ struct elink_phy {
uint32_t mdio_ctrl;
uint32_t supported;
-#define ELINK_SUPPORTED_10baseT_Half (1<<0)
-#define ELINK_SUPPORTED_10baseT_Full (1<<1)
-#define ELINK_SUPPORTED_100baseT_Half (1<<2)
-#define ELINK_SUPPORTED_100baseT_Full (1<<3)
-#define ELINK_SUPPORTED_1000baseT_Full (1<<4)
-#define ELINK_SUPPORTED_2500baseX_Full (1<<5)
-#define ELINK_SUPPORTED_10000baseT_Full (1<<6)
-#define ELINK_SUPPORTED_TP (1<<7)
-#define ELINK_SUPPORTED_FIBRE (1<<8)
-#define ELINK_SUPPORTED_Autoneg (1<<9)
-#define ELINK_SUPPORTED_Pause (1<<10)
-#define ELINK_SUPPORTED_Asym_Pause (1<<11)
-#define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21)
-#define ELINK_SUPPORTED_20000baseKR2_Full (1<<22)
+#define ELINK_SUPPORTED_10baseT_Half (1 << 0)
+#define ELINK_SUPPORTED_10baseT_Full (1 << 1)
+#define ELINK_SUPPORTED_100baseT_Half (1 << 2)
+#define ELINK_SUPPORTED_100baseT_Full (1 << 3)
+#define ELINK_SUPPORTED_1000baseT_Full (1 << 4)
+#define ELINK_SUPPORTED_2500baseX_Full (1 << 5)
+#define ELINK_SUPPORTED_10000baseT_Full (1 << 6)
+#define ELINK_SUPPORTED_TP (1 << 7)
+#define ELINK_SUPPORTED_FIBRE (1 << 8)
+#define ELINK_SUPPORTED_Autoneg (1 << 9)
+#define ELINK_SUPPORTED_Pause (1 << 10)
+#define ELINK_SUPPORTED_Asym_Pause (1 << 11)
+#define ELINK_SUPPORTED_1000baseKX_Full (1 << 17)
+#define ELINK_SUPPORTED_10000baseKR_Full (1 << 19)
+#define ELINK_SUPPORTED_20000baseMLD2_Full (1 << 21)
+#define ELINK_SUPPORTED_20000baseKR2_Full (1 << 22)
uint32_t media_type;
#define ELINK_ETH_PHY_UNSPECIFIED 0x0
@@ -353,17 +394,22 @@ struct elink_params {
/* features */
uint32_t feature_config_flags;
-#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
-#define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1)
-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
-#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
-#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
-#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12)
-#define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13)
-#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
+#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1 << 0)
+#define ELINK_FEATURE_CONFIG_PFC_ENABLED (1 << 1)
+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1 << 2)
+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1 << 3)
+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1 << 4)
+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1 << 5)
+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1 << 6)
+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1 << 7)
+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1 << 8)
+#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1 << 9)
+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1 << 10)
+#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1 << 11)
+#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1 << 12)
+#define ELINK_FEATURE_CONFIG_MT_SUPPORT (1 << 13)
+#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1 << 14)
+#define ELINK_FEATURE_CONFIG_DISABLE_PD (1 << 15)
/* Will be populated during common init */
struct elink_phy phy[ELINK_MAX_PHYS];
@@ -391,10 +437,10 @@ struct elink_params {
#define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
#define ELINK_EEE_MODE_NVRAM_MASK (0x3)
#define ELINK_EEE_MODE_TIMER_MASK (0xfffff)
-#define ELINK_EEE_MODE_OUTPUT_TIME (1<<28)
-#define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29)
-#define ELINK_EEE_MODE_ENABLE_LPI (1<<30)
-#define ELINK_EEE_MODE_ADV_LPI (1<<31)
+#define ELINK_EEE_MODE_OUTPUT_TIME (1 << 28)
+#define ELINK_EEE_MODE_OVERRIDE_NVRAM (1 << 29)
+#define ELINK_EEE_MODE_ENABLE_LPI (1 << 30)
+#define ELINK_EEE_MODE_ADV_LPI (1 << 31)
uint16_t hw_led_mode; /* part of the hw_config read from the shmem */
uint32_t multi_phy_config;
@@ -404,20 +450,23 @@ struct elink_params {
uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when
req_flow_ctrl is set to AUTO */
uint16_t link_flags;
-#define ELINK_LINK_FLAGS_INT_DISABLED (1<<0)
-#define ELINK_PHY_INITIALIZED (1<<1)
+#define ELINK_LINK_FLAGS_INT_DISABLED (1 << 0)
+#define ELINK_PHY_INITIALIZED (1 << 1)
uint32_t lfa_base;
+
+ /* The same definitions as the shmem2 parameter */
+ uint32_t link_attr_sync;
};
/* Output parameters */
struct elink_vars {
uint8_t phy_flags;
-#define PHY_XGXS_FLAG (1<<0)
-#define PHY_SGMII_FLAG (1<<1)
-#define PHY_PHYSICAL_LINK_FLAG (1<<2)
-#define PHY_HALF_OPEN_CONN_FLAG (1<<3)
-#define PHY_OVER_CURRENT_FLAG (1<<4)
-#define PHY_SFP_TX_FAULT_FLAG (1<<5)
+#define PHY_XGXS_FLAG (1 << 0)
+#define PHY_SGMII_FLAG (1 << 1)
+#define PHY_PHYSICAL_LINK_FLAG (1 << 2)
+#define PHY_HALF_OPEN_CONN_FLAG (1 << 3)
+#define PHY_OVER_CURRENT_FLAG (1 << 4)
+#define PHY_SFP_TX_FAULT_FLAG (1 << 5)
uint8_t mac_type;
#define ELINK_MAC_TYPE_NONE 0
@@ -448,8 +497,7 @@ struct elink_vars {
uint8_t rx_tx_asic_rst;
uint8_t turn_to_run_wc_rt;
uint16_t rsrv2;
- /* The same definitions as the shmem2 parameter */
- uint32_t link_attr_sync;
+
};
/***********************************************************/
@@ -460,14 +508,32 @@ struct elink_vars {
/* Reset the link. Should be called when driver or interface goes down
Before calling phy firmware upgrade, the reset_ext_phy should be set
to 0 */
+elink_status_t elink_link_reset(struct elink_params *params,
+ struct elink_vars *vars,
+ uint8_t reset_ext_phy);
elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
/* elink_link_update should be called upon link interrupt */
elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
+/* use the following phy functions to read/write from external_phy
+ * In order to use it to read/write internal phy registers, use
+ * ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
+ * the register
+ */
+elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
+ uint8_t devad, uint16_t reg, uint16_t *ret_val);
+
+elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
+ uint8_t devad, uint16_t reg, uint16_t val);
+
/* Reads the link_status from the shmem,
and update the link vars accordingly */
void elink_link_status_update(struct elink_params *input,
struct elink_vars *output);
+/* returns string representing the fw_version of the external phy */
+elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params,
+ uint8_t *version,
+ uint16_t len);
/* Set/Unset the led
Basically, the CLC takes care of the led for the link, but in case one needs
@@ -481,12 +547,34 @@ elink_status_t elink_set_led(struct elink_params *params,
#define ELINK_LED_MODE_FRONT_PANEL_OFF 3
/* elink_handle_module_detect_int should be called upon module detection
- interrupt */
+ * interrupt
+ */
void elink_handle_module_detect_int(struct elink_params *params);
+/* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up,
+ * otherwise link is down
+ */
+elink_status_t elink_test_link(struct elink_params *params,
+ struct elink_vars *vars,
+ uint8_t is_serdes);
+
+
/* One-time initialization for external phy after power up */
elink_status_t elink_common_init_phy(struct bnx2x_softc *sc, uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);
+ uint32_t shmem2_base_path[], uint32_t chip_id,
+ uint8_t one_port_enabled);
+
+/* Reset the external PHY using GPIO */
+void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port);
+
+/* Reset the external of SFX7101 */
+void elink_sfx7101_sp_sw_reset(struct bnx2x_softc *sc, struct elink_phy *phy);
+
+/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
+elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
+ struct elink_params *params, uint8_t dev_addr,
+ uint16_t addr, uint16_t byte_cnt,
+ uint8_t *o_buf);
void elink_hw_reset_phy(struct elink_params *params);
@@ -569,12 +657,42 @@ elink_status_t elink_update_pfc(struct elink_params *params,
struct elink_vars *vars,
struct elink_nig_brb_pfc_port_params *pfc_params);
+
+/* Used to configure the ETS to disable */
+elink_status_t elink_ets_disabled(struct elink_params *params,
+ struct elink_vars *vars);
+
+/* Used to configure the ETS to BW limited */
+void elink_ets_bw_limit(const struct elink_params *params,
+ const uint32_t cos0_bw,
+ const uint32_t cos1_bw);
+
+/* Used to configure the ETS to strict */
+elink_status_t elink_ets_strict(const struct elink_params *params,
+ const uint8_t strict_cos);
+
+
+/* Configure the COS to ETS according to BW and SP settings.*/
+elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
+ const struct elink_vars *vars,
+ struct elink_ets_params *ets_params);
+/* Read pfc statistic*/
+void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
+ uint32_t pfc_frames_sent[2],
+ uint32_t pfc_frames_received[2]);
void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
uint8_t port);
+/* elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
+ * struct elink_params *params);
+ */
void elink_period_func(struct elink_params *params, struct elink_vars *vars);
+/*elink_status_t elink_check_half_open_conn(struct elink_params *params,
+ * struct elink_vars *vars, uint8_t notify);
+ */
+
void elink_enable_pmd_tx(struct elink_params *params);
--
1.7.10.3
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [dpdk-dev] [PATCH 2/5] net/bnx2x: update link/PHY management
2018-09-19 21:59 ` [dpdk-dev] [PATCH 2/5] net/bnx2x: update link/PHY management Mody, Rasesh
@ 2018-09-21 18:10 ` Ferruh Yigit
2018-09-22 1:37 ` Mody, Rasesh
0 siblings, 1 reply; 13+ messages in thread
From: Ferruh Yigit @ 2018-09-21 18:10 UTC (permalink / raw)
To: Mody, Rasesh, dev; +Cc: Dept-Eng DPDK Dev
On 9/19/2018 10:59 PM, Mody, Rasesh wrote:
> This patch has changes to update the link/PHY management (elink) code
> to the latest.
>
> Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
> ---
> drivers/net/bnx2x/bnx2x.h | 3 +
> drivers/net/bnx2x/ecore_hsi.h | 20 +-
> drivers/net/bnx2x/elink.c | 7951 ++++++++++++++++++++++++++---------------
> drivers/net/bnx2x/elink.h | 234 +-
> 4 files changed, 5231 insertions(+), 2977 deletions(-)
<...>
>
> -static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
> - struct elink_params *params,
> - struct elink_vars *vars)
> +static void elink_xgxs_config_init(struct elink_phy *phy,
> + struct elink_params *params,
> + struct elink_vars *vars)
Getting many build error because of these kind of changes.
.../drivers/net/bnx2x/elink.c:12555:17: error: cast between incompatible
function types from ‘void (*)(struct elink_phy *, struct elink_params *, struct
elink_vars *)’ to ‘uint8_t (*)(struct elink_phy *, struct elink_params *, struct
elink_vars *)’ {aka ‘unsigned char (*)(struct elink_phy *,
struct elink_params *, struct elink_vars *)’} [-Werror=cast-function-type]
.config_init = (config_init_t)elink_xgxs_config_init,
^
perhaps "struct elink_phy" also needs to be updated?
Overall build fail log is long, I am not sharing here, I guess if you can able
to reproduce one, you will be able to reproduce all.
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [dpdk-dev] [PATCH 2/5] net/bnx2x: update link/PHY management
2018-09-21 18:10 ` Ferruh Yigit
@ 2018-09-22 1:37 ` Mody, Rasesh
0 siblings, 0 replies; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-22 1:37 UTC (permalink / raw)
To: Ferruh Yigit, dev; +Cc: Dept-Eng DPDK Dev
>From: Ferruh Yigit <ferruh.yigit@intel.com>
>Sent: Friday, September 21, 2018 11:10 AM
>
>On 9/19/2018 10:59 PM, Mody, Rasesh wrote:
>> This patch has changes to update the link/PHY management (elink) code
>> to the latest.
>>
>> Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
>> ---
>> drivers/net/bnx2x/bnx2x.h | 3 +
>> drivers/net/bnx2x/ecore_hsi.h | 20 +-
>> drivers/net/bnx2x/elink.c | 7951 ++++++++++++++++++++++++++--------
>-------
>> drivers/net/bnx2x/elink.h | 234 +-
>> 4 files changed, 5231 insertions(+), 2977 deletions(-)
>
><...>
>
>>
>> -static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
>> - struct elink_params *params,
>> - struct elink_vars *vars)
>> +static void elink_xgxs_config_init(struct elink_phy *phy,
>> + struct elink_params *params,
>> + struct elink_vars *vars)
>
>
>Getting many build error because of these kind of changes.
>
>.../drivers/net/bnx2x/elink.c:12555:17: error: cast between incompatible
>function types from ‘void (*)(struct elink_phy *, struct elink_params *, struct
>elink_vars *)’ to ‘uint8_t (*)(struct elink_phy *, struct elink_params *, struct
>elink_vars *)’ {aka ‘unsigned char (*)(struct elink_phy *, struct elink_params
>*, struct elink_vars *)’} [-Werror=cast-function-type]
>
>
>
> .config_init = (config_init_t)elink_xgxs_config_init,
>
>
>
> ^
>
>perhaps "struct elink_phy" also needs to be updated?
>
>Overall build fail log is long, I am not sharing here, I guess if you can able to
>reproduce one, you will be able to reproduce all.
We didn’t see build errors with an older gcc. We'll reproduce with latest gcc and address the build errors.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [dpdk-dev] [PATCH 3/5] net/bnx2x: fix to disable further interrupts
2018-09-19 21:59 [dpdk-dev] [PATCH 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
2018-09-19 21:59 ` [dpdk-dev] [PATCH 2/5] net/bnx2x: update link/PHY management Mody, Rasesh
@ 2018-09-19 21:59 ` Mody, Rasesh
2018-09-19 21:59 ` [dpdk-dev] [PATCH 4/5] net/bnx2x: fix call to link handling periodic function Mody, Rasesh
` (6 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-19 21:59 UTC (permalink / raw)
To: dev; +Cc: Mody, Rasesh, ferruh.yigit, Dept-Eng DPDK Dev, stable
Fix to disable further fastpath/slowpath interrupts. These will be
enabled again by their respective handlers
Fixes: 540a211084a7 ("bnx2x: driver core")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 93f8586..0225bea 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -4553,12 +4553,18 @@ int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
fp = &sc->fp[i];
mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
if (status & mask) {
+ /* acknowledge and disable further fastpath interrupts */
+ bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
+ 0, IGU_INT_DISABLE, 0);
bnx2x_handle_fp_tq(fp, scan_fp);
status &= ~mask;
}
}
if (unlikely(status & 0x1)) {
+ /* acknowledge and disable further slowpath interrupts */
+ bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
+ 0, IGU_INT_DISABLE, 0);
rc = bnx2x_handle_sp_tq(sc);
status &= ~0x1;
}
--
1.7.10.3
^ permalink raw reply [flat|nested] 13+ messages in thread* [dpdk-dev] [PATCH 4/5] net/bnx2x: fix call to link handling periodic function
2018-09-19 21:59 [dpdk-dev] [PATCH 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
2018-09-19 21:59 ` [dpdk-dev] [PATCH 2/5] net/bnx2x: update link/PHY management Mody, Rasesh
2018-09-19 21:59 ` [dpdk-dev] [PATCH 3/5] net/bnx2x: fix to disable further interrupts Mody, Rasesh
@ 2018-09-19 21:59 ` Mody, Rasesh
2018-09-19 21:59 ` [dpdk-dev] [PATCH 5/5] net/bnx2x: fix to add phy lock Mody, Rasesh
` (5 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-19 21:59 UTC (permalink / raw)
To: dev; +Cc: Mody, Rasesh, ferruh.yigit, Dept-Eng DPDK Dev, stable
If link handling periodic function is allowed to be called in interrupt
context, the periodic function can get called too frequently and exhaust
the retry credits to check link status.
This change makes sure link handling periodic function is not called in
interrupt context.
Fixes: 540a211084a7 ("bnx2x: driver core")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x_ethdev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/bnx2x/bnx2x_ethdev.c b/drivers/net/bnx2x/bnx2x_ethdev.c
index ae2e60a..0057843 100644
--- a/drivers/net/bnx2x/bnx2x_ethdev.c
+++ b/drivers/net/bnx2x/bnx2x_ethdev.c
@@ -131,7 +131,9 @@ struct rte_bnx2x_xstats_name_off {
PMD_DEBUG_PERIODIC_LOG(INFO, sc, "Interrupt handled");
+ atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
bnx2x_interrupt_action(dev);
+ atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
rte_intr_enable(&sc->pci_dev->intr_handle);
}
--
1.7.10.3
^ permalink raw reply [flat|nested] 13+ messages in thread* [dpdk-dev] [PATCH 5/5] net/bnx2x: fix to add phy lock
2018-09-19 21:59 [dpdk-dev] [PATCH 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
` (2 preceding siblings ...)
2018-09-19 21:59 ` [dpdk-dev] [PATCH 4/5] net/bnx2x: fix call to link handling periodic function Mody, Rasesh
@ 2018-09-19 21:59 ` Mody, Rasesh
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
` (4 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-19 21:59 UTC (permalink / raw)
To: dev; +Cc: Mody, Rasesh, ferruh.yigit, Dept-Eng DPDK Dev, stable
This patch adds phy_lock, acquire/release the lock when performing
PHY transactions. Without this fix driver can run into synchronization
issues with management FW when modifying PHY settings.
Fixes: 540a211084a7 ("bnx2x: driver core")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x.c | 59 ++++++++++++++++++++++++++++++++++++-----
drivers/net/bnx2x/bnx2x.h | 7 +++++
drivers/net/bnx2x/ecore_reg.h | 1 +
3 files changed, 60 insertions(+), 7 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 0225bea..2797593 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -112,6 +112,7 @@ static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod);
+static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
static void bnx2x_link_report(struct bnx2x_softc *sc);
void bnx2x_link_status_update(struct bnx2x_softc *sc);
static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
@@ -198,7 +199,8 @@ static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
uint32_t hw_lock_control_reg;
int cnt;
- PMD_INIT_FUNC_TRACE(sc);
+ if (resource)
+ PMD_INIT_FUNC_TRACE(sc);
/* validate the resource is within range */
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
@@ -234,7 +236,8 @@ static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
DELAY(5000);
}
- PMD_DRV_LOG(NOTICE, sc, "Resource lock timeout!");
+ PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
+ resource, resource_bit);
return -1;
}
@@ -245,13 +248,14 @@ static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
int func = SC_FUNC(sc);
uint32_t hw_lock_control_reg;
- PMD_INIT_FUNC_TRACE(sc);
+ if (resource)
+ PMD_INIT_FUNC_TRACE(sc);
/* validate the resource is within range */
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
PMD_DRV_LOG(NOTICE, sc,
- "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
- resource);
+ "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
+ " resource_bit 0x%x", resource, resource_bit);
return -1;
}
@@ -275,6 +279,18 @@ static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
return 0;
}
+static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
+{
+ BNX2X_PHY_LOCK(sc);
+ bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
+}
+
+static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
+{
+ bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
+ BNX2X_PHY_UNLOCK(sc);
+}
+
/* copy command into DMAE command memory and set DMAE command Go */
void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
{
@@ -2903,7 +2919,7 @@ static void bnx2x_link_attn(struct bnx2x_softc *sc)
}
}
- bnx2x_link_report(sc);
+ bnx2x_link_report_locked(sc);
if (IS_MF(sc)) {
bnx2x_link_sync_notify(sc);
@@ -2942,6 +2958,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
if (asserted & ATTN_HARD_WIRED_MASK) {
if (asserted & ATTN_NIG_FOR_FUNC) {
+ bnx2x_acquire_phy_lock(sc);
/* save nig interrupt mask */
nig_mask = REG_RD(sc, nig_int_mask_addr);
@@ -3039,6 +3056,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
REG_WR(sc, nig_int_mask_addr, nig_mask);
+ bnx2x_release_phy_lock(sc);
}
}
@@ -3838,8 +3856,10 @@ static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
if (sc->link_vars.periodic_flags &
ELINK_PERIODIC_FLAGS_LINK_EVENT) {
/* sync with link */
+ bnx2x_acquire_phy_lock(sc);
sc->link_vars.periodic_flags &=
~ELINK_PERIODIC_FLAGS_LINK_EVENT;
+ bnx2x_release_phy_lock(sc);
if (IS_MF(sc)) {
bnx2x_link_sync_notify(sc);
}
@@ -4029,7 +4049,9 @@ static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
}
if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
+ bnx2x_acquire_phy_lock(sc);
elink_handle_module_detect_int(&sc->link_params);
+ bnx2x_release_phy_lock(sc);
}
if (attn & HW_INTERRUT_ASSERT_SET_0) {
@@ -6867,7 +6889,7 @@ static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
}
/* report link status to OS, should be called under phy_lock */
-static void bnx2x_link_report(struct bnx2x_softc *sc)
+static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
{
struct bnx2x_link_report_data cur_data;
@@ -6888,8 +6910,13 @@ static void bnx2x_link_report(struct bnx2x_softc *sc)
return;
}
+ PMD_DRV_LOG(INFO, sc, "Change in link status : cur_data = %lx, last_reported_link = %lx\n",
+ cur_data.link_report_flags,
+ sc->last_reported_link.link_report_flags);
+
sc->link_cnt++;
+ PMD_DRV_LOG(INFO, sc, "link status change count = %x\n", sc->link_cnt);
/* report new link params and remember the state for the next time */
rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
@@ -6941,6 +6968,14 @@ static void bnx2x_link_report(struct bnx2x_softc *sc)
}
}
+static void
+bnx2x_link_report(struct bnx2x_softc *sc)
+{
+ bnx2x_acquire_phy_lock(sc);
+ bnx2x_link_report_locked(sc);
+ bnx2x_release_phy_lock(sc);
+}
+
void bnx2x_link_status_update(struct bnx2x_softc *sc)
{
if (sc->state != BNX2X_STATE_OPEN) {
@@ -7019,6 +7054,8 @@ static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
bnx2x_set_requested_fc(sc);
+ bnx2x_acquire_phy_lock(sc);
+
if (load_mode == LOAD_DIAG) {
lp->loopback_mode = ELINK_LOOPBACK_XGXS;
/* Prefer doing PHY loopback at 10G speed, if possible */
@@ -7038,6 +7075,8 @@ static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
rc = elink_phy_init(&sc->link_params, &sc->link_vars);
+ bnx2x_release_phy_lock(sc);
+
bnx2x_calc_fc_adv(sc);
if (sc->link_vars.link_up) {
@@ -7088,7 +7127,9 @@ void bnx2x_periodic_callout(struct bnx2x_softc *sc)
*/
mb();
if (sc->port.pmf) {
+ bnx2x_acquire_phy_lock(sc);
elink_period_func(&sc->link_params, &sc->link_vars);
+ bnx2x_release_phy_lock(sc);
}
}
#ifdef BNX2X_PULSE
@@ -9840,8 +9881,10 @@ static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
}
+ bnx2x_acquire_phy_lock(sc);
elink_common_init_phy(sc, shmem_base, shmem2_base,
sc->devinfo.chip_id, 0);
+ bnx2x_release_phy_lock(sc);
}
static void bnx2x_pf_disable(struct bnx2x_softc *sc)
@@ -11320,7 +11363,9 @@ static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
static void bnx2x_link_reset(struct bnx2x_softc *sc)
{
if (!BNX2X_NOMCP(sc)) {
+ bnx2x_acquire_phy_lock(sc);
elink_lfa_reset(&sc->link_params, &sc->link_vars);
+ bnx2x_release_phy_lock(sc);
} else {
if (!CHIP_REV_IS_SLOW(sc)) {
PMD_DRV_LOG(WARNING, sc,
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 1cc5a6b..7478072 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -725,6 +725,13 @@ struct bnx2x_port {
uint32_t phy_addr;
+ /* Used to synchronize phy accesses. */
+ rte_spinlock_t phy_mtx;
+ char phy_mtx_name[32];
+
+#define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx)
+#define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx)
+
/*
* MCP scratchpad address for port specific statistics.
* The device is responsible for writing statistcss
diff --git a/drivers/net/bnx2x/ecore_reg.h b/drivers/net/bnx2x/ecore_reg.h
index ae8a93b..d69e857 100644
--- a/drivers/net/bnx2x/ecore_reg.h
+++ b/drivers/net/bnx2x/ecore_reg.h
@@ -1967,6 +1967,7 @@
#define HW_LOCK_MAX_RESOURCE_VALUE 31
#define HW_LOCK_RESOURCE_DRV_FLAGS 10
#define HW_LOCK_RESOURCE_GPIO 1
+#define HW_LOCK_RESOURCE_MDIO 0
#define HW_LOCK_RESOURCE_NVRAM 12
#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
--
1.7.10.3
^ permalink raw reply [flat|nested] 13+ messages in thread* [dpdk-dev] [PATCH v2 1/5] net/bnx2x: fix logging to include dev name
2018-09-19 21:59 [dpdk-dev] [PATCH 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
` (3 preceding siblings ...)
2018-09-19 21:59 ` [dpdk-dev] [PATCH 5/5] net/bnx2x: fix to add phy lock Mody, Rasesh
@ 2018-09-29 5:42 ` Mody, Rasesh
2018-10-02 12:40 ` Ferruh Yigit
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 2/5] net/bnx2x: update link/PHY management Mody, Rasesh
` (3 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-29 5:42 UTC (permalink / raw)
To: dev; +Cc: Mody, Rasesh, ferruh.yigit, Dept-Eng DPDK Dev, stable
Fix PMD logging scheme to include device name in the messages printed.
Fixes: 540a211084a7 ("bnx2x: driver core")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x.c | 754 ++++++++++++++++++-----------------
drivers/net/bnx2x/bnx2x.h | 32 +-
drivers/net/bnx2x/bnx2x_ethdev.c | 90 +++--
drivers/net/bnx2x/bnx2x_logs.h | 25 +-
drivers/net/bnx2x/bnx2x_rxtx.c | 15 +-
drivers/net/bnx2x/bnx2x_stats.c | 35 +-
drivers/net/bnx2x/bnx2x_vfpf.c | 50 +--
drivers/net/bnx2x/ecore_init.h | 6 +-
drivers/net/bnx2x/ecore_init_ops.h | 8 +-
drivers/net/bnx2x/ecore_sp.c | 258 ++++++------
drivers/net/bnx2x/ecore_sp.h | 4 +-
drivers/net/bnx2x/elink.c | 761 ++++++++++++++++++------------------
12 files changed, 1052 insertions(+), 986 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 4904eaf..93f8586 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -178,13 +178,14 @@ int bnx2x_cmpxchg(volatile int *addr, int old, int new)
SOCKET_ID_ANY,
RTE_MEMZONE_IOVA_CONTIG, align);
if (z == NULL) {
- PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
+ PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
return -ENOMEM;
}
dma->paddr = (uint64_t) z->iova;
dma->vaddr = z->addr;
- PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
+ PMD_DRV_LOG(DEBUG, sc,
+ "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
return 0;
}
@@ -197,11 +198,11 @@ static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
uint32_t hw_lock_control_reg;
int cnt;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
/* validate the resource is within range */
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
resource);
return -1;
@@ -217,7 +218,7 @@ static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
/* validate the resource is not already taken */
lock_status = REG_RD(sc, hw_lock_control_reg);
if (lock_status & resource_bit) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"resource in use (status 0x%x bit 0x%x)",
lock_status, resource_bit);
return -1;
@@ -233,7 +234,7 @@ static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
DELAY(5000);
}
- PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
+ PMD_DRV_LOG(NOTICE, sc, "Resource lock timeout!");
return -1;
}
@@ -244,11 +245,11 @@ static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
int func = SC_FUNC(sc);
uint32_t hw_lock_control_reg;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
/* validate the resource is within range */
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
resource);
return -1;
@@ -264,7 +265,7 @@ static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
/* validate the resource is currently taken */
lock_status = REG_RD(sc, hw_lock_control_reg);
if (!(lock_status & resource_bit)) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"resource not in use (status 0x%x bit 0x%x)",
lock_status, resource_bit);
return -1;
@@ -366,7 +367,7 @@ uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
if (!timeout ||
(sc->recovery_state != BNX2X_RECOVERY_DONE &&
sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
- PMD_DRV_LOG(INFO, "DMAE timeout!");
+ PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
return DMAE_TIMEOUT;
}
@@ -375,7 +376,7 @@ uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
}
if (*wb_comp & DMAE_PCI_ERR_FLAG) {
- PMD_DRV_LOG(INFO, "DMAE PCI error!");
+ PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
return DMAE_PCI_ERROR;
}
@@ -534,7 +535,7 @@ void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
__rte_unused const elink_log_id_t elink_log_id, ...)
{
- PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
+ PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
}
static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
@@ -543,7 +544,7 @@ static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
/* Only 2 SPIOs are configurable */
if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
- PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
+ PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
return -1;
}
@@ -593,7 +594,7 @@ static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
uint32_t gpio_reg;
if (gpio_num > MISC_REGISTERS_GPIO_3) {
- PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
+ PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
return -1;
}
@@ -618,7 +619,7 @@ static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
uint32_t gpio_reg;
if (gpio_num > MISC_REGISTERS_GPIO_3) {
- PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
+ PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
return -1;
}
@@ -687,7 +688,8 @@ static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
break;
default:
- PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
+ PMD_DRV_LOG(NOTICE, sc,
+ "Invalid GPIO mode assignment %d", mode);
bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
return -1;
}
@@ -713,7 +715,7 @@ static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
uint32_t gpio_reg;
if (gpio_num > MISC_REGISTERS_GPIO_3) {
- PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
+ PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
return -1;
}
@@ -790,7 +792,7 @@ void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"wrote command 0x%08x to FW MB param 0x%08x",
(command | seq), param);
@@ -805,7 +807,7 @@ void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
rc &= FW_MSG_CODE_MASK;
} else {
/* Ruh-roh! */
- PMD_DRV_LOG(NOTICE, "FW failed to respond!");
+ PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
rc = 0;
}
@@ -1023,12 +1025,12 @@ static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
if (common) {
if (!atomic_load_acq_long(&sc->eq_spq_left)) {
- PMD_DRV_LOG(INFO, "EQ ring is full!");
+ PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
return -1;
}
} else {
if (!atomic_load_acq_long(&sc->cq_spq_left)) {
- PMD_DRV_LOG(INFO, "SPQ ring is full!");
+ PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
return -1;
}
}
@@ -1061,7 +1063,7 @@ static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
atomic_subtract_acq_long(&sc->cq_spq_left, 1);
}
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
"data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
sc->spq_prod_idx,
@@ -1132,44 +1134,45 @@ static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"fp=%d cid=%d got ramrod #%d state is %x type is %d",
fp->index, cid, command, sc->state,
rr_cqe->ramrod_cqe.ramrod_type);
switch (command) {
case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
- PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
+ PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
drv_cmd = ECORE_Q_CMD_UPDATE;
break;
case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
- PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
+ PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
drv_cmd = ECORE_Q_CMD_SETUP;
break;
case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
- PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
+ PMD_DRV_LOG(DEBUG, sc,
+ "got MULTI[%d] tx-only setup ramrod", cid);
drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
break;
case (RAMROD_CMD_ID_ETH_HALT):
- PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
+ PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
drv_cmd = ECORE_Q_CMD_HALT;
break;
case (RAMROD_CMD_ID_ETH_TERMINATE):
- PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
+ PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
drv_cmd = ECORE_Q_CMD_TERMINATE;
break;
case (RAMROD_CMD_ID_ETH_EMPTY):
- PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
+ PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
drv_cmd = ECORE_Q_CMD_EMPTY;
break;
default:
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"ERROR: unexpected MC reply (%d)"
"on fp[%d]", command, fp->index);
return;
@@ -1191,7 +1194,7 @@ static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
atomic_add_acq_long(&sc->cq_spq_left, 1);
- PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
+ PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
atomic_load_acq_long(&sc->cq_spq_left));
}
@@ -1387,7 +1390,7 @@ static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
if (rc < 0)
- PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
+ PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
return rc;
}
@@ -1538,13 +1541,13 @@ static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
int path = SC_PATH(sc);
int port = SC_PORT(sc);
- PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
+ PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
path, load_count[path][0], load_count[path][1],
load_count[path][2]);
load_count[path][0]++;
load_count[path][1 + port]++;
- PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
+ PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
path, load_count[path][0], load_count[path][1],
load_count[path][2]);
if (load_count[path][0] == 1)
@@ -1561,12 +1564,12 @@ static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
int port = SC_PORT(sc);
int path = SC_PATH(sc);
- PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
+ PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
path, load_count[path][0], load_count[path][1],
load_count[path][2]);
load_count[path][0]--;
load_count[path][1 + port]--;
- PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
+ PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
path, load_count[path][0], load_count[path][1],
load_count[path][2]);
if (load_count[path][0] == 0) {
@@ -1646,7 +1649,7 @@ static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
*/
struct ecore_func_state_params func_params = { NULL };
- PMD_DRV_LOG(NOTICE, "Unexpected function state! "
+ PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
"Forcing STARTED-->TX_STOPPED-->STARTED");
func_params.f_obj = &sc->func_obj;
@@ -1670,7 +1673,7 @@ static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
struct ecore_queue_state_params q_params = { NULL };
int rc;
- PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
+ PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
/* We want to wait for completion in this context */
@@ -1721,7 +1724,7 @@ static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
tmp = atomic_load_acq_long(&sc->sp_state);
if (tmp & mask) {
- PMD_DRV_LOG(INFO, "Filtering completion timed out: "
+ PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
"sp_state 0x%lx, mask 0x%lx", tmp, mask);
return FALSE;
}
@@ -1747,7 +1750,7 @@ static int bnx2x_func_stop(struct bnx2x_softc *sc)
*/
rc = ecore_func_state_change(sc, &func_params);
if (rc) {
- PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
+ PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
"Running a dry transaction");
bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
return ecore_func_state_change(sc, &func_params);
@@ -1796,14 +1799,16 @@ static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
FALSE);
if (rc < 0) {
- PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
+ PMD_DRV_LOG(NOTICE, sc,
+ "Failed to delete all ETH MACs (%d)", rc);
}
/* Clean up UC list */
rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
TRUE);
if (rc < 0) {
- PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
+ PMD_DRV_LOG(NOTICE, sc,
+ "Failed to delete UC MACs list (%d)", rc);
}
/* Disable LLH */
@@ -1826,7 +1831,7 @@ static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
rparam.mcast_obj = &sc->mcast_obj;
rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
if (rc < 0) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"Failed to send DEL MCAST command (%d)", rc);
}
@@ -1843,7 +1848,7 @@ static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
*/
rc = bnx2x_func_wait_started(sc);
if (rc) {
- PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
+ PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
}
/*
@@ -1861,14 +1866,14 @@ static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
* very wrong has happen.
*/
if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
- PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
+ PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
}
unload_error:
rc = bnx2x_func_stop(sc);
if (rc) {
- PMD_DRV_LOG(NOTICE, "Function stop failed!");
+ PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
}
/* disable HW interrupts */
@@ -1877,7 +1882,7 @@ static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
/* Reset the chip */
rc = bnx2x_reset_hw(sc, reset_code);
if (rc) {
- PMD_DRV_LOG(NOTICE, "Hardware reset failed");
+ PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
}
/* Report UNLOAD_DONE to MCP */
@@ -1888,7 +1893,7 @@ static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
{
uint32_t val;
- PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
+ PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
@@ -1919,7 +1924,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
&ramrod_flags);
if (rc != 0) {
- PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
+ PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
}
/* Cleanup UC list */
@@ -1927,7 +1932,8 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
if (rc != 0) {
- PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
+ PMD_DRV_LOG(NOTICE, sc,
+ "Failed to clean UC list MACs (%d)", rc);
}
/* Now clean mcast object... */
@@ -1938,7 +1944,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
/* Add a DEL command... */
rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
if (rc < 0) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"Failed to send DEL MCAST command (%d)", rc);
}
@@ -1947,7 +1953,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
while (rc != 0) {
if (rc < 0) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"Failed to clean MCAST object (%d)", rc);
return;
}
@@ -1964,7 +1970,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
uint8_t global = FALSE;
uint32_t val;
- PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
+ PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
/* mark driver as unloaded in shmem2 */
if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
@@ -1988,7 +1994,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
bnx2x_release_leader_lock(sc);
mb();
- PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
+ PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
return -1;
}
@@ -2093,7 +2099,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
bnx2x_disable_close_the_gate(sc);
}
- PMD_DRV_LOG(DEBUG, "Ended NIC unload");
+ PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
return 0;
}
@@ -2241,7 +2247,7 @@ static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
struct ecore_ilt *ilt = sc->ilt;
uint16_t line = 0;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
@@ -2395,7 +2401,7 @@ static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
bnx2x_alloc_ilt_lines_mem(sc);
if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
- PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
+ PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
bnx2x_free_mem(sc);
return -1;
}
@@ -2598,7 +2604,7 @@ static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
@@ -2651,14 +2657,14 @@ static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
/* send load requrest to mcp and analyze response */
static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
{
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
/* init fw_seq */
sc->fw_seq =
(SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
DRV_MSG_SEQ_NUMBER_MASK);
- PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
+ PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
#ifdef BNX2X_PULSE
/* get the current FW pulse sequence */
@@ -2677,13 +2683,13 @@ static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
/* if the MCP fails to respond we must abort */
if (!(*load_code)) {
- PMD_DRV_LOG(NOTICE, "MCP response failure!");
+ PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
return -1;
}
/* if MCP refused then must abort */
if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
- PMD_DRV_LOG(NOTICE, "MCP refused load request");
+ PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
return -1;
}
@@ -2710,12 +2716,12 @@ static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code
/* read loaded FW from chip */
loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
- PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
+ PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
loaded_fw, my_fw);
/* abort nic load if version mismatch */
if (my_fw != loaded_fw) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"FW 0x%08x already loaded (mine is 0x%08x)",
loaded_fw, my_fw);
return -1;
@@ -2730,7 +2736,7 @@ static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
{
uint32_t ncsi_oem_data_addr;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
(load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
@@ -2745,7 +2751,7 @@ static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
sc->port.pmf = 0;
}
- PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
+ PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
@@ -2788,10 +2794,10 @@ static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
FUNC_MF_CFG_FUNC_DISABLED) {
- PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
+ PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
sc->flags |= BNX2X_MF_FUNC_DIS;
} else {
- PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
+ PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
sc->flags &= ~BNX2X_MF_FUNC_DIS;
}
}
@@ -2812,7 +2818,7 @@ static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
}
if (!(val & (1L << 31))) {
- PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
+ PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
return -1;
}
@@ -2840,7 +2846,7 @@ static void bnx2x_fan_failure(struct bnx2x_softc *sc)
ext_phy_config);
/* log the failure */
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"Fan Failure has caused the driver to shutdown "
"the card to prevent permanent damage. "
"Please contact OEM Support for assistance");
@@ -2918,7 +2924,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
uint32_t cnt;
if (sc->attn_state & asserted) {
- PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
+ PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
}
bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
@@ -2950,45 +2956,45 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
}
if (asserted & ATTN_SW_TIMER_4_FUNC) {
- PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
+ PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
}
if (asserted & GPIO_2_FUNC) {
- PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
+ PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
}
if (asserted & GPIO_3_FUNC) {
- PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
+ PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
}
if (asserted & GPIO_4_FUNC) {
- PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
+ PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
}
if (port == 0) {
if (asserted & ATTN_GENERAL_ATTN_1) {
- PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
+ PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
}
if (asserted & ATTN_GENERAL_ATTN_2) {
- PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
+ PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
}
if (asserted & ATTN_GENERAL_ATTN_3) {
- PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
+ PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
}
} else {
if (asserted & ATTN_GENERAL_ATTN_4) {
- PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
+ PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
}
if (asserted & ATTN_GENERAL_ATTN_5) {
- PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
+ PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
}
if (asserted & ATTN_GENERAL_ATTN_6) {
- PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
+ PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
}
}
@@ -3002,7 +3008,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
}
- PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
+ PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
asserted,
(sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
reg_addr);
@@ -3024,7 +3030,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
&& (++cnt < MAX_IGU_ATTN_ACK_TO));
if (!igu_acked) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Failed to verify IGU ack on time");
}
@@ -3040,7 +3046,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
__rte_unused const char *blk)
{
- PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
+ PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
}
static int
@@ -3348,7 +3354,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
(sig[2] & HW_PRTY_ASSERT_SET_2) ||
(sig[3] & HW_PRTY_ASSERT_SET_3) ||
(sig[4] & HW_PRTY_ASSERT_SET_4)) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Parity error: HW block parity attention:"
"[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
(uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
@@ -3358,7 +3364,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
(uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
if (print)
- PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
+ PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
par_num =
bnx2x_check_blocks_with_parity0(sc, sig[0] &
@@ -3382,7 +3388,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
par_num, print);
if (print)
- PMD_DRV_LOG(INFO, "");
+ PMD_DRV_LOG(INFO, sc, "");
return TRUE;
}
@@ -3414,64 +3420,64 @@ static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
- PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
+ PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
if (val &
PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
if (val &
PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
}
if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
- PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
+ PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
}
if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"ERROR: FATAL parity attention set4 0x%08x",
(uint32_t) (attn &
(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
@@ -3594,11 +3600,11 @@ static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
*/
if (sc->devinfo.
mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
- PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
+ PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
sc->flags |= BNX2X_MF_FUNC_DIS;
bnx2x_e1h_disable(sc);
} else {
- PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
+ PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
sc->flags &= ~BNX2X_MF_FUNC_DIS;
bnx2x_e1h_enable(sc);
}
@@ -3653,7 +3659,7 @@ static int bnx2x_mc_assert(struct bnx2x_softc *sc)
last_idx =
REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
if (last_idx)
- PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
+ PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
/* print the asserts */
for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
@@ -3675,7 +3681,7 @@ static int bnx2x_mc_assert(struct bnx2x_softc *sc)
12);
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
i, row3, row2, row1, row0);
rc++;
@@ -3688,7 +3694,7 @@ static int bnx2x_mc_assert(struct bnx2x_softc *sc)
last_idx =
REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
if (last_idx) {
- PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
+ PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
}
/* print the asserts */
@@ -3711,7 +3717,7 @@ static int bnx2x_mc_assert(struct bnx2x_softc *sc)
12);
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
i, row3, row2, row1, row0);
rc++;
@@ -3724,7 +3730,7 @@ static int bnx2x_mc_assert(struct bnx2x_softc *sc)
last_idx =
REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
if (last_idx) {
- PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
+ PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
}
/* print the asserts */
@@ -3747,7 +3753,7 @@ static int bnx2x_mc_assert(struct bnx2x_softc *sc)
12);
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
i, row3, row2, row1, row0);
rc++;
@@ -3760,7 +3766,7 @@ static int bnx2x_mc_assert(struct bnx2x_softc *sc)
last_idx =
REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
if (last_idx) {
- PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
+ PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
}
/* print the asserts */
@@ -3783,7 +3789,7 @@ static int bnx2x_mc_assert(struct bnx2x_softc *sc)
12);
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
i, row3, row2, row1, row0);
rc++;
@@ -3848,7 +3854,7 @@ static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
} else if (attn & BNX2X_MC_ASSERT_BITS) {
- PMD_DRV_LOG(ERR, "MC assert!");
+ PMD_DRV_LOG(ERR, sc, "MC assert!");
bnx2x_mc_assert(sc);
REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
@@ -3858,24 +3864,24 @@ static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
} else if (attn & BNX2X_MCP_ASSERT) {
- PMD_DRV_LOG(ERR, "MCP assert!");
+ PMD_DRV_LOG(ERR, sc, "MCP assert!");
REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
} else {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Unknown HW assert! (attn 0x%08x)", attn);
}
}
if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
- PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
+ PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
if (attn & BNX2X_GRC_TIMEOUT) {
val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
- PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
+ PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
}
if (attn & BNX2X_GRC_RSV) {
val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
- PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
+ PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
}
REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
}
@@ -3890,24 +3896,24 @@ static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
- PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
+ PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
/* CFC error attention */
if (val & 0x2) {
- PMD_DRV_LOG(ERR, "FATAL error from CFC");
+ PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
}
}
if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
- PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
+ PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
/* RQ_USDMDP_FIFO_OVERFLOW */
if (val & 0x18000) {
- PMD_DRV_LOG(ERR, "FATAL error from PXP");
+ PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
}
if (!CHIP_IS_E1x(sc)) {
val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
- PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
+ PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
}
}
#define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
@@ -3935,7 +3941,7 @@ static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
/* print the register, since no one can restore it */
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
/*
@@ -3943,7 +3949,7 @@ static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
* then notify
*/
if (val0 & PXP2_EOP_ERROR_BIT) {
- PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
+ PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
/*
* if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
@@ -3964,7 +3970,7 @@ static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
REG_WR(sc, reg_offset, val);
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"FATAL HW block attention set2 0x%x",
(uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
rte_panic("HW block attention set2");
@@ -3979,10 +3985,10 @@ static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
- PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
+ PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
/* DORQ discard attention */
if (val & 0x2) {
- PMD_DRV_LOG(ERR, "FATAL error from DORQ");
+ PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
}
}
@@ -3994,7 +4000,7 @@ static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
REG_WR(sc, reg_offset, val);
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"FATAL HW block attention set1 0x%08x",
(uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
rte_panic("HW block attention set1");
@@ -4015,7 +4021,7 @@ static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
REG_WR(sc, reg_offset, val);
- PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
+ PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
/* Fan failure attention */
elink_hw_reset_phy(&sc->link_params);
@@ -4105,14 +4111,14 @@ static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserte
}
val = ~deasserted;
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"about to mask 0x%08x at %s addr 0x%08x", val,
(sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
reg_addr);
REG_WR(sc, reg_addr, val);
if (~sc->attn_state & deasserted) {
- PMD_DRV_LOG(ERR, "IGU error");
+ PMD_DRV_LOG(ERR, sc, "IGU error");
}
reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
@@ -4142,12 +4148,12 @@ static void bnx2x_attn_int(struct bnx2x_softc *sc)
uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
attn_bits, attn_ack, asserted, deasserted);
if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
- PMD_DRV_LOG(ERR, "BAD attention state");
+ PMD_DRV_LOG(ERR, sc, "BAD attention state");
}
/* handle bits that were raised */
@@ -4204,7 +4210,7 @@ static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
if (rc < 0) {
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"Failed to send pending mcast commands (%d)",
rc);
}
@@ -4224,17 +4230,17 @@ static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
case ECORE_FILTER_MAC_PENDING:
- PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
+ PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
break;
case ECORE_FILTER_MCAST_PENDING:
- PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
+ PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
bnx2x_handle_mcast_eqe(sc);
return;
default:
- PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
+ PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
elem->message.data.eth_event.echo);
return;
}
@@ -4242,9 +4248,10 @@ static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
if (rc < 0) {
- PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
+ PMD_DRV_LOG(NOTICE, sc,
+ "Failed to schedule new commands (%d)", rc);
} else if (rc > 0) {
- PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
+ PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
}
}
@@ -4308,7 +4315,7 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
/* handle eq element */
switch (opcode) {
case EVENT_RING_OPCODE_STAT_QUERY:
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
sc->stats_comp++);
/* nothing to do with stats comp */
goto next_spqe;
@@ -4316,7 +4323,7 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
case EVENT_RING_OPCODE_CFC_DEL:
/* handle according to cid range */
/* we may want to verify here that the sc state is HALTING */
- PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
+ PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
cid);
q_obj = bnx2x_cid_to_q_obj(sc, cid);
if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
@@ -4325,14 +4332,14 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
goto next_spqe;
case EVENT_RING_OPCODE_STOP_TRAFFIC:
- PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
+ PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
break;
}
goto next_spqe;
case EVENT_RING_OPCODE_START_TRAFFIC:
- PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
+ PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
if (f_obj->complete_cmd
(sc, f_obj, ECORE_F_CMD_TX_START)) {
break;
@@ -4342,7 +4349,7 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
case EVENT_RING_OPCODE_FUNCTION_UPDATE:
echo = elem->message.data.function_update_event.echo;
if (echo == SWITCH_UPDATE) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"got FUNC_SWITCH_UPDATE ramrod");
if (f_obj->complete_cmd(sc, f_obj,
ECORE_F_CMD_SWITCH_UPDATE))
@@ -4350,7 +4357,7 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
break;
}
} else {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"AFEX: ramrod completed FUNCTION_UPDATE");
f_obj->complete_cmd(sc, f_obj,
ECORE_F_CMD_AFEX_UPDATE);
@@ -4366,14 +4373,14 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
goto next_spqe;
case EVENT_RING_OPCODE_FUNCTION_START:
- PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
+ PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
break;
}
goto next_spqe;
case EVENT_RING_OPCODE_FUNCTION_STOP:
- PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
+ PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
break;
}
@@ -4385,7 +4392,7 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
cid =
elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
- PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
+ PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
cid);
rss_raw->clear_pending(rss_raw);
break;
@@ -4396,7 +4403,7 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"got (un)set mac ramrod");
bnx2x_handle_classification_eqe(sc, elem);
break;
@@ -4404,7 +4411,7 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"got mcast ramrod");
bnx2x_handle_mcast_eqe(sc);
break;
@@ -4412,14 +4419,14 @@ static void bnx2x_eq_int(struct bnx2x_softc *sc)
case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"got rx_mode ramrod");
bnx2x_handle_rx_mode_eqe(sc);
break;
default:
/* unknown event log error and continue */
- PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
+ PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
elem->message.opcode, sc->state);
}
@@ -4445,12 +4452,16 @@ static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
uint16_t status;
int rc = 0;
+ PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
+
/* what work needs to be performed? */
status = bnx2x_update_dsb_idx(sc);
+ PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
+
/* HW attentions */
if (status & BNX2X_DEF_SB_ATT_IDX) {
- PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
+ PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
bnx2x_attn_int(sc);
status &= ~BNX2X_DEF_SB_ATT_IDX;
rc = 1;
@@ -4459,7 +4470,7 @@ static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
/* SP events: STAT_QUERY and others */
if (status & BNX2X_DEF_SB_IDX) {
/* handle EQ completions */
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
+ PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
bnx2x_eq_int(sc);
bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
le16toh(sc->def_idx), IGU_INT_NOP, 1);
@@ -4468,7 +4479,7 @@ static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
/* if status is non zero then something went wrong */
if (unlikely(status)) {
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"Got an unknown SP interrupt! (0x%04x)", status);
}
@@ -4484,7 +4495,8 @@ static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
struct bnx2x_softc *sc = fp->sc;
uint8_t more_rx = FALSE;
- PMD_DRV_LOG(DEBUG, "---> FP TASK QUEUE (%d) <--", fp->index);
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
+ "---> FP TASK QUEUE (%d) <--", fp->index);
/* update the fastpath index */
bnx2x_update_fp_sb_idx(fp);
@@ -4534,7 +4546,7 @@ int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
return 0;
}
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
//bnx2x_dump_status_block(sc);
FOR_EACH_ETH_QUEUE(sc, i) {
@@ -4552,7 +4564,7 @@ int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
}
if (unlikely(status)) {
- PMD_DRV_LOG(WARNING,
+ PMD_DRV_LOG(WARNING, sc,
"Unexpected fastpath status (0x%08x)!", status);
}
@@ -4588,7 +4600,7 @@ static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
{
sc->dmae_ready = 0;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
ecore_init_func_obj(sc,
&sc->func_obj,
@@ -4604,7 +4616,7 @@ static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
struct ecore_func_state_params func_params = { NULL };
int rc;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
/* prepare the parameters for function state transitions */
bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
@@ -5193,7 +5205,7 @@ static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
break;
default:
- PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
+ PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
load_code);
break;
}
@@ -5284,7 +5296,7 @@ static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *in
FUNC_MF_CFG_MAX_BW_SHIFT);
if (!max_cfg) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Max BW configured to 0 - using 100 instead");
max_cfg = 100;
}
@@ -5548,7 +5560,7 @@ static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
val |= IGU_PF_CONF_FUNC_EN;
- PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
+ PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
@@ -5596,7 +5608,7 @@ static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
REG_WR(sc, addr, val);
if (REG_RD(sc, addr) != val) {
- PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
+ PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
}
}
@@ -5607,14 +5619,14 @@ static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
- PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
+ PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
/* flush all outstanding writes */
mb();
REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
- PMD_DRV_LOG(ERR, "proper val not read from IGU!");
+ PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
}
}
@@ -5631,7 +5643,7 @@ static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
{
int i;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
for (i = 0; i < sc->num_queues; i++) {
bnx2x_init_eth_fp(sc, i);
@@ -5761,7 +5773,7 @@ static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
/* If there is no power capability, silently succeed */
if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
- PMD_DRV_LOG(WARNING, "No power capability");
+ PMD_DRV_LOG(WARNING, sc, "No power capability");
return 0;
}
@@ -5806,7 +5818,7 @@ static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
break;
default:
- PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
+ PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
state);
return -1;
}
@@ -5824,7 +5836,7 @@ static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
/* Validating that the resource is within range */
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
resource, HW_LOCK_MAX_RESOURCE_VALUE);
return FALSE;
@@ -5844,7 +5856,7 @@ static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
return TRUE;
}
- PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
+ PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
return FALSE;
}
@@ -5937,7 +5949,7 @@ static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
} while (cnt-- > 0);
if (cnt <= 0) {
- PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
+ PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
pend_bits);
return -1;
}
@@ -6018,7 +6030,7 @@ static int bnx2x_init_shmem(struct bnx2x_softc *sc)
} while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
- PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
+ PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
return -1;
}
@@ -6173,7 +6185,7 @@ static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
} while (cnt-- > 0);
if (cnt <= 0) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"ERROR: Tetris buffer didn't get empty or there "
"are still outstanding read requests after 1s! "
"sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
@@ -6246,14 +6258,14 @@ static int bnx2x_leader_reset(struct bnx2x_softc *sc)
load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
if (!load_code) {
- PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
+ PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
rc = -1;
goto exit_leader_reset;
}
if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
(load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"MCP unexpected response, aborting");
rc = -1;
goto exit_leader_reset2;
@@ -6261,7 +6273,7 @@ static int bnx2x_leader_reset(struct bnx2x_softc *sc)
load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
if (!load_code) {
- PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
+ PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
rc = -1;
goto exit_leader_reset2;
}
@@ -6269,7 +6281,7 @@ static int bnx2x_leader_reset(struct bnx2x_softc *sc)
/* try to recover after the failure */
if (bnx2x_process_kill(sc, global)) {
- PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
+ PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
SC_PATH(sc));
rc = -1;
goto exit_leader_reset2;
@@ -6428,12 +6440,12 @@ static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
/* validate rings have enough entries to cross high thresholds */
if (sc->dropless_fc &&
pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
- PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
+ PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
}
if (sc->dropless_fc &&
pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
- PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
+ PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
}
pause->pri_map = 1;
@@ -6504,7 +6516,7 @@ static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
int rc;
- PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
+ PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
@@ -6522,11 +6534,11 @@ static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
/* Change the state to INIT */
rc = ecore_queue_state_change(sc, &q_params);
if (rc) {
- PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
+ PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
return rc;
}
- PMD_DRV_LOG(DEBUG, "init complete");
+ PMD_DRV_LOG(DEBUG, sc, "init complete");
/* now move the Queue to the SETUP state */
memset(setup_params, 0, sizeof(*setup_params));
@@ -6550,7 +6562,7 @@ static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
/* change the state to SETUP */
rc = ecore_queue_state_change(sc, &q_params);
if (rc) {
- PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
+ PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
return rc;
}
@@ -6678,11 +6690,11 @@ static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
rc = ecore_config_vlan_mac(sc, &ramrod_param);
if (rc == ECORE_EXISTS) {
- PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
+ PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
/* do not treat adding same MAC as error */
rc = 0;
} else if (rc < 0) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
}
@@ -6693,7 +6705,7 @@ static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
{
unsigned long ramrod_flags = 0;
- PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
+ PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
@@ -6877,7 +6889,7 @@ static void bnx2x_link_report(struct bnx2x_softc *sc)
if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
&cur_data.link_report_flags)) {
- PMD_DRV_LOG(INFO, "NIC Link is Down");
+ PMD_DRV_LOG(INFO, sc, "NIC Link is Down");
} else {
__rte_unused const char *duplex;
__rte_unused const char *flow;
@@ -6917,7 +6929,7 @@ static void bnx2x_link_report(struct bnx2x_softc *sc)
flow = "none";
}
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
cur_data.line_speed, duplex, flow);
}
@@ -7058,7 +7070,7 @@ void bnx2x_periodic_callout(struct bnx2x_softc *sc)
{
if ((sc->state != BNX2X_STATE_OPEN) ||
(atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
- PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
+ PMD_DRV_LOG(INFO, sc, "periodic callout exit (state=0x%x)",
sc->state);
return;
}
@@ -7095,7 +7107,7 @@ void bnx2x_periodic_callout(struct bnx2x_softc *sc)
if ((drv_pulse != mcp_pulse) &&
(drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
/* someone lost a heartbeat... */
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"drv_pulse (0x%x) != mcp_pulse (0x%x)",
drv_pulse, mcp_pulse);
}
@@ -7111,7 +7123,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
uint32_t load_code = 0;
int i, rc = 0;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
@@ -7165,7 +7177,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
goto bnx2x_nic_load_error2;
}
} else {
- PMD_DRV_LOG(INFO, "Device has no MCP!");
+ PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
load_code = bnx2x_nic_load_no_mcp(sc);
}
@@ -7177,7 +7189,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
/* Initialize HW */
if (bnx2x_init_hw(sc, load_code) != 0) {
- PMD_DRV_LOG(NOTICE, "HW init failed");
+ PMD_DRV_LOG(NOTICE, sc, "HW init failed");
bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
sc->state = BNX2X_STATE_CLOSED;
rc = -ENXIO;
@@ -7197,7 +7209,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
rc = bnx2x_func_start(sc);
if (rc) {
- PMD_DRV_LOG(NOTICE, "Function start failed!");
+ PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
sc->state = BNX2X_STATE_ERROR;
goto bnx2x_nic_load_error3;
@@ -7208,7 +7220,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
load_code =
bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
if (!load_code) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"MCP response failure, aborting");
sc->state = BNX2X_STATE_ERROR;
rc = -ENXIO;
@@ -7219,7 +7231,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
rc = bnx2x_setup_leading(sc);
if (rc) {
- PMD_DRV_LOG(NOTICE, "Setup leading failed!");
+ PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
sc->state = BNX2X_STATE_ERROR;
goto bnx2x_nic_load_error3;
}
@@ -7231,7 +7243,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
if (rc) {
- PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
+ PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
sc->state = BNX2X_STATE_ERROR;
goto bnx2x_nic_load_error3;
}
@@ -7239,7 +7251,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
rc = bnx2x_init_rss_pf(sc);
if (rc) {
- PMD_DRV_LOG(NOTICE, "PF RSS init failed");
+ PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
sc->state = BNX2X_STATE_ERROR;
goto bnx2x_nic_load_error3;
}
@@ -7255,7 +7267,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
}
if (rc) {
- PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
+ PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
sc->state = BNX2X_STATE_ERROR;
goto bnx2x_nic_load_error3;
}
@@ -7307,13 +7319,13 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)
/* wait for all pending SP commands to complete */
if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
- PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
+ PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
bnx2x_periodic_stop(sc);
bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
return -ENXIO;
}
- PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
+ PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
return 0;
@@ -7362,7 +7374,7 @@ int bnx2x_init(struct bnx2x_softc *sc)
/* Check if the driver is still running and bail out if it is. */
if (sc->state != BNX2X_STATE_CLOSED) {
- PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
+ PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
rc = 0;
goto bnx2x_init_done;
}
@@ -7400,7 +7412,7 @@ int bnx2x_init(struct bnx2x_softc *sc)
&& (!global ||!other_load_status))
&& bnx2x_trylock_leader_lock(sc)
&& !bnx2x_leader_reset(sc)) {
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"Recovered during init");
break;
}
@@ -7410,7 +7422,7 @@ int bnx2x_init(struct bnx2x_softc *sc)
sc->recovery_state = BNX2X_RECOVERY_FAILED;
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"Recovery flow hasn't properly "
"completed yet, try again later. "
"If you still see this message after a "
@@ -7429,7 +7441,7 @@ int bnx2x_init(struct bnx2x_softc *sc)
bnx2x_init_done:
if (rc) {
- PMD_DRV_LOG(NOTICE, "Initialization failed, "
+ PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
"stack notified driver is NOT running!");
}
@@ -7461,7 +7473,7 @@ static void bnx2x_get_function_num(struct bnx2x_softc *sc)
sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
}
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Relative function %d, Absolute function %d, Path %d",
sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
}
@@ -7498,14 +7510,14 @@ static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
/* ensure PCIe capability is enabled */
caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
if (NULL != caps) {
- PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
+ PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
"id=0x%04X type=0x%04X addr=0x%08X",
caps->id, caps->type, caps->addr);
pci_read(sc, (caps->addr + reg), &ret, 2);
return ret;
}
- PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
+ PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
return 0;
}
@@ -7523,7 +7535,7 @@ static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
*/
static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
{
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
struct bnx2x_pci_cap *caps;
uint16_t link_status;
@@ -7532,7 +7544,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
/* check if PCI Power Management is enabled */
caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
if (NULL != caps) {
- PMD_DRV_LOG(DEBUG, "Found PM capability: "
+ PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
"id=0x%04X type=0x%04X addr=0x%08X",
caps->id, caps->type, caps->addr);
@@ -7546,7 +7558,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
sc->devinfo.pcie_link_width =
((link_status & PCIM_LINK_STA_WIDTH) >> 4);
- PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
+ PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
@@ -7554,7 +7566,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
/* check if MSI capability is enabled */
caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
if (NULL != caps) {
- PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
+ PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
sc->devinfo.pcie_msi_cap_reg = caps->addr;
@@ -7563,7 +7575,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
/* check if MSI-X capability is enabled */
caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
if (NULL != caps) {
- PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
+ PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
sc->devinfo.pcie_msix_cap_reg = caps->addr;
@@ -7583,7 +7595,7 @@ static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
mf_info->multi_vnics_mode = 1;
if (!VALID_OVLAN(mf_info->ext_id)) {
- PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
+ PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
return 1;
}
@@ -7707,14 +7719,14 @@ static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
/* various MF mode sanity checks... */
if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"Enumerated function %d is marked as hidden",
SC_PORT(sc));
return 1;
}
if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
- PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
+ PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
mf_info->vnics_per_port, mf_info->multi_vnics_mode);
return 1;
}
@@ -7722,13 +7734,13 @@ static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
/* vnic id > 0 must have valid ovlan in switch-dependent mode */
if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
- PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
+ PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
SC_VN(sc), OVLAN(sc));
return 1;
}
if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"mf_mode=SD multi_vnics_mode=%d ovlan=%d",
mf_info->multi_vnics_mode, OVLAN(sc));
return 1;
@@ -7747,7 +7759,7 @@ static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
&& !VALID_OVLAN(ovlan1))
|| ((!mf_info->multi_vnics_mode)
&& VALID_OVLAN(ovlan1)))) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"mf_mode=SD function %d MF config "
"mismatch, multi_vnics_mode=%d ovlan=%d",
i, mf_info->multi_vnics_mode,
@@ -7771,7 +7783,7 @@ static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
&& !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
&& VALID_OVLAN(ovlan2)
&& (ovlan1 == ovlan2)) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"mf_mode=SD functions %d and %d "
"have the same ovlan (%d)",
i, j, ovlan1);
@@ -7801,7 +7813,7 @@ static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
}
if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
- PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
+ PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
return 1;
}
@@ -7819,7 +7831,7 @@ static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
mf_info->mf_mode = MULTI_FUNCTION_SI;
} else {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"Invalid config for Switch Independent mode");
}
@@ -7835,7 +7847,7 @@ static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
mf_info->mf_mode = MULTI_FUNCTION_SD;
} else {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"Invalid config for Switch Dependent mode");
}
@@ -7859,14 +7871,14 @@ static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
(mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
mf_info->mf_mode = MULTI_FUNCTION_AFEX;
} else {
- PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
+ PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
}
break;
default:
- PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
+ PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
(val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
return 1;
@@ -7898,7 +7910,7 @@ static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
if (mf_info->mf_mode == SINGLE_FUNCTION) {
/* invalid MF config */
if (SC_VN(sc) >= 1) {
- PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
+ PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
return 1;
}
@@ -7927,7 +7939,7 @@ static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
default:
- PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
+ PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
mf_info->mf_mode);
return 1;
}
@@ -7955,7 +7967,7 @@ static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
int port;
uint32_t mac_hi, mac_lo, val;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
port = SC_PORT(sc);
mac_hi = mac_lo = 0;
@@ -8029,7 +8041,7 @@ static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
if ((mac_lo == 0) && (mac_hi == 0)) {
*sc->mac_addr_str = 0;
- PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
+ PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
} else {
sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
@@ -8045,7 +8057,8 @@ static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
sc->link_params.mac_addr[3],
sc->link_params.mac_addr[4],
sc->link_params.mac_addr[5]);
- PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
+ PMD_DRV_LOG(DEBUG, sc,
+ "Ethernet address: %s", sc->mac_addr_str);
}
return 0;
@@ -8060,24 +8073,24 @@ static void bnx2x_media_detect(struct bnx2x_softc *sc)
case ELINK_ETH_PHY_XFP_FIBER:
case ELINK_ETH_PHY_KR:
case ELINK_ETH_PHY_CX4:
- PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
+ PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
sc->media = IFM_10G_CX4;
break;
case ELINK_ETH_PHY_DA_TWINAX:
- PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
+ PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
sc->media = IFM_10G_TWINAX;
break;
case ELINK_ETH_PHY_BASE_T:
- PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
+ PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
sc->media = IFM_10G_T;
break;
case ELINK_ETH_PHY_NOT_PRESENT:
- PMD_DRV_LOG(INFO, "Media not present.");
+ PMD_DRV_LOG(INFO, sc, "Media not present.");
sc->media = 0;
break;
case ELINK_ETH_PHY_UNSPECIFIED:
default:
- PMD_DRV_LOG(INFO, "Unknown media!");
+ PMD_DRV_LOG(INFO, sc, "Unknown media!");
sc->media = 0;
break;
}
@@ -8140,7 +8153,7 @@ static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
if (igu_sb_cnt == 0) {
- PMD_DRV_LOG(ERR, "CAM configuration error");
+ PMD_DRV_LOG(ERR, sc, "CAM configuration error");
return -1;
}
@@ -8177,7 +8190,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
sc->devinfo.chip_id |= 0x1;
}
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
sc->devinfo.chip_id,
((sc->devinfo.chip_id >> 16) & 0xffff),
@@ -8188,7 +8201,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
val = (REG_RD(sc, 0x2874) & 0x55);
if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
sc->flags |= BNX2X_ONE_PORT_FLAG;
- PMD_DRV_LOG(DEBUG, "single port device");
+ PMD_DRV_LOG(DEBUG, sc, "single port device");
}
/* set the doorbell size */
@@ -8212,7 +8225,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
sc->devinfo.chip_port_mode =
(val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
- PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
+ PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
}
/* get the function and path info for the device */
@@ -8227,7 +8240,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
if (!sc->devinfo.shmem_base) {
/* this should ONLY prevent upcoming shmem reads */
- PMD_DRV_LOG(INFO, "MCP not active");
+ PMD_DRV_LOG(INFO, sc, "MCP not active");
sc->flags |= BNX2X_NO_MCP_FLAG;
return 0;
}
@@ -8236,7 +8249,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
(SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
- PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
+ PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
val);
return 0;
}
@@ -8249,7 +8262,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
((sc->devinfo.bc_ver >> 24) & 0xff),
((sc->devinfo.bc_ver >> 16) & 0xff),
((sc->devinfo.bc_ver >> 8) & 0xff));
- PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
+ PMD_DRV_LOG(INFO, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
/* get the bootcode shmem address */
sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
@@ -8304,7 +8317,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
}
if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"FORCING IGU Normal Mode failed!!!");
bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
return -1;
@@ -8312,10 +8325,10 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
}
if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
- PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
+ PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
} else {
- PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
+ PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
}
rc = bnx2x_get_igu_cam_info(sc);
@@ -8389,7 +8402,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
}
if (!(sc->port.supported[0] || sc->port.supported[1])) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
SHMEM_RD(sc,
dev_info.port_hw_config
@@ -8415,7 +8428,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
break;
default:
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid switch config in"
"link_config=0x%08x",
sc->port.link_config[0]);
@@ -8423,7 +8436,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
}
}
- PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
+ PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
/* mask what we support according to speed_cap_mask per configuration */
for (idx = 0; idx < cfg_size; idx++) {
@@ -8476,7 +8489,7 @@ static int bnx2x_get_device_info(struct bnx2x_softc *sc)
}
}
- PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
+ PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
sc->port.supported[0], sc->port.supported[1]);
}
@@ -8535,7 +8548,7 @@ static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
sc->port.advertising[idx] |=
(ADVERTISED_10baseT_Full | ADVERTISED_TP);
} else {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid NVRAM config link_config=0x%08x "
"speed_cap_mask=0x%08x",
link_config,
@@ -8555,7 +8568,7 @@ static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
sc->port.advertising[idx] |=
(ADVERTISED_10baseT_Half | ADVERTISED_TP);
} else {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid NVRAM config link_config=0x%08x "
"speed_cap_mask=0x%08x",
link_config,
@@ -8574,7 +8587,7 @@ static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
sc->port.advertising[idx] |=
(ADVERTISED_100baseT_Full | ADVERTISED_TP);
} else {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid NVRAM config link_config=0x%08x "
"speed_cap_mask=0x%08x",
link_config,
@@ -8594,7 +8607,7 @@ static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
sc->port.advertising[idx] |=
(ADVERTISED_100baseT_Half | ADVERTISED_TP);
} else {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid NVRAM config link_config=0x%08x "
"speed_cap_mask=0x%08x",
link_config,
@@ -8612,7 +8625,7 @@ static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
sc->port.advertising[idx] |=
(ADVERTISED_1000baseT_Full | ADVERTISED_TP);
} else {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid NVRAM config link_config=0x%08x "
"speed_cap_mask=0x%08x",
link_config,
@@ -8630,7 +8643,7 @@ static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
sc->port.advertising[idx] |=
(ADVERTISED_2500baseX_Full | ADVERTISED_TP);
} else {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid NVRAM config link_config=0x%08x "
"speed_cap_mask=0x%08x",
link_config,
@@ -8649,7 +8662,7 @@ static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
(ADVERTISED_10000baseT_Full |
ADVERTISED_FIBRE);
} else {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid NVRAM config link_config=0x%08x "
"speed_cap_mask=0x%08x",
link_config,
@@ -8664,7 +8677,7 @@ static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
break;
default:
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Invalid NVRAM config link_config=0x%08x "
"speed_cap_mask=0x%08x", link_config,
sc->link_params.speed_cap_mask[idx]);
@@ -8695,7 +8708,7 @@ static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
uint8_t port = SC_PORT(sc);
uint32_t eee_mode;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
/* shmem data already read in bnx2x_get_shmem_info() */
@@ -8855,7 +8868,7 @@ int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
snprintf(buf, sizeof(buf), "fp_%d_sb", i);
if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
&fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
- PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
+ PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
return -1;
} else {
if (CHIP_IS_E2E3(sc)) {
@@ -8945,7 +8958,7 @@ static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
if (!rc) {
- PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
+ PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
return -1;
}
@@ -8977,12 +8990,12 @@ static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
tmp = bnx2x_prev_path_get_entry(sc);
if (tmp) {
if (tmp->aer) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Path %d/%d/%d was marked by AER",
sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
} else {
rc = TRUE;
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Path %d/%d/%d was already cleaned from previous drivers",
sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
}
@@ -9003,11 +9016,11 @@ static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
tmp = bnx2x_prev_path_get_entry(sc);
if (tmp) {
if (!tmp->aer) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Re-marking AER in path %d/%d/%d",
sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
} else {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Removing AER indication from path %d/%d/%d",
sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
tmp->aer = 0;
@@ -9023,7 +9036,7 @@ static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
RTE_CACHE_LINE_SIZE);
if (!tmp) {
- PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
+ PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
return -1;
}
@@ -9048,13 +9061,13 @@ static int bnx2x_do_flr(struct bnx2x_softc *sc)
/* only E2 and onwards support FLR */
if (CHIP_IS_E1x(sc)) {
- PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
+ PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
return -1;
}
/* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
- PMD_DRV_LOG(WARNING,
+ PMD_DRV_LOG(WARNING, sc,
"FLR not supported by BC_VER: 0x%08x",
sc->devinfo.bc_ver);
return -1;
@@ -9071,7 +9084,7 @@ static int bnx2x_do_flr(struct bnx2x_softc *sc)
}
}
- PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
+ PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
"proceeding with reset anyway");
clear:
@@ -9219,7 +9232,7 @@ static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
if (tmp_reg == 0x7) {
- PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
+ PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
prev_undi = TRUE;
/* clear the UNDI indication */
REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
@@ -9238,7 +9251,7 @@ static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
break;
}
- PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
+ PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
/* reset timer as long as BRB actually gets emptied */
if (prev_brb > tmp_reg) {
@@ -9256,7 +9269,7 @@ static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
}
if (!timer_count) {
- PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
+ PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
}
}
@@ -9311,7 +9324,7 @@ static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
return 0;
}
- PMD_DRV_LOG(INFO, "Could not FLR");
+ PMD_DRV_LOG(INFO, sc, "Could not FLR");
/* Close the MCP request, return failure */
rc = bnx2x_prev_mcp_done(sc);
@@ -9358,7 +9371,7 @@ static int bnx2x_prev_unload(struct bnx2x_softc *sc)
/* Lock MCP using an unload request */
fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
if (!fw) {
- PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
+ PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
rc = -1;
break;
}
@@ -9378,7 +9391,7 @@ static int bnx2x_prev_unload(struct bnx2x_softc *sc)
} while (--time_counter);
if (!time_counter || rc) {
- PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
+ PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
rc = -1;
}
@@ -9395,7 +9408,7 @@ static int bnx2x_prev_unload(struct bnx2x_softc *sc)
sc->dcb_state = FALSE;
sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
}
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"DCB state [%s:%s]",
dcb_on ? "ON" : "OFF",
(dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
@@ -9428,7 +9441,7 @@ static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
if (cos < sc->max_cos) {
sc->prio_to_cos[pri] = cos;
} else {
- PMD_DRV_LOG(WARNING,
+ PMD_DRV_LOG(WARNING, sc,
"Invalid COS %d for priority %d "
"(max COS is %d), setting to 0", cos, pri,
(sc->max_cos - 1));
@@ -9449,7 +9462,7 @@ static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
RTE_CACHE_LINE_SIZE);
if (!cap) {
- PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
+ PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
return -ENOMEM;
}
@@ -9460,7 +9473,7 @@ static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
pci_read(sc, PCIR_STATUS, &status, 2);
if (!(status & PCIM_STATUS_CAPPRESENT)) {
#endif
- PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
+ PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
return -1;
}
@@ -9480,7 +9493,7 @@ static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
sizeof(struct bnx2x_pci_cap),
RTE_CACHE_LINE_SIZE);
if (!cap->next) {
- PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
+ PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
return -ENOMEM;
}
cap = cap->next;
@@ -9516,25 +9529,25 @@ void bnx2x_load_firmware(struct bnx2x_softc *sc)
? FW_NAME_57711 : FW_NAME_57810;
f = open(fwname, O_RDONLY);
if (f < 0) {
- PMD_DRV_LOG(NOTICE, "Can't open firmware file");
+ PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
return;
}
if (fstat(f, &st) < 0) {
- PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
+ PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
close(f);
return;
}
sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
if (!sc->firmware) {
- PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
+ PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
close(f);
return;
}
if (read(f, sc->firmware, st.st_size) != st.st_size) {
- PMD_DRV_LOG(NOTICE, "Can't read firmware data");
+ PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
close(f);
return;
}
@@ -9542,10 +9555,11 @@ void bnx2x_load_firmware(struct bnx2x_softc *sc)
sc->fw_len = st.st_size;
if (sc->fw_len < FW_HEADER_LEN) {
- PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
+ PMD_DRV_LOG(NOTICE, sc,
+ "Invalid fw size: %" PRIu64, sc->fw_len);
return;
}
- PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
+ PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
}
static void
@@ -9612,11 +9626,11 @@ int bnx2x_attach(struct bnx2x_softc *sc)
{
int rc;
- PMD_DRV_LOG(DEBUG, "Starting attach...");
+ PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
rc = bnx2x_pci_get_caps(sc);
if (rc) {
- PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
+ PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
return rc;
}
@@ -9655,7 +9669,7 @@ int bnx2x_attach(struct bnx2x_softc *sc)
/* get device info and set params */
if (bnx2x_get_device_info(sc) != 0) {
- PMD_DRV_LOG(NOTICE, "getting device info");
+ PMD_DRV_LOG(NOTICE, sc, "getting device info");
return -ENXIO;
}
@@ -9754,7 +9768,7 @@ int bnx2x_attach(struct bnx2x_softc *sc)
mb();
- PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
ctl, igu_addr_ctl);
REG_WR(sc, igu_addr_ctl, ctl);
@@ -9766,7 +9780,7 @@ int bnx2x_attach(struct bnx2x_softc *sc)
}
if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Unable to finish IGU cleanup: "
"idu_sb_id %d offset %d bit %d (cnt %d)",
idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
@@ -9786,7 +9800,7 @@ static void bnx2x_reset_common(struct bnx2x_softc *sc)
{
uint32_t val = 0x1400;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
/* reset_common */
REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
@@ -9995,7 +10009,8 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
uint8_t abs_func_id;
uint32_t val;
- PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
+ PMD_DRV_LOG(DEBUG, sc,
+ "starting common init for func %d", SC_ABS_FUNC(sc));
/*
* take the RESET lock to protect undi_unload flow from accessing
@@ -10078,12 +10093,12 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
if (val != 1) {
- PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
+ PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
return -1;
}
val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
if (val != 1) {
- PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
+ PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
return -1;
}
@@ -10205,7 +10220,7 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
} while (factor-- && (val != 1));
if (val != 1) {
- PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
+ PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
return -1;
}
}
@@ -10343,7 +10358,7 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
if (sizeof(union cdu_context) != 1024) {
/* we currently assume that a context is 1024 bytes */
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"please adjust the size of cdu_context(%ld)",
(long)sizeof(union cdu_context));
}
@@ -10405,17 +10420,17 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
/* finish CFC init */
val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
if (val != 1) {
- PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
+ PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
return -1;
}
val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
if (val != 1) {
- PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
+ PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
return -1;
}
val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
if (val != 1) {
- PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
+ PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
return -1;
}
REG_WR(sc, CFC_REG_DEBUG0, 0);
@@ -10468,7 +10483,7 @@ static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
uint32_t low, high;
uint32_t val;
- PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
+ PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
@@ -10695,7 +10710,7 @@ static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
if (val != 0) {
- PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
+ PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
return -1;
}
@@ -10787,7 +10802,7 @@ static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cn
int ret = 0;
if (REG_RD(sc, comp_addr)) {
- PMD_DRV_LOG(NOTICE,
+ PMD_DRV_LOG(NOTICE, sc,
"Cleanup complete was not 0 before sending");
return -1;
}
@@ -10800,8 +10815,8 @@ static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cn
REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
- PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
- PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
+ PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
+ PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
(REG_RD(sc, comp_addr)));
rte_panic("FLR cleanup failed");
return -1;
@@ -10917,28 +10932,30 @@ static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
__rte_unused uint32_t val;
val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
- PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
+ PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
val = REG_RD(sc, PBF_REG_DISABLE_PF);
- PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
+ PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
- PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
+ PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
- PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
+ PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
- PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
+ PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
- PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
+ PMD_DRV_LOG(DEBUG, sc,
+ "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
- PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
+ PMD_DRV_LOG(DEBUG, sc,
+ "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
- PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
val);
}
@@ -10982,7 +10999,7 @@ static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
/* Verify no pending pci transactions */
if (bnx2x_is_pcie_pending(sc)) {
- PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
+ PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
}
/* Debug */
@@ -11009,13 +11026,13 @@ static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
int main_mem_width, rc;
uint32_t i;
- PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
+ PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
/* FLR cleanup */
if (!CHIP_IS_E1x(sc)) {
rc = bnx2x_pf_flr_clnup(sc);
if (rc) {
- PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
+ PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
return rc;
}
}
@@ -11262,7 +11279,7 @@ static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
val = REG_RD(sc, main_mem_prty_clr);
if (val) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Parity errors in HC block during function init (0x%x)!",
val);
}
@@ -11300,7 +11317,7 @@ static void bnx2x_link_reset(struct bnx2x_softc *sc)
elink_lfa_reset(&sc->link_params, &sc->link_vars);
} else {
if (!CHIP_REV_IS_SLOW(sc)) {
- PMD_DRV_LOG(WARNING,
+ PMD_DRV_LOG(WARNING, sc,
"Bootcode is missing - cannot reset link");
}
}
@@ -11330,7 +11347,7 @@ static void bnx2x_reset_port(struct bnx2x_softc *sc)
/* Check for BRB port occupancy */
val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
if (val) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"BRB1 is not empty, %d blocks are occupied", val);
}
}
@@ -11524,10 +11541,10 @@ static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
int ret;
int data_begin = cut_gzip_prefix(zbuf, len);
- PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
+ PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
if (data_begin <= 0) {
- PMD_DRV_LOG(NOTICE, "bad gzip prefix");
+ PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
return -1;
}
@@ -11539,19 +11556,19 @@ static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
ret = inflateInit2(&zlib_stream, -MAX_WBITS);
if (ret != Z_OK) {
- PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
+ PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
return ret;
}
ret = inflate(&zlib_stream, Z_FINISH);
if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
- PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
+ PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
zlib_stream.msg);
}
sc->gz_outlen = zlib_stream.total_out;
if (sc->gz_outlen & 0x3) {
- PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
+ PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
sc->gz_outlen);
}
sc->gz_outlen >>= 2;
@@ -11670,7 +11687,7 @@ void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
int i = 0;
__rte_unused uint32_t ext_phy_type;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
sc->
@@ -11689,97 +11706,102 @@ void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
dev_info.port_hw_config
[0].external_phy_config)));
- PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
+ PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
/* Hardware chip info. */
- PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
- PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
+ PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
+ PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
(CHIP_METAL(sc) >> 4));
/* Bus info. */
- PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
+ PMD_DRV_LOG(INFO, sc,
+ "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
switch (sc->devinfo.pcie_link_speed) {
case 1:
- PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
+ PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
break;
case 2:
- PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
+ PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
break;
case 4:
- PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
+ PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
break;
default:
- PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
+ PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
}
/* Device features. */
- PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
+ PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
/* Miscellaneous flags. */
if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
- PMD_INIT_LOG(DEBUG, "%18s", "MSI");
+ PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
i++;
}
if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
if (i > 0)
- PMD_INIT_LOG(DEBUG, "|");
- PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
+ PMD_DRV_LOG(INFO, sc, "|");
+ PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
i++;
}
if (IS_PF(sc)) {
- PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
+ PMD_DRV_LOG(INFO, sc, "%12s : ", "Queues");
switch (sc->sp->rss_rdata.rss_mode) {
case ETH_RSS_MODE_DISABLED:
- PMD_INIT_LOG(DEBUG, "%19s", "None");
+ PMD_DRV_LOG(INFO, sc, "%19s", "None");
break;
case ETH_RSS_MODE_REGULAR:
- PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
+ PMD_DRV_LOG(INFO, sc,
+ "%18s : %d", "RSS", sc->num_queues);
break;
default:
- PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
+ PMD_DRV_LOG(INFO, sc, "%22s", "Unknown");
break;
}
}
/* RTE and Driver versions */
- PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
- rte_version());
- PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
- bnx2x_pmd_version());
+ PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
+ rte_version());
+ PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
+ bnx2x_pmd_version());
/* Firmware versions and device features. */
- PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
+ PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
"Firmware",
BNX2X_5710_FW_MAJOR_VERSION,
BNX2X_5710_FW_MINOR_VERSION,
BNX2X_5710_FW_REVISION_VERSION);
- PMD_INIT_LOG(DEBUG, "%12s : %s",
+ PMD_DRV_LOG(INFO, sc, "%12s : %s",
"Bootcode", sc->devinfo.bc_ver_str);
- PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
- PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
- PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
- PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
+ PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
+ PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
+ PMD_DRV_LOG(INFO, sc,
+ "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
+ PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
(sc->dmae_ready ? "Ready" : "Not Ready"));
- PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
- PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
- PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
- PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
- PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
+ PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
+ PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
+ PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
+ PMD_DRV_LOG(INFO, sc,
+ "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
+ PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
sc->link_params.mac_addr[0],
sc->link_params.mac_addr[1],
sc->link_params.mac_addr[2],
sc->link_params.mac_addr[3],
sc->link_params.mac_addr[4],
sc->link_params.mac_addr[5]);
- PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
- PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
+ PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
+ PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
if (sc->recovery_state)
- PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
+ PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
get_recovery_state(sc->recovery_state));
- PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
+ PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
sc->cq_spq_left, sc->eq_spq_left);
- PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
- PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
+ PMD_DRV_LOG(INFO, sc,
+ "%12s : %x", "Switch", sc->link_params.switch_cfg);
+ PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
}
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 0f6024f..2d545f5 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -803,6 +803,10 @@ struct bnx2x_mf_info {
/* Device information data structure. */
struct bnx2x_devinfo {
+#if 1
+#define NAME_SIZE 128
+ char name[NAME_SIZE];
+#endif
/* PCIe info */
uint16_t vendor_id;
uint16_t device_id;
@@ -1418,7 +1422,7 @@ struct bnx2x_func_init_params {
static inline void
bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
{
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
(unsigned long)offset, val);
rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
}
@@ -1428,10 +1432,10 @@ struct bnx2x_func_init_params {
{
#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
if ((offset % 2) != 0)
- PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx",
+ PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit write to 0x%08lx",
(unsigned long)offset);
#endif
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%04x",
(unsigned long)offset, val);
rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
@@ -1442,11 +1446,11 @@ struct bnx2x_func_init_params {
{
#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
if ((offset % 4) != 0)
- PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx",
+ PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit write to 0x%08lx",
(unsigned long)offset);
#endif
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
(unsigned long)offset, val);
rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
}
@@ -1457,7 +1461,7 @@ struct bnx2x_func_init_params {
uint8_t val;
val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset);
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
(unsigned long)offset, val);
return val;
@@ -1470,12 +1474,12 @@ struct bnx2x_func_init_params {
#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
if ((offset % 2) != 0)
- PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx",
+ PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit read from 0x%08lx",
(unsigned long)offset);
#endif
val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset));
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
(unsigned long)offset, val);
return val;
@@ -1488,12 +1492,12 @@ struct bnx2x_func_init_params {
#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
if ((offset % 4) != 0)
- PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx",
+ PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit read from 0x%08lx",
(unsigned long)offset);
#endif
val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset));
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
(unsigned long)offset, val);
return val;
@@ -1970,7 +1974,7 @@ int bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
bnx2x_vf_set_rx_mode(sc);
}
} else {
- PMD_DRV_LOG(NOTICE, "Card is not ready to change mode");
+ PMD_DRV_LOG(NOTICE, sc, "Card is not ready to change mode");
}
}
@@ -1978,7 +1982,7 @@ static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
void *val, uint8_t size)
{
if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
- PMD_DRV_LOG(ERR, "Can't read from PCI config space");
+ PMD_DRV_LOG(ERR, sc, "Can't read from PCI config space");
return ENXIO;
}
@@ -1991,7 +1995,7 @@ static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
if (rte_pci_write_config(sc->pci_dev, &val16,
sizeof(val16), addr) <= 0) {
- PMD_DRV_LOG(ERR, "Can't write to PCI config space");
+ PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
return ENXIO;
}
@@ -2003,7 +2007,7 @@ static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
uint32_t val32 = val;
if (rte_pci_write_config(sc->pci_dev, &val32,
sizeof(val32), addr) <= 0) {
- PMD_DRV_LOG(ERR, "Can't write to PCI config space");
+ PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
return ENXIO;
}
diff --git a/drivers/net/bnx2x/bnx2x_ethdev.c b/drivers/net/bnx2x/bnx2x_ethdev.c
index 575271a..ae2e60a 100644
--- a/drivers/net/bnx2x/bnx2x_ethdev.c
+++ b/drivers/net/bnx2x/bnx2x_ethdev.c
@@ -85,7 +85,7 @@ struct rte_bnx2x_xstats_name_off {
struct bnx2x_softc *sc = dev->data->dev_private;
struct rte_eth_link link;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
bnx2x_link_status_update(sc);
memset(&link, 0, sizeof(link));
@@ -129,7 +129,7 @@ struct rte_bnx2x_xstats_name_off {
struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
struct bnx2x_softc *sc = dev->data->dev_private;
- PMD_DEBUG_PERIODIC_LOG(INFO, "Interrupt handled");
+ PMD_DEBUG_PERIODIC_LOG(INFO, sc, "Interrupt handled");
bnx2x_interrupt_action(dev);
rte_intr_enable(&sc->pci_dev->intr_handle);
@@ -147,8 +147,8 @@ static void bnx2x_periodic_start(void *param)
ret = rte_eal_alarm_set(BNX2X_SP_TIMER_PERIOD,
bnx2x_periodic_start, (void *)dev);
if (ret) {
- PMD_DRV_LOG(ERR, "Unable to start periodic"
- " timer rc %d", ret);
+ PMD_DRV_LOG(ERR, sc, "Unable to start periodic"
+ " timer rc %d", ret);
assert(false && "Unable to start periodic timer");
}
}
@@ -176,34 +176,34 @@ void bnx2x_periodic_stop(void *param)
int mp_ncpus = sysconf(_SC_NPROCESSORS_CONF);
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
sc->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len;
if (dev->data->nb_tx_queues > dev->data->nb_rx_queues) {
- PMD_DRV_LOG(ERR, "The number of TX queues is greater than number of RX queues");
+ PMD_DRV_LOG(ERR, sc, "The number of TX queues is greater than number of RX queues");
return -EINVAL;
}
sc->num_queues = MAX(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
if (sc->num_queues > mp_ncpus) {
- PMD_DRV_LOG(ERR, "The number of queues is more than number of CPUs");
+ PMD_DRV_LOG(ERR, sc, "The number of queues is more than number of CPUs");
return -EINVAL;
}
- PMD_DRV_LOG(DEBUG, "num_queues=%d, mtu=%d",
+ PMD_DRV_LOG(DEBUG, sc, "num_queues=%d, mtu=%d",
sc->num_queues, sc->mtu);
/* allocate ilt */
if (bnx2x_alloc_ilt_mem(sc) != 0) {
- PMD_DRV_LOG(ERR, "bnx2x_alloc_ilt_mem was failed");
+ PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_ilt_mem was failed");
return -ENXIO;
}
/* allocate the host hardware/software hsi structures */
if (bnx2x_alloc_hsi_mem(sc) != 0) {
- PMD_DRV_LOG(ERR, "bnx2x_alloc_hsi_mem was failed");
+ PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
bnx2x_free_ilt_mem(sc);
return -ENXIO;
}
@@ -217,7 +217,7 @@ void bnx2x_periodic_stop(void *param)
struct bnx2x_softc *sc = dev->data->dev_private;
int ret = 0;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
/* start the periodic callout */
if (sc->periodic_flags & PERIODIC_STOP)
@@ -225,7 +225,7 @@ void bnx2x_periodic_stop(void *param)
ret = bnx2x_init(sc);
if (ret) {
- PMD_DRV_LOG(DEBUG, "bnx2x_init failed (%d)", ret);
+ PMD_DRV_LOG(DEBUG, sc, "bnx2x_init failed (%d)", ret);
return -1;
}
@@ -234,12 +234,12 @@ void bnx2x_periodic_stop(void *param)
bnx2x_interrupt_handler, (void *)dev);
if (rte_intr_enable(&sc->pci_dev->intr_handle))
- PMD_DRV_LOG(ERR, "rte_intr_enable failed");
+ PMD_DRV_LOG(ERR, sc, "rte_intr_enable failed");
}
ret = bnx2x_dev_rx_init(dev);
if (ret != 0) {
- PMD_DRV_LOG(DEBUG, "bnx2x_dev_rx_init returned error code");
+ PMD_DRV_LOG(DEBUG, sc, "bnx2x_dev_rx_init returned error code");
return -3;
}
@@ -255,7 +255,7 @@ void bnx2x_periodic_stop(void *param)
struct bnx2x_softc *sc = dev->data->dev_private;
int ret = 0;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
if (IS_PF(sc)) {
rte_intr_disable(&sc->pci_dev->intr_handle);
@@ -268,7 +268,7 @@ void bnx2x_periodic_stop(void *param)
ret = bnx2x_nic_unload(sc, UNLOAD_NORMAL, FALSE);
if (ret) {
- PMD_DRV_LOG(DEBUG, "bnx2x_nic_unload failed (%d)", ret);
+ PMD_DRV_LOG(DEBUG, sc, "bnx2x_nic_unload failed (%d)", ret);
return;
}
@@ -280,7 +280,7 @@ void bnx2x_periodic_stop(void *param)
{
struct bnx2x_softc *sc = dev->data->dev_private;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
if (IS_VF(sc))
bnx2x_vf_close(sc);
@@ -300,7 +300,7 @@ void bnx2x_periodic_stop(void *param)
{
struct bnx2x_softc *sc = dev->data->dev_private;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
sc->rx_mode = BNX2X_RX_MODE_PROMISC;
if (rte_eth_allmulticast_get(dev->data->port_id) == 1)
sc->rx_mode = BNX2X_RX_MODE_ALLMULTI_PROMISC;
@@ -312,7 +312,7 @@ void bnx2x_periodic_stop(void *param)
{
struct bnx2x_softc *sc = dev->data->dev_private;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
sc->rx_mode = BNX2X_RX_MODE_NORMAL;
if (rte_eth_allmulticast_get(dev->data->port_id) == 1)
sc->rx_mode = BNX2X_RX_MODE_ALLMULTI;
@@ -324,7 +324,7 @@ void bnx2x_periodic_stop(void *param)
{
struct bnx2x_softc *sc = dev->data->dev_private;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
sc->rx_mode = BNX2X_RX_MODE_ALLMULTI;
if (rte_eth_promiscuous_get(dev->data->port_id) == 1)
sc->rx_mode = BNX2X_RX_MODE_ALLMULTI_PROMISC;
@@ -336,7 +336,7 @@ void bnx2x_periodic_stop(void *param)
{
struct bnx2x_softc *sc = dev->data->dev_private;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
sc->rx_mode = BNX2X_RX_MODE_NORMAL;
if (rte_eth_promiscuous_get(dev->data->port_id) == 1)
sc->rx_mode = BNX2X_RX_MODE_PROMISC;
@@ -346,7 +346,9 @@ void bnx2x_periodic_stop(void *param)
static int
bnx2x_dev_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
{
- PMD_INIT_FUNC_TRACE();
+ struct bnx2x_softc *sc = dev->data->dev_private;
+
+ PMD_INIT_FUNC_TRACE(sc);
return bnx2x_link_update(dev);
}
@@ -361,7 +363,7 @@ void bnx2x_periodic_stop(void *param)
bnx2x_check_bull(sc);
if (sc->old_bulletin.valid_bitmap & (1 << CHANNEL_DOWN)) {
- PMD_DRV_LOG(ERR, "PF indicated channel is down."
+ PMD_DRV_LOG(ERR, sc, "PF indicated channel is down."
"VF device is no longer operational");
dev->data->dev_link.link_status = ETH_LINK_DOWN;
}
@@ -377,7 +379,7 @@ void bnx2x_periodic_stop(void *param)
uint64_t brb_drops;
uint64_t brb_truncates;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
bnx2x_stats_handle(sc, STATS_EVENT_UPDATE);
@@ -568,27 +570,35 @@ void bnx2x_periodic_stop(void *param)
{
int ret = 0;
struct rte_pci_device *pci_dev;
+ struct rte_pci_addr pci_addr;
struct bnx2x_softc *sc;
- PMD_INIT_FUNC_TRACE();
+ /* Extract key data structures */
+ sc = eth_dev->data->dev_private;
+ pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
+ pci_addr = pci_dev->addr;
+
+ snprintf(sc->devinfo.name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
+ pci_addr.bus, pci_addr.devid, pci_addr.function,
+ eth_dev->data->port_id);
+
+ PMD_INIT_FUNC_TRACE(sc);
eth_dev->dev_ops = is_vf ? &bnx2xvf_eth_dev_ops : &bnx2x_eth_dev_ops;
- pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
rte_eth_copy_pci_info(eth_dev, pci_dev);
- sc = eth_dev->data->dev_private;
sc->pcie_bus = pci_dev->addr.bus;
sc->pcie_device = pci_dev->addr.devid;
- if (is_vf)
- sc->flags = BNX2X_IS_VF_FLAG;
-
sc->devinfo.vendor_id = pci_dev->id.vendor_id;
sc->devinfo.device_id = pci_dev->id.device_id;
sc->devinfo.subvendor_id = pci_dev->id.subsystem_vendor_id;
sc->devinfo.subdevice_id = pci_dev->id.subsystem_device_id;
+ if (is_vf)
+ sc->flags = BNX2X_IS_VF_FLAG;
+
sc->pcie_func = pci_dev->addr.function;
sc->bar[BAR0].base_addr = (void *)pci_dev->mem_resource[0].addr;
if (is_vf)
@@ -616,7 +626,7 @@ void bnx2x_periodic_stop(void *param)
sc->pci_dev = pci_dev;
ret = bnx2x_attach(sc);
if (ret) {
- PMD_DRV_LOG(ERR, "bnx2x_attach failed (%d)", ret);
+ PMD_DRV_LOG(ERR, sc, "bnx2x_attach failed (%d)", ret);
return ret;
}
@@ -625,21 +635,21 @@ void bnx2x_periodic_stop(void *param)
ret = rte_eal_alarm_set(BNX2X_SP_TIMER_PERIOD,
bnx2x_periodic_start, (void *)eth_dev);
if (ret) {
- PMD_DRV_LOG(ERR, "Unable to start periodic"
- " timer rc %d", ret);
+ PMD_DRV_LOG(ERR, sc, "Unable to start periodic"
+ " timer rc %d", ret);
return -EINVAL;
}
}
eth_dev->data->mac_addrs = (struct ether_addr *)sc->link_params.mac_addr;
- PMD_DRV_LOG(INFO, "pcie_bus=%d, pcie_device=%d",
+ PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
sc->pcie_bus, sc->pcie_device);
- PMD_DRV_LOG(INFO, "bar0.addr=%p, bar1.addr=%p",
+ PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
- PMD_DRV_LOG(INFO, "port=%d, path=%d, vnic=%d, func=%d",
+ PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));
- PMD_DRV_LOG(INFO, "portID=%d vendorID=0x%x deviceID=0x%x",
+ PMD_DRV_LOG(INFO, sc, "portID=%d vendorID=0x%x deviceID=0x%x",
eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id);
if (IS_VF(sc)) {
@@ -679,14 +689,16 @@ void bnx2x_periodic_stop(void *param)
static int
eth_bnx2x_dev_init(struct rte_eth_dev *eth_dev)
{
- PMD_INIT_FUNC_TRACE();
+ struct bnx2x_softc *sc = eth_dev->data->dev_private;
+ PMD_INIT_FUNC_TRACE(sc);
return bnx2x_common_dev_init(eth_dev, 0);
}
static int
eth_bnx2xvf_dev_init(struct rte_eth_dev *eth_dev)
{
- PMD_INIT_FUNC_TRACE();
+ struct bnx2x_softc *sc = eth_dev->data->dev_private;
+ PMD_INIT_FUNC_TRACE(sc);
return bnx2x_common_dev_init(eth_dev, 1);
}
diff --git a/drivers/net/bnx2x/bnx2x_logs.h b/drivers/net/bnx2x/bnx2x_logs.h
index 9e232a9..753bccd 100644
--- a/drivers/net/bnx2x/bnx2x_logs.h
+++ b/drivers/net/bnx2x/bnx2x_logs.h
@@ -9,11 +9,11 @@
#define _PMD_LOGS_H_
extern int bnx2x_logtype_init;
-#define PMD_INIT_LOG(level, fmt, args...) \
- rte_log(RTE_LOG_ ## level, bnx2x_logtype_init, \
- "%s(): " fmt "\n", __func__, ##args)
+#define PMD_INIT_LOG(level, sc, fmt, args...) \
+ RTE_LOG(level, PMD, \
+ "[bnx2x_pmd: %s] %s() " fmt "\n", (sc)->devinfo.name, __func__, ##args)
-#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>")
+#define PMD_INIT_FUNC_TRACE(sc) PMD_INIT_LOG(DEBUG, sc, " >>")
#ifdef RTE_LIBRTE_BNX2X_DEBUG_RX
#define PMD_RX_LOG(level, fmt, args...) \
@@ -37,18 +37,19 @@
#endif
extern int bnx2x_logtype_driver;
-#define PMD_DRV_LOG_RAW(level, fmt, args...) \
- rte_log(RTE_LOG_ ## level, bnx2x_logtype_driver, \
- "%s(): " fmt, __func__, ## args)
+#define PMD_DRV_LOG_RAW(level, sc, fmt, args...) \
+ RTE_LOG(level, PMD, "[%s:%d(%s)] " fmt, __func__, __LINE__, \
+ (sc)->devinfo.name ? (sc)->devinfo.name : "", ## args)
-#define PMD_DRV_LOG(level, fmt, args...) \
- PMD_DRV_LOG_RAW(level, fmt "\n", ## args)
+#define PMD_DRV_LOG(level, sc, fmt, args...) \
+ PMD_DRV_LOG_RAW(level, sc, fmt "\n", ## args)
#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
-#define PMD_DEBUG_PERIODIC_LOG(level, fmt, args...) \
- RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
+#define PMD_DEBUG_PERIODIC_LOG(level, sc, fmt, args...) \
+ RTE_LOG(level, PMD, "%s(%s): " fmt "\n", __func__, \
+ (sc)->devinfo.name ? (sc)->devinfo.name : "", ## args)
#else
-#define PMD_DEBUG_PERIODIC_LOG(level, fmt, args...) do { } while(0)
+#define PMD_DEBUG_PERIODIC_LOG(level, sc, fmt, args...) do { } while (0)
#endif
#endif /* _PMD_LOGS_H_ */
diff --git a/drivers/net/bnx2x/bnx2x_rxtx.c b/drivers/net/bnx2x/bnx2x_rxtx.c
index d9a4127..589735e 100644
--- a/drivers/net/bnx2x/bnx2x_rxtx.c
+++ b/drivers/net/bnx2x/bnx2x_rxtx.c
@@ -76,7 +76,7 @@
rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct bnx2x_rx_queue),
RTE_CACHE_LINE_SIZE, socket_id);
if (NULL == rxq) {
- PMD_INIT_LOG(ERR, "rte_zmalloc for rxq failed!");
+ PMD_DRV_LOG(ERR, sc, "rte_zmalloc for rxq failed!");
return -ENOMEM;
}
rxq->sc = sc;
@@ -92,7 +92,7 @@
sc->rx_ring_size = USABLE_RX_BD(rxq);
rxq->nb_cq_pages = RCQ_BD_PAGES(rxq);
- PMD_INIT_LOG(DEBUG, "fp[%02d] req_bd=%u, usable_bd=%lu, "
+ PMD_DRV_LOG(DEBUG, sc, "fp[%02d] req_bd=%u, usable_bd=%lu, "
"total_bd=%lu, rx_pages=%u, cq_pages=%u",
queue_idx, nb_desc, (unsigned long)USABLE_RX_BD(rxq),
(unsigned long)TOTAL_RX_BD(rxq), rxq->nb_rx_pages,
@@ -275,7 +275,7 @@
txq->tx_free_thresh = min(txq->tx_free_thresh,
txq->nb_tx_desc - BDS_PER_TX_PKT);
- PMD_INIT_LOG(DEBUG, "fp[%02d] req_bd=%u, thresh=%u, usable_bd=%lu, "
+ PMD_DRV_LOG(DEBUG, sc, "fp[%02d] req_bd=%u, thresh=%u, usable_bd=%lu, "
"total_bd=%lu, tx_pages=%u",
queue_idx, nb_desc, txq->tx_free_thresh,
(unsigned long)USABLE_TX_BD(txq),
@@ -301,7 +301,7 @@
return -ENOMEM;
}
- /* PMD_DRV_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
+ /* PMD_DRV_LOG(DEBUG, sc, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr); */
/* Link TX pages */
@@ -310,7 +310,9 @@
busaddr = txq->tx_ring_phys_addr + BNX2X_PAGE_SIZE * (i % txq->nb_tx_pages);
tx_n_bd->addr_hi = rte_cpu_to_le_32(U64_HI(busaddr));
tx_n_bd->addr_lo = rte_cpu_to_le_32(U64_LO(busaddr));
- /* PMD_DRV_LOG(DEBUG, "link tx page %lu", (TOTAL_TX_BD_PER_PAGE * i - 1)); */
+ /* PMD_DRV_LOG(DEBUG, sc, "link tx page %lu",
+ * (TOTAL_TX_BD_PER_PAGE * i - 1));
+ */
}
txq->queue_id = queue_idx;
@@ -461,9 +463,10 @@
void
bnx2x_dev_clear_queues(struct rte_eth_dev *dev)
{
+ struct bnx2x_softc *sc = dev->data->dev_private;
uint8_t i;
- PMD_INIT_FUNC_TRACE();
+ PMD_INIT_FUNC_TRACE(sc);
for (i = 0; i < dev->data->nb_tx_queues; i++) {
struct bnx2x_tx_queue *txq = dev->data->tx_queues[i];
diff --git a/drivers/net/bnx2x/bnx2x_stats.c b/drivers/net/bnx2x/bnx2x_stats.c
index edc86cc..1cd9725 100644
--- a/drivers/net/bnx2x/bnx2x_stats.c
+++ b/drivers/net/bnx2x/bnx2x_stats.c
@@ -82,7 +82,7 @@
sc->fw_stats_req->hdr.drv_stats_counter =
htole16(sc->stats_counter++);
- PMD_DEBUG_PERIODIC_LOG(DEBUG,
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
"sending statistics ramrod %d",
le16toh(sc->fw_stats_req->hdr.drv_stats_counter));
@@ -154,7 +154,7 @@
while (*stats_comp != DMAE_COMP_VAL) {
if (!cnt) {
- PMD_DRV_LOG(ERR, "Timeout waiting for stats finished");
+ PMD_DRV_LOG(ERR, sc, "Timeout waiting for stats finished");
break;
}
@@ -189,7 +189,7 @@
}
/* sanity */
if (!sc->port.pmf || !sc->port.port_stx) {
- PMD_DRV_LOG(ERR, "BUG!");
+ PMD_DRV_LOG(ERR, sc, "BUG!");
return;
}
@@ -239,7 +239,7 @@
/* sanity */
if (!sc->link_vars.link_up || !sc->port.pmf) {
- PMD_DRV_LOG(ERR, "BUG!");
+ PMD_DRV_LOG(ERR, sc, "BUG!");
return;
}
@@ -463,7 +463,7 @@
/* sanity */
if (!sc->func_stx) {
- PMD_DRV_LOG(ERR, "BUG!");
+ PMD_DRV_LOG(ERR, sc, "BUG!");
return;
}
@@ -797,12 +797,12 @@
break;
case ELINK_MAC_TYPE_NONE: /* unreached */
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"stats updated by DMAE but no MAC active");
return -1;
default: /* unreached */
- PMD_DRV_LOG(ERR, "stats update failed, unknown MAC type");
+ PMD_DRV_LOG(ERR, sc, "stats update failed, unknown MAC type");
}
ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
@@ -837,7 +837,7 @@
nig_timer_max = SHMEM_RD(sc, port_mb[SC_PORT(sc)].stat_nig_timer);
if (nig_timer_max != estats->nig_timer_max) {
estats->nig_timer_max = nig_timer_max;
- PMD_DRV_LOG(ERR, "invalid NIG timer max (%u)",
+ PMD_DRV_LOG(ERR, sc, "invalid NIG timer max (%u)",
estats->nig_timer_max);
}
}
@@ -859,7 +859,7 @@
/* are storm stats valid? */
if (le16toh(counters->xstats_counter) != cur_stats_counter) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"stats not updated by xstorm, "
"counter 0x%x != stats_counter 0x%x",
le16toh(counters->xstats_counter), sc->stats_counter);
@@ -867,7 +867,7 @@
}
if (le16toh(counters->ustats_counter) != cur_stats_counter) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"stats not updated by ustorm, "
"counter 0x%x != stats_counter 0x%x",
le16toh(counters->ustats_counter), sc->stats_counter);
@@ -875,7 +875,7 @@
}
if (le16toh(counters->cstats_counter) != cur_stats_counter) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"stats not updated by cstorm, "
"counter 0x%x != stats_counter 0x%x",
le16toh(counters->cstats_counter), sc->stats_counter);
@@ -883,7 +883,7 @@
}
if (le16toh(counters->tstats_counter) != cur_stats_counter) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"stats not updated by tstorm, "
"counter 0x%x != stats_counter 0x%x",
le16toh(counters->tstats_counter), sc->stats_counter);
@@ -929,12 +929,13 @@
uint32_t diff;
- /* PMD_DRV_LOG(DEBUG,
+ /* PMD_DRV_LOG(DEBUG, sc,
"queue[%d]: ucast_sent 0x%x bcast_sent 0x%x mcast_sent 0x%x",
i, xclient->ucast_pkts_sent, xclient->bcast_pkts_sent,
xclient->mcast_pkts_sent);
- PMD_DRV_LOG(DEBUG, "---------------"); */
+ PMD_DRV_LOG(DEBUG, sc, "---------------");
+ */
UPDATE_QSTAT(tclient->rcv_bcast_bytes,
total_broadcast_bytes_received);
@@ -1288,7 +1289,7 @@ void bnx2x_stats_handle(struct bnx2x_softc *sc, enum bnx2x_stats_event event)
bnx2x_stats_stm[state][event].action(sc);
if (event != STATS_EVENT_UPDATE) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"state %d -> event %d -> state %d",
state, event, sc->stats_state);
}
@@ -1302,7 +1303,7 @@ void bnx2x_stats_handle(struct bnx2x_softc *sc, enum bnx2x_stats_event event)
/* sanity */
if (!sc->port.pmf || !sc->port.port_stx) {
- PMD_DRV_LOG(ERR, "BUG!");
+ PMD_DRV_LOG(ERR, sc, "BUG!");
return;
}
@@ -1474,7 +1475,7 @@ void bnx2x_memset_stats(struct bnx2x_softc *sc)
sc->func_stx = 0;
}
- PMD_DRV_LOG(DEBUG, "port_stx 0x%x func_stx 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "port_stx 0x%x func_stx 0x%x",
sc->port.port_stx, sc->func_stx);
/* pmf should retrieve port statistics from SP on a non-init*/
diff --git a/drivers/net/bnx2x/bnx2x_vfpf.c b/drivers/net/bnx2x/bnx2x_vfpf.c
index 50099d4..048bf12 100644
--- a/drivers/net/bnx2x/bnx2x_vfpf.c
+++ b/drivers/net/bnx2x/bnx2x_vfpf.c
@@ -37,12 +37,12 @@
if (bull->crc == bnx2x_vf_crc(bull))
break;
- PMD_DRV_LOG(ERR, "bad crc on bulletin board. contained %x computed %x",
+ PMD_DRV_LOG(ERR, sc, "bad crc on bulletin board. contained %x computed %x",
bull->crc, bnx2x_vf_crc(bull));
++tries;
}
if (tries == BNX2X_VF_BULLETIN_TRIES) {
- PMD_DRV_LOG(ERR, "pf to vf bulletin board crc was wrong %d consecutive times. Aborting",
+ PMD_DRV_LOG(ERR, sc, "pf to vf bulletin board crc was wrong %d consecutive times. Aborting",
tries);
return FALSE;
}
@@ -82,7 +82,7 @@
rte_spinlock_lock(&sc->vf2pf_lock);
- PMD_DRV_LOG(DEBUG, "Preparing %d tlv for sending", type);
+ PMD_DRV_LOG(DEBUG, sc, "Preparing %d tlv for sending", type);
memset(mbox, 0, sizeof(struct bnx2x_vf_mbx_msg));
@@ -97,7 +97,7 @@
bnx2x_vf_finalize(struct bnx2x_softc *sc,
__rte_unused struct vf_first_tlv *first_tlv)
{
- PMD_DRV_LOG(DEBUG, "done sending [%d] tlv over vf pf channel",
+ PMD_DRV_LOG(DEBUG, sc, "done sending [%d] tlv over vf pf channel",
first_tlv->tl.type);
rte_spinlock_unlock(&sc->vf2pf_lock);
@@ -116,14 +116,14 @@
uint8_t i;
if (*status) {
- PMD_DRV_LOG(ERR, "status should be zero before message"
+ PMD_DRV_LOG(ERR, sc, "status should be zero before message"
" to pf was sent");
return -EINVAL;
}
bnx2x_check_bull(sc);
if (sc->old_bulletin.valid_bitmap & (1 << CHANNEL_DOWN)) {
- PMD_DRV_LOG(ERR, "channel is down. Aborting message sending");
+ PMD_DRV_LOG(ERR, sc, "channel is down. Aborting message sending");
return -EINVAL;
}
@@ -143,11 +143,11 @@
}
if (!*status) {
- PMD_DRV_LOG(ERR, "Response from PF timed out");
+ PMD_DRV_LOG(ERR, sc, "Response from PF timed out");
return -EAGAIN;
}
- PMD_DRV_LOG(DEBUG, "Response from PF was received");
+ PMD_DRV_LOG(DEBUG, sc, "Response from PF was received");
return 0;
}
@@ -195,7 +195,7 @@ int bnx2x_loop_obtain_resources(struct bnx2x_softc *sc)
int rc;
do {
- PMD_DRV_LOG(DEBUG, "trying to get resources");
+ PMD_DRV_LOG(DEBUG, sc, "trying to get resources");
rc = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
if (rc)
@@ -207,11 +207,11 @@ int bnx2x_loop_obtain_resources(struct bnx2x_softc *sc)
/* check PF to request acceptance */
if (sc_resp->status == BNX2X_VF_STATUS_SUCCESS) {
- PMD_DRV_LOG(DEBUG, "resources obtained successfully");
+ PMD_DRV_LOG(DEBUG, sc, "resources obtained successfully");
res_obtained = true;
} else if (sc_resp->status == BNX2X_VF_STATUS_NO_RESOURCES &&
tries < BNX2X_VF_OBTAIN_MAX_TRIES) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"PF cannot allocate requested amount of resources");
res_query = &sc->vf2pf_mbox->query[0].acquire.res_query;
@@ -227,7 +227,7 @@ int bnx2x_loop_obtain_resources(struct bnx2x_softc *sc)
memset(&sc->vf2pf_mbox->resp, 0, sizeof(union resp_tlvs));
} else {
- PMD_DRV_LOG(ERR, "Failed to get the requested "
+ PMD_DRV_LOG(ERR, sc, "Failed to get the requested "
"amount of resources: %d.",
sc_resp->status);
return -EINVAL;
@@ -296,7 +296,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
sc->doorbell_size = sc_resp.db_size;
sc->flags |= BNX2X_NO_WOL_FLAG | BNX2X_NO_ISCSI_OOO_FLAG | BNX2X_NO_ISCSI_FLAG | BNX2X_NO_FCOE_FLAG;
- PMD_DRV_LOG(DEBUG, "status block count = %d, base status block = %x",
+ PMD_DRV_LOG(DEBUG, sc, "status block count = %d, base status block = %x",
sc->igu_sb_cnt, sc->igu_base_sb);
strncpy(sc->fw_ver, sc_resp.fw_ver, sizeof(sc->fw_ver));
@@ -333,7 +333,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
rc = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
if (rc || reply->status != BNX2X_VF_STATUS_SUCCESS)
- PMD_DRV_LOG(ERR, "Failed to release VF");
+ PMD_DRV_LOG(ERR, sc, "Failed to release VF");
bnx2x_vf_finalize(sc, &query->first_tlv);
}
@@ -367,12 +367,12 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
if (rc)
goto out;
if (reply->status != BNX2X_VF_STATUS_SUCCESS) {
- PMD_DRV_LOG(ERR, "Failed to init VF");
+ PMD_DRV_LOG(ERR, sc, "Failed to init VF");
rc = -EINVAL;
goto out;
}
- PMD_DRV_LOG(DEBUG, "VF was initialized");
+ PMD_DRV_LOG(DEBUG, sc, "VF was initialized");
out:
bnx2x_vf_finalize(sc, &query->first_tlv);
return rc;
@@ -403,7 +403,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
rc = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
if (rc || reply->status != BNX2X_VF_STATUS_SUCCESS)
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Bad reply for vf_q %d teardown", i);
bnx2x_vf_finalize(sc, &query_op->first_tlv);
@@ -423,7 +423,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
rc = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
if (rc || reply->status != BNX2X_VF_STATUS_SUCCESS)
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Bad reply from PF for close message");
bnx2x_vf_finalize(sc, &query->first_tlv);
@@ -450,7 +450,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
rxq = sc->rx_queues[fp->index];
if (!rxq) {
- PMD_DRV_LOG(ERR, "RX queue %d is NULL", fp->index);
+ PMD_DRV_LOG(ERR, sc, "RX queue %d is NULL", fp->index);
return;
}
@@ -474,7 +474,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
txq = sc->tx_queues[fp->index];
if (!txq) {
- PMD_DRV_LOG(ERR, "TX queue %d is NULL", fp->index);
+ PMD_DRV_LOG(ERR, sc, "TX queue %d is NULL", fp->index);
return;
}
@@ -511,7 +511,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
if (rc)
goto out;
if (reply->status != BNX2X_VF_STATUS_SUCCESS) {
- PMD_DRV_LOG(ERR, "Failed to setup VF queue[%d]",
+ PMD_DRV_LOG(ERR, sc, "Failed to setup VF queue[%d]",
fp->index);
rc = -EINVAL;
}
@@ -566,7 +566,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
}
if (BNX2X_VF_STATUS_SUCCESS != reply->status) {
- PMD_DRV_LOG(ERR, "Bad reply from PF for SET MAC message: %d",
+ PMD_DRV_LOG(ERR, sc, "Bad reply from PF for SET MAC message: %d",
reply->status);
rc = -EINVAL;
}
@@ -608,7 +608,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
goto out;
if (reply->status != BNX2X_VF_STATUS_SUCCESS) {
- PMD_DRV_LOG(ERR, "Failed to configure RSS");
+ PMD_DRV_LOG(ERR, sc, "Failed to configure RSS");
rc = -EINVAL;
}
out:
@@ -652,7 +652,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
query->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
break;
default:
- PMD_DRV_LOG(ERR, "BAD rx mode (%d)", sc->rx_mode);
+ PMD_DRV_LOG(ERR, sc, "BAD rx mode (%d)", sc->rx_mode);
rc = -EINVAL;
goto out;
}
@@ -666,7 +666,7 @@ int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_
goto out;
if (reply->status != BNX2X_VF_STATUS_SUCCESS) {
- PMD_DRV_LOG(ERR, "Failed to set RX mode");
+ PMD_DRV_LOG(ERR, sc, "Failed to set RX mode");
rc = -EINVAL;
}
diff --git a/drivers/net/bnx2x/ecore_init.h b/drivers/net/bnx2x/ecore_init.h
index f2de07e..97dfe69 100644
--- a/drivers/net/bnx2x/ecore_init.h
+++ b/drivers/net/bnx2x/ecore_init.h
@@ -741,7 +741,7 @@ static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
if (dis_mask) {
REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
dis_mask);
- ECORE_MSG("Setting parity mask "
+ ECORE_MSG(sc, "Setting parity mask "
"for %s to\t\t0x%x",
ecore_blocks_parity_data[i].name, dis_mask);
}
@@ -776,7 +776,7 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
reg_val = REG_RD(sc, ecore_blocks_parity_data[i].
sts_clr_addr);
if (reg_val & reg_mask)
- ECORE_MSG("Parity errors in %s: 0x%x",
+ ECORE_MSG(sc, "Parity errors in %s: 0x%x",
ecore_blocks_parity_data[i].name,
reg_val & reg_mask);
}
@@ -785,7 +785,7 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
/* Check if there were parity attentions in MCP */
reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);
if (reg_val & mcp_aeu_bits)
- ECORE_MSG("Parity error in MCP: 0x%x",
+ ECORE_MSG(sc, "Parity error in MCP: 0x%x",
reg_val & mcp_aeu_bits);
/* Clear parity attentions in MCP:
diff --git a/drivers/net/bnx2x/ecore_init_ops.h b/drivers/net/bnx2x/ecore_init_ops.h
index 2b003af..733ad1a 100644
--- a/drivers/net/bnx2x/ecore_init_ops.h
+++ b/drivers/net/bnx2x/ecore_init_ops.h
@@ -424,20 +424,20 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,
uint32_t val, i;
if (r_order > MAX_RD_ORD) {
- ECORE_MSG("read order of %d order adjusted to %d",
+ ECORE_MSG(sc, "read order of %d order adjusted to %d",
r_order, MAX_RD_ORD);
r_order = MAX_RD_ORD;
}
if (w_order > MAX_WR_ORD) {
- ECORE_MSG("write order of %d order adjusted to %d",
+ ECORE_MSG(sc, "write order of %d order adjusted to %d",
w_order, MAX_WR_ORD);
w_order = MAX_WR_ORD;
}
if (CHIP_REV_IS_FPGA(sc)) {
- ECORE_MSG("write order adjusted to 1 for FPGA");
+ ECORE_MSG(sc, "write order adjusted to 1 for FPGA");
w_order = 0;
}
- ECORE_MSG("read order %d write order %d", r_order, w_order);
+ ECORE_MSG(sc, "read order %d write order %d", r_order, w_order);
for (i = 0; i < NUM_RD_Q-1; i++) {
REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
diff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c
index 0c8685c..ab730ab 100644
--- a/drivers/net/bnx2x/ecore_sp.c
+++ b/drivers/net/bnx2x/ecore_sp.c
@@ -53,14 +53,14 @@
o->execute = exec;
o->get = get;
- ECORE_MSG("Setup the execution queue with the chunk length of %d",
+ ECORE_MSG(sc, "Setup the execution queue with the chunk length of %d",
exe_len);
}
static void ecore_exe_queue_free_elem(struct bnx2x_softc *sc __rte_unused,
struct ecore_exeq_elem *elem)
{
- ECORE_MSG("Deleting an exe_queue element");
+ ECORE_MSG(sc, "Deleting an exe_queue element");
ECORE_FREE(sc, elem, sizeof(*elem));
}
@@ -106,7 +106,7 @@ static int ecore_exe_queue_add(struct bnx2x_softc *sc,
/* Check if this request is ok */
rc = o->validate(sc, o->owner, elem);
if (rc) {
- ECORE_MSG("Preamble failed: %d", rc);
+ ECORE_MSG(sc, "Preamble failed: %d", rc);
goto free_and_exit;
}
}
@@ -176,8 +176,8 @@ static int ecore_exe_queue_step(struct bnx2x_softc *sc,
*/
if (!ECORE_LIST_IS_EMPTY(&o->pending_comp)) {
if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
- ECORE_MSG
- ("RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list");
+ ECORE_MSG(sc,
+ "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list");
__ecore_exe_queue_reset_pending(sc, o);
} else {
return ECORE_PENDING;
@@ -240,7 +240,7 @@ static struct ecore_exeq_elem *ecore_exe_queue_alloc_elem(struct
bnx2x_softc *sc
__rte_unused)
{
- ECORE_MSG("Allocating a new exe_queue element");
+ ECORE_MSG(sc, "Allocating a new exe_queue element");
return ECORE_ZALLOC(sizeof(struct ecore_exeq_elem), GFP_ATOMIC, sc);
}
@@ -290,14 +290,14 @@ static int ecore_state_wait(struct bnx2x_softc *sc, int state,
if (CHIP_REV_IS_EMUL(sc))
cnt *= 20;
- ECORE_MSG("waiting for state to become %d", state);
+ ECORE_MSG(sc, "waiting for state to become %d", state);
ECORE_MIGHT_SLEEP();
while (cnt--) {
bnx2x_intr_legacy(sc, 1);
if (!ECORE_TEST_BIT(state, pstate)) {
#ifdef ECORE_STOP_ON_ERROR
- ECORE_MSG("exit (cnt %d)", 5000 - cnt);
+ ECORE_MSG(sc, "exit (cnt %d)", 5000 - cnt);
#endif
return ECORE_SUCCESS;
}
@@ -309,7 +309,7 @@ static int ecore_state_wait(struct bnx2x_softc *sc, int state,
}
/* timeout! */
- PMD_DRV_LOG(ERR, "timeout waiting for state %d", state);
+ PMD_DRV_LOG(ERR, sc, "timeout waiting for state %d", state);
#ifdef ECORE_STOP_ON_ERROR
ecore_panic();
#endif
@@ -370,11 +370,11 @@ static int __ecore_vlan_mac_h_write_trylock(struct bnx2x_softc *sc __rte_unused,
struct ecore_vlan_mac_obj *o)
{
if (o->head_reader) {
- ECORE_MSG("vlan_mac_lock writer - There are readers; Busy");
+ ECORE_MSG(sc, "vlan_mac_lock writer - There are readers; Busy");
return ECORE_BUSY;
}
- ECORE_MSG("vlan_mac_lock writer - Taken");
+ ECORE_MSG(sc, "vlan_mac_lock writer - Taken");
return ECORE_SUCCESS;
}
@@ -394,13 +394,13 @@ static void __ecore_vlan_mac_h_exec_pending(struct bnx2x_softc *sc,
int rc;
unsigned long ramrod_flags = o->saved_ramrod_flags;
- ECORE_MSG("vlan_mac_lock execute pending command with ramrod flags %lu",
+ ECORE_MSG(sc, "vlan_mac_lock execute pending command with ramrod flags %lu",
ramrod_flags);
o->head_exe_request = FALSE;
o->saved_ramrod_flags = 0;
rc = ecore_exe_queue_step(sc, &o->exe_queue, &ramrod_flags);
if (rc != ECORE_SUCCESS) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"execution of pending commands failed with rc %d",
rc);
#ifdef ECORE_STOP_ON_ERROR
@@ -425,7 +425,7 @@ static void __ecore_vlan_mac_h_pend(struct bnx2x_softc *sc __rte_unused,
{
o->head_exe_request = TRUE;
o->saved_ramrod_flags = ramrod_flags;
- ECORE_MSG("Placing pending execution with ramrod flags %lu",
+ ECORE_MSG(sc, "Placing pending execution with ramrod flags %lu",
ramrod_flags);
}
@@ -446,8 +446,8 @@ static void __ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc,
* executed. If so, execute again. [Ad infinitum]
*/
while (o->head_exe_request) {
- ECORE_MSG
- ("vlan_mac_lock - writer release encountered a pending request");
+ ECORE_MSG(sc,
+ "vlan_mac_lock - writer release encountered a pending request");
__ecore_vlan_mac_h_exec_pending(sc, o);
}
}
@@ -483,7 +483,8 @@ static int __ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc __rte_unused,
{
/* If we got here, we're holding lock --> no WRITER exists */
o->head_reader++;
- ECORE_MSG("vlan_mac_lock - locked reader - number %d", o->head_reader);
+ ECORE_MSG(sc,
+ "vlan_mac_lock - locked reader - number %d", o->head_reader);
return ECORE_SUCCESS;
}
@@ -522,14 +523,14 @@ static void __ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,
struct ecore_vlan_mac_obj *o)
{
if (!o->head_reader) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Need to release vlan mac reader lock, but lock isn't taken");
#ifdef ECORE_STOP_ON_ERROR
ecore_panic();
#endif
} else {
o->head_reader--;
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"vlan_mac_lock - decreased readers to %d",
o->head_reader);
}
@@ -538,7 +539,7 @@ static void __ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,
* was last - if so we need to execute the command.
*/
if (!o->head_reader && o->head_exe_request) {
- PMD_DRV_LOG(INFO,
+ PMD_DRV_LOG(INFO, sc,
"vlan_mac_lock - reader release encountered a pending request");
/* Writer release will do the trick */
@@ -581,10 +582,10 @@ static int ecore_get_n_elements(struct bnx2x_softc *sc,
uint8_t *next = base;
int counter = 0, read_lock;
- ECORE_MSG("get_n_elements - taking vlan_mac_lock (reader)");
+ ECORE_MSG(sc, "get_n_elements - taking vlan_mac_lock (reader)");
read_lock = ecore_vlan_mac_h_read_lock(sc, o);
if (read_lock != ECORE_SUCCESS)
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"get_n_elements failed to get vlan mac reader lock; Access without lock");
/* traverse list */
@@ -593,15 +594,15 @@ static int ecore_get_n_elements(struct bnx2x_softc *sc,
if (counter < n) {
ECORE_MEMCPY(next, &pos->u, size);
counter++;
- ECORE_MSG
- ("copied element number %d to address %p element was:",
+ ECORE_MSG
+ (sc, "copied element number %d to address %p element was:",
counter, next);
next += stride + size;
}
}
if (read_lock == ECORE_SUCCESS) {
- ECORE_MSG("get_n_elements - releasing vlan_mac_lock (reader)");
+ ECORE_MSG(sc, "get_n_elements - releasing vlan_mac_lock (reader)");
ecore_vlan_mac_h_read_unlock(sc, o);
}
@@ -615,7 +616,7 @@ static int ecore_check_mac_add(struct bnx2x_softc *sc __rte_unused,
{
struct ecore_vlan_mac_registry_elem *pos;
- ECORE_MSG("Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for ADD command",
+ ECORE_MSG(sc, "Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for ADD command",
data->mac.mac[0], data->mac.mac[1], data->mac.mac[2],
data->mac.mac[3], data->mac.mac[4], data->mac.mac[5]);
@@ -644,7 +645,7 @@ static struct ecore_vlan_mac_registry_elem *ecore_check_mac_del(struct bnx2x_sof
{
struct ecore_vlan_mac_registry_elem *pos;
- ECORE_MSG("Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for DEL command",
+ ECORE_MSG(sc, "Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for DEL command",
data->mac.mac[0], data->mac.mac[1], data->mac.mac[2],
data->mac.mac[3], data->mac.mac[4], data->mac.mac[5]);
@@ -722,7 +723,7 @@ static void ecore_set_mac_in_nig(struct bnx2x_softc *sc,
if (index > ECORE_LLH_CAM_MAX_PF_LINE)
return;
- ECORE_MSG("Going to %s LLH configuration at entry %d",
+ ECORE_MSG(sc, "Going to %s LLH configuration at entry %d",
(add ? "ADD" : "DELETE"), index);
if (add) {
@@ -838,7 +839,7 @@ static void ecore_set_one_mac_e2(struct bnx2x_softc *sc,
ecore_vlan_mac_set_cmd_hdr_e2(o, add, CLASSIFY_RULE_OPCODE_MAC,
&rule_entry->mac.header);
- ECORE_MSG("About to %s MAC %02x:%02x:%02x:%02x:%02x:%02x for Queue %d",
+ ECORE_MSG(sc, "About to %s MAC %02x:%02x:%02x:%02x:%02x:%02x for Queue %d",
(add ? "add" : "delete"), mac[0], mac[1], mac[2], mac[3],
mac[4], mac[5], raw->cl_id);
@@ -943,7 +944,7 @@ static void ecore_vlan_mac_set_rdata_e1x(struct bnx2x_softc *sc
ecore_vlan_mac_set_cfg_entry_e1x(o, add, opcode, mac, vlan_id,
cfg_entry);
- ECORE_MSG("%s MAC %02x:%02x:%02x:%02x:%02x:%02x CLID %d CAM offset %d",
+ ECORE_MSG(sc, "%s MAC %02x:%02x:%02x:%02x:%02x:%02x CLID %d CAM offset %d",
(add ? "setting" : "clearing"),
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
o->raw.cl_id, cam_offset);
@@ -1088,8 +1089,8 @@ static int ecore_validate_vlan_mac_add(struct bnx2x_softc *sc,
/* Check the registry */
rc = o->check_add(sc, o, &elem->cmd_data.vlan_mac.u);
if (rc) {
- ECORE_MSG
- ("ADD command is not allowed considering current registry state.");
+ ECORE_MSG(sc,
+ "ADD command is not allowed considering current registry state.");
return rc;
}
@@ -1097,7 +1098,7 @@ static int ecore_validate_vlan_mac_add(struct bnx2x_softc *sc,
* MAC/VLAN/VLAN-MAC. Return an error if there is.
*/
if (exeq->get(exeq, elem)) {
- ECORE_MSG("There is a pending ADD command already");
+ ECORE_MSG(sc, "There is a pending ADD command already");
return ECORE_EXISTS;
}
@@ -1136,8 +1137,8 @@ static int ecore_validate_vlan_mac_del(struct bnx2x_softc *sc,
*/
pos = o->check_del(sc, o, &elem->cmd_data.vlan_mac.u);
if (!pos) {
- ECORE_MSG
- ("DEL command is not allowed considering current registry state");
+ ECORE_MSG(sc,
+ "DEL command is not allowed considering current registry state");
return ECORE_EXISTS;
}
@@ -1149,13 +1150,13 @@ static int ecore_validate_vlan_mac_del(struct bnx2x_softc *sc,
/* Check for MOVE commands */
query_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_MOVE;
if (exeq->get(exeq, &query_elem)) {
- PMD_DRV_LOG(ERR, "There is a pending MOVE command already");
+ PMD_DRV_LOG(ERR, sc, "There is a pending MOVE command already");
return ECORE_INVAL;
}
/* Check for DEL commands */
if (exeq->get(exeq, elem)) {
- ECORE_MSG("There is a pending DEL command already");
+ ECORE_MSG(sc, "There is a pending DEL command already");
return ECORE_EXISTS;
}
@@ -1163,7 +1164,7 @@ static int ecore_validate_vlan_mac_del(struct bnx2x_softc *sc,
if (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,
&elem->cmd_data.vlan_mac.vlan_mac_flags) ||
o->put_credit(o))) {
- PMD_DRV_LOG(ERR, "Failed to return a credit");
+ PMD_DRV_LOG(ERR, sc, "Failed to return a credit");
return ECORE_INVAL;
}
@@ -1196,8 +1197,8 @@ static int ecore_validate_vlan_mac_move(struct bnx2x_softc *sc,
* state.
*/
if (!src_o->check_move(sc, src_o, dest_o, &elem->cmd_data.vlan_mac.u)) {
- ECORE_MSG
- ("MOVE command is not allowed considering current registry state");
+ ECORE_MSG(sc,
+ "MOVE command is not allowed considering current registry state");
return ECORE_INVAL;
}
@@ -1210,21 +1211,21 @@ static int ecore_validate_vlan_mac_move(struct bnx2x_softc *sc,
/* Check DEL on source */
query_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_DEL;
if (src_exeq->get(src_exeq, &query_elem)) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"There is a pending DEL command on the source queue already");
return ECORE_INVAL;
}
/* Check MOVE on source */
if (src_exeq->get(src_exeq, elem)) {
- ECORE_MSG("There is a pending MOVE command already");
+ ECORE_MSG(sc, "There is a pending MOVE command already");
return ECORE_EXISTS;
}
/* Check ADD on destination */
query_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_ADD;
if (dest_exeq->get(dest_exeq, &query_elem)) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"There is a pending ADD command on the destination queue already");
return ECORE_INVAL;
}
@@ -1329,7 +1330,7 @@ static int __ecore_vlan_mac_execute_step(struct bnx2x_softc *sc,
ECORE_SPIN_LOCK_BH(&o->exe_queue.lock);
- ECORE_MSG("vlan_mac_execute_step - trying to take writer lock");
+ ECORE_MSG(sc, "vlan_mac_execute_step - trying to take writer lock");
rc = __ecore_vlan_mac_h_write_trylock(sc, o);
if (rc != ECORE_SUCCESS) {
@@ -1426,17 +1427,17 @@ static int ecore_optimize_vlan_mac(struct bnx2x_softc *sc,
&pos->cmd_data.vlan_mac.vlan_mac_flags)) {
if ((query.cmd_data.vlan_mac.cmd ==
ECORE_VLAN_MAC_ADD) && !o->put_credit(o)) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Failed to return the credit for the optimized ADD command");
return ECORE_INVAL;
} else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Failed to recover the credit from the optimized DEL command");
return ECORE_INVAL;
}
}
- ECORE_MSG("Optimizing %s command",
+ ECORE_MSG(sc, "Optimizing %s command",
(elem->cmd_data.vlan_mac.cmd == ECORE_VLAN_MAC_ADD) ?
"ADD" : "DEL");
@@ -1486,7 +1487,7 @@ static int ecore_vlan_mac_get_registry_elem(struct bnx2x_softc *sc,
return ECORE_INVAL;
}
- ECORE_MSG("Got cam offset %d", reg_elem->cam_offset);
+ ECORE_MSG(sc, "Got cam offset %d", reg_elem->cam_offset);
/* Set a VLAN-MAC data */
ECORE_MEMCPY(®_elem->u, &elem->cmd_data.vlan_mac.u,
@@ -1695,8 +1696,8 @@ int ecore_config_vlan_mac(struct bnx2x_softc *sc,
rc = ECORE_PENDING;
if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
- ECORE_MSG
- ("RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.");
+ ECORE_MSG(sc,
+ "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.");
raw->clear_pending(raw);
}
@@ -1775,7 +1776,7 @@ static int ecore_vlan_mac_del_all(struct bnx2x_softc *sc,
*vlan_mac_flags) {
rc = exeq->remove(sc, exeq->owner, exeq_pos);
if (rc) {
- PMD_DRV_LOG(ERR, "Failed to remove command");
+ PMD_DRV_LOG(ERR, sc, "Failed to remove command");
ECORE_SPIN_UNLOCK_BH(&exeq->lock);
return rc;
}
@@ -1800,7 +1801,7 @@ static int ecore_vlan_mac_del_all(struct bnx2x_softc *sc,
ECORE_CLEAR_BIT_NA(RAMROD_EXEC, &p.ramrod_flags);
ECORE_CLEAR_BIT_NA(RAMROD_CONT, &p.ramrod_flags);
- ECORE_MSG("vlan_mac_del_all -- taking vlan_mac_lock (reader)");
+ ECORE_MSG(sc, "vlan_mac_del_all -- taking vlan_mac_lock (reader)");
read_lock = ecore_vlan_mac_h_read_lock(sc, o);
if (read_lock != ECORE_SUCCESS)
return read_lock;
@@ -1812,7 +1813,7 @@ static int ecore_vlan_mac_del_all(struct bnx2x_softc *sc,
ECORE_MEMCPY(&p.user_req.u, &pos->u, sizeof(pos->u));
rc = ecore_config_vlan_mac(sc, &p);
if (rc < 0) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Failed to add a new DEL command");
ecore_vlan_mac_h_read_unlock(sc, o);
return rc;
@@ -1820,7 +1821,7 @@ static int ecore_vlan_mac_del_all(struct bnx2x_softc *sc,
}
}
- ECORE_MSG("vlan_mac_del_all -- releasing vlan_mac_lock (reader)");
+ ECORE_MSG(sc, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)");
ecore_vlan_mac_h_read_unlock(sc, o);
p.ramrod_flags = *ramrod_flags;
@@ -2007,7 +2008,7 @@ static int ecore_set_rx_mode_e1x(struct bnx2x_softc *sc,
mac_filters->unmatched_unicast | mask :
mac_filters->unmatched_unicast & ~mask;
- ECORE_MSG("drop_ucast 0x%xdrop_mcast 0x%x accp_ucast 0x%x"
+ ECORE_MSG(sc, "drop_ucast 0x%xdrop_mcast 0x%x accp_ucast 0x%x"
"accp_mcast 0x%xaccp_bcast 0x%x",
mac_filters->ucast_drop_all, mac_filters->mcast_drop_all,
mac_filters->ucast_accept_all, mac_filters->mcast_accept_all,
@@ -2153,8 +2154,8 @@ static int ecore_set_rx_mode_e2(struct bnx2x_softc *sc,
*/
ecore_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx);
- ECORE_MSG
- ("About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx",
+ ECORE_MSG
+ (sc, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx",
data->header.rule_cnt, p->rx_accept_flags, p->tx_accept_flags);
/* No need for an explicit memory barrier here as long we would
@@ -2207,7 +2208,7 @@ int ecore_config_rx_mode(struct bnx2x_softc *sc,
return rc;
}
} else {
- ECORE_MSG("ERROR: config_rx_mode is NULL");
+ ECORE_MSG(sc, "ERROR: config_rx_mode is NULL");
return -1;
}
@@ -2288,7 +2289,7 @@ static int ecore_mcast_enqueue_cmd(struct bnx2x_softc *sc __rte_unused,
if (!new_cmd)
return ECORE_NOMEM;
- ECORE_MSG("About to enqueue a new %d command. macs_list_len=%d",
+ ECORE_MSG(sc, "About to enqueue a new %d command. macs_list_len=%d",
cmd, macs_list_len);
ECORE_LIST_INIT(&new_cmd->data.macs_head);
@@ -2324,7 +2325,7 @@ static int ecore_mcast_enqueue_cmd(struct bnx2x_softc *sc __rte_unused,
default:
ECORE_FREE(sc, new_cmd, total_sz);
- PMD_DRV_LOG(ERR, "Unknown command: %d", cmd);
+ PMD_DRV_LOG(ERR, sc, "Unknown command: %d", cmd);
return ECORE_INVAL;
}
@@ -2436,11 +2437,11 @@ static void ecore_mcast_set_one_rule_e2(struct bnx2x_softc *sc __rte_unused,
break;
default:
- PMD_DRV_LOG(ERR, "Unknown command: %d", cmd);
+ PMD_DRV_LOG(ERR, sc, "Unknown command: %d", cmd);
return;
}
- ECORE_MSG("%s bin %d",
+ ECORE_MSG(sc, "%s bin %d",
((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ?
"Setting" : "Clearing"), bin);
@@ -2475,7 +2476,7 @@ static int ecore_mcast_handle_restore_cmd_e2(struct bnx2x_softc *sc,
cnt++;
- ECORE_MSG("About to configure a bin %d", cur_bin);
+ ECORE_MSG(sc, "About to configure a bin %d", cur_bin);
/* Break if we reached the maximum number
* of rules.
@@ -2507,8 +2508,8 @@ static void ecore_mcast_hdl_pending_add_e2(struct bnx2x_softc *sc,
cnt++;
- ECORE_MSG
- ("About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC",
+ ECORE_MSG
+ (sc, "About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC",
pmac_pos->mac[0], pmac_pos->mac[1], pmac_pos->mac[2],
pmac_pos->mac[3], pmac_pos->mac[4], pmac_pos->mac[5]);
@@ -2543,7 +2544,7 @@ static void ecore_mcast_hdl_pending_del_e2(struct bnx2x_softc *sc,
cmd_pos->data.macs_num--;
- ECORE_MSG("Deleting MAC. %d left,cnt is %d",
+ ECORE_MSG(sc, "Deleting MAC. %d left,cnt is %d",
cmd_pos->data.macs_num, cnt);
/* Break if we reached the maximum
@@ -2602,7 +2603,8 @@ static int ecore_mcast_handle_pending_cmds_e2(struct bnx2x_softc *sc, struct
break;
default:
- PMD_DRV_LOG(ERR, "Unknown command: %d", cmd_pos->type);
+ PMD_DRV_LOG(ERR, sc,
+ "Unknown command: %d", cmd_pos->type);
return ECORE_INVAL;
}
@@ -2639,8 +2641,8 @@ static void ecore_mcast_hdl_add(struct bnx2x_softc *sc,
cnt++;
- ECORE_MSG
- ("About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC",
+ ECORE_MSG
+ (sc, "About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC",
mlist_pos->mac[0], mlist_pos->mac[1], mlist_pos->mac[2],
mlist_pos->mac[3], mlist_pos->mac[4], mlist_pos->mac[5]);
}
@@ -2660,7 +2662,8 @@ static void ecore_mcast_hdl_del(struct bnx2x_softc *sc,
cnt++;
- ECORE_MSG("Deleting MAC. %d left", p->mcast_list_len - i - 1);
+ ECORE_MSG(sc,
+ "Deleting MAC. %d left", p->mcast_list_len - i - 1);
}
*line_idx = cnt;
@@ -2686,7 +2689,7 @@ static int ecore_mcast_handle_current_cmd(struct bnx2x_softc *sc, struct
struct ecore_mcast_obj *o = p->mcast_obj;
int cnt = start_cnt;
- ECORE_MSG("p->mcast_list_len=%d", p->mcast_list_len);
+ ECORE_MSG(sc, "p->mcast_list_len=%d", p->mcast_list_len);
switch (cmd) {
case ECORE_MCAST_CMD_ADD:
@@ -2702,7 +2705,7 @@ static int ecore_mcast_handle_current_cmd(struct bnx2x_softc *sc, struct
break;
default:
- PMD_DRV_LOG(ERR, "Unknown command: %d", cmd);
+ PMD_DRV_LOG(ERR, sc, "Unknown command: %d", cmd);
return ECORE_INVAL;
}
@@ -2747,7 +2750,7 @@ static int ecore_mcast_validate_e2(__rte_unused struct bnx2x_softc *sc,
break;
default:
- PMD_DRV_LOG(ERR, "Unknown command: %d", cmd);
+ PMD_DRV_LOG(ERR, sc, "Unknown command: %d", cmd);
return ECORE_INVAL;
}
@@ -2933,8 +2936,8 @@ static void ecore_mcast_hdl_add_e1h(struct bnx2x_softc *sc __rte_unused,
bit = ecore_mcast_bin_from_mac(mlist_pos->mac);
ECORE_57711_SET_MC_FILTER(mc_filter, bit);
- ECORE_MSG
- ("About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC, bin %d",
+ ECORE_MSG
+ (sc, "About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC, bin %d",
mlist_pos->mac[0], mlist_pos->mac[1], mlist_pos->mac[2],
mlist_pos->mac[3], mlist_pos->mac[4], mlist_pos->mac[5],
bit);
@@ -2954,7 +2957,7 @@ static void ecore_mcast_hdl_restore_e1h(struct bnx2x_softc *sc
for (bit = ecore_mcast_get_next_bin(o, 0);
bit >= 0; bit = ecore_mcast_get_next_bin(o, bit + 1)) {
ECORE_57711_SET_MC_FILTER(mc_filter, bit);
- ECORE_MSG("About to set bin %d", bit);
+ ECORE_MSG(sc, "About to set bin %d", bit);
}
}
@@ -2985,7 +2988,7 @@ static int ecore_mcast_setup_e1h(struct bnx2x_softc *sc,
break;
case ECORE_MCAST_CMD_DEL:
- ECORE_MSG("Invalidating multicast MACs configuration");
+ ECORE_MSG(sc, "Invalidating multicast MACs configuration");
/* clear the registry */
ECORE_MEMSET(o->registry.aprox_match.vec, 0,
@@ -2997,7 +3000,7 @@ static int ecore_mcast_setup_e1h(struct bnx2x_softc *sc,
break;
default:
- PMD_DRV_LOG(ERR, "Unknown command: %d", cmd);
+ PMD_DRV_LOG(ERR, sc, "Unknown command: %d", cmd);
return ECORE_INVAL;
}
@@ -3048,8 +3051,8 @@ int ecore_config_mcast(struct bnx2x_softc *sc,
if ((!p->mcast_list_len) && (!o->check_sched(o)))
return ECORE_SUCCESS;
- ECORE_MSG
- ("o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d",
+ ECORE_MSG
+ (sc, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d",
o->total_pending_num, p->mcast_list_len, o->max_cmd_len);
/* Enqueue the current command to the pending list if we can't complete
@@ -3478,7 +3481,7 @@ static int ecore_setup_rss(struct bnx2x_softc *sc,
ECORE_MEMSET(data, 0, sizeof(*data));
- ECORE_MSG("Configuring RSS");
+ ECORE_MSG(sc, "Configuring RSS");
/* Set an echo field */
data->echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) |
@@ -3492,7 +3495,7 @@ static int ecore_setup_rss(struct bnx2x_softc *sc,
data->rss_mode = rss_mode;
- ECORE_MSG("rss_mode=%d", rss_mode);
+ ECORE_MSG(sc, "rss_mode=%d", rss_mode);
/* RSS capabilities */
if (ECORE_TEST_BIT(ECORE_RSS_IPV4, &p->rss_flags))
@@ -3532,7 +3535,7 @@ static int ecore_setup_rss(struct bnx2x_softc *sc,
/* RSS engine ID */
data->rss_engine_id = o->engine_id;
- ECORE_MSG("rss_engine_id=%d", data->rss_engine_id);
+ ECORE_MSG(sc, "rss_engine_id=%d", data->rss_engine_id);
/* Indirection table */
ECORE_MEMCPY(data->indirection_table, p->ind_table,
@@ -3627,15 +3630,15 @@ int ecore_queue_state_change(struct bnx2x_softc *sc,
/* Check that the requested transition is legal */
rc = o->check_transition(sc, o, params);
if (rc) {
- PMD_DRV_LOG(ERR, "check transition returned an error. rc %d",
+ PMD_DRV_LOG(ERR, sc, "check transition returned an error. rc %d",
rc);
return ECORE_INVAL;
}
/* Set "pending" bit */
- ECORE_MSG("pending bit was=%lx", o->pending);
+ ECORE_MSG(sc, "pending bit was=%lx", o->pending);
pending_bit = o->set_pending(o, params);
- ECORE_MSG("pending bit now=%lx", o->pending);
+ ECORE_MSG(sc, "pending bit now=%lx", o->pending);
/* Don't send a command if only driver cleanup was requested */
if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags))
@@ -3702,7 +3705,7 @@ static int ecore_queue_comp_cmd(struct bnx2x_softc *sc __rte_unused,
unsigned long cur_pending = o->pending;
if (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d",
cmd, o->cids[ECORE_PRIMARY_CID_INDEX], o->state,
cur_pending, o->next_state);
@@ -3713,15 +3716,15 @@ static int ecore_queue_comp_cmd(struct bnx2x_softc *sc __rte_unused,
/* >= because tx only must always be smaller than cos since the
* primary connection supports COS 0
*/
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"illegal value for next tx_only: %d. max cos was %d",
o->next_tx_only, o->max_cos);
- ECORE_MSG("Completing command %d for queue %d, setting state to %d",
+ ECORE_MSG(sc, "Completing command %d for queue %d, setting state to %d",
cmd, o->cids[ECORE_PRIMARY_CID_INDEX], o->next_state);
if (o->next_tx_only) /* print num tx-only if any exist */
- ECORE_MSG("primary cid %d: num tx-only cons %d",
+ ECORE_MSG(sc, "primary cid %d: num tx-only cons %d",
o->cids[ECORE_PRIMARY_CID_INDEX], o->next_tx_only);
o->state = o->next_state;
@@ -3782,7 +3785,7 @@ static void ecore_q_fill_init_general_data(struct bnx2x_softc *sc __rte_unused,
ECORE_TEST_BIT(ECORE_Q_FLG_FCOE, flags) ?
LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
- ECORE_MSG("flags: active %d, cos %d, stats en %d",
+ ECORE_MSG(sc, "flags: active %d, cos %d, stats en %d",
gen_data->activate_flg, gen_data->cos,
gen_data->statistics_en_flg);
}
@@ -3923,7 +3926,7 @@ static void ecore_q_fill_setup_tx_only(struct bnx2x_softc *sc, struct ecore_queu
ecore_q_fill_init_tx_data(&cmd_params->params.tx_only.txq_params,
&data->tx, &cmd_params->params.tx_only.flags);
- ECORE_MSG("cid %d, tx bd page lo %x hi %x",
+ ECORE_MSG(sc, "cid %d, tx bd page lo %x hi %x",
cmd_params->q_obj->cids[0],
data->tx.tx_bd_page_base.lo, data->tx.tx_bd_page_base.hi);
}
@@ -3973,9 +3976,9 @@ static int ecore_q_init(struct bnx2x_softc *sc,
/* Set CDU context validation values */
for (cos = 0; cos < o->max_cos; cos++) {
- ECORE_MSG("setting context validation. cid %d, cos %d",
+ ECORE_MSG(sc, "setting context validation. cid %d, cos %d",
o->cids[cos], cos);
- ECORE_MSG("context pointer %p", init->cxts[cos]);
+ ECORE_MSG(sc, "context pointer %p", init->cxts[cos]);
ECORE_SET_CTX_VALIDATION(sc, init->cxts[cos], o->cids[cos]);
}
@@ -4059,15 +4062,15 @@ static int ecore_q_send_setup_tx_only(struct bnx2x_softc *sc, struct ecore_queue
if (ECORE_TEST_BIT(ECORE_Q_TYPE_FWD, &o->type))
ramrod = RAMROD_CMD_ID_ETH_FORWARD_SETUP;
- ECORE_MSG("sending forward tx-only ramrod");
+ ECORE_MSG(sc, "sending forward tx-only ramrod");
if (cid_index >= o->max_cos) {
- PMD_DRV_LOG(ERR, "queue[%d]: cid_index (%d) is out of range",
+ PMD_DRV_LOG(ERR, sc, "queue[%d]: cid_index (%d) is out of range",
o->cl_id, cid_index);
return ECORE_INVAL;
}
- ECORE_MSG("parameters received: cos: %d sp-id: %d",
+ ECORE_MSG(sc, "parameters received: cos: %d sp-id: %d",
tx_only_params->gen_params.cos,
tx_only_params->gen_params.spcl_id);
@@ -4077,8 +4080,8 @@ static int ecore_q_send_setup_tx_only(struct bnx2x_softc *sc, struct ecore_queue
/* Fill the ramrod data */
ecore_q_fill_setup_tx_only(sc, params, rdata);
- ECORE_MSG
- ("sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d",
+ ECORE_MSG
+ (sc, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d",
o->cids[cid_index], rdata->general.client_id,
rdata->general.sp_client_id, rdata->general.cos);
@@ -4173,7 +4176,7 @@ static int ecore_q_send_update(struct bnx2x_softc *sc,
uint8_t cid_index = update_params->cid_index;
if (cid_index >= o->max_cos) {
- PMD_DRV_LOG(ERR, "queue[%d]: cid_index (%d) is out of range",
+ PMD_DRV_LOG(ERR, sc, "queue[%d]: cid_index (%d) is out of range",
o->cl_id, cid_index);
return ECORE_INVAL;
}
@@ -4267,7 +4270,7 @@ static int ecore_q_send_cfc_del(struct bnx2x_softc *sc,
uint8_t cid_idx = params->params.cfc_del.cid_index;
if (cid_idx >= o->max_cos) {
- PMD_DRV_LOG(ERR, "queue[%d]: cid_index (%d) is out of range",
+ PMD_DRV_LOG(ERR, sc, "queue[%d]: cid_index (%d) is out of range",
o->cl_id, cid_idx);
return ECORE_INVAL;
}
@@ -4283,7 +4286,7 @@ static int ecore_q_send_terminate(struct bnx2x_softc *sc, struct ecore_queue_sta
uint8_t cid_index = params->params.terminate.cid_index;
if (cid_index >= o->max_cos) {
- PMD_DRV_LOG(ERR, "queue[%d]: cid_index (%d) is out of range",
+ PMD_DRV_LOG(ERR, sc, "queue[%d]: cid_index (%d) is out of range",
o->cl_id, cid_index);
return ECORE_INVAL;
}
@@ -4327,7 +4330,7 @@ static int ecore_queue_send_cmd_cmn(struct bnx2x_softc *sc, struct ecore_queue_s
case ECORE_Q_CMD_EMPTY:
return ecore_q_send_empty(sc, params);
default:
- PMD_DRV_LOG(ERR, "Unknown command: %d", params->cmd);
+ PMD_DRV_LOG(ERR, sc, "Unknown command: %d", params->cmd);
return ECORE_INVAL;
}
}
@@ -4350,7 +4353,7 @@ static int ecore_queue_send_cmd_e1x(struct bnx2x_softc *sc,
case ECORE_Q_CMD_EMPTY:
return ecore_queue_send_cmd_cmn(sc, params);
default:
- PMD_DRV_LOG(ERR, "Unknown command: %d", params->cmd);
+ PMD_DRV_LOG(ERR, sc, "Unknown command: %d", params->cmd);
return ECORE_INVAL;
}
}
@@ -4373,7 +4376,7 @@ static int ecore_queue_send_cmd_e2(struct bnx2x_softc *sc,
case ECORE_Q_CMD_EMPTY:
return ecore_queue_send_cmd_cmn(sc, params);
default:
- PMD_DRV_LOG(ERR, "Unknown command: %d", params->cmd);
+ PMD_DRV_LOG(ERR, sc, "Unknown command: %d", params->cmd);
return ECORE_INVAL;
}
}
@@ -4416,7 +4419,7 @@ static int ecore_queue_chk_transition(struct bnx2x_softc *sc __rte_unused,
* the previous one.
*/
if (o->pending) {
- PMD_DRV_LOG(ERR, "Blocking transition since pending was %lx",
+ PMD_DRV_LOG(ERR, sc, "Blocking transition since pending was %lx",
o->pending);
return ECORE_BUSY;
}
@@ -4543,19 +4546,19 @@ static int ecore_queue_chk_transition(struct bnx2x_softc *sc __rte_unused,
break;
default:
- PMD_DRV_LOG(ERR, "Illegal state: %d", state);
+ PMD_DRV_LOG(ERR, sc, "Illegal state: %d", state);
}
/* Transition is assured */
if (next_state != ECORE_Q_STATE_MAX) {
- ECORE_MSG("Good state transition: %d(%d)->%d",
+ ECORE_MSG(sc, "Good state transition: %d(%d)->%d",
state, cmd, next_state);
o->next_state = next_state;
o->next_tx_only = next_tx_only;
return ECORE_SUCCESS;
}
- ECORE_MSG("Bad state transition request: %d %d", state, cmd);
+ ECORE_MSG(sc, "Bad state transition request: %d %d", state, cmd);
return ECORE_INVAL;
}
@@ -4606,18 +4609,18 @@ static int ecore_queue_chk_fwd_transition(struct bnx2x_softc *sc __rte_unused,
break;
default:
- PMD_DRV_LOG(ERR, "Illegal state: %d", state);
+ PMD_DRV_LOG(ERR, sc, "Illegal state: %d", state);
}
/* Transition is assured */
if (next_state != ECORE_Q_STATE_MAX) {
- ECORE_MSG("Good state transition: %d(%d)->%d",
+ ECORE_MSG(sc, "Good state transition: %d(%d)->%d",
state, cmd, next_state);
o->next_state = next_state;
return ECORE_SUCCESS;
}
- ECORE_MSG("Bad state transition request: %d %d", state, cmd);
+ ECORE_MSG(sc, "Bad state transition request: %d %d", state, cmd);
return ECORE_INVAL;
}
@@ -4697,14 +4700,14 @@ static int ecore_func_wait_comp(struct bnx2x_softc *sc,
unsigned long cur_pending = o->pending;
if (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) {
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d",
cmd, ECORE_FUNC_ID(sc), o->state, cur_pending,
o->next_state);
return ECORE_INVAL;
}
- ECORE_MSG("Completing command %d for func %d, setting state to %d",
+ ECORE_MSG(sc, "Completing command %d for func %d, setting state to %d",
cmd, ECORE_FUNC_ID(sc), o->next_state);
o->state = o->next_state;
@@ -4827,18 +4830,19 @@ static int ecore_func_chk_transition(struct bnx2x_softc *sc __rte_unused,
break;
default:
- PMD_DRV_LOG(ERR, "Unknown state: %d", state);
+ PMD_DRV_LOG(ERR, sc, "Unknown state: %d", state);
}
/* Transition is assured */
if (next_state != ECORE_F_STATE_MAX) {
- ECORE_MSG("Good function state transition: %d(%d)->%d",
+ ECORE_MSG(sc, "Good function state transition: %d(%d)->%d",
state, cmd, next_state);
o->next_state = next_state;
return ECORE_SUCCESS;
}
- ECORE_MSG("Bad function state transition request: %d %d", state, cmd);
+ ECORE_MSG(sc,
+ "Bad function state transition request: %d %d", state, cmd);
return ECORE_INVAL;
}
@@ -4928,13 +4932,13 @@ static int ecore_func_hw_init(struct bnx2x_softc *sc,
const struct ecore_func_sp_drv_ops *drv = o->drv;
int rc = 0;
- ECORE_MSG("function %d load_code %x",
+ ECORE_MSG(sc, "function %d load_code %x",
ECORE_ABS_FUNC_ID(sc), load_code);
/* Prepare FW */
rc = drv->init_fw(sc);
if (rc) {
- PMD_DRV_LOG(ERR, "Error loading firmware");
+ PMD_DRV_LOG(ERR, sc, "Error loading firmware");
goto init_err;
}
@@ -4965,7 +4969,7 @@ static int ecore_func_hw_init(struct bnx2x_softc *sc,
break;
default:
- PMD_DRV_LOG(ERR, "Unknown load_code (0x%x) from MCP",
+ PMD_DRV_LOG(ERR, sc, "Unknown load_code (0x%x) from MCP",
load_code);
rc = ECORE_INVAL;
}
@@ -5041,7 +5045,7 @@ static int ecore_func_hw_reset(struct bnx2x_softc *sc,
struct ecore_func_sp_obj *o = params->f_obj;
const struct ecore_func_sp_drv_ops *drv = o->drv;
- ECORE_MSG("function %d reset_phase %x", ECORE_ABS_FUNC_ID(sc),
+ ECORE_MSG(sc, "function %d reset_phase %x", ECORE_ABS_FUNC_ID(sc),
reset_phase);
switch (reset_phase) {
@@ -5055,7 +5059,7 @@ static int ecore_func_hw_reset(struct bnx2x_softc *sc,
ecore_func_reset_func(sc, drv);
break;
default:
- PMD_DRV_LOG(ERR, "Unknown reset_phase (0x%x) from MCP",
+ PMD_DRV_LOG(ERR, sc, "Unknown reset_phase (0x%x) from MCP",
reset_phase);
break;
}
@@ -5146,7 +5150,7 @@ static int ecore_func_send_afex_update(struct bnx2x_softc *sc, struct ecore_func
* read and we will have to put a full memory barrier there
* (inside ecore_sp_post()).
*/
- ECORE_MSG("afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x",
+ ECORE_MSG(sc, "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x",
rdata->vif_id,
rdata->afex_default_vlan, rdata->allowed_priorities);
@@ -5184,8 +5188,8 @@ inline int ecore_func_send_afex_viflists(struct bnx2x_softc *sc,
* (inside ecore_sp_post()).
*/
- ECORE_MSG
- ("afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x",
+ ECORE_MSG
+ (sc, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x",
rdata->afex_vif_list_command, rdata->vif_list_index,
rdata->func_bit_map, rdata->func_to_clear);
@@ -5256,7 +5260,7 @@ static int ecore_func_send_cmd(struct bnx2x_softc *sc,
case ECORE_F_CMD_SWITCH_UPDATE:
return ecore_func_send_switch_update(sc, params);
default:
- PMD_DRV_LOG(ERR, "Unknown command: %d", params->cmd);
+ PMD_DRV_LOG(ERR, sc, "Unknown command: %d", params->cmd);
return ECORE_INVAL;
}
}
@@ -5317,7 +5321,7 @@ int ecore_func_state_change(struct bnx2x_softc *sc,
}
if (rc == ECORE_BUSY) {
ECORE_MUTEX_UNLOCK(&o->one_pending_mutex);
- PMD_DRV_LOG(ERR,
+ PMD_DRV_LOG(ERR, sc,
"timeout waiting for previous ramrod completion");
return rc;
}
diff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h
index 6b65a49..f295bf5 100644
--- a/drivers/net/bnx2x/ecore_sp.h
+++ b/drivers/net/bnx2x/ecore_sp.h
@@ -215,8 +215,8 @@ uint32_t ecore_calc_crc32(uint32_t crc, uint8_t const *p,
} while (0)
-#define ECORE_MSG(m, ...) \
- PMD_DRV_LOG(DEBUG, m, ##__VA_ARGS__)
+#define ECORE_MSG(sc, m, ...) \
+ PMD_DRV_LOG(DEBUG, sc, m, ##__VA_ARGS__)
typedef struct _ecore_list_entry_t
{
diff --git a/drivers/net/bnx2x/elink.c b/drivers/net/bnx2x/elink.c
index b63fd23..1f94476 100644
--- a/drivers/net/bnx2x/elink.c
+++ b/drivers/net/bnx2x/elink.c
@@ -942,7 +942,7 @@ static int elink_check_lfa(struct elink_params *params)
* to verify DCC bit is cleared in any case!
*/
if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
- PMD_DRV_LOG(DEBUG, "No LFA due to DCC flap after clp exit");
+ PMD_DRV_LOG(DEBUG, sc, "No LFA due to DCC flap after clp exit");
REG_WR(sc, params->lfa_base +
offsetof(struct shmem_lfa, additional_config),
additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
@@ -983,7 +983,7 @@ static int elink_check_lfa(struct elink_params *params)
offsetof(struct shmem_lfa, req_duplex));
req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
- PMD_DRV_LOG(INFO, "Duplex mismatch %x vs. %x",
+ PMD_DRV_LOG(INFO, sc, "Duplex mismatch %x vs. %x",
(saved_val & lfa_mask), (req_val & lfa_mask));
return LFA_DUPLEX_MISMATCH;
}
@@ -992,7 +992,7 @@ static int elink_check_lfa(struct elink_params *params)
offsetof(struct shmem_lfa, req_flow_ctrl));
req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
- PMD_DRV_LOG(DEBUG, "Flow control mismatch %x vs. %x",
+ PMD_DRV_LOG(DEBUG, sc, "Flow control mismatch %x vs. %x",
(saved_val & lfa_mask), (req_val & lfa_mask));
return LFA_FLOW_CTRL_MISMATCH;
}
@@ -1001,7 +1001,7 @@ static int elink_check_lfa(struct elink_params *params)
offsetof(struct shmem_lfa, req_line_speed));
req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
- PMD_DRV_LOG(DEBUG, "Link speed mismatch %x vs. %x",
+ PMD_DRV_LOG(DEBUG, sc, "Link speed mismatch %x vs. %x",
(saved_val & lfa_mask), (req_val & lfa_mask));
return LFA_LINK_SPEED_MISMATCH;
}
@@ -1012,7 +1012,7 @@ static int elink_check_lfa(struct elink_params *params)
speed_cap_mask[cfg_idx]));
if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
- PMD_DRV_LOG(DEBUG, "Speed Cap mismatch %x vs. %x",
+ PMD_DRV_LOG(DEBUG, sc, "Speed Cap mismatch %x vs. %x",
cur_speed_cap_mask,
params->speed_cap_mask[cfg_idx]);
return LFA_SPEED_CAP_MISMATCH;
@@ -1025,7 +1025,7 @@ static int elink_check_lfa(struct elink_params *params)
REQ_FC_AUTO_ADV_MASK;
if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {
- PMD_DRV_LOG(DEBUG, "Flow Ctrl AN mismatch %x vs. %x",
+ PMD_DRV_LOG(DEBUG, sc, "Flow Ctrl AN mismatch %x vs. %x",
cur_req_fc_auto_adv, params->req_fc_auto_adv);
return LFA_FLOW_CTRL_MISMATCH;
}
@@ -1038,7 +1038,8 @@ static int elink_check_lfa(struct elink_params *params)
(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
(params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
- PMD_DRV_LOG(DEBUG, "EEE mismatch %x vs. %x", params->eee_mode,
+ PMD_DRV_LOG(DEBUG, sc,
+ "EEE mismatch %x vs. %x", params->eee_mode,
eee_status);
return LFA_EEE_MISMATCH;
}
@@ -1057,7 +1058,7 @@ static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
*en = 0;
/* Sanity check */
if (epio_pin > 31) {
- PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to get", epio_pin);
+ PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to get", epio_pin);
return;
}
@@ -1075,10 +1076,10 @@ static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t e
/* Sanity check */
if (epio_pin > 31) {
- PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to set", epio_pin);
+ PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to set", epio_pin);
return;
}
- PMD_DRV_LOG(DEBUG, "Setting EPIO pin %d to %d", epio_pin, en);
+ PMD_DRV_LOG(DEBUG, sc, "Setting EPIO pin %d to %d", epio_pin, en);
epio_mask = 1 << epio_pin;
/* Set this EPIO to output */
gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
@@ -1209,7 +1210,7 @@ static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
new_mode |= clc_cnt;
new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
- PMD_DRV_LOG(DEBUG, "Changing emac_mode from 0x%x to 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Changing emac_mode from 0x%x to 0x%x",
cur_mode, new_mode);
REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
DELAY(40);
@@ -1262,9 +1263,9 @@ static void elink_emac_init(struct elink_params *params)
timeout = 200;
do {
val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
- PMD_DRV_LOG(DEBUG, "EMAC reset reg is %u", val);
+ PMD_DRV_LOG(DEBUG, sc, "EMAC reset reg is %u", val);
if (!timeout) {
- PMD_DRV_LOG(DEBUG, "EMAC timeout!");
+ PMD_DRV_LOG(DEBUG, sc, "EMAC timeout!");
return;
}
timeout--;
@@ -1327,7 +1328,7 @@ static void elink_umac_enable(struct elink_params *params,
REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
(MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
- PMD_DRV_LOG(DEBUG, "enabling UMAC");
+ PMD_DRV_LOG(DEBUG, sc, "enabling UMAC");
/* This register opens the gate for the UMAC despite its name */
REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
@@ -1350,7 +1351,7 @@ static void elink_umac_enable(struct elink_params *params,
val |= (3 << 2);
break;
default:
- PMD_DRV_LOG(DEBUG, "Invalid speed for UMAC %d",
+ PMD_DRV_LOG(DEBUG, sc, "Invalid speed for UMAC %d",
vars->line_speed);
break;
}
@@ -1368,7 +1369,7 @@ static void elink_umac_enable(struct elink_params *params,
/* Configure UMAC for EEE */
if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
- PMD_DRV_LOG(DEBUG, "configured UMAC for EEE");
+ PMD_DRV_LOG(DEBUG, sc, "configured UMAC for EEE");
REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
@@ -1426,7 +1427,7 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
is_port4mode &&
(REG_RD(sc, MISC_REG_RESET_REG_2) &
MISC_REGISTERS_RESET_REG_2_XMAC)) {
- PMD_DRV_LOG(DEBUG, "XMAC already out of reset in 4-port mode");
+ PMD_DRV_LOG(DEBUG, sc, "XMAC already out of reset in 4-port mode");
return;
}
@@ -1438,7 +1439,7 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
MISC_REGISTERS_RESET_REG_2_XMAC);
if (is_port4mode) {
- PMD_DRV_LOG(DEBUG, "Init XMAC to 2 ports x 10G per path");
+ PMD_DRV_LOG(DEBUG, sc, "Init XMAC to 2 ports x 10G per path");
/* Set the number of ports on the system side to up to 2 */
REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
@@ -1449,12 +1450,12 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
/* Set the number of ports on the system side to 1 */
REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
if (max_speed == ELINK_SPEED_10000) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Init XMAC to 10G x 1 port per path");
/* Set the number of ports on the Warp Core to 10G */
REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
} else {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Init XMAC to 20G x 2 ports per path");
/* Set the number of ports on the Warp Core to 20G */
REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
@@ -1487,7 +1488,7 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
(pfc_ctrl & ~(1 << 1)));
REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
(pfc_ctrl | (1 << 1)));
- PMD_DRV_LOG(DEBUG, "Disable XMAC on port %x", port);
+ PMD_DRV_LOG(DEBUG, sc, "Disable XMAC on port %x", port);
val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
if (en)
val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
@@ -1502,7 +1503,7 @@ static elink_status_t elink_xmac_enable(struct elink_params *params,
{
uint32_t val, xmac_base;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "enabling XMAC");
+ PMD_DRV_LOG(DEBUG, sc, "enabling XMAC");
xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
@@ -1539,7 +1540,7 @@ static elink_status_t elink_xmac_enable(struct elink_params *params,
elink_update_pfc_xmac(params, vars);
if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
- PMD_DRV_LOG(DEBUG, "Setting XMAC for EEE");
+ PMD_DRV_LOG(DEBUG, sc, "Setting XMAC for EEE");
REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
} else {
@@ -1575,7 +1576,7 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
uint32_t val;
- PMD_DRV_LOG(DEBUG, "enabling EMAC");
+ PMD_DRV_LOG(DEBUG, sc, "enabling EMAC");
/* Disable BMAC */
REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
@@ -1589,14 +1590,14 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
- PMD_DRV_LOG(DEBUG, "XGXS");
+ PMD_DRV_LOG(DEBUG, sc, "XGXS");
/* select the master lanes (out of 0-3) */
REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);
/* select XGXS */
REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
} else { /* SerDes */
- PMD_DRV_LOG(DEBUG, "SerDes");
+ PMD_DRV_LOG(DEBUG, sc, "SerDes");
/* select SerDes */
REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
}
@@ -1642,7 +1643,7 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
*/
elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
- PMD_DRV_LOG(DEBUG, "PFC is enabled");
+ PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
/* Enable PFC again */
elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
EMAC_REG_RX_PFC_MODE_RX_EN |
@@ -1762,7 +1763,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
- PMD_DRV_LOG(DEBUG, "PFC is enabled");
+ PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
/* Enable PFC RX & TX & STATS and set 8 COS */
wb_data[0] = 0x0;
wb_data[0] |= (1 << 0); /* RX */
@@ -1776,7 +1777,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
/* Clear the force Xon */
wb_data[0] &= ~(1 << 2);
} else {
- PMD_DRV_LOG(DEBUG, "PFC is disabled");
+ PMD_DRV_LOG(DEBUG, sc, "PFC is disabled");
/* Disable PFC RX & TX & STATS and set 8 COS */
wb_data[0] = 0x8;
wb_data[1] = 0;
@@ -1802,7 +1803,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
val = 0x3; /* Enable RX and TX */
if (is_lb) {
val |= 0x4; /* Local loopback */
- PMD_DRV_LOG(DEBUG, "enable bmac loopback");
+ PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
}
/* When PFC enabled, Pass pause frames towards the NIG. */
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
@@ -1896,7 +1897,7 @@ static void elink_update_pfc_nig(struct elink_params *params,
int set_pfc = params->feature_config_flags &
ELINK_FEATURE_CONFIG_PFC_ENABLED;
- PMD_DRV_LOG(DEBUG, "updating pfc nig parameters");
+ PMD_DRV_LOG(DEBUG, sc, "updating pfc nig parameters");
/* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
* MAC control frames (that are not pause packets)
@@ -2008,7 +2009,7 @@ elink_status_t elink_update_pfc(struct elink_params *params,
if (!vars->link_up)
return elink_status;
- PMD_DRV_LOG(DEBUG, "About to update PFC in BMAC");
+ PMD_DRV_LOG(DEBUG, sc, "About to update PFC in BMAC");
if (CHIP_IS_E3(sc)) {
if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
@@ -2018,7 +2019,7 @@ elink_status_t elink_update_pfc(struct elink_params *params,
if ((val &
(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
== 0) {
- PMD_DRV_LOG(DEBUG, "About to update PFC in EMAC");
+ PMD_DRV_LOG(DEBUG, sc, "About to update PFC in EMAC");
elink_emac_enable(params, vars, 0);
return elink_status;
}
@@ -2047,7 +2048,7 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params,
uint32_t wb_data[2];
uint32_t val;
- PMD_DRV_LOG(DEBUG, "Enabling BigMAC1");
+ PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC1");
/* XGXS control */
wb_data[0] = 0x3c;
@@ -2066,7 +2067,7 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params,
val = 0x3;
if (is_lb) {
val |= 0x4;
- PMD_DRV_LOG(DEBUG, "enable bmac loopback");
+ PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
}
wb_data[0] = val;
wb_data[1] = 0;
@@ -2107,7 +2108,7 @@ static elink_status_t elink_bmac2_enable(struct elink_params *params,
NIG_REG_INGRESS_BMAC0_MEM;
uint32_t wb_data[2];
- PMD_DRV_LOG(DEBUG, "Enabling BigMAC2");
+ PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC2");
wb_data[0] = 0;
wb_data[1] = 0;
@@ -2245,7 +2246,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
/* Wait for init credit */
init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);
crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
- PMD_DRV_LOG(DEBUG, "init_crd 0x%x crd 0x%x", init_crd, crd);
+ PMD_DRV_LOG(DEBUG, sc, "init_crd 0x%x crd 0x%x", init_crd, crd);
while ((init_crd != crd) && count) {
DELAY(1000 * 5);
@@ -2254,7 +2255,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
}
crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
if (init_crd != crd) {
- PMD_DRV_LOG(DEBUG, "BUG! init_crd 0x%x != crd 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "BUG! init_crd 0x%x != crd 0x%x",
init_crd, crd);
return ELINK_STATUS_ERROR;
}
@@ -2281,13 +2282,13 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
init_crd = thresh + 553 - 22;
break;
default:
- PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
line_speed);
return ELINK_STATUS_ERROR;
}
}
REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);
- PMD_DRV_LOG(DEBUG, "PBF updated to speed %d credit %d",
+ PMD_DRV_LOG(DEBUG, sc, "PBF updated to speed %d credit %d",
line_speed, init_crd);
/* Probe the credit changes */
@@ -2377,7 +2378,7 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
}
}
if (tmp & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, "write phy register failed");
+ PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
rc = ELINK_STATUS_TIMEOUT;
}
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
@@ -2413,7 +2414,7 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
}
}
if (val & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, "read phy register failed");
+ PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
*ret_val = 0;
rc = ELINK_STATUS_TIMEOUT;
@@ -2454,7 +2455,7 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
}
}
if (val & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, "read phy register failed");
+ PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
*ret_val = 0;
@@ -2478,7 +2479,7 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
}
}
if (val & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, "read phy register failed");
+ PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
*ret_val = 0;
@@ -2530,7 +2531,7 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
}
}
if (tmp & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, "write phy register failed");
+ PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
rc = ELINK_STATUS_TIMEOUT;
@@ -2552,7 +2553,7 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
}
}
if (tmp & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, "write phy register failed");
+ PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
rc = ELINK_STATUS_TIMEOUT;
@@ -2675,7 +2676,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,
} else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
(params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
(params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
- PMD_DRV_LOG(DEBUG, "Error: Tx LPI is enabled with timer 0");
+ PMD_DRV_LOG(DEBUG, sc, "Error: Tx LPI is enabled with timer 0");
return ELINK_STATUS_ERROR;
}
@@ -2742,11 +2743,11 @@ static elink_status_t elink_eee_advertise(struct elink_phy *phy,
REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
if (modes & SHMEM_EEE_10G_ADV) {
- PMD_DRV_LOG(DEBUG, "Advertise 10GBase-T EEE");
+ PMD_DRV_LOG(DEBUG, sc, "Advertise 10GBase-T EEE");
val |= 0x8;
}
if (modes & SHMEM_EEE_1G_ADV) {
- PMD_DRV_LOG(DEBUG, "Advertise 1GBase-T EEE");
+ PMD_DRV_LOG(DEBUG, sc, "Advertise 1GBase-T EEE");
val |= 0x4;
}
@@ -2786,7 +2787,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
if (adv & 0x2) {
if (vars->line_speed == ELINK_SPEED_100)
neg = 1;
- PMD_DRV_LOG(DEBUG, "EEE negotiated - 100M");
+ PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 100M");
}
}
if (lp & 0x14) {
@@ -2794,7 +2795,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
if (adv & 0x14) {
if (vars->line_speed == ELINK_SPEED_1000)
neg = 1;
- PMD_DRV_LOG(DEBUG, "EEE negotiated - 1G");
+ PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 1G");
}
}
if (lp & 0x68) {
@@ -2802,7 +2803,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
if (adv & 0x68) {
if (vars->line_speed == ELINK_SPEED_10000)
neg = 1;
- PMD_DRV_LOG(DEBUG, "EEE negotiated - 10G");
+ PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 10G");
}
}
@@ -2810,7 +2811,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
if (neg) {
- PMD_DRV_LOG(DEBUG, "EEE is active");
+ PMD_DRV_LOG(DEBUG, sc, "EEE is active");
vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
}
}
@@ -2840,7 +2841,7 @@ static void elink_bsc_module_sel(struct elink_params *params)
e3_cmn_pin_cfg));
i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
- PMD_DRV_LOG(DEBUG, "Setting BSC switch");
+ PMD_DRV_LOG(DEBUG, sc, "Setting BSC switch");
for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
}
@@ -2856,7 +2857,7 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
elink_status_t rc = ELINK_STATUS_OK;
if (xfer_cnt > 16) {
- PMD_DRV_LOG(DEBUG, "invalid xfer_cnt %d. Max is 16 bytes",
+ PMD_DRV_LOG(DEBUG, sc, "invalid xfer_cnt %d. Max is 16 bytes",
xfer_cnt);
return ELINK_STATUS_ERROR;
}
@@ -2888,7 +2889,7 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
DELAY(10);
val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
if (i++ > 1000) {
- PMD_DRV_LOG(DEBUG, "wr 0 byte timed out after %d try",
+ PMD_DRV_LOG(DEBUG, sc, "wr 0 byte timed out after %d try",
i);
rc = ELINK_STATUS_TIMEOUT;
break;
@@ -2912,7 +2913,8 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
DELAY(10);
val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
if (i++ > 1000) {
- PMD_DRV_LOG(DEBUG, "rd op timed out after %d try", i);
+ PMD_DRV_LOG(DEBUG, sc,
+ "rd op timed out after %d try", i);
rc = ELINK_STATUS_TIMEOUT;
break;
}
@@ -3057,7 +3059,7 @@ static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)
{
uint32_t val;
- PMD_DRV_LOG(DEBUG, "elink_serdes_deassert");
+ PMD_DRV_LOG(DEBUG, sc, "elink_serdes_deassert");
val = ELINK_SERDES_RESET_BITS << (port * 16);
@@ -3092,7 +3094,7 @@ static void elink_xgxs_deassert(struct elink_params *params)
struct bnx2x_softc *sc = params->sc;
uint8_t port;
uint32_t val;
- PMD_DRV_LOG(DEBUG, "elink_xgxs_deassert");
+ PMD_DRV_LOG(DEBUG, sc, "elink_xgxs_deassert");
port = params->port;
val = ELINK_XGXS_RESET_BITS << (port * 16);
@@ -3143,7 +3145,7 @@ static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
break;
}
- PMD_DRV_LOG(DEBUG, "ieee_fc = 0x%x", *ieee_fc);
+ PMD_DRV_LOG(DEBUG, params->sc, "ieee_fc = 0x%x", *ieee_fc);
}
static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
@@ -3177,7 +3179,7 @@ static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
ELINK_SPEED_AUTO_NEG)
vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
- PMD_DRV_LOG(DEBUG, "req_flow_ctrl %x, req_line_speed %x,"
+ PMD_DRV_LOG(DEBUG, params->sc, "req_flow_ctrl %x, req_line_speed %x,"
" speed_cap_mask %x",
params->phy[actual_phy_idx].req_flow_ctrl,
params->phy[actual_phy_idx].req_line_speed,
@@ -3208,7 +3210,7 @@ static void elink_ext_phy_set_pause(struct elink_params *params,
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
}
- PMD_DRV_LOG(DEBUG, "Ext phy AN advertize 0x%x", val);
+ PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize 0x%x", val);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
}
@@ -3287,7 +3289,7 @@ static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
}
pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
- PMD_DRV_LOG(DEBUG, "Ext PHY pause result 0x%x", pause_result);
+ PMD_DRV_LOG(DEBUG, sc, "Ext PHY pause result 0x%x", pause_result);
elink_pause_resolve(vars, pause_result);
}
@@ -3356,7 +3358,7 @@ static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
};
- PMD_DRV_LOG(DEBUG, "Enabling 20G-KR2");
+ PMD_DRV_LOG(DEBUG, sc, "Enabling 20G-KR2");
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));
@@ -3393,7 +3395,7 @@ static void elink_disable_kr2(struct elink_params *params,
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
};
- PMD_DRV_LOG(DEBUG, "Disabling 20G-KR2");
+ PMD_DRV_LOG(DEBUG, sc, "Disabling 20G-KR2");
for (i = 0; i < ARRAY_SIZE(reg_set); i++)
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
@@ -3409,7 +3411,7 @@ static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "Configure WC for LPI pass through");
+ PMD_DRV_LOG(DEBUG, sc, "Configure WC for LPI pass through");
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
@@ -3447,7 +3449,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
{MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
};
- PMD_DRV_LOG(DEBUG, "Enable Auto Negotiation for KR");
+ PMD_DRV_LOG(DEBUG, sc, "Enable Auto Negotiation for KR");
/* Set to default registers that may be overridden by 10G force */
for (i = 0; i < ARRAY_SIZE(reg_set); i++)
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
@@ -3469,7 +3471,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
/* Enable CL37 1G Parallel Detect */
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
- PMD_DRV_LOG(DEBUG, "Advertize 1G");
+ PMD_DRV_LOG(DEBUG, sc, "Advertize 1G");
}
if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
@@ -3483,7 +3485,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
elink_set_aer_mmd(params, phy);
- PMD_DRV_LOG(DEBUG, "Advertize 10G");
+ PMD_DRV_LOG(DEBUG, sc, "Advertize 10G");
}
/* Set Transmit PMD settings */
@@ -3520,7 +3522,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
1);
- PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR");
+ PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
}
/* Advertise pause */
@@ -3857,7 +3859,7 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
0x1000);
- PMD_DRV_LOG(DEBUG, "set SGMII AUTONEG");
+ PMD_DRV_LOG(DEBUG, sc, "set SGMII AUTONEG");
} else {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
@@ -3872,7 +3874,7 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
val16 |= 0x0040;
break;
default:
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Speed not supported: 0x%x",
phy->req_line_speed);
return;
@@ -3884,11 +3886,11 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
- PMD_DRV_LOG(DEBUG, "set SGMII force speed %d",
+ PMD_DRV_LOG(DEBUG, sc, "set SGMII force speed %d",
phy->req_line_speed);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
- PMD_DRV_LOG(DEBUG, " (readback) %x", val16);
+ PMD_DRV_LOG(DEBUG, sc, " (readback) %x", val16);
}
/* SGMII Slave mode and disable signal detect */
@@ -3999,7 +4001,7 @@ static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
*/
if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
(cfg_pin > PIN_CFG_GPIO3_P1)) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"No cfg pin %x for module detect indication",
cfg_pin);
return ELINK_STATUS_ERROR;
@@ -4091,7 +4093,7 @@ static void elink_warpcore_config_runtime(struct elink_phy *phy,
0x1200);
vars->rx_tx_asic_rst--;
- PMD_DRV_LOG(DEBUG, "0x%x retry left",
+ PMD_DRV_LOG(DEBUG, sc, "0x%x retry left",
vars->rx_tx_asic_rst);
}
break;
@@ -4113,10 +4115,10 @@ static void elink_warpcore_config_sfi(struct elink_phy *phy,
if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
ELINK_SPEED_10000) &&
(phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
- PMD_DRV_LOG(DEBUG, "Setting 10G SFI");
+ PMD_DRV_LOG(DEBUG, params->sc, "Setting 10G SFI");
elink_warpcore_set_10G_XFI(phy, params, 0);
} else {
- PMD_DRV_LOG(DEBUG, "Setting 1G Fiber");
+ PMD_DRV_LOG(DEBUG, params->sc, "Setting 1G Fiber");
elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
}
}
@@ -4133,7 +4135,7 @@ static void elink_sfp_e3_set_transmitter(struct elink_params *params,
dev_info.port_hw_config[port].e3_sfp_ctrl)) &
PORT_HW_CFG_E3_TX_LASER_MASK;
/* Set the !tx_en since this pin is DISABLE_TX_LASER */
- PMD_DRV_LOG(DEBUG, "Setting WC TX to %d", tx_en);
+ PMD_DRV_LOG(DEBUG, sc, "Setting WC TX to %d", tx_en);
/* For 20G, the expected pin to be used is 3 pins after the current */
elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
@@ -4154,7 +4156,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
dev_info.port_hw_config[params->port].
default_cfg)) &
PORT_HW_CFG_NET_SERDES_IF_MASK);
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Begin Warpcore init, link_speed %d, "
"serdes_net_if = 0x%x", vars->line_speed, serdes_net_if);
elink_set_aer_mmd(params, phy);
@@ -4165,7 +4167,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
((phy->req_line_speed == ELINK_SPEED_100) ||
(phy->req_line_speed == ELINK_SPEED_10)))) {
vars->phy_flags |= PHY_SGMII_FLAG;
- PMD_DRV_LOG(DEBUG, "Setting SGMII mode");
+ PMD_DRV_LOG(DEBUG, sc, "Setting SGMII mode");
elink_warpcore_clear_regs(phy, params, lane);
elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
} else {
@@ -4175,7 +4177,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
if (params->loopback_mode != ELINK_LOOPBACK_EXT)
elink_warpcore_enable_AN_KR(phy, params, vars);
else {
- PMD_DRV_LOG(DEBUG, "Setting KR 10G-Force");
+ PMD_DRV_LOG(DEBUG, sc, "Setting KR 10G-Force");
elink_warpcore_set_10G_KR(phy, params);
}
break;
@@ -4183,14 +4185,14 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
case PORT_HW_CFG_NET_SERDES_IF_XFI:
elink_warpcore_clear_regs(phy, params, lane);
if (vars->line_speed == ELINK_SPEED_10000) {
- PMD_DRV_LOG(DEBUG, "Setting 10G XFI");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 10G XFI");
elink_warpcore_set_10G_XFI(phy, params, 1);
} else {
if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
- PMD_DRV_LOG(DEBUG, "1G Fiber");
+ PMD_DRV_LOG(DEBUG, sc, "1G Fiber");
fiber_mode = 1;
} else {
- PMD_DRV_LOG(DEBUG, "10/100/1G SGMII");
+ PMD_DRV_LOG(DEBUG, sc, "10/100/1G SGMII");
fiber_mode = 0;
}
elink_warpcore_set_sgmii_speed(phy,
@@ -4219,10 +4221,10 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
if (vars->line_speed != ELINK_SPEED_20000) {
- PMD_DRV_LOG(DEBUG, "Speed not supported yet");
+ PMD_DRV_LOG(DEBUG, sc, "Speed not supported yet");
return 0;
}
- PMD_DRV_LOG(DEBUG, "Setting 20G DXGXS");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 20G DXGXS");
elink_warpcore_set_20G_DXGXS(sc, phy, lane);
/* Issue Module detection */
@@ -4232,12 +4234,12 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
if (!params->loopback_mode) {
elink_warpcore_enable_AN_KR(phy, params, vars);
} else {
- PMD_DRV_LOG(DEBUG, "Setting KR 20G-Force");
+ PMD_DRV_LOG(DEBUG, sc, "Setting KR 20G-Force");
elink_warpcore_set_20G_force_KR2(phy, params);
}
break;
default:
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Unsupported Serdes Net Interface 0x%x",
serdes_net_if);
return 0;
@@ -4246,7 +4248,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
/* Take lane out of reset after configuration is finished */
elink_warpcore_reset_lane(sc, phy, 0);
- PMD_DRV_LOG(DEBUG, "Exit config init");
+ PMD_DRV_LOG(DEBUG, sc, "Exit config init");
return 0;
}
@@ -4311,7 +4313,7 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t val16;
uint32_t lane;
- PMD_DRV_LOG(DEBUG, "Setting Warpcore loopback type %x, speed %d",
+ PMD_DRV_LOG(DEBUG, sc, "Setting Warpcore loopback type %x, speed %d",
params->loopback_mode, phy->req_line_speed);
if (phy->req_line_speed < ELINK_SPEED_10000 ||
@@ -4356,7 +4358,7 @@ static void elink_sync_link(struct elink_params *params,
vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
if (vars->link_up) {
- PMD_DRV_LOG(DEBUG, "phy link up");
+ PMD_DRV_LOG(DEBUG, sc, "phy link up");
vars->phy_link_up = 1;
vars->duplex = DUPLEX_FULL;
@@ -4434,7 +4436,7 @@ static void elink_sync_link(struct elink_params *params,
vars->mac_type = ELINK_MAC_TYPE_EMAC;
}
} else { /* Link down */
- PMD_DRV_LOG(DEBUG, "phy link down");
+ PMD_DRV_LOG(DEBUG, sc, "phy link down");
vars->phy_link_up = 0;
@@ -4491,7 +4493,7 @@ void elink_link_status_update(struct elink_params *params,
params->phy[ELINK_EXT_PHY2].media_type =
(media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
- PMD_DRV_LOG(DEBUG, "media_types = 0x%x", media_types);
+ PMD_DRV_LOG(DEBUG, sc, "media_types = 0x%x", media_types);
/* Sync AEU offset */
sync_offset = params->shmem_base +
@@ -4512,9 +4514,9 @@ void elink_link_status_update(struct elink_params *params,
vars->link_attr_sync = SHMEM2_RD(sc,
link_attr_sync[params->port]);
- PMD_DRV_LOG(DEBUG, "link_status 0x%x phy_link_up %x int_mask 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "link_status 0x%x phy_link_up %x int_mask 0x%x",
vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
- PMD_DRV_LOG(DEBUG, "line_speed %x duplex %x flow_ctrl 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "line_speed %x duplex %x flow_ctrl 0x%x",
vars->line_speed, vars->duplex, vars->flow_ctrl);
}
@@ -4575,7 +4577,7 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,
elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
// " Port %d",
- PMD_DRV_LOG(DEBUG, "BUG! XGXS is still in reset!");
+ PMD_DRV_LOG(DEBUG, sc, "BUG! XGXS is still in reset!");
return ELINK_STATUS_ERROR;
}
@@ -4634,7 +4636,7 @@ static void elink_set_parallel_detection(struct elink_phy *phy,
control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
else
control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
- PMD_DRV_LOG(DEBUG, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
phy->speed_cap_mask, control2);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
@@ -4642,7 +4644,7 @@ static void elink_set_parallel_detection(struct elink_phy *phy,
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
- PMD_DRV_LOG(DEBUG, "XGXS");
+ PMD_DRV_LOG(DEBUG, sc, "XGXS");
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_10G_PARALLEL_DETECT,
@@ -4795,7 +4797,7 @@ static void elink_program_serdes(struct elink_phy *phy,
MDIO_REG_BANK_SERDES_DIGITAL,
MDIO_SERDES_DIGITAL_MISC1, ®_val);
/* Clearing the speed value before setting the right speed */
- PMD_DRV_LOG(DEBUG, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
+ PMD_DRV_LOG(DEBUG, sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
@@ -4863,7 +4865,7 @@ static void elink_restart_autoneg(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t mii_control;
- PMD_DRV_LOG(DEBUG, "elink_restart_autoneg");
+ PMD_DRV_LOG(DEBUG, sc, "elink_restart_autoneg");
/* Enable and restart BAM/CL37 aneg */
if (enable_cl73) {
@@ -4883,7 +4885,7 @@ static void elink_restart_autoneg(struct elink_phy *phy,
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"elink_restart_autoneg mii_control before = 0x%x",
mii_control);
CL22_WR_OVER_CL45(sc, phy,
@@ -4942,7 +4944,7 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
break;
default:
/* Invalid speed for SGMII */
- PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
vars->line_speed);
break;
}
@@ -4977,7 +4979,7 @@ static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
MDIO_REG_BANK_SERDES_DIGITAL,
MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
- PMD_DRV_LOG(DEBUG, "1G parallel detect link on port %d",
+ PMD_DRV_LOG(DEBUG, sc, "1G parallel detect link on port %d",
params->port);
return ELINK_STATUS_ERROR;
}
@@ -4987,7 +4989,7 @@ static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);
if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
- PMD_DRV_LOG(DEBUG, "10G parallel detect link on port %d",
+ PMD_DRV_LOG(DEBUG, sc, "10G parallel detect link on port %d",
params->port);
return ELINK_STATUS_ERROR;
}
@@ -5018,7 +5020,7 @@ static void elink_update_adv_fc(struct elink_phy *phy,
MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
pause_result |= (lp_pause &
MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
- PMD_DRV_LOG(DEBUG, "pause_result CL73 0x%x", pause_result);
+ PMD_DRV_LOG(DEBUG, sc, "pause_result CL73 0x%x", pause_result);
} else {
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
@@ -5031,7 +5033,7 @@ static void elink_update_adv_fc(struct elink_phy *phy,
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;
pause_result |= (lp_pause &
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;
- PMD_DRV_LOG(DEBUG, "pause_result CL37 0x%x", pause_result);
+ PMD_DRV_LOG(DEBUG, sc, "pause_result CL37 0x%x", pause_result);
}
elink_pause_resolve(vars, pause_result);
@@ -5060,7 +5062,7 @@ static void elink_flow_ctrl_resolve(struct elink_phy *phy,
}
elink_update_adv_fc(phy, params, vars, gp_status);
}
- PMD_DRV_LOG(DEBUG, "flow_ctrl 0x%x", vars->flow_ctrl);
+ PMD_DRV_LOG(DEBUG, params->sc, "flow_ctrl 0x%x", vars->flow_ctrl);
}
static void elink_check_fallback_to_cl37(struct elink_phy *phy,
@@ -5068,13 +5070,13 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
{
struct bnx2x_softc *sc = params->sc;
uint16_t rx_status, ustat_val, cl37_fsm_received;
- PMD_DRV_LOG(DEBUG, "elink_check_fallback_to_cl37");
+ PMD_DRV_LOG(DEBUG, sc, "elink_check_fallback_to_cl37");
/* Step 1: Make sure signal is detected */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);
if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
(MDIO_RX0_RX_STATUS_SIGDET)) {
- PMD_DRV_LOG(DEBUG, "Signal is not detected. Restoring CL73."
+ PMD_DRV_LOG(DEBUG, sc, "Signal is not detected. Restoring CL73."
"rx_status(0x80b0) = 0x%x", rx_status);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB0,
@@ -5091,7 +5093,7 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
(MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
- PMD_DRV_LOG(DEBUG, "CL73 state-machine is not stable. "
+ PMD_DRV_LOG(DEBUG, sc, "CL73 state-machine is not stable. "
"ustat_val(0x8371) = 0x%x", ustat_val);
return;
}
@@ -5106,7 +5108,7 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
(MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
- PMD_DRV_LOG(DEBUG, "No CL37 FSM were received. "
+ PMD_DRV_LOG(DEBUG, sc, "No CL37 FSM were received. "
"misc_rx_status(0x8330) = 0x%x", cl37_fsm_received);
return;
}
@@ -5122,7 +5124,7 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);
/* Restart CL37 autoneg */
elink_restart_autoneg(phy, params, 0);
- PMD_DRV_LOG(DEBUG, "Disabling CL73, and restarting CL37 autoneg");
+ PMD_DRV_LOG(DEBUG, sc, "Disabling CL73, and restarting CL37 autoneg");
}
static void elink_xgxs_an_resolve(struct elink_phy *phy,
@@ -5146,7 +5148,7 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
if (is_link_up) {
- PMD_DRV_LOG(DEBUG, "phy link up");
+ PMD_DRV_LOG(DEBUG, params->sc, "phy link up");
vars->phy_link_up = 1;
vars->link_status |= LINK_STATUS_LINK_UP;
@@ -5187,7 +5189,7 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
case ELINK_GP_STATUS_5G:
case ELINK_GP_STATUS_6G:
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, params->sc,
"link speed unsupported gp_status 0x%x",
speed_mask);
return ELINK_STATUS_ERROR;
@@ -5207,13 +5209,13 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
vars->link_status |= ELINK_LINK_20GTFD;
break;
default:
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, params->sc,
"link speed unsupported gp_status 0x%x",
speed_mask);
return ELINK_STATUS_ERROR;
}
} else { /* link_down */
- PMD_DRV_LOG(DEBUG, "phy link down");
+ PMD_DRV_LOG(DEBUG, params->sc, "phy link down");
vars->phy_link_up = 0;
@@ -5221,7 +5223,7 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
vars->mac_type = ELINK_MAC_TYPE_NONE;
}
- PMD_DRV_LOG(DEBUG, " phy_link_up %x line_speed %d",
+ PMD_DRV_LOG(DEBUG, params->sc, " phy_link_up %x line_speed %d",
vars->phy_link_up, vars->line_speed);
return ELINK_STATUS_OK;
}
@@ -5244,7 +5246,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
link_up = 1;
speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
- PMD_DRV_LOG(DEBUG, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
gp_status, link_up, speed_mask);
rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
duplex);
@@ -5294,7 +5296,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
}
- PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
vars->duplex, vars->flow_ctrl, vars->link_status);
return rc;
}
@@ -5320,7 +5322,7 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
uint16_t temp_link_up;
elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);
- PMD_DRV_LOG(DEBUG, "PCS RX link status = 0x%x-->0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "PCS RX link status = 0x%x-->0x%x",
temp_link_up, link_up);
link_up &= (1 << 2);
if (link_up)
@@ -5328,7 +5330,7 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
} else {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
- PMD_DRV_LOG(DEBUG, "0x81d1 = 0x%x", gp_status1);
+ PMD_DRV_LOG(DEBUG, sc, "0x81d1 = 0x%x", gp_status1);
/* Check for either KR, 1G, or AN up. */
link_up = ((gp_status1 >> 8) |
(gp_status1 >> 12) | (gp_status1)) & (1 << lane);
@@ -5398,7 +5400,7 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
}
- PMD_DRV_LOG(DEBUG, "lane %d gp_speed 0x%x", lane, gp_speed);
+ PMD_DRV_LOG(DEBUG, sc, "lane %d gp_speed 0x%x", lane, gp_speed);
if ((lane & 1) == 0)
gp_speed <<= 8;
@@ -5414,7 +5416,7 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
(!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
- PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
vars->duplex, vars->flow_ctrl, vars->link_status);
return rc;
}
@@ -5461,7 +5463,7 @@ static elink_status_t elink_emac_program(struct elink_params *params,
uint8_t port = params->port;
uint16_t mode = 0;
- PMD_DRV_LOG(DEBUG, "setting link speed & duplex");
+ PMD_DRV_LOG(DEBUG, sc, "setting link speed & duplex");
elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +
EMAC_REG_EMAC_MODE,
(EMAC_MODE_25G_MODE |
@@ -5485,7 +5487,8 @@ static elink_status_t elink_emac_program(struct elink_params *params,
default:
/* 10G not valid for EMAC */
- PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", vars->line_speed);
+ PMD_DRV_LOG(DEBUG, sc,
+ "Invalid line_speed 0x%x", vars->line_speed);
return ELINK_STATUS_ERROR;
}
@@ -5537,7 +5540,7 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
(ELINK_SINGLE_MEDIA_DIRECT(params) &&
params->loopback_mode == ELINK_LOOPBACK_EXT)) {
- PMD_DRV_LOG(DEBUG, "not SGMII, no AN");
+ PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, no AN");
/* Disable autoneg */
elink_set_autoneg(phy, params, vars, 0);
@@ -5546,7 +5549,7 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
elink_program_serdes(phy, params, vars);
} else { /* AN_mode */
- PMD_DRV_LOG(DEBUG, "not SGMII, AN");
+ PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, AN");
/* AN enabled */
elink_set_brcm_cl37_advertisement(phy, params);
@@ -5563,7 +5566,7 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
}
} else { /* SGMII mode */
- PMD_DRV_LOG(DEBUG, "SGMII");
+ PMD_DRV_LOG(DEBUG, params->sc, "SGMII");
elink_initialize_sgmii_process(phy, params, vars);
}
@@ -5632,7 +5635,7 @@ static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,
elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
// " Port %d",
- PMD_DRV_LOG(DEBUG, "control reg 0x%x (after %d ms)", ctrl, cnt);
+ PMD_DRV_LOG(DEBUG, sc, "control reg 0x%x (after %d ms)", ctrl, cnt);
return cnt;
}
@@ -5650,35 +5653,35 @@ static void elink_link_int_enable(struct elink_params *params)
} else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
ELINK_NIG_MASK_XGXS0_LINK_STATUS);
- PMD_DRV_LOG(DEBUG, "enabled XGXS interrupt");
+ PMD_DRV_LOG(DEBUG, sc, "enabled XGXS interrupt");
if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
params->phy[ELINK_INT_PHY].type !=
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
mask |= ELINK_NIG_MASK_MI_INT;
- PMD_DRV_LOG(DEBUG, "enabled external phy int");
+ PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
}
} else { /* SerDes */
mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
- PMD_DRV_LOG(DEBUG, "enabled SerDes interrupt");
+ PMD_DRV_LOG(DEBUG, sc, "enabled SerDes interrupt");
if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
params->phy[ELINK_INT_PHY].type !=
PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
mask |= ELINK_NIG_MASK_MI_INT;
- PMD_DRV_LOG(DEBUG, "enabled external phy int");
+ PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
}
}
elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);
- PMD_DRV_LOG(DEBUG, "port %x, is_xgxs %x, int_status 0x%x", port,
+ PMD_DRV_LOG(DEBUG, sc, "port %x, is_xgxs %x, int_status 0x%x", port,
(params->switch_cfg == ELINK_SWITCH_CFG_10G),
REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
- PMD_DRV_LOG(DEBUG, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
+ PMD_DRV_LOG(DEBUG, sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
REG_RD(sc,
NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
- PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x",
+ PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
}
@@ -5694,7 +5697,7 @@ static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
*/
/* Read Latched signals */
latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);
- PMD_DRV_LOG(DEBUG, "latch_status = 0x%x", latch_status);
+ PMD_DRV_LOG(DEBUG, sc, "latch_status = 0x%x", latch_status);
/* Handle only those with latched-signal=up. */
if (exp_mi_int)
elink_bits_en(sc,
@@ -5746,7 +5749,7 @@ static void elink_link_int_ack(struct elink_params *params,
} else
mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
}
- PMD_DRV_LOG(DEBUG, "Ack link up interrupt with mask 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Ack link up interrupt with mask 0x%x",
mask);
elink_bits_en(sc,
NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);
@@ -5809,7 +5812,7 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,
if (phy->req_line_speed != ELINK_SPEED_1000) {
uint32_t md_devad = 0;
- PMD_DRV_LOG(DEBUG, "XGXS 10G loopback enable");
+ PMD_DRV_LOG(DEBUG, sc, "XGXS 10G loopback enable");
if (!CHIP_IS_E3(sc)) {
/* Change the uni_phy_addr in the nig */
@@ -5841,7 +5844,7 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,
}
} else {
uint16_t mii_ctrl;
- PMD_DRV_LOG(DEBUG, "XGXS 1G loopback enable");
+ PMD_DRV_LOG(DEBUG, sc, "XGXS 1G loopback enable");
elink_cl45_read(sc, phy, 5,
(MDIO_REG_BANK_COMBO_IEEE0 +
(MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
@@ -5865,8 +5868,9 @@ elink_status_t elink_set_led(struct elink_params *params,
uint32_t tmp;
uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "elink_set_led: port %x, mode %d", port, mode);
- PMD_DRV_LOG(DEBUG, "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode);
+ PMD_DRV_LOG(DEBUG, sc, "elink_set_led: port %x, mode %d", port, mode);
+ PMD_DRV_LOG(DEBUG, sc,
+ "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode);
/* In case */
for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
if (params->phy[phy_idx].set_link_led) {
@@ -5986,7 +5990,8 @@ elink_status_t elink_set_led(struct elink_params *params,
default:
rc = ELINK_STATUS_ERROR;
- PMD_DRV_LOG(DEBUG, "elink_set_led: Invalid led mode %d", mode);
+ PMD_DRV_LOG(DEBUG, sc,
+ "elink_set_led: Invalid led mode %d", mode);
break;
}
return rc;
@@ -6053,7 +6058,7 @@ static elink_status_t elink_link_initialize(struct elink_params *params,
if (phy_index == ELINK_EXT_PHY2 &&
(elink_phy_selection(params) ==
PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Not initializing second phy");
continue;
}
@@ -6094,7 +6099,7 @@ static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,
MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
- PMD_DRV_LOG(DEBUG, "reset external PHY");
+ PMD_DRV_LOG(DEBUG, sc, "reset external PHY");
}
static elink_status_t elink_update_link_down(struct elink_params *params,
@@ -6103,7 +6108,7 @@ static elink_status_t elink_update_link_down(struct elink_params *params,
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
- PMD_DRV_LOG(DEBUG, "Port %x: Link is down", port);
+ PMD_DRV_LOG(DEBUG, sc, "Port %x: Link is down", port);
elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
/* Indicate no mac active */
@@ -6164,7 +6169,7 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
if (link_10g) {
if (elink_xmac_enable(params, vars, 0) ==
ELINK_STATUS_NO_LINK) {
- PMD_DRV_LOG(DEBUG, "Found errors on XMAC");
+ PMD_DRV_LOG(DEBUG, sc, "Found errors on XMAC");
vars->link_up = 0;
vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
vars->link_status &= ~LINK_STATUS_LINK_UP;
@@ -6176,7 +6181,7 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
(vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
- PMD_DRV_LOG(DEBUG, "Enabling LPI assertion");
+ PMD_DRV_LOG(DEBUG, sc, "Enabling LPI assertion");
REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
(params->port << 2), 1);
REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
@@ -6188,7 +6193,7 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
if (link_10g) {
if (elink_bmac_enable(params, vars, 0, 1) ==
ELINK_STATUS_NO_LINK) {
- PMD_DRV_LOG(DEBUG, "Found errors on BMAC");
+ PMD_DRV_LOG(DEBUG, sc, "Found errors on BMAC");
vars->link_up = 0;
vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
vars->link_status &= ~LINK_STATUS_LINK_UP;
@@ -6273,19 +6278,19 @@ elink_status_t elink_link_update(struct elink_params * params,
if (USES_WARPCORE(sc))
elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
- PMD_DRV_LOG(DEBUG, "port %x, XGXS?%x, int_status 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "port %x, XGXS?%x, int_status 0x%x",
port, (vars->phy_flags & PHY_XGXS_FLAG),
REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
port * 0x18) > 0);
- PMD_DRV_LOG(DEBUG, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
+ PMD_DRV_LOG(DEBUG, sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
is_mi_int,
REG_RD(sc,
NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
- PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x",
+ PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
@@ -6309,10 +6314,10 @@ elink_status_t elink_link_update(struct elink_params * params,
cur_link_up = phy->read_status(phy, params,
&phy_vars[phy_index]);
if (cur_link_up) {
- PMD_DRV_LOG(DEBUG, "phy in index %d link is up",
+ PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is up",
phy_index);
} else {
- PMD_DRV_LOG(DEBUG, "phy in index %d link is down",
+ PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is down",
phy_index);
continue;
}
@@ -6345,7 +6350,7 @@ elink_status_t elink_link_update(struct elink_params * params,
* to link up by itself (using configuration)
* - DEFAULT should be overridden during initialization
*/
- PMD_DRV_LOG(DEBUG, "Invalid link indication"
+ PMD_DRV_LOG(DEBUG, sc, "Invalid link indication"
"mpc=0x%x. DISABLING LINK !!!",
params->multi_phy_config);
ext_phy_link_up = 0;
@@ -6383,7 +6388,7 @@ elink_status_t elink_link_update(struct elink_params * params,
*/
if (active_external_phy == ELINK_EXT_PHY1) {
if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
- PMD_DRV_LOG(DEBUG, "Disabling TX on EXT_PHY2");
+ PMD_DRV_LOG(DEBUG, sc, "Disabling TX on EXT_PHY2");
params->phy[ELINK_EXT_PHY2].
phy_specific_func(¶ms->
phy[ELINK_EXT_PHY2],
@@ -6401,7 +6406,7 @@ elink_status_t elink_link_update(struct elink_params * params,
vars->eee_status = phy_vars[active_external_phy].eee_status;
- PMD_DRV_LOG(DEBUG, "Active external phy selected: %x",
+ PMD_DRV_LOG(DEBUG, sc, "Active external phy selected: %x",
active_external_phy);
}
@@ -6415,7 +6420,7 @@ elink_status_t elink_link_update(struct elink_params * params,
break;
}
}
- PMD_DRV_LOG(DEBUG, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
+ PMD_DRV_LOG(DEBUG, sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
" ext_phy_line_speed = %d", vars->flow_ctrl,
vars->link_status, ext_phy_line_speed);
/* Upon link speed change set the NIG into drain mode. Comes to
@@ -6426,7 +6431,7 @@ elink_status_t elink_link_update(struct elink_params * params,
if (vars->phy_link_up) {
if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
(ext_phy_line_speed != vars->line_speed)) {
- PMD_DRV_LOG(DEBUG, "Internal link speed %d is"
+ PMD_DRV_LOG(DEBUG, sc, "Internal link speed %d is"
" different than the external"
" link speed %d", vars->line_speed,
ext_phy_line_speed);
@@ -6452,7 +6457,7 @@ elink_status_t elink_link_update(struct elink_params * params,
* initialize it
*/
if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
- PMD_DRV_LOG(DEBUG, "ext_phy_link_up = %d, int_link_up = %d,"
+ PMD_DRV_LOG(DEBUG, sc, "ext_phy_link_up = %d, int_link_up = %d,"
" init_preceding = %d", ext_phy_link_up,
vars->phy_link_up,
params->phy[ELINK_EXT_PHY1].flags &
@@ -6517,7 +6522,7 @@ static void elink_save_spirom_version(struct bnx2x_softc *sc,
__rte_unused uint8_t port,
uint32_t spirom_ver, uint32_t ver_addr)
{
- PMD_DRV_LOG(DEBUG, "FW version 0x%x:0x%x for port %d",
+ PMD_DRV_LOG(DEBUG, sc, "FW version 0x%x:0x%x for port %d",
(uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);
if (ver_addr)
@@ -6583,7 +6588,7 @@ static void elink_8073_resolve_fc(struct elink_phy *phy,
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
elink_pause_resolve(vars, pause_result);
- PMD_DRV_LOG(DEBUG, "Ext PHY CL37 pause result 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Ext PHY CL37 pause result 0x%x",
pause_result);
}
}
@@ -6627,7 +6632,7 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
do {
count++;
if (count > 300) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"elink_8073_8727_external_rom_boot port %x:"
"Download failed. fw version = 0x%x",
port, fw_ver1);
@@ -6652,7 +6657,7 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
elink_save_bnx2x_spirom_ver(sc, phy, port);
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"elink_8073_8727_external_rom_boot port %x:"
"Download complete. fw version = 0x%x", port, fw_ver1);
@@ -6713,10 +6718,10 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
* these bits indicate 2.5G or 1G link up).
*/
if (!(val & (1 << 14)) || !(val & (1 << 13))) {
- PMD_DRV_LOG(DEBUG, "XAUI work-around not required");
+ PMD_DRV_LOG(DEBUG, sc, "XAUI work-around not required");
return ELINK_STATUS_OK;
} else if (!(val & (1 << 15))) {
- PMD_DRV_LOG(DEBUG, "bit 15 went off");
+ PMD_DRV_LOG(DEBUG, sc, "bit 15 went off");
/* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
* MSB (bit15) goes to 1 (indicating that the XAUI
* workaround has completed), then continue on with
@@ -6728,7 +6733,7 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
MDIO_PMA_REG_8073_XAUI_WA,
&val);
if (val & (1 << 15)) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"XAUI workaround has completed");
return ELINK_STATUS_OK;
}
@@ -6738,7 +6743,7 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
}
DELAY(1000 * 3);
}
- PMD_DRV_LOG(DEBUG, "Warning: XAUI work-around timeout !!!");
+ PMD_DRV_LOG(DEBUG, sc, "Warning: XAUI work-around timeout !!!");
return ELINK_STATUS_ERROR;
}
@@ -6780,7 +6785,7 @@ static void elink_8073_set_pause_cl37(struct elink_params *params,
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
}
- PMD_DRV_LOG(DEBUG, "Ext phy AN advertize cl37 0x%x", cl37_val);
+ PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize cl37 0x%x", cl37_val);
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
@@ -6811,7 +6816,7 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t val = 0, tmp1;
uint8_t gpio_port;
- PMD_DRV_LOG(DEBUG, "Init 8073");
+ PMD_DRV_LOG(DEBUG, sc, "Init 8073");
if (CHIP_IS_E2(sc))
gpio_port = SC_PATH(sc);
@@ -6832,12 +6837,12 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
- PMD_DRV_LOG(DEBUG, "Before rom RX_ALARM(port1): 0x%x", tmp1);
+ PMD_DRV_LOG(DEBUG, sc, "Before rom RX_ALARM(port1): 0x%x", tmp1);
/* Swap polarity if required - Must be done only in non-1G mode */
if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
/* Configure the 8073 to swap _P and _N of the KR lines */
- PMD_DRV_LOG(DEBUG, "Swapping polarity for the 8073");
+ PMD_DRV_LOG(DEBUG, sc, "Swapping polarity for the 8073");
/* 10G Rx/Tx and 1G Tx signal polarity swap */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
@@ -6859,11 +6864,11 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);
- PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR");
+ PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
}
if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
elink_807x_force_10G(sc, phy);
- PMD_DRV_LOG(DEBUG, "Forced speed 10G on 807X");
+ PMD_DRV_LOG(DEBUG, sc, "Forced speed 10G on 807X");
return ELINK_STATUS_OK;
} else {
elink_cl45_write(sc, phy,
@@ -6889,7 +6894,7 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
(PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
val |= (1 << 5);
- PMD_DRV_LOG(DEBUG, "807x autoneg val = 0x%x", val);
+ PMD_DRV_LOG(DEBUG, sc, "807x autoneg val = 0x%x", val);
}
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
@@ -6903,13 +6908,13 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
&phy_ver);
- PMD_DRV_LOG(DEBUG, "Add 2.5G");
+ PMD_DRV_LOG(DEBUG, sc, "Add 2.5G");
if (phy_ver > 0)
tmp1 |= 1;
else
tmp1 &= 0xfffe;
} else {
- PMD_DRV_LOG(DEBUG, "Disable 2.5G");
+ PMD_DRV_LOG(DEBUG, sc, "Disable 2.5G");
tmp1 &= 0xfffe;
}
@@ -6943,7 +6948,7 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
/* Restart autoneg */
DELAY(1000 * 500);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
- PMD_DRV_LOG(DEBUG, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
+ PMD_DRV_LOG(DEBUG, sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
return ELINK_STATUS_OK;
}
@@ -6960,12 +6965,12 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- PMD_DRV_LOG(DEBUG, "8703 LASI status 0x%x", val1);
+ PMD_DRV_LOG(DEBUG, sc, "8703 LASI status 0x%x", val1);
/* Clear the interrupt LASI status register */
elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, "807x PCS status 0x%x->0x%x", val2, val1);
+ PMD_DRV_LOG(DEBUG, sc, "807x PCS status 0x%x->0x%x", val2, val1);
/* Clear MSG-OUT */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
@@ -6973,16 +6978,16 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
/* Check the LASI */
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
- PMD_DRV_LOG(DEBUG, "KR 0x9003 0x%x", val2);
+ PMD_DRV_LOG(DEBUG, sc, "KR 0x9003 0x%x", val2);
/* Check the link status */
elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
- PMD_DRV_LOG(DEBUG, "KR PCS status 0x%x", val2);
+ PMD_DRV_LOG(DEBUG, sc, "KR PCS status 0x%x", val2);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
link_up = ((val1 & 4) == 4);
- PMD_DRV_LOG(DEBUG, "PMA_REG_STATUS=0x%x", val1);
+ PMD_DRV_LOG(DEBUG, sc, "PMA_REG_STATUS=0x%x", val1);
if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {
if (elink_8073_xaui_wa(sc, phy) != 0)
@@ -6996,7 +7001,7 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
/* Check the link status on 1.1.2 */
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, "KR PMA status 0x%x->0x%x,"
+ PMD_DRV_LOG(DEBUG, sc, "KR PMA status 0x%x->0x%x,"
"an_link_status=0x%x", val2, val1, an1000_status);
link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));
@@ -7022,21 +7027,21 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_10000;
- PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G",
+ PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
params->port);
} else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_2500;
- PMD_DRV_LOG(DEBUG, "port %x: External link up in 2.5G",
+ PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 2.5G",
params->port);
} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_1000;
- PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G",
+ PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
params->port);
} else {
link_up = 0;
- PMD_DRV_LOG(DEBUG, "port %x: External link is down",
+ PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
params->port);
}
@@ -7051,7 +7056,7 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
* when it`s in 10G mode.
*/
if (vars->line_speed == ELINK_SPEED_1000) {
- PMD_DRV_LOG(DEBUG, "Swapping 1G polarity for"
+ PMD_DRV_LOG(DEBUG, sc, "Swapping 1G polarity for"
"the 8073");
val1 |= (1 << 3);
} else
@@ -7090,7 +7095,7 @@ static void elink_8073_link_reset(__rte_unused struct elink_phy *phy,
gpio_port = SC_PATH(sc);
else
gpio_port = params->port;
- PMD_DRV_LOG(DEBUG, "Setting 8073 port %d into low power mode",
+ PMD_DRV_LOG(DEBUG, sc, "Setting 8073 port %d into low power mode",
gpio_port);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
@@ -7105,7 +7110,7 @@ static uint8_t elink_8705_config_init(struct elink_phy *phy,
*vars)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "init 8705");
+ PMD_DRV_LOG(DEBUG, sc, "init 8705");
/* Restore normal power mode */
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
@@ -7133,21 +7138,21 @@ static uint8_t elink_8705_read_status(struct elink_phy *phy,
uint8_t link_up = 0;
uint16_t val1, rx_sd;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "read status 8705");
+ PMD_DRV_LOG(DEBUG, sc, "read status 8705");
elink_cl45_read(sc, phy,
MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1);
+ PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
elink_cl45_read(sc, phy,
MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1);
+ PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
- PMD_DRV_LOG(DEBUG, "8705 1.c809 val=0x%x", val1);
+ PMD_DRV_LOG(DEBUG, sc, "8705 1.c809 val=0x%x", val1);
link_up = ((rx_sd & 0x1) && (val1 & (1 << 9))
&& ((val1 & (1 << 8)) == 0));
if (link_up) {
@@ -7171,13 +7176,13 @@ static void elink_set_disable_pmd_transmit(struct elink_params *params,
if (pmd_dis) {
if (params->feature_config_flags &
ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
- PMD_DRV_LOG(DEBUG, "Disabling PMD transmitter");
+ PMD_DRV_LOG(DEBUG, sc, "Disabling PMD transmitter");
} else {
- PMD_DRV_LOG(DEBUG, "NOT disabling PMD transmitter");
+ PMD_DRV_LOG(DEBUG, sc, "NOT disabling PMD transmitter");
return;
}
} else {
- PMD_DRV_LOG(DEBUG, "Enabling PMD transmitter");
+ PMD_DRV_LOG(DEBUG, sc, "Enabling PMD transmitter");
}
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);
@@ -7211,7 +7216,7 @@ static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
offsetof(struct shmem_region,
dev_info.port_hw_config[port].sfp_ctrl)) &
PORT_HW_CFG_TX_LASER_MASK;
- PMD_DRV_LOG(DEBUG, "Setting transmitter tx_en=%x for port %x "
+ PMD_DRV_LOG(DEBUG, sc, "Setting transmitter tx_en=%x for port %x "
"mode = %x", tx_en, port, tx_en_mode);
switch (tx_en_mode) {
case PORT_HW_CFG_TX_LASER_MDIO:
@@ -7247,7 +7252,8 @@ static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
break;
}
default:
- PMD_DRV_LOG(DEBUG, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
+ PMD_DRV_LOG(DEBUG, sc,
+ "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
break;
}
}
@@ -7256,7 +7262,7 @@ static void elink_sfp_set_transmitter(struct elink_params *params,
struct elink_phy *phy, uint8_t tx_en)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "Setting SFP+ transmitter to %d", tx_en);
+ PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ transmitter to %d", tx_en);
if (CHIP_IS_E3(sc))
elink_sfp_e3_set_transmitter(params, phy, tx_en);
else
@@ -7277,7 +7283,7 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
uint16_t val = 0;
uint16_t i;
if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
- PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf");
+ PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
return ELINK_STATUS_ERROR;
}
/* Set the read command byte count */
@@ -7308,7 +7314,7 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Got bad status 0x%x when reading from SFP+ EEPROM",
(val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
return ELINK_STATUS_ERROR;
@@ -7349,7 +7355,7 @@ static void elink_warpcore_power_module(struct elink_params *params,
if (pin_cfg == PIN_CFG_NA)
return;
- PMD_DRV_LOG(DEBUG, "Setting SFP+ module power to %d using pin cfg %d",
+ PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ module power to %d using pin cfg %d",
power, pin_cfg);
/* Low ==> corresponding SFP+ module is powered
* high ==> the SFP+ module is powered down
@@ -7374,7 +7380,7 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
struct bnx2x_softc *sc = params->sc;
if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Reading from eeprom is limited to 16 bytes");
return ELINK_STATUS_ERROR;
}
@@ -7416,7 +7422,7 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
uint16_t val, i;
if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
- PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf");
+ PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
return ELINK_STATUS_ERROR;
}
@@ -7470,7 +7476,7 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Got bad status 0x%x when reading from SFP+ EEPROM",
(val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
return ELINK_STATUS_TIMEOUT;
@@ -7511,7 +7517,8 @@ static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
read_sfp_module_eeprom_func_p read_func;
if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
- PMD_DRV_LOG(DEBUG, "invalid dev_addr 0x%x", dev_addr);
+ PMD_DRV_LOG(DEBUG, params->sc,
+ "invalid dev_addr 0x%x", dev_addr);
return ELINK_STATUS_ERROR;
}
@@ -7557,7 +7564,7 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
ELINK_I2C_DEV_ADDR_A0,
ELINK_SFP_EEPROM_CON_TYPE_ADDR,
2, (uint8_t *) val) != 0) {
- PMD_DRV_LOG(DEBUG, "Failed to read from SFP+ module EEPROM");
+ PMD_DRV_LOG(DEBUG, sc, "Failed to read from SFP+ module EEPROM");
return ELINK_STATUS_ERROR;
}
@@ -7576,7 +7583,7 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
1,
&copper_module_type) !=
0) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Failed to read copper-cable-type"
" from SFP+ EEPROM");
return ELINK_STATUS_ERROR;
@@ -7584,7 +7591,7 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
if (copper_module_type &
ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Active Copper cable detected");
if (phy->type ==
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
@@ -7594,11 +7601,11 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
} else if (copper_module_type &
ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)
{
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Passive Copper cable detected");
*edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
} else {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Unknown copper-cable-type 0x%x !!!",
copper_module_type);
return ELINK_STATUS_ERROR;
@@ -7611,7 +7618,7 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
- PMD_DRV_LOG(DEBUG, "1G SFP module detected");
+ PMD_DRV_LOG(DEBUG, sc, "1G SFP module detected");
gport = params->port;
phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
if (phy->req_line_speed != ELINK_SPEED_1000) {
@@ -7627,7 +7634,7 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
}
} else {
int idx, cfg_idx = 0;
- PMD_DRV_LOG(DEBUG, "10G Optic module detected");
+ PMD_DRV_LOG(DEBUG, sc, "10G Optic module detected");
for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
if (params->phy[idx].type == phy->type) {
cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
@@ -7639,7 +7646,7 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
}
break;
default:
- PMD_DRV_LOG(DEBUG, "Unable to determine module type 0x%x !!!",
+ PMD_DRV_LOG(DEBUG, sc, "Unable to determine module type 0x%x !!!",
val[0]);
return ELINK_STATUS_ERROR;
}
@@ -7669,7 +7676,7 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
ELINK_SFP_EEPROM_OPTIONS_ADDR,
ELINK_SFP_EEPROM_OPTIONS_SIZE,
options) != 0) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Failed to read Option field from module EEPROM");
return ELINK_STATUS_ERROR;
}
@@ -7678,7 +7685,7 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
else
*edc_mode = ELINK_EDC_MODE_LIMITING;
}
- PMD_DRV_LOG(DEBUG, "EDC mode is set to 0x%x", *edc_mode);
+ PMD_DRV_LOG(DEBUG, sc, "EDC mode is set to 0x%x", *edc_mode);
return ELINK_STATUS_OK;
}
@@ -7700,7 +7707,7 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
config));
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
- PMD_DRV_LOG(DEBUG, "NOT enforcing module verification");
+ PMD_DRV_LOG(DEBUG, sc, "NOT enforcing module verification");
return ELINK_STATUS_OK;
}
@@ -7712,21 +7719,21 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
/* Use first phy request only in case of non-dual media */
if (ELINK_DUAL_MEDIA(params)) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"FW does not support OPT MDL verification");
return ELINK_STATUS_ERROR;
}
cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
} else {
/* No support in OPT MDL detection */
- PMD_DRV_LOG(DEBUG, "FW does not support OPT MDL verification");
+ PMD_DRV_LOG(DEBUG, sc, "FW does not support OPT MDL verification");
return ELINK_STATUS_ERROR;
}
fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
- PMD_DRV_LOG(DEBUG, "Approved module");
+ PMD_DRV_LOG(DEBUG, sc, "Approved module");
return ELINK_STATUS_OK;
}
@@ -7782,7 +7789,7 @@ static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
ELINK_I2C_DEV_ADDR_A0,
1, 1, &val);
if (rc == 0) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, params->sc,
"SFP+ module initialization took %d ms",
timeout * 5);
return ELINK_STATUS_OK;
@@ -7833,17 +7840,18 @@ static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);
- PMD_DRV_LOG(DEBUG, "Current Limiting mode is 0x%x", cur_limiting_mode);
+ PMD_DRV_LOG(DEBUG, sc,
+ "Current Limiting mode is 0x%x", cur_limiting_mode);
if (edc_mode == ELINK_EDC_MODE_LIMITING) {
- PMD_DRV_LOG(DEBUG, "Setting LIMITING MODE");
+ PMD_DRV_LOG(DEBUG, sc, "Setting LIMITING MODE");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_ROM_VER2,
ELINK_EDC_MODE_LIMITING);
} else { /* LRM mode ( default ) */
- PMD_DRV_LOG(DEBUG, "Setting LRM MODE");
+ PMD_DRV_LOG(DEBUG, sc, "Setting LRM MODE");
/* Changing to LRM mode takes quite few seconds. So do it only
* if current mode is limiting (default is LRM)
@@ -7933,7 +7941,7 @@ static void elink_8727_specific_func(struct elink_phy *phy,
val);
break;
default:
- PMD_DRV_LOG(DEBUG, "Function 0x%x not supported by 8727",
+ PMD_DRV_LOG(DEBUG, sc, "Function 0x%x not supported by 8727",
action);
return;
}
@@ -7961,14 +7969,14 @@ static void elink_set_e1e2_module_fault_led(struct elink_params *params,
uint8_t gpio_port = elink_get_gpio_port(params);
uint16_t gpio_pin = fault_led_gpio -
PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
- PMD_DRV_LOG(DEBUG, "Set fault module-detected led "
+ PMD_DRV_LOG(DEBUG, sc, "Set fault module-detected led "
"pin %x port %x mode %x",
gpio_pin, gpio_port, gpio_mode);
elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
}
break;
default:
- PMD_DRV_LOG(DEBUG, "Error: Invalid fault led mode 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Error: Invalid fault led mode 0x%x",
fault_led_gpio);
}
}
@@ -7984,7 +7992,7 @@ static void elink_set_e3_module_fault_led(struct elink_params *params,
dev_info.port_hw_config[port].e3_sfp_ctrl)) &
PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
- PMD_DRV_LOG(DEBUG, "Setting Fault LED to %d using pin cfg %d",
+ PMD_DRV_LOG(DEBUG, sc, "Setting Fault LED to %d using pin cfg %d",
gpio_mode, pin_cfg);
elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
}
@@ -7993,7 +8001,8 @@ static void elink_set_sfp_module_fault_led(struct elink_params *params,
uint8_t gpio_mode)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "Setting SFP+ module fault LED to %d", gpio_mode);
+ PMD_DRV_LOG(DEBUG, sc,
+ "Setting SFP+ module fault LED to %d", gpio_mode);
if (CHIP_IS_E3(sc)) {
/* Low ==> if SFP+ module is supported otherwise
* High ==> if SFP+ module is not on the approved vendor list
@@ -8020,7 +8029,7 @@ static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,
static void elink_power_sfp_module(struct elink_params *params,
struct elink_phy *phy, uint8_t power)
{
- PMD_DRV_LOG(DEBUG, "Setting SFP+ power to %x", power);
+ PMD_DRV_LOG(DEBUG, params->sc, "Setting SFP+ power to %x", power);
switch (phy->type) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
@@ -8106,16 +8115,16 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
config));
/* Enabled transmitter by default */
elink_sfp_set_transmitter(params, phy, 1);
- PMD_DRV_LOG(DEBUG, "SFP+ module plugged in/out detected on port %d",
+ PMD_DRV_LOG(DEBUG, sc, "SFP+ module plugged in/out detected on port %d",
params->port);
/* Power up module */
elink_power_sfp_module(params, phy, 1);
if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
- PMD_DRV_LOG(DEBUG, "Failed to get valid module type");
+ PMD_DRV_LOG(DEBUG, sc, "Failed to get valid module type");
return ELINK_STATUS_ERROR;
} else if (elink_verify_sfp_module(phy, params) != 0) {
/* Check SFP+ module compatibility */
- PMD_DRV_LOG(DEBUG, "Module verification failed!!");
+ PMD_DRV_LOG(DEBUG, sc, "Module verification failed!!");
rc = ELINK_STATUS_ERROR;
/* Turn on fault module-detected led */
elink_set_sfp_module_fault_led(params,
@@ -8124,7 +8133,7 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
/* Check if need to power down the SFP+ module */
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
- PMD_DRV_LOG(DEBUG, "Shutdown SFP+ module!!");
+ PMD_DRV_LOG(DEBUG, sc, "Shutdown SFP+ module!!");
elink_power_sfp_module(params, phy, 0);
return rc;
}
@@ -8165,7 +8174,7 @@ void elink_handle_module_detect_int(struct elink_params *params)
if (elink_get_mod_abs_int_cfg(sc, params->shmem_base,
params->port, &gpio_num, &gpio_port) ==
ELINK_STATUS_ERROR) {
- PMD_DRV_LOG(DEBUG, "Failed to get MOD_ABS interrupt config");
+ PMD_DRV_LOG(DEBUG, sc, "Failed to get MOD_ABS interrupt config");
return;
}
@@ -8205,7 +8214,7 @@ void elink_handle_module_detect_int(struct elink_params *params)
}
}
} else {
- PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized");
+ PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
}
} else {
elink_cb_gpio_int_write(sc, gpio_num,
@@ -8250,7 +8259,7 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
uint8_t link_up = 0;
uint16_t val1, val2, rx_sd, pcs_status;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "XGXS 8706/8726");
+ PMD_DRV_LOG(DEBUG, sc, "XGXS 8706/8726");
/* Clear RX Alarm */
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
@@ -8260,7 +8269,8 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
/* Clear LASI indication */
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
- PMD_DRV_LOG(DEBUG, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
+ PMD_DRV_LOG(DEBUG, sc,
+ "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
elink_cl45_read(sc, phy,
@@ -8268,7 +8278,7 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
- PMD_DRV_LOG(DEBUG, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
+ PMD_DRV_LOG(DEBUG, sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
" link_status 0x%x", rx_sd, pcs_status, val2);
/* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
* are set, or if the autoneg bit 1 is set
@@ -8322,7 +8332,7 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
break;
DELAY(1000 * 10);
}
- PMD_DRV_LOG(DEBUG, "XGXS 8706 is initialized after %d ms", cnt);
+ PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 is initialized after %d ms", cnt);
if ((params->feature_config_flags &
ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
uint8_t i;
@@ -8336,14 +8346,14 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
val &= ~0x7;
/* Set control bits according to configuration */
val |= (phy->rx_preemphasis[i] & 0x7);
- PMD_DRV_LOG(DEBUG, "Setting RX Equalizer to BNX2X8706"
+ PMD_DRV_LOG(DEBUG, sc, "Setting RX Equalizer to BNX2X8706"
" reg 0x%x <-- val 0x%x", reg, val);
elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
}
}
/* Force speed */
if (phy->req_line_speed == ELINK_SPEED_10000) {
- PMD_DRV_LOG(DEBUG, "XGXS 8706 force 10Gbps");
+ PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 force 10Gbps");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -8357,7 +8367,7 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
/* Force 1Gbps using autoneg with 1G advertisement */
/* Allow CL37 through CL73 */
- PMD_DRV_LOG(DEBUG, "XGXS 8706 AutoNeg");
+ PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 AutoNeg");
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
@@ -8392,7 +8402,7 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
& PORT_HW_CFG_TX_LASER_MASK;
if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
- PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS");
+ PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
&tmp1);
@@ -8419,7 +8429,7 @@ static void elink_8726_config_loopback(struct elink_phy *phy,
struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "PMA/PMD ext_phy_loopback: 8726");
+ PMD_DRV_LOG(DEBUG, sc, "PMA/PMD ext_phy_loopback: 8726");
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
}
@@ -8471,7 +8481,7 @@ static uint8_t elink_8726_read_status(struct elink_phy *phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
&val1);
if (val1 & (1 << 15)) {
- PMD_DRV_LOG(DEBUG, "Tx is disabled");
+ PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
link_up = 0;
vars->line_speed = 0;
}
@@ -8484,7 +8494,7 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "Initializing BNX2X8726");
+ PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8726");
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
elink_wait_reset_complete(sc, phy, params);
@@ -8499,7 +8509,7 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
elink_sfp_module_detection(phy, params);
if (phy->req_line_speed == ELINK_SPEED_1000) {
- PMD_DRV_LOG(DEBUG, "Setting 1G force");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
elink_cl45_write(sc, phy,
@@ -8514,7 +8524,7 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
((phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
- PMD_DRV_LOG(DEBUG, "Setting 1G clause37");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
/* Set Flow control */
elink_ext_phy_set_pause(params, phy, vars);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
@@ -8542,7 +8552,7 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
/* Set TX PreEmphasis if needed */
if ((params->feature_config_flags &
ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
elink_cl45_write(sc, phy,
@@ -8564,7 +8574,7 @@ static void elink_8726_link_reset(struct elink_phy *phy,
struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "elink_8726_link_reset port %d", params->port);
+ PMD_DRV_LOG(DEBUG, sc, "elink_8726_link_reset port %d", params->port);
/* Set serial boot control for external load */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
@@ -8637,14 +8647,14 @@ static void elink_8727_config_speed(struct elink_phy *phy,
/* Set option 1G speed */
if ((phy->req_line_speed == ELINK_SPEED_1000) ||
(phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
- PMD_DRV_LOG(DEBUG, "Setting 1G force");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
- PMD_DRV_LOG(DEBUG, "1.7 = 0x%x", tmp1);
+ PMD_DRV_LOG(DEBUG, sc, "1.7 = 0x%x", tmp1);
/* Power down the XAUI until link is up in case of dual-media
* and 1G
*/
@@ -8664,7 +8674,7 @@ static void elink_8727_config_speed(struct elink_phy *phy,
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
- PMD_DRV_LOG(DEBUG, "Setting 1G clause37");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
elink_cl45_write(sc, phy,
@@ -8698,7 +8708,7 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,
elink_wait_reset_complete(sc, phy, params);
- PMD_DRV_LOG(DEBUG, "Initializing BNX2X8727");
+ PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8727");
elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
/* Initially configure MOD_ABS to interrupt when module is
@@ -8731,7 +8741,7 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,
/* Set TX PreEmphasis if needed */
if ((params->feature_config_flags &
ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
- PMD_DRV_LOG(DEBUG, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
@@ -8753,7 +8763,7 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,
if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
- PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS");
+ PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
&tmp2);
@@ -8785,7 +8795,7 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,
if (mod_abs & (1 << 8)) {
/* Module is absent */
- PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is absent");
+ PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is absent");
phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
/* 1. Set mod_abs to detect next module
* presence event
@@ -8810,7 +8820,7 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,
} else {
/* Module is present */
- PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is present");
+ PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is present");
/* First disable transmitter, and if the module is ok, the
* module_detection will enable it
* 1. Set mod_abs to detect next module absent event ( bit 8)
@@ -8841,14 +8851,14 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,
if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
elink_sfp_module_detection(phy, params);
} else {
- PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized");
+ PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
}
/* Reconfigure link speed based on module type limitations */
elink_8727_config_speed(phy, params);
}
- PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
+ PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
/* No need to check link status in case of module plugged in/out */
}
@@ -8871,14 +8881,14 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
vars->line_speed = 0;
- PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
+ PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
MDIO_PMA_LASI_TXCTRL);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- PMD_DRV_LOG(DEBUG, "8727 LASI status 0x%x", val1);
+ PMD_DRV_LOG(DEBUG, sc, "8727 LASI status 0x%x", val1);
/* Clear MSG-OUT */
elink_cl45_read(sc, phy,
@@ -8896,7 +8906,7 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
if ((val1 & (1 << 8)) == 0) {
if (!CHIP_IS_E1x(sc))
oc_port = SC_PATH(sc) + (params->port << 1);
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"8727 Power fault has been detected on port %d",
oc_port);
elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
@@ -8939,10 +8949,10 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
}
if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
- PMD_DRV_LOG(DEBUG, "Enabling 8727 TX laser");
+ PMD_DRV_LOG(DEBUG, sc, "Enabling 8727 TX laser");
elink_sfp_set_transmitter(params, phy, 1);
} else {
- PMD_DRV_LOG(DEBUG, "Tx is disabled");
+ PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
return 0;
}
@@ -8956,16 +8966,16 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_10000;
- PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G",
+ PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
params->port);
} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_1000;
- PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G",
+ PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
params->port);
} else {
link_up = 0;
- PMD_DRV_LOG(DEBUG, "port %x: External link is down",
+ PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
params->port);
}
@@ -8985,7 +8995,7 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
if (link_up) {
elink_ext_phy_resolve_fc(phy, params, vars);
vars->duplex = DUPLEX_FULL;
- PMD_DRV_LOG(DEBUG, "duplex = 0x%x", vars->duplex);
+ PMD_DRV_LOG(DEBUG, sc, "duplex = 0x%x", vars->duplex);
}
if ((ELINK_DUAL_MEDIA(params)) &&
@@ -9057,7 +9067,7 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
DELAY(5);
}
if (cnt == 100) {
- PMD_DRV_LOG(DEBUG, "Unable to read 848xx "
+ PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx "
"phy fw version(1)");
elink_save_spirom_version(sc, port, 0, phy->ver_addr);
return;
@@ -9074,7 +9084,7 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
DELAY(5);
}
if (cnt == 100) {
- PMD_DRV_LOG(DEBUG, "Unable to read 848xx phy fw "
+ PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx phy fw "
"version(2)");
elink_save_spirom_version(sc, port, 0, phy->ver_addr);
return;
@@ -9187,7 +9197,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
autoneg_val |= (1 << 9 | 1 << 12);
if (phy->req_duplex == DUPLEX_FULL)
an_1000_val |= (1 << 9);
- PMD_DRV_LOG(DEBUG, "Advertising 1G");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
} else
an_1000_val &= ~((1 << 8) | (1 << 9));
@@ -9203,7 +9213,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
*/
autoneg_val |= (1 << 9 | 1 << 12);
an_10_100_val |= (1 << 8);
- PMD_DRV_LOG(DEBUG, "Advertising 100M-FD");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
}
if (phy->speed_cap_mask &
@@ -9212,7 +9222,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
*/
autoneg_val |= (1 << 9 | 1 << 12);
an_10_100_val |= (1 << 7);
- PMD_DRV_LOG(DEBUG, "Advertising 100M-HD");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
}
if ((phy->speed_cap_mask &
@@ -9220,7 +9230,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
an_10_100_val |= (1 << 6);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, "Advertising 10M-FD");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
}
if ((phy->speed_cap_mask &
@@ -9228,7 +9238,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
an_10_100_val |= (1 << 5);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, "Advertising 10M-HD");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
}
}
@@ -9243,7 +9253,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(1 << 15 | 1 << 9 | 7 << 0));
/* The PHY needs this set even for forced link. */
an_10_100_val |= (1 << 8) | (1 << 7);
- PMD_DRV_LOG(DEBUG, "Setting 100M force");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
}
if ((phy->req_line_speed == ELINK_SPEED_10) &&
(phy->supported &
@@ -9252,7 +9262,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
(1 << 15 | 1 << 9 | 7 << 0));
- PMD_DRV_LOG(DEBUG, "Setting 10M force");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
}
elink_cl45_write(sc, phy,
@@ -9276,7 +9286,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
(phy->req_line_speed == ELINK_SPEED_10000)) {
- PMD_DRV_LOG(DEBUG, "Advertising 10G");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 10G");
/* Restart autoneg for 10G */
elink_cl45_read_or_write(sc, phy,
@@ -9332,7 +9342,7 @@ static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
DELAY(1000 * 1);
}
if (idx >= PHY84833_CMDHDLR_WAIT) {
- PMD_DRV_LOG(DEBUG, "FW cmd: FW not ready.");
+ PMD_DRV_LOG(DEBUG, sc, "FW cmd: FW not ready.");
return ELINK_STATUS_ERROR;
}
@@ -9354,7 +9364,7 @@ static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
}
if ((idx >= PHY84833_CMDHDLR_WAIT) ||
(val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
- PMD_DRV_LOG(DEBUG, "FW cmd failed.");
+ PMD_DRV_LOG(DEBUG, sc, "FW cmd failed.");
return ELINK_STATUS_ERROR;
}
/* Gather returning data */
@@ -9396,7 +9406,7 @@ static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
PHY84833_CMD_SET_PAIR_SWAP, data,
PHY84833_CMDHDLR_MAX_ARGS);
if (status == ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "Pairswap OK, val=0x%x", data[1]);
+ PMD_DRV_LOG(DEBUG, sc, "Pairswap OK, val=0x%x", data[1]);
}
return status;
@@ -9472,7 +9482,8 @@ static void elink_84833_hw_reset_phy(struct elink_phy *phy,
elink_cb_gpio_mult_write(sc, reset_gpios,
MISC_REGISTERS_GPIO_OUTPUT_LOW);
DELAY(10);
- PMD_DRV_LOG(DEBUG, "84833 hw reset on pin values 0x%x", reset_gpios);
+ PMD_DRV_LOG(DEBUG, sc,
+ "84833 hw reset on pin values 0x%x", reset_gpios);
}
static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
@@ -9482,13 +9493,13 @@ static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
elink_status_t rc;
uint16_t cmd_args = 0;
- PMD_DRV_LOG(DEBUG, "Don't Advertise 10GBase-T EEE");
+ PMD_DRV_LOG(DEBUG, params->sc, "Don't Advertise 10GBase-T EEE");
/* Prevent Phy from working in EEE and advertising it */
rc = elink_84833_cmd_hdlr(phy, params,
PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "EEE disable failed.");
+ PMD_DRV_LOG(DEBUG, params->sc, "EEE disable failed.");
return rc;
}
@@ -9505,7 +9516,7 @@ static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
rc = elink_84833_cmd_hdlr(phy, params,
PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "EEE enable failed.");
+ PMD_DRV_LOG(DEBUG, params->sc, "EEE enable failed.");
return rc;
}
@@ -9598,7 +9609,7 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
MDIO_CTL_REG_84823_MEDIA, val);
- PMD_DRV_LOG(DEBUG, "Multi_phy config = 0x%x, Media control = 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Multi_phy config = 0x%x, Media control = 0x%x",
params->multi_phy_config, val);
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
@@ -9614,7 +9625,7 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
PHY84833_CMD_SET_EEE_MODE, cmd_args,
PHY84833_CMDHDLR_MAX_ARGS);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "Cfg AutogrEEEn failed.");
+ PMD_DRV_LOG(DEBUG, sc, "Cfg AutogrEEEn failed.");
}
}
if (initialize) {
@@ -9651,7 +9662,7 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
elink_eee_has_cap(params)) {
rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers");
+ PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
elink_8483x_disable_eee(phy, params, vars);
return rc;
}
@@ -9664,7 +9675,7 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
else
rc = elink_8483x_disable_eee(phy, params, vars);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "Failed to set EEE advertisement");
+ PMD_DRV_LOG(DEBUG, sc, "Failed to set EEE advertisement");
return rc;
}
} else {
@@ -9696,7 +9707,7 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);
- PMD_DRV_LOG(DEBUG, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
+ PMD_DRV_LOG(DEBUG, sc, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
/* Check link 10G */
if (val2 & (1 << 11)) {
@@ -9718,7 +9729,8 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
&legacy_status);
- PMD_DRV_LOG(DEBUG, "Legacy speed status = 0x%x", legacy_status);
+ PMD_DRV_LOG(DEBUG, sc,
+ "Legacy speed status = 0x%x", legacy_status);
link_up = ((legacy_status & (1 << 11)) == (1 << 11));
legacy_speed = (legacy_status & (3 << 9));
if (legacy_speed == (0 << 9))
@@ -9748,7 +9760,7 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
else
vars->duplex = DUPLEX_HALF;
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Link is up in %dMbps, is_duplex_full= %d",
vars->line_speed,
(vars->duplex == DUPLEX_FULL));
@@ -9770,7 +9782,7 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
}
}
if (link_up) {
- PMD_DRV_LOG(DEBUG, "BNX2X848x3: link speed is %d",
+ PMD_DRV_LOG(DEBUG, sc, "BNX2X848x3: link speed is %d",
vars->line_speed);
elink_ext_phy_resolve_fc(phy, params, vars);
@@ -9887,7 +9899,7 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
switch (mode) {
case ELINK_LED_MODE_OFF:
- PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OFF", port);
+ PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OFF", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
@@ -9917,7 +9929,8 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
break;
case ELINK_LED_MODE_FRONT_PANEL_OFF:
- PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE FRONT PANEL OFF", port);
+ PMD_DRV_LOG(DEBUG, sc,
+ "Port 0x%x: LED MODE FRONT PANEL OFF", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
@@ -9967,7 +9980,7 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
break;
case ELINK_LED_MODE_ON:
- PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE ON", port);
+ PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE ON", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
@@ -10027,7 +10040,7 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
case ELINK_LED_MODE_OPER:
- PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OPER", port);
+ PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OPER", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
@@ -10042,7 +10055,7 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
>>
MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))
{
- PMD_DRV_LOG(DEBUG, "Setting LINK_SIGNAL");
+ PMD_DRV_LOG(DEBUG, sc, "Setting LINK_SIGNAL");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8481_LINK_SIGNAL,
@@ -10155,7 +10168,7 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
uint32_t cfg_pin;
- PMD_DRV_LOG(DEBUG, "54618SE cfg init");
+ PMD_DRV_LOG(DEBUG, sc, "54618SE cfg init");
DELAY(1000 * 1);
/* This works with E3 only, no need to check the chip
@@ -10228,7 +10241,7 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
autoneg_val |= (1 << 9 | 1 << 12);
if (phy->req_duplex == DUPLEX_FULL)
an_1000_val |= (1 << 9);
- PMD_DRV_LOG(DEBUG, "Advertising 1G");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
} else
an_1000_val &= ~((1 << 8) | (1 << 9));
@@ -10241,25 +10254,25 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
an_10_100_val |= (1 << 5);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, "Advertising 10M-HD");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
}
if (phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
an_10_100_val |= (1 << 6);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, "Advertising 10M-FD");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
}
if (phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
an_10_100_val |= (1 << 7);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, "Advertising 100M-HD");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
}
if (phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
an_10_100_val |= (1 << 8);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, "Advertising 100M-FD");
+ PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
}
}
@@ -10268,12 +10281,12 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
autoneg_val |= (1 << 13);
/* Enabled AUTO-MDIX when autoneg is disabled */
elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
- PMD_DRV_LOG(DEBUG, "Setting 100M force");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
}
if (phy->req_line_speed == ELINK_SPEED_10) {
/* Enabled AUTO-MDIX when autoneg is disabled */
elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
- PMD_DRV_LOG(DEBUG, "Setting 10M force");
+ PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
}
if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
@@ -10288,7 +10301,7 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers");
+ PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
elink_eee_disable(phy, params, vars);
} else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
(phy->req_duplex == DUPLEX_FULL) &&
@@ -10302,7 +10315,7 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
elink_eee_advertise(phy, params, vars,
SHMEM_EEE_1G_ADV);
} else {
- PMD_DRV_LOG(DEBUG, "Don't Advertise 1GBase-T EEE");
+ PMD_DRV_LOG(DEBUG, sc, "Don't Advertise 1GBase-T EEE");
elink_eee_disable(phy, params, vars);
}
} else {
@@ -10314,10 +10327,10 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
if (params->feature_config_flags &
ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
temp = 6;
- PMD_DRV_LOG(DEBUG, "Enabling Auto-GrEEEn");
+ PMD_DRV_LOG(DEBUG, sc, "Enabling Auto-GrEEEn");
} else {
temp = 0;
- PMD_DRV_LOG(DEBUG, "Don't Adv. EEE");
+ PMD_DRV_LOG(DEBUG, sc, "Don't Adv. EEE");
}
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_EEE_ADV, temp);
@@ -10345,7 +10358,7 @@ static void elink_5461x_set_link_led(struct elink_phy *phy,
elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
temp &= 0xff00;
- PMD_DRV_LOG(DEBUG, "54618x set link led (mode=%x)", mode);
+ PMD_DRV_LOG(DEBUG, sc, "54618x set link led (mode=%x)", mode);
switch (mode) {
case ELINK_LED_MODE_FRONT_PANEL_OFF:
case ELINK_LED_MODE_OFF:
@@ -10403,7 +10416,7 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,
/* Get speed operation status */
elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);
- PMD_DRV_LOG(DEBUG, "54618SE read_status: 0x%x", legacy_status);
+ PMD_DRV_LOG(DEBUG, sc, "54618SE read_status: 0x%x", legacy_status);
/* Read status to clear the PHY interrupt. */
elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);
@@ -10435,7 +10448,7 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,
} else /* Should not happen */
vars->line_speed = 0;
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Link is up in %dMbps, is_duplex_full= %d",
vars->line_speed, (vars->duplex == DUPLEX_FULL));
@@ -10449,7 +10462,7 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,
vars->link_status |=
LINK_STATUS_PARALLEL_DETECTION_USED;
- PMD_DRV_LOG(DEBUG, "BNX2X54618SE: link speed is %d",
+ PMD_DRV_LOG(DEBUG, sc, "BNX2X54618SE: link speed is %d",
vars->line_speed);
elink_ext_phy_resolve_fc(phy, params, vars);
@@ -10497,7 +10510,7 @@ static void elink_54618se_config_loopback(struct elink_phy *phy,
uint16_t val;
uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
- PMD_DRV_LOG(DEBUG, "2PMA/PMD ext_phy_loopback: 54618se");
+ PMD_DRV_LOG(DEBUG, sc, "2PMA/PMD ext_phy_loopback: 54618se");
/* Enable master/slave manual mmode and set to master */
/* mii write 9 [bits set 11 12] */
@@ -10548,7 +10561,7 @@ static uint8_t elink_7101_config_init(struct elink_phy *phy,
{
uint16_t fw_ver1, fw_ver2, val;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LASI indication");
+ PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LASI indication");
/* Restore normal power mode */
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
@@ -10558,7 +10571,7 @@ static uint8_t elink_7101_config_init(struct elink_phy *phy,
elink_wait_reset_complete(sc, phy, params);
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
- PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LED to blink on traffic");
+ PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LED to blink on traffic");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));
@@ -10589,10 +10602,10 @@ static uint8_t elink_7101_read_status(struct elink_phy *phy,
uint16_t val1, val2;
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- PMD_DRV_LOG(DEBUG, "10G-base-T LASI status 0x%x->0x%x", val2, val1);
+ PMD_DRV_LOG(DEBUG, sc, "10G-base-T LASI status 0x%x->0x%x", val2, val1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, "10G-base-T PMA status 0x%x->0x%x", val2, val1);
+ PMD_DRV_LOG(DEBUG, sc, "10G-base-T PMA status 0x%x->0x%x", val2, val1);
link_up = ((val1 & 4) == 4);
/* If link is up print the AN outcome of the SFX7101 PHY */
if (link_up) {
@@ -10601,7 +10614,7 @@ static uint8_t elink_7101_read_status(struct elink_phy *phy,
&val2);
vars->line_speed = ELINK_SPEED_10000;
vars->duplex = DUPLEX_FULL;
- PMD_DRV_LOG(DEBUG, "SFX7101 AN status 0x%x->Master=%x",
+ PMD_DRV_LOG(DEBUG, sc, "SFX7101 AN status 0x%x->Master=%x",
val2, (val2 & (1 << 14)));
elink_ext_phy_10G_an_resolve(sc, phy, vars);
elink_ext_phy_resolve_fc(phy, params, vars);
@@ -11208,7 +11221,7 @@ static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,
external_phy_config2));
break;
default:
- PMD_DRV_LOG(DEBUG, "Invalid phy_index %d", phy_index);
+ PMD_DRV_LOG(DEBUG, sc, "Invalid phy_index %d", phy_index);
return ELINK_STATUS_ERROR;
}
@@ -11231,7 +11244,7 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
(REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
- PMD_DRV_LOG(DEBUG, ":chip_id = 0x%x", chip_id);
+ PMD_DRV_LOG(DEBUG, sc, ":chip_id = 0x%x", chip_id);
if (USES_WARPCORE(sc)) {
uint32_t serdes_net_if;
phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
@@ -11308,7 +11321,7 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
break;
default:
- PMD_DRV_LOG(DEBUG, "Unknown WC interface type 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Unknown WC interface type 0x%x",
serdes_net_if);
break;
}
@@ -11336,7 +11349,7 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
*phy = phy_xgxs;
break;
default:
- PMD_DRV_LOG(DEBUG, "Invalid switch_cfg");
+ PMD_DRV_LOG(DEBUG, sc, "Invalid switch_cfg");
return ELINK_STATUS_ERROR;
}
}
@@ -11349,7 +11362,7 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
else
phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
- PMD_DRV_LOG(DEBUG, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
port, phy->addr, phy->mdio_ctrl);
elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
@@ -11476,9 +11489,9 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
ELINK_SUPPORTED_100baseT_Full);
}
- PMD_DRV_LOG(DEBUG, "phy_type 0x%x port %d found in index %d",
+ PMD_DRV_LOG(DEBUG, sc, "phy_type 0x%x port %d found in index %d",
phy_type, port, phy_index);
- PMD_DRV_LOG(DEBUG, " addr=0x%x, mdio_ctl=0x%x",
+ PMD_DRV_LOG(DEBUG, sc, " addr=0x%x, mdio_ctl=0x%x",
phy->addr, phy->mdio_ctrl);
return ELINK_STATUS_OK;
}
@@ -11527,7 +11540,7 @@ static void elink_phy_def_cfg(struct elink_params *params,
speed_capability_mask));
}
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
phy_index, link_config, phy->speed_cap_mask);
@@ -11618,7 +11631,7 @@ elink_status_t elink_phy_probe(struct elink_params * params)
struct bnx2x_softc *sc = params->sc;
struct elink_phy *phy;
params->num_phys = 0;
- PMD_DRV_LOG(DEBUG, "Begin phy probe");
+ PMD_DRV_LOG(DEBUG, sc, "Begin phy probe");
phy_config_swapped = params->multi_phy_config &
PORT_HW_CFG_PHY_SWAPPED_ENABLED;
@@ -11631,7 +11644,7 @@ elink_status_t elink_phy_probe(struct elink_params * params)
else if (phy_index == ELINK_EXT_PHY2)
actual_phy_idx = ELINK_EXT_PHY1;
}
- PMD_DRV_LOG(DEBUG, "phy_config_swapped %x, phy_index %x,"
+ PMD_DRV_LOG(DEBUG, sc, "phy_config_swapped %x, phy_index %x,"
" actual_phy_idx %x", phy_config_swapped,
phy_index, actual_phy_idx);
phy = ¶ms->phy[actual_phy_idx];
@@ -11639,7 +11652,7 @@ elink_status_t elink_phy_probe(struct elink_params * params)
params->shmem2_base, params->port,
phy) != ELINK_STATUS_OK) {
params->num_phys = 0;
- PMD_DRV_LOG(DEBUG, "phy probe failed in phy index %d",
+ PMD_DRV_LOG(DEBUG, sc, "phy probe failed in phy index %d",
phy_index);
for (phy_index = ELINK_INT_PHY;
phy_index < ELINK_MAX_PHYS; phy_index++)
@@ -11680,7 +11693,8 @@ elink_status_t elink_phy_probe(struct elink_params * params)
params->num_phys++;
}
- PMD_DRV_LOG(DEBUG, "End phy probe. #phys found %x", params->num_phys);
+ PMD_DRV_LOG(DEBUG, sc,
+ "End phy probe. #phys found %x", params->num_phys);
return ELINK_STATUS_OK;
}
@@ -11850,7 +11864,7 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,
for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
struct elink_phy *phy = ¶ms->phy[phy_idx];
if (phy->phy_specific_func) {
- PMD_DRV_LOG(DEBUG, "Calling PHY specific func");
+ PMD_DRV_LOG(DEBUG, sc, "Calling PHY specific func");
phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
}
if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
@@ -11970,12 +11984,13 @@ elink_status_t elink_phy_init(struct elink_params *params,
{
int lfa_status;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, "Phy Initialization started");
- PMD_DRV_LOG(DEBUG, "(1) req_speed %d, req_flowctrl %d",
+ PMD_DRV_LOG(DEBUG, sc, "Phy Initialization started");
+ PMD_DRV_LOG(DEBUG, sc, "(1) req_speed %d, req_flowctrl %d",
params->req_line_speed[0], params->req_flow_ctrl[0]);
- PMD_DRV_LOG(DEBUG, "(2) req_speed %d, req_flowctrl %d",
+ PMD_DRV_LOG(DEBUG, sc, "(2) req_speed %d, req_flowctrl %d",
params->req_line_speed[1], params->req_flow_ctrl[1]);
- PMD_DRV_LOG(DEBUG, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
+ PMD_DRV_LOG(DEBUG, sc,
+ "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
vars->link_status = 0;
vars->phy_link_up = 0;
vars->link_up = 0;
@@ -11992,11 +12007,13 @@ elink_status_t elink_phy_init(struct elink_params *params,
lfa_status = elink_check_lfa(params);
if (lfa_status == 0) {
- PMD_DRV_LOG(DEBUG, "Link Flap Avoidance in progress");
+ PMD_DRV_LOG(DEBUG, sc,
+ "Link Flap Avoidance in progress");
return elink_avoid_link_flap(params, vars);
}
- PMD_DRV_LOG(DEBUG, "Cannot avoid link flap lfa_sta=0x%x", lfa_status);
+ PMD_DRV_LOG(DEBUG, sc,
+ "Cannot avoid link flap lfa_sta=0x%x", lfa_status);
elink_cannot_avoid_link_flap(params, vars, lfa_status);
/* Disable attentions */
@@ -12012,12 +12029,12 @@ elink_status_t elink_phy_init(struct elink_params *params,
vars->link_status |= LINK_STATUS_PFC_ENABLED;
if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {
- PMD_DRV_LOG(DEBUG, "No phy found for initialization !!");
+ PMD_DRV_LOG(DEBUG, sc, "No phy found for initialization !!");
return ELINK_STATUS_ERROR;
}
set_phy_vars(params, vars);
- PMD_DRV_LOG(DEBUG, "Num of phys on board: %d", params->num_phys);
+ PMD_DRV_LOG(DEBUG, sc, "Num of phys on board: %d", params->num_phys);
switch (params->loopback_mode) {
case ELINK_LOOPBACK_BMAC:
@@ -12060,7 +12077,7 @@ static elink_status_t elink_link_reset(struct elink_params *params,
{
struct bnx2x_softc *sc = params->sc;
uint8_t phy_index, port = params->port, clear_latch_ind = 0;
- PMD_DRV_LOG(DEBUG, "Resetting the link of port %d", port);
+ PMD_DRV_LOG(DEBUG, sc, "Resetting the link of port %d", port);
/* Disable attentions */
vars->link_status = 0;
elink_update_mng(params, vars->link_status);
@@ -12238,7 +12255,7 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port_of_path, &phy[port]) !=
ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "populate_phy failed");
+ PMD_DRV_LOG(DEBUG, sc, "populate_phy failed");
return ELINK_STATUS_ERROR;
}
/* Disable attentions */
@@ -12278,7 +12295,7 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
else
port_of_path = 0;
- PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
phy_blk[port]->addr);
if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
port_of_path))
@@ -12362,7 +12379,7 @@ static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
/* Extract the ext phy address for the port */
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port, &phy) != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "populate phy failed");
+ PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
return ELINK_STATUS_ERROR;
}
@@ -12482,7 +12499,7 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port_of_path, &phy[port]) !=
ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "populate phy failed");
+ PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
return ELINK_STATUS_ERROR;
}
/* disable attentions */
@@ -12513,7 +12530,7 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
port_of_path = port;
else
port_of_path = 0;
- PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
phy_blk[port]->addr);
if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
port_of_path))
@@ -12540,7 +12557,8 @@ static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
DELAY(10);
elink_cb_gpio_mult_write(sc, reset_gpios,
MISC_REGISTERS_GPIO_OUTPUT_HIGH);
- PMD_DRV_LOG(DEBUG, "84833 reset pulse on pin values 0x%x", reset_gpios);
+ PMD_DRV_LOG(DEBUG, sc,
+ "84833 reset pulse on pin values 0x%x", reset_gpios);
return ELINK_STATUS_OK;
}
@@ -12588,7 +12606,7 @@ static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
rc = ELINK_STATUS_ERROR;
break;
default:
- PMD_DRV_LOG(DEBUG,
+ PMD_DRV_LOG(DEBUG, sc,
"ext_phy 0x%x common init not required",
ext_phy_type);
break;
@@ -12614,7 +12632,7 @@ elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
elink_set_mdio_clk(sc, GRCBASE_EMAC0);
elink_set_mdio_clk(sc, GRCBASE_EMAC1);
- PMD_DRV_LOG(DEBUG, "Begin common phy init");
+ PMD_DRV_LOG(DEBUG, sc, "Begin common phy init");
if (CHIP_IS_E3(sc)) {
/* Enable EPIO */
val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
@@ -12625,7 +12643,7 @@ elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
offsetof(struct shmem_region,
port_mb[PORT_0].ext_phy_fw_version));
if (phy_ver) {
- PMD_DRV_LOG(DEBUG, "Not doing common init; phy ver is 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Not doing common init; phy ver is 0x%x",
phy_ver);
return ELINK_STATUS_OK;
}
@@ -12697,15 +12715,15 @@ static uint8_t elink_analyze_link_error(struct elink_params *params,
/* If values differ */
switch (phy_flag) {
case PHY_HALF_OPEN_CONN_FLAG:
- PMD_DRV_LOG(DEBUG, "Analyze Remote Fault");
+ PMD_DRV_LOG(DEBUG, sc, "Analyze Remote Fault");
break;
case PHY_SFP_TX_FAULT_FLAG:
- PMD_DRV_LOG(DEBUG, "Analyze TX Fault");
+ PMD_DRV_LOG(DEBUG, sc, "Analyze TX Fault");
break;
default:
- PMD_DRV_LOG(DEBUG, "Analyze UNKNOWN");
+ PMD_DRV_LOG(DEBUG, sc, "Analyze UNKNOWN");
}
- PMD_DRV_LOG(DEBUG, "Link changed:[%x %x]->%x", vars->link_up,
+ PMD_DRV_LOG(DEBUG, sc, "Link changed:[%x %x]->%x", vars->link_up,
old_status, status);
/* a. Update shmem->link_status accordingly
@@ -12831,7 +12849,7 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
PORT_HW_CFG_E3_TX_FAULT_SHIFT;
if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
- PMD_DRV_LOG(DEBUG, "Failed to read pin 0x%02x", cfg_pin);
+ PMD_DRV_LOG(DEBUG, sc, "Failed to read pin 0x%02x", cfg_pin);
return;
}
@@ -12853,7 +12871,7 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
/* If module is unapproved, led should be on regardless */
if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
- PMD_DRV_LOG(DEBUG, "Change TX_Fault LED: ->%x",
+ PMD_DRV_LOG(DEBUG, sc, "Change TX_Fault LED: ->%x",
led_mode);
elink_set_e3_module_fault_led(params, led_mode);
}
@@ -12863,7 +12881,7 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
static void elink_kr2_recovery(struct elink_params *params,
struct elink_vars *vars, struct elink_phy *phy)
{
- PMD_DRV_LOG(DEBUG, "KR2 recovery");
+ PMD_DRV_LOG(DEBUG, params->sc, "KR2 recovery");
elink_warpcore_enable_AN_KR2(phy, params, vars);
elink_warpcore_restart_AN_KR(phy, params);
@@ -12890,7 +12908,7 @@ static void elink_check_kr2_wa(struct elink_params *params,
if (!sigdet) {
if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
elink_kr2_recovery(params, vars, phy);
- PMD_DRV_LOG(DEBUG, "No sigdet");
+ PMD_DRV_LOG(DEBUG, sc, "No sigdet");
}
return;
}
@@ -12908,7 +12926,7 @@ static void elink_check_kr2_wa(struct elink_params *params,
if (base_page == 0) {
if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
elink_kr2_recovery(params, vars, phy);
- PMD_DRV_LOG(DEBUG, "No BP");
+ PMD_DRV_LOG(DEBUG, sc, "No BP");
}
return;
}
@@ -12924,7 +12942,7 @@ static void elink_check_kr2_wa(struct elink_params *params,
/* In case KR2 is already disabled, check if we need to re-enable it */
if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
if (!not_kr2_device) {
- PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page,
+ PMD_DRV_LOG(DEBUG, sc, "BP=0x%x, NP=0x%x", base_page,
next_page);
elink_kr2_recovery(params, vars, phy);
}
@@ -12933,7 +12951,8 @@ static void elink_check_kr2_wa(struct elink_params *params,
/* KR2 is enabled, but not KR2 device */
if (not_kr2_device) {
/* Disable KR2 on both lanes */
- PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, next_page);
+ PMD_DRV_LOG(DEBUG, sc,
+ "BP=0x%x, NP=0x%x", base_page, next_page);
elink_disable_kr2(params, vars, phy);
/* Restart AN on leading lane */
elink_warpcore_restart_AN_KR(phy, params);
@@ -12950,7 +12969,7 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)
elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
if (elink_check_half_open_conn(params, vars, 1) !=
ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "Fault detection failed");
+ PMD_DRV_LOG(DEBUG, sc, "Fault detection failed");
}
break;
}
@@ -12996,7 +13015,7 @@ uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port, &phy)
!= ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "populate phy failed");
+ PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
return 0;
}
fan_failure_det_req |= (phy.flags &
@@ -13046,7 +13065,7 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
if (elink_populate_phy(sc, phy_index, shmem_base,
shmem2_base, port, &phy)
!= ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, "populate phy failed");
+ PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
return;
}
if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {
@@ -13076,7 +13095,7 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
dev_info.port_hw_config[port].aeu_int_mask);
REG_WR(sc, sync_offset, vars->aeu_int_mask);
- PMD_DRV_LOG(DEBUG, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
+ PMD_DRV_LOG(DEBUG, sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
gpio_num, gpio_port, vars->aeu_int_mask);
if (port == 0)
--
1.7.10.3
^ permalink raw reply [flat|nested] 13+ messages in thread* [dpdk-dev] [PATCH v2 2/5] net/bnx2x: update link/PHY management
2018-09-19 21:59 [dpdk-dev] [PATCH 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
` (4 preceding siblings ...)
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
@ 2018-09-29 5:42 ` Mody, Rasesh
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 3/5] net/bnx2x: fix to disable further interrupts Mody, Rasesh
` (2 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-29 5:42 UTC (permalink / raw)
To: dev; +Cc: Mody, Rasesh, ferruh.yigit, Dept-Eng DPDK Dev
This patch has changes to update the link/PHY management (elink) code
to the latest.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x.h | 3 +
drivers/net/bnx2x/ecore_hsi.h | 20 +-
drivers/net/bnx2x/elink.c | 7916 ++++++++++++++++++++++++++---------------
drivers/net/bnx2x/elink.h | 236 +-
4 files changed, 5217 insertions(+), 2958 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 2d545f5..1cc5a6b 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -824,6 +824,7 @@ struct bnx2x_devinfo {
#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
/* device ids */
+#define CHIP_NUM_57710 0x164e
#define CHIP_NUM_57711 0x164f
#define CHIP_NUM_57711E 0x1650
#define CHIP_NUM_57712 0x1662
@@ -865,6 +866,8 @@ struct bnx2x_devinfo {
#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
+#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
+#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h
index 57085eb..1192e5d 100644
--- a/drivers/net/bnx2x/ecore_hsi.h
+++ b/drivers/net/bnx2x/ecore_hsi.h
@@ -500,6 +500,18 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
+ /* Set non-default values for TXFIR in SFP mode. */
+ #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
+ #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
+
+ /* Set non-default values for IPREDRIVER in SFP mode. */
+ #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
+ #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24
+
+ /* Set non-default values for POST2 in SFP mode. */
+ #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
+ #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28
+
uint32_t reserved0[5]; /* 0x17c */
uint32_t aeu_int_mask; /* 0x190 */
@@ -783,6 +795,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722 0x00000f00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616 0x00001000
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834 0x00001100
+ #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858 0x00001200
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
@@ -2532,7 +2545,12 @@ struct shmem2_region {
uint32_t drv_func_info_addr; /* Offset 0x14C */
uint32_t drv_func_info_size; /* Offset 0x150 */
uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */
- #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0)
+ #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
+ #define LINK_ATTR_84858 0x00000002
+ #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
+ #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
+
+ uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
};
diff --git a/drivers/net/bnx2x/elink.c b/drivers/net/bnx2x/elink.c
index 1f94476..9b3e00a 100644
--- a/drivers/net/bnx2x/elink.c
+++ b/drivers/net/bnx2x/elink.c
@@ -18,166 +18,159 @@
#include "ecore_hsi.h"
#include "ecore_reg.h"
-static elink_status_t elink_link_reset(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t reset_ext_phy);
-static elink_status_t elink_check_half_open_conn(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t notify);
-static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
- struct elink_params *params);
#define MDIO_REG_BANK_CL73_IEEEB0 0x0
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
+ #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
+ #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
+ #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
+ #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
#define MDIO_REG_BANK_CL73_IEEEB1 0x10
-#define MDIO_CL73_IEEEB1_AN_ADV1 0x00
-#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
-#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
-#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
-#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
-#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
-#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
-#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
-#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
+ #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
+ #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
+ #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
+ #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
+ #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
+ #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
+ #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
+ #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
+ #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
+ #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
+ #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
#define MDIO_REG_BANK_RX0 0x80b0
-#define MDIO_RX0_RX_STATUS 0x10
-#define MDIO_RX0_RX_STATUS_SIGDET 0x8000
-#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
-#define MDIO_RX0_RX_EQ_BOOST 0x1c
-#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX0_RX_STATUS 0x10
+ #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
+ #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
+ #define MDIO_RX0_RX_EQ_BOOST 0x1c
+ #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_RX1 0x80c0
-#define MDIO_RX1_RX_EQ_BOOST 0x1c
-#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX1_RX_EQ_BOOST 0x1c
+ #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_RX2 0x80d0
-#define MDIO_RX2_RX_EQ_BOOST 0x1c
-#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX2_RX_EQ_BOOST 0x1c
+ #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_RX3 0x80e0
-#define MDIO_RX3_RX_EQ_BOOST 0x1c
-#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX3_RX_EQ_BOOST 0x1c
+ #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_RX_ALL 0x80f0
-#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
-#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
-#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
+ #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
+ #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+ #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
#define MDIO_REG_BANK_TX0 0x8060
-#define MDIO_TX0_TX_DRIVER 0x17
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+ #define MDIO_TX0_TX_DRIVER 0x17
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+ #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
#define MDIO_REG_BANK_TX1 0x8070
-#define MDIO_TX1_TX_DRIVER 0x17
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+ #define MDIO_TX1_TX_DRIVER 0x17
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+ #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
#define MDIO_REG_BANK_TX2 0x8080
-#define MDIO_TX2_TX_DRIVER 0x17
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+ #define MDIO_TX2_TX_DRIVER 0x17
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+ #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
#define MDIO_REG_BANK_TX3 0x8090
-#define MDIO_TX3_TX_DRIVER 0x17
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+ #define MDIO_TX3_TX_DRIVER 0x17
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+ #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+ #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+ #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+ #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+ #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
-#define MDIO_BLOCK0_XGXS_CONTROL 0x10
+ #define MDIO_BLOCK0_XGXS_CONTROL 0x10
#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
-#define MDIO_BLOCK1_LANE_CTRL0 0x15
-#define MDIO_BLOCK1_LANE_CTRL1 0x16
-#define MDIO_BLOCK1_LANE_CTRL2 0x17
-#define MDIO_BLOCK1_LANE_PRBS 0x19
+ #define MDIO_BLOCK1_LANE_CTRL0 0x15
+ #define MDIO_BLOCK1_LANE_CTRL1 0x16
+ #define MDIO_BLOCK1_LANE_CTRL2 0x17
+ #define MDIO_BLOCK1_LANE_PRBS 0x19
#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
-#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
-#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
-#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
-#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
-#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
-#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
-#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
-#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
-#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
+ #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
+ #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
+ #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
+ #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
+ #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
+ #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
+ #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
+ #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
+ #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
#define MDIO_REG_BANK_GP_STATUS 0x8120
#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
-#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
+ #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
+
#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
@@ -320,6 +313,7 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
Theotherbitsarereservedandshouldbezero*/
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
+
#define MDIO_PMA_DEVAD 0x1
/*ieee*/
#define MDIO_PMA_REG_CTRL 0x0
@@ -328,7 +322,7 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PMA_REG_TX_DISABLE 0x0009
#define MDIO_PMA_REG_RX_SD 0xa
/*bnx2x*/
-#define MDIO_PMA_REG_BNX2X_CTRL 0x0096
+#define MDIO_PMA_REG_BCM_CTRL 0x0096
#define MDIO_PMA_REG_FEC_CTRL 0x00ab
#define MDIO_PMA_LASI_RXCTRL 0x9000
#define MDIO_PMA_LASI_TXCTRL 0x9001
@@ -343,8 +337,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
#define MDIO_PMA_REG_MISC_CTRL 0xca0a
#define MDIO_PMA_REG_GEN_CTRL 0xca10
-#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
-#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
+ #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
+ #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
#define MDIO_PMA_REG_ROM_VER1 0xca19
@@ -358,21 +352,21 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PMA_REG_MISC_CTRL1 0xca85
#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
-#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
-#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
-#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
+ #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
-#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
+ #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
#define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
@@ -404,6 +398,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
+
+
#define MDIO_WIS_DEVAD 0x2
/*bnx2x*/
#define MDIO_WIS_REG_LASI_CNTL 0x9002
@@ -415,13 +411,15 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
-#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
+ #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
-#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
-#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
-#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
+ #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
+ #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
+ #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
+
+
#define MDIO_XS_DEVAD 0x4
#define MDIO_XS_REG_STATUS 0x0001
#define MDIO_XS_PLL_SEQUENCER 0x8000
@@ -439,12 +437,12 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
/*ieee*/
#define MDIO_AN_REG_CTRL 0x0000
#define MDIO_AN_REG_STATUS 0x0001
-#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
+ #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
#define MDIO_AN_REG_ADV_PAUSE 0x0010
-#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
-#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
-#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
-#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
+ #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
+ #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
+ #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
+ #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
#define MDIO_AN_REG_ADV 0x0011
#define MDIO_AN_REG_ADV2 0x0012
#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
@@ -465,13 +463,16 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
-#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
+ #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
+#define MDIO_AN_REG_848xx_ID_MSB 0xffe2
+ #define BNX2X84858_PHY_ID 0x600d
+#define MDIO_AN_REG_848xx_ID_LSB 0xffe3
#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
-#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
+ #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
@@ -480,62 +481,62 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
/* BNX2X84823 only */
#define MDIO_CTL_DEVAD 0x1e
#define MDIO_CTL_REG_84823_MEDIA 0x401a
-#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
+ #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
/* These pins configure the BNX2X84823 interface to MAC after reset. */
-#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
-#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
+ #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
+ #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
/* These pins configure the BNX2X84823 interface to Line after reset. */
-#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
-#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
-#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
+ #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
+ #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
+ #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
/* When this pin is active high during reset, 10GBASE-T core is power
* down, When it is active low the 10GBASE-T is power up
*/
-#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
-#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
-#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
-#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
-#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
+ #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
+ #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
+ #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
+ #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
+ #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
-#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
+ #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
-#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
+ #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
-#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
+ #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
/* BNX2X84833 only */
#define MDIO_84833_TOP_CFG_FW_REV 0x400f
-#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
-#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
+#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
+#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
-#define MDIO_84833_SUPER_ISOLATE 0x8000
-/* These are mailbox register set used by 84833. */
-#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
-#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
-#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
-#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
-#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
-#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
-#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
-#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
-#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
-#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
-#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
-#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
-#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
-#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
-#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
-#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
-#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
-#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
-
-/* Mailbox command set used by 84833. */
-#define PHY84833_CMD_SET_PAIR_SWAP 0x8001
-#define PHY84833_CMD_GET_EEE_MODE 0x8008
-#define PHY84833_CMD_SET_EEE_MODE 0x8009
-#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
-/* Mailbox status set used by 84833. */
+#define MDIO_84833_SUPER_ISOLATE 0x8000
+/* These are mailbox register set used by 84833/84858. */
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
+#define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
+#define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)
+#define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)
+#define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)
+#define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)
+#define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)
+#define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)
+#define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)
+
+/* Mailbox command set used by 84833/84858 */
+#define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
+#define PHY848xx_CMD_GET_EEE_MODE 0x8008
+#define PHY848xx_CMD_SET_EEE_MODE 0x8009
+#define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031
+/* Mailbox status set used by 84833 only */
#define PHY84833_STATUS_CMD_RECEIVED 0x0001
#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
@@ -545,6 +546,19 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
+/* Mailbox Process */
+#define PHY84833_MB_PROCESS1 1
+#define PHY84833_MB_PROCESS2 2
+#define PHY84833_MB_PROCESS3 3
+
+
+/* Mailbox status set used by 84858 only */
+#define PHY84858_STATUS_CMD_RECEIVED 0x0001
+#define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
+#define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
+#define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
+#define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
+
/* Warpcore clause 45 addressing */
#define MDIO_WC_DEVAD 0x3
@@ -553,8 +567,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
-#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
-#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
+ #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
+ #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
#define MDIO_WC_REG_PCS_STATUS2 0x0021
#define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
@@ -570,6 +584,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
+#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
@@ -585,7 +601,9 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
+#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
+#define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a
#define MDIO_WC_REG_XGXS_STATUS3 0x8129
#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
@@ -599,35 +617,35 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
-#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
+ #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
+ #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
+ #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
+ #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
-#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
+ #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
#define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
#define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
#define MDIO_WC_REG_DSC_SMC 0x8213
#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
#define MDIO_WC_REG_TX_FIR_TAP 0x82e2
-#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
-#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
-#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
-#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
-#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
-#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
-#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
+ #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
+ #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
+ #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
+ #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
+ #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
+ #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
+ #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
@@ -689,8 +707,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
-#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
-#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
+#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
+#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
@@ -700,33 +718,31 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
#define MDIO_REG_GPHY_MII_STATUS 0x1
#define MDIO_REG_GPHY_PHYID_LSB 0x3
#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
-#define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
-#define MDIO_REG_GPHY_CL45_REG_READ 0xc000
+ #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
+ #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
-#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
+ #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
#define MDIO_REG_GPHY_EXP_ACCESS 0x17
-#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
-#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
+ #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
+ #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
#define MDIO_REG_GPHY_AUX_STATUS 0x19
#define MDIO_REG_INTR_STATUS 0x1a
#define MDIO_REG_INTR_MASK 0x1b
-#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
+ #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
#define MDIO_REG_GPHY_SHADOW 0x1c
-#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
-#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
-#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
-#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
-#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
-
-typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
- struct elink_params *
- params,
- uint8_t dev_addr,
- uint16_t addr,
- uint8_t byte_cnt,
- uint8_t * o_buf,
- uint8_t);
+ #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
+ #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
+ #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
+ #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
+ #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
+
+
+typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
+ struct elink_params *params,
+ uint8_t dev_addr, uint16_t addr,
+ uint8_t byte_cnt,
+ uint8_t *o_buf, uint8_t);
/********************************************************/
#define ELINK_ETH_HLEN 14
/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
@@ -850,21 +866,29 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
#define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
-#define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
-#define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
-#define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
+ #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
+ #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
+ #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
+ #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
+
+
+#define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR 0x3
+ #define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK (1 << 4)
+ #define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK (1 << 5)
+ #define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1 << 6)
-#define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
-#define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
-#define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
-#define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
+#define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR 0x6
+ #define ELINK_SFP_EEPROM_1G_COMP_CODE_SX (1 << 0)
+ #define ELINK_SFP_EEPROM_1G_COMP_CODE_LX (1 << 1)
+ #define ELINK_SFP_EEPROM_1G_COMP_CODE_CX (1 << 2)
+ #define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T (1 << 3)
#define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
-#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
-#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
+ #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
+ #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
#define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
-#define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
+ #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
#define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
#define ELINK_EDC_MODE_LINEAR 0x0022
@@ -883,6 +907,10 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
#define ELINK_MAX_PACKET_SIZE (9700)
#define MAX_KR_LINK_RETRY 4
+#define DEFAULT_TX_DRV_BRDCT 2
+#define DEFAULT_TX_DRV_IFIR 0
+#define DEFAULT_TX_DRV_POST2 3
+#define DEFAULT_TX_DRV_IPRE_DRIVER 6
/**********************************************************/
/* INTERFACE */
@@ -900,6 +928,11 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
(_bank + (_addr & 0xf)), \
_val)
+static elink_status_t elink_check_half_open_conn(struct elink_params *params,
+ struct elink_vars *vars, uint8_t notify);
+static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
+ struct elink_params *params);
+
static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits)
{
uint32_t val = REG_RD(sc, reg);
@@ -935,16 +968,16 @@ static int elink_check_lfa(struct elink_params *params)
struct bnx2x_softc *sc = params->sc;
additional_config =
- REG_RD(sc, params->lfa_base +
- offsetof(struct shmem_lfa, additional_config));
+ REG_RD(sc, params->lfa_base +
+ offsetof(struct shmem_lfa, additional_config));
/* NOTE: must be first condition checked -
- * to verify DCC bit is cleared in any case!
- */
+ * to verify DCC bit is cleared in any case!
+ */
if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
- PMD_DRV_LOG(DEBUG, sc, "No LFA due to DCC flap after clp exit");
+ ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit");
REG_WR(sc, params->lfa_base +
- offsetof(struct shmem_lfa, additional_config),
+ offsetof(struct shmem_lfa, additional_config),
additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
return LFA_DCC_LFA_DISABLED;
}
@@ -983,8 +1016,8 @@ static int elink_check_lfa(struct elink_params *params)
offsetof(struct shmem_lfa, req_duplex));
req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
- PMD_DRV_LOG(INFO, sc, "Duplex mismatch %x vs. %x",
- (saved_val & lfa_mask), (req_val & lfa_mask));
+ ELINK_DEBUG_P2(sc, "Duplex mismatch %x vs. %x",
+ (saved_val & lfa_mask), (req_val & lfa_mask));
return LFA_DUPLEX_MISMATCH;
}
/* Compare Flow Control */
@@ -992,8 +1025,8 @@ static int elink_check_lfa(struct elink_params *params)
offsetof(struct shmem_lfa, req_flow_ctrl));
req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
- PMD_DRV_LOG(DEBUG, sc, "Flow control mismatch %x vs. %x",
- (saved_val & lfa_mask), (req_val & lfa_mask));
+ ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x",
+ (saved_val & lfa_mask), (req_val & lfa_mask));
return LFA_FLOW_CTRL_MISMATCH;
}
/* Compare Link Speed */
@@ -1001,8 +1034,8 @@ static int elink_check_lfa(struct elink_params *params)
offsetof(struct shmem_lfa, req_line_speed));
req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
- PMD_DRV_LOG(DEBUG, sc, "Link speed mismatch %x vs. %x",
- (saved_val & lfa_mask), (req_val & lfa_mask));
+ ELINK_DEBUG_P2(sc, "Link speed mismatch %x vs. %x",
+ (saved_val & lfa_mask), (req_val & lfa_mask));
return LFA_LINK_SPEED_MISMATCH;
}
@@ -1012,21 +1045,21 @@ static int elink_check_lfa(struct elink_params *params)
speed_cap_mask[cfg_idx]));
if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
- PMD_DRV_LOG(DEBUG, sc, "Speed Cap mismatch %x vs. %x",
- cur_speed_cap_mask,
- params->speed_cap_mask[cfg_idx]);
+ ELINK_DEBUG_P2(sc, "Speed Cap mismatch %x vs. %x",
+ cur_speed_cap_mask,
+ params->speed_cap_mask[cfg_idx]);
return LFA_SPEED_CAP_MISMATCH;
}
}
cur_req_fc_auto_adv =
- REG_RD(sc, params->lfa_base +
- offsetof(struct shmem_lfa, additional_config)) &
- REQ_FC_AUTO_ADV_MASK;
+ REG_RD(sc, params->lfa_base +
+ offsetof(struct shmem_lfa, additional_config)) &
+ REQ_FC_AUTO_ADV_MASK;
- if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {
- PMD_DRV_LOG(DEBUG, sc, "Flow Ctrl AN mismatch %x vs. %x",
- cur_req_fc_auto_adv, params->req_fc_auto_adv);
+ if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
+ ELINK_DEBUG_P2(sc, "Flow Ctrl AN mismatch %x vs. %x",
+ cur_req_fc_auto_adv, params->req_fc_auto_adv);
return LFA_FLOW_CTRL_MISMATCH;
}
@@ -1038,27 +1071,25 @@ static int elink_check_lfa(struct elink_params *params)
(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
(params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
- PMD_DRV_LOG(DEBUG, sc,
- "EEE mismatch %x vs. %x", params->eee_mode,
- eee_status);
+ ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x", params->eee_mode,
+ eee_status);
return LFA_EEE_MISMATCH;
}
/* LFA conditions are met */
return 0;
}
-
/******************************************************************/
/* EPIO/GPIO section */
/******************************************************************/
static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
- uint32_t * en)
+ uint32_t *en)
{
uint32_t epio_mask, gp_oenable;
*en = 0;
/* Sanity check */
if (epio_pin > 31) {
- PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to get", epio_pin);
+ ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to get", epio_pin);
return;
}
@@ -1069,17 +1100,16 @@ static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
*en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
}
-
static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en)
{
uint32_t epio_mask, gp_output, gp_oenable;
/* Sanity check */
if (epio_pin > 31) {
- PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to set", epio_pin);
+ ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to set", epio_pin);
return;
}
- PMD_DRV_LOG(DEBUG, sc, "Setting EPIO pin %d to %d", epio_pin, en);
+ ELINK_DEBUG_P2(sc, "Setting EPIO pin %d to %d", epio_pin, en);
epio_mask = 1 << epio_pin;
/* Set this EPIO to output */
gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
@@ -1105,12 +1135,12 @@ static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
} else {
uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
- elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port);
+ elink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port);
}
}
static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
- uint32_t * val)
+ uint32_t *val)
{
if (pin_cfg == PIN_CFG_NA)
return ELINK_STATUS_ERROR;
@@ -1122,14 +1152,939 @@ static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
*val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
}
return ELINK_STATUS_OK;
+}
+
+/******************************************************************/
+/* ETS section */
+/******************************************************************/
+static void elink_ets_e2e3a0_disabled(struct elink_params *params)
+{
+ /* ETS disabled configuration*/
+ struct bnx2x_softc *sc = params->sc;
+
+ ELINK_DEBUG_P0(sc, "ETS E2E3 disabled configuration");
+
+ /* mapping between entry priority to client number (0,1,2 -debug and
+ * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
+ * 3bits client num.
+ * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
+ * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
+ */
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ * as strict. Bits 0,1,2 - debug and management entries, 3 -
+ * COS0 entry, 4 - COS1 entry.
+ * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
+ * bit4 bit3 bit2 bit1 bit0
+ * MCP and debug are strict
+ */
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
+ /* defines which entries (clients) are subjected to WFQ arbitration */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
+ /* For strict priority entries defines the number of consecutive
+ * slots for the highest priority.
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
+ /* mapping between the CREDIT_WEIGHT registers and actual client
+ * numbers
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
+ REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
+ /* ETS mode disable */
+ REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
+ /* If ETS mode is enabled (there is no strict priority) defines a WFQ
+ * weight for COS0/COS1.
+ */
+ REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);
+ REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);
+ /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
+ REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);
+ REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);
+ /* Defines the number of consecutive slots for the strict priority */
+ REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
+}
+/******************************************************************************
+ * Description:
+ * Getting min_w_val will be set according to line speed .
+ *.
+ ******************************************************************************/
+static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars)
+{
+ uint32_t min_w_val = 0;
+ /* Calculate min_w_val.*/
+ if (vars->link_up) {
+ if (vars->line_speed == ELINK_SPEED_20000)
+ min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
+ else
+ min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
+ } else {
+ min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
+ }
+ /* If the link isn't up (static configuration for example ) The
+ * link will be according to 20GBPS.
+ */
+ return min_w_val;
+}
+/******************************************************************************
+ * Description:
+ * Getting credit upper bound form min_w_val.
+ *.
+ ******************************************************************************/
+static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val)
+{
+ const uint32_t credit_upper_bound = (uint32_t)
+ ELINK_MAXVAL((150 * min_w_val),
+ ELINK_MAX_PACKET_SIZE);
+ return credit_upper_bound;
+}
+/******************************************************************************
+ * Description:
+ * Set credit upper bound for NIG.
+ *.
+ ******************************************************************************/
+static void elink_ets_e3b0_set_credit_upper_bound_nig(
+ const struct elink_params *params,
+ const uint32_t min_w_val)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint32_t credit_upper_bound =
+ elink_ets_get_credit_upper_bound(min_w_val);
+
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
+ NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
+
+ if (!port) {
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
+ credit_upper_bound);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
+ credit_upper_bound);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
+ credit_upper_bound);
+ }
+}
+/******************************************************************************
+ * Description:
+ * Will return the NIG ETS registers to init values.Except
+ * credit_upper_bound.
+ * That isn't used in this configuration (No WFQ is enabled) and will be
+ * configured according to spec
+ *.
+ ******************************************************************************/
+static void elink_ets_e3b0_nig_disabled(const struct elink_params *params,
+ const struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars);
+ /* Mapping between entry priority to client number (0,1,2 -debug and
+ * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
+ * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
+ * reset value or init tool
+ */
+ if (port) {
+ REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
+ REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
+ } else {
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
+ }
+ /* For strict priority entries defines the number of consecutive
+ * slots for the highest priority.
+ */
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
+ NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
+ /* Mapping between the CREDIT_WEIGHT registers and actual client
+ * numbers
+ */
+ if (port) {
+ /*Port 1 has 6 COS*/
+ REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
+ REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
+ } else {
+ /*Port 0 has 9 COS*/
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
+ 0x43210876);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
+ }
+
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ * as strict. Bits 0,1,2 - debug and management entries, 3 -
+ * COS0 entry, 4 - COS1 entry.
+ * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
+ * bit4 bit3 bit2 bit1 bit0
+ * MCP and debug are strict
+ */
+ if (port)
+ REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
+ else
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
+ /* defines which entries (clients) are subjected to WFQ arbitration */
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
+ NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
+
+ /* Please notice the register address are note continuous and a
+ * for here is note appropriate.In 2 port mode port0 only COS0-5
+ * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
+ * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
+ * are never used for WFQ
+ */
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
+ if (!port) {
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
+ }
+
+ elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
+}
+/******************************************************************************
+ * Description:
+ * Set credit upper bound for PBF.
+ *.
+ ******************************************************************************/
+static void elink_ets_e3b0_set_credit_upper_bound_pbf(
+ const struct elink_params *params,
+ const uint32_t min_w_val)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint32_t credit_upper_bound =
+ elink_ets_get_credit_upper_bound(min_w_val);
+ const uint8_t port = params->port;
+ uint32_t base_upper_bound = 0;
+ uint8_t max_cos = 0;
+ uint8_t i = 0;
+ /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
+ * port mode port1 has COS0-2 that can be used for WFQ.
+ */
+ if (!port) {
+ base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
+ max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+ } else {
+ base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
+ max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
+ }
+
+ for (i = 0; i < max_cos; i++)
+ REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound);
+}
+
+/******************************************************************************
+ * Description:
+ * Will return the PBF ETS registers to init values.Except
+ * credit_upper_bound.
+ * That isn't used in this configuration (No WFQ is enabled) and will be
+ * configured according to spec
+ *.
+ ******************************************************************************/
+static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
+ uint8_t i = 0;
+ uint32_t base_weight = 0;
+ uint8_t max_cos = 0;
+
+ /* Mapping between entry priority to client number 0 - COS0
+ * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
+ * TODO_ETS - Should be done by reset value or init tool
+ */
+ if (port)
+ /* 0x688 (|011|0 10|00 1|000) */
+ REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1, 0x688);
+ else
+ /* (10 1|100 |011|0 10|00 1|000) */
+ REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0, 0x2C688);
+
+ /* TODO_ETS - Should be done by reset value or init tool */
+ if (port)
+ /* 0x688 (|011|0 10|00 1|000)*/
+ REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
+ else
+ /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
+ REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
+ PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0, 0x100);
+
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
+ PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0, 0);
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
+ PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 0);
+ /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
+ * In 4 port mode port1 has COS0-2 that can be used for WFQ.
+ */
+ if (!port) {
+ base_weight = PBF_REG_COS0_WEIGHT_P0;
+ max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+ } else {
+ base_weight = PBF_REG_COS0_WEIGHT_P1;
+ max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
+ }
+
+ for (i = 0; i < max_cos; i++)
+ REG_WR(sc, base_weight + (0x4 * i), 0);
+
+ elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
+}
+/******************************************************************************
+ * Description:
+ * E3B0 disable will return basicly the values to init values.
+ *.
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params,
+ const struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+
+ if (!CHIP_IS_E3B0(sc)) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_disabled the chip isn't E3B0");
+ return ELINK_STATUS_ERROR;
+ }
+
+ elink_ets_e3b0_nig_disabled(params, vars);
+
+ elink_ets_e3b0_pbf_disabled(params);
+
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * Disable will return basicly the values to init values.
+ *
+ ******************************************************************************/
+elink_status_t elink_ets_disabled(struct elink_params *params,
+ struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+ elink_status_t elink_status = ELINK_STATUS_OK;
+
+ if ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc))) {
+ elink_ets_e2e3a0_disabled(params);
+ } else if (CHIP_IS_E3B0(sc)) {
+ elink_status = elink_ets_e3b0_disabled(params, vars);
+ } else {
+ ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported");
+ return ELINK_STATUS_ERROR;
+ }
+
+ return elink_status;
+}
+
+/******************************************************************************
+ * Description
+ * Set the COS mappimg to SP and BW until this point all the COS are not
+ * set as SP or BW.
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params,
+ __rte_unused const struct elink_ets_params *ets_params,
+ const uint8_t cos_sp_bitmap,
+ const uint8_t cos_bw_bitmap)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
+ const uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap;
+ const uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
+ const uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
+
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
+ NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
+ PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0, pbf_cli_sp_bitmap);
+
+ REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
+ NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
+ nig_cli_subject2wfq_bitmap);
+
+ REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
+ PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
+ pbf_cli_subject2wfq_bitmap);
+
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
+ * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_set_cos_bw(struct bnx2x_softc *sc,
+ const uint8_t cos_entry,
+ const uint32_t min_w_val_nig,
+ const uint32_t min_w_val_pbf,
+ const uint16_t total_bw,
+ const uint8_t bw,
+ const uint8_t port)
+{
+ uint32_t nig_reg_address_crd_weight = 0;
+ uint32_t pbf_reg_address_crd_weight = 0;
+ /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
+ const uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
+ const uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
+
+ switch (cos_entry) {
+ case 0:
+ nig_reg_address_crd_weight =
+ (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
+ pbf_reg_address_crd_weight = (port) ?
+ PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
+ break;
+ case 1:
+ nig_reg_address_crd_weight = (port) ?
+ NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
+ pbf_reg_address_crd_weight = (port) ?
+ PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
+ break;
+ case 2:
+ nig_reg_address_crd_weight = (port) ?
+ NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
+
+ pbf_reg_address_crd_weight = (port) ?
+ PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
+ break;
+ case 3:
+ if (port)
+ return ELINK_STATUS_ERROR;
+ nig_reg_address_crd_weight =
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
+ pbf_reg_address_crd_weight =
+ PBF_REG_COS3_WEIGHT_P0;
+ break;
+ case 4:
+ if (port)
+ return ELINK_STATUS_ERROR;
+ nig_reg_address_crd_weight =
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
+ pbf_reg_address_crd_weight = PBF_REG_COS4_WEIGHT_P0;
+ break;
+ case 5:
+ if (port)
+ return ELINK_STATUS_ERROR;
+ nig_reg_address_crd_weight =
+ NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
+ pbf_reg_address_crd_weight = PBF_REG_COS5_WEIGHT_P0;
+ break;
+ }
+
+ REG_WR(sc, nig_reg_address_crd_weight, cos_bw_nig);
+
+ REG_WR(sc, pbf_reg_address_crd_weight, cos_bw_pbf);
+
+ return ELINK_STATUS_OK;
+}
+/******************************************************************************
+ * Description:
+ * Calculate the total BW.A value of 0 isn't legal.
+ *
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_get_total_bw(
+ const struct elink_params *params,
+ struct elink_ets_params *ets_params,
+ uint16_t *total_bw)
+{
+ struct bnx2x_softc *sc = params->sc;
+ uint8_t cos_idx = 0;
+ uint8_t is_bw_cos_exist = 0;
+
+ *total_bw = 0;
+ /* Calculate total BW requested */
+ for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
+ if (ets_params->cos[cos_idx].state == elink_cos_state_bw) {
+ is_bw_cos_exist = 1;
+ if (!ets_params->cos[cos_idx].params.bw_params.bw) {
+ ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config BW"
+ " was set to 0");
+ /* This is to prevent a state when ramrods
+ * can't be sent
+ */
+ ets_params->cos[cos_idx].params.bw_params.bw
+ = 1;
+ }
+ *total_bw +=
+ ets_params->cos[cos_idx].params.bw_params.bw;
+ }
+ }
+
+ /* Check total BW is valid */
+ if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
+ if (*total_bw == 0) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_E3B0_config total BW shouldn't be 0");
+ return ELINK_STATUS_ERROR;
+ }
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_E3B0_config total BW should be 100");
+ /* We can handle a case whre the BW isn't 100 this can happen
+ * if the TC are joined.
+ */
+ }
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * Invalidate all the sp_pri_to_cos.
+ *
+ ******************************************************************************/
+static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos)
+{
+ uint8_t pri = 0;
+ for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)
+ sp_pri_to_cos[pri] = DCBX_INVALID_COS;
+}
+/******************************************************************************
+ * Description:
+ * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
+ * according to sp_pri_to_cos.
+ *
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(
+ const struct elink_params *params,
+ uint8_t *sp_pri_to_cos,
+ const uint8_t pri,
+ const uint8_t cos_entry)
+{
+ struct bnx2x_softc *sc = params->sc;
+ const uint8_t port = params->port;
+ const uint8_t max_num_of_cos = (port) ?
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+
+ if (pri >= max_num_of_cos) {
+ ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
+ "parameter Illegal strict priority");
+ return ELINK_STATUS_ERROR;
+ }
+
+ if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
+ ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
+ "parameter There can't be two COS's with "
+ "the same strict pri");
+ return ELINK_STATUS_ERROR;
+ }
+
+ sp_pri_to_cos[pri] = cos_entry;
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * Returns the correct value according to COS and priority in
+ * the sp_pri_cli register.
+ *
+ ******************************************************************************/
+static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos,
+ const uint8_t cos_offset,
+ const uint8_t pri_set,
+ const uint8_t pri_offset,
+ const uint8_t entry_size)
+{
+ uint64_t pri_cli_nig = 0;
+ pri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size *
+ (pri_set + pri_offset));
+
+ return pri_cli_nig;
+}
+/******************************************************************************
+ * Description:
+ * Returns the correct value according to COS and priority in the
+ * sp_pri_cli register for NIG.
+ *
+ ******************************************************************************/
+static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos,
+ const uint8_t pri_set)
+{
+ /* MCP Dbg0 and dbg1 are always with higher strict pri*/
+ const uint8_t nig_cos_offset = 3;
+ const uint8_t nig_pri_offset = 3;
+
+ return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
+ nig_pri_offset, 4);
+}
+
+/******************************************************************************
+ * Description:
+ * Returns the correct value according to COS and priority in the
+ * sp_pri_cli register for PBF.
+ *
+ ******************************************************************************/
+static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos,
+ const uint8_t pri_set)
+{
+ const uint8_t pbf_cos_offset = 0;
+ const uint8_t pbf_pri_offset = 0;
+
+ return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
+ pbf_pri_offset, 3);
+}
+
+/******************************************************************************
+ * Description:
+ * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
+ * according to sp_pri_to_cos.(which COS has higher priority)
+ *
+ ******************************************************************************/
+static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(
+ const struct elink_params *params,
+ uint8_t *sp_pri_to_cos)
+{
+ struct bnx2x_softc *sc = params->sc;
+ uint8_t i = 0;
+ const uint8_t port = params->port;
+ /* MCP Dbg0 and dbg1 are always with higher strict pri*/
+ uint64_t pri_cli_nig = 0x210;
+ uint32_t pri_cli_pbf = 0x0;
+ uint8_t pri_set = 0;
+ uint8_t pri_bitmask = 0;
+ const uint8_t max_num_of_cos = (port) ?
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+
+ uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1;
+
+ /* Set all the strict priority first */
+ for (i = 0; i < max_num_of_cos; i++) {
+ if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
+ if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_sp_set_pri_cli_reg "
+ "invalid cos entry");
+ return ELINK_STATUS_ERROR;
+ }
+
+ pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
+ sp_pri_to_cos[i], pri_set);
+
+ pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
+ sp_pri_to_cos[i], pri_set);
+ pri_bitmask = 1 << sp_pri_to_cos[i];
+ /* COS is used remove it from bitmap.*/
+ if (!(pri_bitmask & cos_bit_to_set)) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_sp_set_pri_cli_reg "
+ "invalid There can't be two COS's with"
+ " the same strict pri");
+ return ELINK_STATUS_ERROR;
+ }
+ cos_bit_to_set &= ~pri_bitmask;
+ pri_set++;
+ }
+ }
+
+ /* Set all the Non strict priority i= COS*/
+ for (i = 0; i < max_num_of_cos; i++) {
+ pri_bitmask = 1 << i;
+ /* Check if COS was already used for SP */
+ if (pri_bitmask & cos_bit_to_set) {
+ /* COS wasn't used for SP */
+ pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
+ i, pri_set);
+
+ pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
+ i, pri_set);
+ /* COS is used remove it from bitmap.*/
+ cos_bit_to_set &= ~pri_bitmask;
+ pri_set++;
+ }
+ }
+
+ if (pri_set != max_num_of_cos) {
+ ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_set_pri_cli_reg not all "
+ "entries were set");
+ return ELINK_STATUS_ERROR;
+ }
+
+ if (port) {
+ /* Only 6 usable clients*/
+ REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
+ (uint32_t)pri_cli_nig);
+
+ REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1, pri_cli_pbf);
+ } else {
+ /* Only 9 usable clients*/
+ const uint32_t pri_cli_nig_lsb = (uint32_t)(pri_cli_nig);
+ const uint32_t pri_cli_nig_msb = (uint32_t)
+ ((pri_cli_nig >> 32) & 0xF);
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
+ pri_cli_nig_lsb);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
+ pri_cli_nig_msb);
+
+ REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0, pri_cli_pbf);
+ }
+ return ELINK_STATUS_OK;
+}
+
+/******************************************************************************
+ * Description:
+ * Configure the COS to ETS according to BW and SP settings.
+ ******************************************************************************/
+elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
+ const struct elink_vars *vars,
+ struct elink_ets_params *ets_params)
+{
+ struct bnx2x_softc *sc = params->sc;
+ elink_status_t elink_status = ELINK_STATUS_OK;
+ const uint8_t port = params->port;
+ uint16_t total_bw = 0;
+ const uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars);
+ const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
+ uint8_t cos_bw_bitmap = 0;
+ uint8_t cos_sp_bitmap = 0;
+ uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};
+ const uint8_t max_num_of_cos = (port) ?
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
+ ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
+ uint8_t cos_entry = 0;
+
+ if (!CHIP_IS_E3B0(sc)) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_disabled the chip isn't E3B0");
+ return ELINK_STATUS_ERROR;
+ }
+
+ if (ets_params->num_of_cos > max_num_of_cos) {
+ ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config the number of COS "
+ "isn't supported");
+ return ELINK_STATUS_ERROR;
+ }
+
+ /* Prepare sp strict priority parameters*/
+ elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
+
+ /* Prepare BW parameters*/
+ elink_status = elink_ets_e3b0_get_total_bw(params, ets_params,
+ &total_bw);
+ if (elink_status != ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_E3B0_config get_total_bw failed");
+ return ELINK_STATUS_ERROR;
+ }
+
+ /* Upper bound is set according to current link speed (min_w_val
+ * should be the same for upper bound and COS credit val).
+ */
+ elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
+ elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
+
+
+ for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
+ if (elink_cos_state_bw == ets_params->cos[cos_entry].state) {
+ cos_bw_bitmap |= (1 << cos_entry);
+ /* The function also sets the BW in HW(not the mappin
+ * yet)
+ */
+ elink_status = elink_ets_e3b0_set_cos_bw(
+ sc, cos_entry, min_w_val_nig, min_w_val_pbf,
+ total_bw,
+ ets_params->cos[cos_entry].params.bw_params.bw,
+ port);
+ } else if (elink_cos_state_strict ==
+ ets_params->cos[cos_entry].state){
+ cos_sp_bitmap |= (1 << cos_entry);
+
+ elink_status = elink_ets_e3b0_sp_pri_to_cos_set(
+ params,
+ sp_pri_to_cos,
+ ets_params->cos[cos_entry].params.sp_params.pri,
+ cos_entry);
+
+ } else {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_config cos state not valid");
+ return ELINK_STATUS_ERROR;
+ }
+ if (elink_status != ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_e3b0_config set cos bw failed");
+ return elink_status;
+ }
+ }
+
+ /* Set SP register (which COS has higher priority) */
+ elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params,
+ sp_pri_to_cos);
+
+ if (elink_status != ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc,
+ "elink_ets_E3B0_config set_pri_cli_reg failed");
+ return elink_status;
+ }
+
+ /* Set client mapping of BW and strict */
+ elink_status = elink_ets_e3b0_cli_map(params, ets_params,
+ cos_sp_bitmap,
+ cos_bw_bitmap);
+
+ if (elink_status != ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config SP failed");
+ return elink_status;
+ }
+ return ELINK_STATUS_OK;
+}
+static void elink_ets_bw_limit_common(const struct elink_params *params)
+{
+ /* ETS disabled configuration */
+ struct bnx2x_softc *sc = params->sc;
+ ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration");
+ /* Defines which entries (clients) are subjected to WFQ arbitration
+ * COS0 0x8
+ * COS1 0x10
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
+ /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
+ * client numbers (WEIGHT_0 does not actually have to represent
+ * client 0)
+ * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
+ * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
+ ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
+ ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+
+ /* ETS mode enabled*/
+ REG_WR(sc, PBF_REG_ETS_ENABLED, 1);
+
+ /* Defines the number of consecutive slots for the strict priority */
+ REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
+ * entry, 4 - COS1 entry.
+ * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
+ * bit4 bit3 bit2 bit1 bit0
+ * MCP and debug are strict
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
+ /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
+ REG_WR(sc, PBF_REG_COS0_UPPER_BOUND,
+ ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+ REG_WR(sc, PBF_REG_COS1_UPPER_BOUND,
+ ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+}
+
+void elink_ets_bw_limit(const struct elink_params *params,
+ const uint32_t cos0_bw,
+ const uint32_t cos1_bw)
+{
+ /* ETS disabled configuration*/
+ struct bnx2x_softc *sc = params->sc;
+ const uint32_t total_bw = cos0_bw + cos1_bw;
+ uint32_t cos0_credit_weight = 0;
+ uint32_t cos1_credit_weight = 0;
+
+ ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration");
+
+ if ((!total_bw) ||
+ (!cos0_bw) ||
+ (!cos1_bw)) {
+ ELINK_DEBUG_P0(sc, "Total BW can't be zero");
+ return;
+ }
+
+ cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT) /
+ total_bw;
+ cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT) /
+ total_bw;
+
+ elink_ets_bw_limit_common(params);
+
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
+
+ REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
+ REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
+}
+
+elink_status_t elink_ets_strict(const struct elink_params *params,
+ const uint8_t strict_cos)
+{
+ /* ETS disabled configuration*/
+ struct bnx2x_softc *sc = params->sc;
+ uint32_t val = 0;
+
+ ELINK_DEBUG_P0(sc, "ETS enabled strict configuration");
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ * as strict. Bits 0,1,2 - debug and management entries,
+ * 3 - COS0 entry, 4 - COS1 entry.
+ * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
+ * bit4 bit3 bit2 bit1 bit0
+ * MCP and debug are strict
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
+ /* For strict priority entries defines the number of consecutive slots
+ * for the highest priority.
+ */
+ REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
+ /* ETS mode disable */
+ REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
+ /* Defines the number of consecutive slots for the strict priority */
+ REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
+
+ /* Defines the number of consecutive slots for the strict priority */
+ REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
+
+ /* Mapping between entry priority to client number (0,1,2 -debug and
+ * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
+ * 3bits client num.
+ * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
+ * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
+ * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
+ */
+ val = (!strict_cos) ? 0x2318 : 0x22E0;
+ REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
+
+ return ELINK_STATUS_OK;
}
/******************************************************************/
/* PFC section */
/******************************************************************/
static void elink_update_pfc_xmac(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars,
+ __rte_unused uint8_t is_lb)
{
struct bnx2x_softc *sc = params->sc;
uint32_t xmac_base;
@@ -1144,7 +2099,8 @@ static void elink_update_pfc_xmac(struct elink_params *params,
pfc1_val = 0x2;
/* No PFC support */
- if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
/* RX flow control - Process pause frame in receive direction
*/
@@ -1154,12 +2110,12 @@ static void elink_update_pfc_xmac(struct elink_params *params,
/* TX flow control - Send pause packet when buffer is full */
if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
- } else { /* PFC support */
+ } else {/* PFC support */
pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
- XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
- XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
- XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
- XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
+ XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
+ XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
+ XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
+ XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
/* Write pause and PFC registers */
REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
@@ -1173,21 +2129,76 @@ static void elink_update_pfc_xmac(struct elink_params *params,
REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
+
/* Set MAC address for source TX Pause/PFC frames */
REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
((params->mac_addr[2] << 24) |
(params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | (params->mac_addr[5])));
+ (params->mac_addr[4] << 8) |
+ (params->mac_addr[5])));
REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
- ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
+ ((params->mac_addr[0] << 8) |
+ (params->mac_addr[1])));
DELAY(30);
}
+static void elink_emac_get_pfc_stat(struct elink_params *params,
+ uint32_t pfc_frames_sent[2],
+ uint32_t pfc_frames_received[2])
+{
+ /* Read pfc statistic */
+ struct bnx2x_softc *sc = params->sc;
+ uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+ uint32_t val_xon = 0;
+ uint32_t val_xoff = 0;
+
+ ELINK_DEBUG_P0(sc, "pfc statistic read from EMAC");
+
+ /* PFC received frames */
+ val_xoff = REG_RD(sc, emac_base +
+ EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
+ val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
+ val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
+ val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
+
+ pfc_frames_received[0] = val_xon + val_xoff;
+
+ /* PFC received sent */
+ val_xoff = REG_RD(sc, emac_base +
+ EMAC_REG_RX_PFC_STATS_XOFF_SENT);
+ val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
+ val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
+ val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
+
+ pfc_frames_sent[0] = val_xon + val_xoff;
+}
+
+/* Read pfc statistic*/
+void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
+ uint32_t pfc_frames_sent[2],
+ uint32_t pfc_frames_received[2])
+{
+ /* Read pfc statistic */
+ struct bnx2x_softc *sc = params->sc;
+
+ ELINK_DEBUG_P0(sc, "pfc statistic");
+
+ if (!vars->link_up)
+ return;
+
+ if (vars->mac_type == ELINK_MAC_TYPE_EMAC) {
+ ELINK_DEBUG_P0(sc, "About to read PFC stats from EMAC");
+ elink_emac_get_pfc_stat(params, pfc_frames_sent,
+ pfc_frames_received);
+ }
+}
/******************************************************************/
/* MAC/PBF section */
/******************************************************************/
-static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
+static void elink_set_mdio_clk(struct bnx2x_softc *sc,
+ __rte_unused uint32_t chip_id,
+ uint32_t emac_base)
{
uint32_t new_mode, cur_mode;
uint32_t clc_cnt;
@@ -1206,26 +2217,16 @@ static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
return;
new_mode = cur_mode &
- ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
+ ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
new_mode |= clc_cnt;
new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
- PMD_DRV_LOG(DEBUG, sc, "Changing emac_mode from 0x%x to 0x%x",
- cur_mode, new_mode);
+ ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x",
+ cur_mode, new_mode);
REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
DELAY(40);
}
-static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,
- struct elink_params *params)
-{
- uint8_t phy_index;
- /* Set mdio clock per phy */
- for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
- phy_index++)
- elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl);
-}
-
static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)
{
uint32_t port4mode_ovwr_val;
@@ -1233,13 +2234,26 @@ static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)
port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
if (port4mode_ovwr_val & (1 << 0)) {
/* Return 4-port mode override value */
- return (port4mode_ovwr_val & (1 << 1)) == (1 << 1);
+ return ((port4mode_ovwr_val & (1 << 1)) == (1 << 1));
}
/* Return 4-port mode from input pin */
- return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN);
+ return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);
+}
+
+static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,
+ struct elink_params *params)
+{
+ uint8_t phy_index;
+
+ /* Set mdio clock per phy */
+ for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
+ phy_index++)
+ elink_set_mdio_clk(sc, params->chip_id,
+ params->phy[phy_index].mdio_ctrl);
}
-static void elink_emac_init(struct elink_params *params)
+static void elink_emac_init(struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
/* reset and unreset the emac core */
struct bnx2x_softc *sc = params->sc;
@@ -1263,9 +2277,9 @@ static void elink_emac_init(struct elink_params *params)
timeout = 200;
do {
val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
- PMD_DRV_LOG(DEBUG, sc, "EMAC reset reg is %u", val);
+ ELINK_DEBUG_P1(sc, "EMAC reset reg is %u", val);
if (!timeout) {
- PMD_DRV_LOG(DEBUG, sc, "EMAC timeout!");
+ ELINK_DEBUG_P0(sc, "EMAC timeout!");
return;
}
timeout--;
@@ -1273,17 +2287,20 @@ static void elink_emac_init(struct elink_params *params)
elink_set_mdio_emac_per_phy(sc, params);
/* Set mac address */
- val = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
+ val = ((params->mac_addr[0] << 8) |
+ params->mac_addr[1]);
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
val = ((params->mac_addr[2] << 24) |
(params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | params->mac_addr[5]);
+ (params->mac_addr[4] << 8) |
+ params->mac_addr[5]);
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
}
static void elink_set_xumac_nig(struct elink_params *params,
- uint16_t tx_pause_en, uint8_t enable)
+ uint16_t tx_pause_en,
+ uint8_t enable)
{
struct bnx2x_softc *sc = params->sc;
@@ -1301,7 +2318,7 @@ static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
uint32_t val;
struct bnx2x_softc *sc = params->sc;
if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
- (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
+ (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
return;
val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
if (en)
@@ -1315,7 +2332,7 @@ static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
}
static void elink_umac_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t lb)
+ struct elink_vars *vars, uint8_t lb)
{
uint32_t val;
uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
@@ -1328,15 +2345,15 @@ static void elink_umac_enable(struct elink_params *params,
REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
(MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
- PMD_DRV_LOG(DEBUG, sc, "enabling UMAC");
+ ELINK_DEBUG_P0(sc, "enabling UMAC");
/* This register opens the gate for the UMAC despite its name */
REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
- UMAC_COMMAND_CONFIG_REG_PAD_EN |
- UMAC_COMMAND_CONFIG_REG_SW_RESET |
- UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
+ UMAC_COMMAND_CONFIG_REG_PAD_EN |
+ UMAC_COMMAND_CONFIG_REG_SW_RESET |
+ UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
switch (vars->line_speed) {
case ELINK_SPEED_10:
val |= (0 << 2);
@@ -1351,8 +2368,8 @@ static void elink_umac_enable(struct elink_params *params,
val |= (3 << 2);
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Invalid speed for UMAC %d",
- vars->line_speed);
+ ELINK_DEBUG_P1(sc, "Invalid speed for UMAC %d",
+ vars->line_speed);
break;
}
if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
@@ -1369,7 +2386,7 @@ static void elink_umac_enable(struct elink_params *params,
/* Configure UMAC for EEE */
if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
- PMD_DRV_LOG(DEBUG, sc, "configured UMAC for EEE");
+ ELINK_DEBUG_P0(sc, "configured UMAC for EEE");
REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
@@ -1381,13 +2398,16 @@ static void elink_umac_enable(struct elink_params *params,
REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
((params->mac_addr[2] << 24) |
(params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | (params->mac_addr[5])));
+ (params->mac_addr[4] << 8) |
+ (params->mac_addr[5])));
REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
- ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
+ ((params->mac_addr[0] << 8) |
+ (params->mac_addr[1])));
/* Enable RX and TX */
val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
- val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA;
+ val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
+ UMAC_COMMAND_CONFIG_REG_RX_ENA;
REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
DELAY(50);
@@ -1427,7 +2447,8 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
is_port4mode &&
(REG_RD(sc, MISC_REG_RESET_REG_2) &
MISC_REGISTERS_RESET_REG_2_XMAC)) {
- PMD_DRV_LOG(DEBUG, sc, "XMAC already out of reset in 4-port mode");
+ ELINK_DEBUG_P0(sc,
+ "XMAC already out of reset in 4-port mode");
return;
}
@@ -1439,7 +2460,7 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
MISC_REGISTERS_RESET_REG_2_XMAC);
if (is_port4mode) {
- PMD_DRV_LOG(DEBUG, sc, "Init XMAC to 2 ports x 10G per path");
+ ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path");
/* Set the number of ports on the system side to up to 2 */
REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
@@ -1450,13 +2471,13 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
/* Set the number of ports on the system side to 1 */
REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
if (max_speed == ELINK_SPEED_10000) {
- PMD_DRV_LOG(DEBUG, sc,
- "Init XMAC to 10G x 1 port per path");
+ ELINK_DEBUG_P0(sc,
+ "Init XMAC to 10G x 1 port per path");
/* Set the number of ports on the Warp Core to 10G */
REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
} else {
- PMD_DRV_LOG(DEBUG, sc,
- "Init XMAC to 20G x 2 ports per path");
+ ELINK_DEBUG_P0(sc,
+ "Init XMAC to 20G x 2 ports per path");
/* Set the number of ports on the Warp Core to 20G */
REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
}
@@ -1478,7 +2499,8 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
uint32_t val;
- if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) {
+ if (REG_RD(sc, MISC_REG_RESET_REG_2) &
+ MISC_REGISTERS_RESET_REG_2_XMAC) {
/* Send an indication to change the state in the NIG back to XON
* Clearing this bit enables the next set of this bit to get
* rising edge
@@ -1488,7 +2510,7 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
(pfc_ctrl & ~(1 << 1)));
REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
(pfc_ctrl | (1 << 1)));
- PMD_DRV_LOG(DEBUG, sc, "Disable XMAC on port %x", port);
+ ELINK_DEBUG_P1(sc, "Disable XMAC on port %x", port);
val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
if (en)
val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
@@ -1499,11 +2521,11 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
}
static elink_status_t elink_xmac_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t lb)
+ struct elink_vars *vars, uint8_t lb)
{
uint32_t val, xmac_base;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "enabling XMAC");
+ ELINK_DEBUG_P0(sc, "enabling XMAC");
xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
@@ -1537,10 +2559,10 @@ static elink_status_t elink_xmac_enable(struct elink_params *params,
REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
/* update PFC */
- elink_update_pfc_xmac(params, vars);
+ elink_update_pfc_xmac(params, vars, 0);
if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
- PMD_DRV_LOG(DEBUG, sc, "Setting XMAC for EEE");
+ ELINK_DEBUG_P0(sc, "Setting XMAC for EEE");
REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
} else {
@@ -1569,14 +2591,14 @@ static elink_status_t elink_xmac_enable(struct elink_params *params,
}
static elink_status_t elink_emac_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t lb)
+ struct elink_vars *vars, uint8_t lb)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
uint32_t val;
- PMD_DRV_LOG(DEBUG, sc, "enabling EMAC");
+ ELINK_DEBUG_P0(sc, "enabling EMAC");
/* Disable BMAC */
REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
@@ -1585,19 +2607,39 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
/* enable emac and not bmac */
REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);
+#ifdef ELINK_INCLUDE_EMUL
+ /* for paladium */
+ if (CHIP_REV_IS_EMUL(sc)) {
+ /* Use lane 1 (of lanes 0-3) */
+ REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);
+ REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
+ }
+ /* for fpga */
+ else
+#endif
+#ifdef ELINK_INCLUDE_FPGA
+ if (CHIP_REV_IS_FPGA(sc)) {
+ /* Use lane 1 (of lanes 0-3) */
+ ELINK_DEBUG_P0(sc, "elink_emac_enable: Setting FPGA");
+
+ REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);
+ REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
+ } else
+#endif
+ /* ASIC */
if (vars->phy_flags & PHY_XGXS_FLAG) {
uint32_t ser_lane = ((params->lane_config &
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
- PMD_DRV_LOG(DEBUG, sc, "XGXS");
+ ELINK_DEBUG_P0(sc, "XGXS");
/* select the master lanes (out of 0-3) */
REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);
/* select XGXS */
REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
- } else { /* SerDes */
- PMD_DRV_LOG(DEBUG, sc, "SerDes");
+ } else { /* SerDes */
+ ELINK_DEBUG_P0(sc, "SerDes");
/* select SerDes */
REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
}
@@ -1607,28 +2649,39 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
EMAC_TX_MODE_RESET);
- /* pause enable/disable */
- elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
- EMAC_RX_MODE_FLOW_EN);
-
- elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
- (EMAC_TX_MODE_EXT_PAUSE_EN |
- EMAC_TX_MODE_FLOW_EN));
- if (!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
- if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
- elink_bits_en(sc, emac_base +
- EMAC_REG_EMAC_RX_MODE,
- EMAC_RX_MODE_FLOW_EN);
+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
+ if (CHIP_REV_IS_SLOW(sc)) {
+ /* config GMII mode */
+ val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
+ elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,
+ (val | EMAC_MODE_PORT_GMII));
+ } else { /* ASIC */
+#endif
+ /* pause enable/disable */
+ elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
+ EMAC_RX_MODE_FLOW_EN);
- if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
- elink_bits_en(sc, emac_base +
- EMAC_REG_EMAC_TX_MODE,
- (EMAC_TX_MODE_EXT_PAUSE_EN |
- EMAC_TX_MODE_FLOW_EN));
- } else
- elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
- EMAC_TX_MODE_FLOW_EN);
+ elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
+ (EMAC_TX_MODE_EXT_PAUSE_EN |
+ EMAC_TX_MODE_FLOW_EN));
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
+ if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
+ elink_bits_en(sc, emac_base +
+ EMAC_REG_EMAC_RX_MODE,
+ EMAC_RX_MODE_FLOW_EN);
+
+ if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
+ elink_bits_en(sc, emac_base +
+ EMAC_REG_EMAC_TX_MODE,
+ (EMAC_TX_MODE_EXT_PAUSE_EN |
+ EMAC_TX_MODE_FLOW_EN));
+ } else
+ elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
+ EMAC_TX_MODE_FLOW_EN);
+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
+ }
+#endif
/* KEEP_VLAN_TAG, promiscuous */
val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
@@ -1643,18 +2696,18 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
*/
elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
- PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
+ ELINK_DEBUG_P0(sc, "PFC is enabled");
/* Enable PFC again */
elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
- EMAC_REG_RX_PFC_MODE_RX_EN |
- EMAC_REG_RX_PFC_MODE_TX_EN |
- EMAC_REG_RX_PFC_MODE_PRIORITIES);
+ EMAC_REG_RX_PFC_MODE_RX_EN |
+ EMAC_REG_RX_PFC_MODE_TX_EN |
+ EMAC_REG_RX_PFC_MODE_PRIORITIES);
elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
- ((0x0101 <<
- EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
- (0x00ff <<
- EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
+ ((0x0101 <<
+ EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
+ (0x00ff <<
+ EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
}
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
@@ -1672,9 +2725,8 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
/* Enable emac for jumbo packets */
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
- (EMAC_RX_MTU_SIZE_JUMBO_ENA |
- (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
- ELINK_ETH_OVREHEAD)));
+ (EMAC_RX_MTU_SIZE_JUMBO_ENA |
+ (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD)));
/* Strip CRC */
REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);
@@ -1688,13 +2740,23 @@ static elink_status_t elink_emac_enable(struct elink_params *params,
REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);
val = 0;
if ((params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
+ ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
val = 1;
REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);
REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);
+#ifdef ELINK_INCLUDE_EMUL
+ if (CHIP_REV_IS_EMUL(sc)) {
+ /* Take the BigMac out of reset */
+ REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+ /* Enable access for bmac registers */
+ REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
+ } else
+#endif
REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
vars->mac_type = ELINK_MAC_TYPE_EMAC;
@@ -1706,13 +2768,13 @@ static void elink_update_pfc_bmac1(struct elink_params *params,
{
uint32_t wb_data[2];
struct bnx2x_softc *sc = params->sc;
- uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t val = 0x14;
if ((!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
- (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
+ ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
+ (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
/* Enable BigMAC to react on received Pause packets */
val |= (1 << 5);
wb_data[0] = val;
@@ -1723,7 +2785,7 @@ static void elink_update_pfc_bmac1(struct elink_params *params,
val = 0xc0;
if (!(params->feature_config_flags &
ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
- (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
+ (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
val |= 0x800000;
wb_data[0] = val;
wb_data[1] = 0;
@@ -1731,7 +2793,8 @@ static void elink_update_pfc_bmac1(struct elink_params *params,
}
static void elink_update_pfc_bmac2(struct elink_params *params,
- struct elink_vars *vars, uint8_t is_lb)
+ struct elink_vars *vars,
+ uint8_t is_lb)
{
/* Set rx control: Strip CRC and enable BigMAC to relay
* control packets to the system as well
@@ -1739,12 +2802,12 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
uint32_t wb_data[2];
struct bnx2x_softc *sc = params->sc;
uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t val = 0x14;
if ((!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
- (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
+ ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
+ (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
/* Enable BigMAC to react on received Pause packets */
val |= (1 << 5);
wb_data[0] = val;
@@ -1755,7 +2818,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
/* Tx control */
val = 0xc0;
if (!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
+ ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
val |= 0x800000;
wb_data[0] = val;
@@ -1763,21 +2826,21 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
- PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
+ ELINK_DEBUG_P0(sc, "PFC is enabled");
/* Enable PFC RX & TX & STATS and set 8 COS */
wb_data[0] = 0x0;
- wb_data[0] |= (1 << 0); /* RX */
- wb_data[0] |= (1 << 1); /* TX */
- wb_data[0] |= (1 << 2); /* Force initial Xon */
- wb_data[0] |= (1 << 3); /* 8 cos */
- wb_data[0] |= (1 << 5); /* STATS */
+ wb_data[0] |= (1 << 0); /* RX */
+ wb_data[0] |= (1 << 1); /* TX */
+ wb_data[0] |= (1 << 2); /* Force initial Xon */
+ wb_data[0] |= (1 << 3); /* 8 cos */
+ wb_data[0] |= (1 << 5); /* STATS */
wb_data[1] = 0;
REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
wb_data, 2);
/* Clear the force Xon */
wb_data[0] &= ~(1 << 2);
} else {
- PMD_DRV_LOG(DEBUG, sc, "PFC is disabled");
+ ELINK_DEBUG_P0(sc, "PFC is disabled");
/* Disable PFC RX & TX & STATS and set 8 COS */
wb_data[0] = 0x8;
wb_data[1] = 0;
@@ -1792,7 +2855,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
*/
val = 0x8000;
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
- val |= (1 << 16); /* enable automatic re-send */
+ val |= (1 << 16); /* enable automatic re-send */
wb_data[0] = val;
wb_data[1] = 0;
@@ -1800,10 +2863,10 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
wb_data, 2);
/* mac control */
- val = 0x3; /* Enable RX and TX */
+ val = 0x3; /* Enable RX and TX */
if (is_lb) {
- val |= 0x4; /* Local loopback */
- PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
+ val |= 0x4; /* Local loopback */
+ ELINK_DEBUG_P0(sc, "enable bmac loopback");
}
/* When PFC enabled, Pass pause frames towards the NIG. */
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
@@ -1815,47 +2878,46 @@ static void elink_update_pfc_bmac2(struct elink_params *params,
}
/******************************************************************************
-* Description:
-* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
-* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
-******************************************************************************/
+ * Description:
+ * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
+ * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
+ ******************************************************************************/
static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,
- uint8_t cos_entry,
- uint32_t priority_mask,
- uint8_t port)
+ uint8_t cos_entry,
+ uint32_t priority_mask, uint8_t port)
{
uint32_t nig_reg_rx_priority_mask_add = 0;
switch (cos_entry) {
case 0:
- nig_reg_rx_priority_mask_add = (port) ?
- NIG_REG_P1_RX_COS0_PRIORITY_MASK :
- NIG_REG_P0_RX_COS0_PRIORITY_MASK;
+ nig_reg_rx_priority_mask_add = (port) ?
+ NIG_REG_P1_RX_COS0_PRIORITY_MASK :
+ NIG_REG_P0_RX_COS0_PRIORITY_MASK;
break;
case 1:
- nig_reg_rx_priority_mask_add = (port) ?
- NIG_REG_P1_RX_COS1_PRIORITY_MASK :
- NIG_REG_P0_RX_COS1_PRIORITY_MASK;
+ nig_reg_rx_priority_mask_add = (port) ?
+ NIG_REG_P1_RX_COS1_PRIORITY_MASK :
+ NIG_REG_P0_RX_COS1_PRIORITY_MASK;
break;
case 2:
- nig_reg_rx_priority_mask_add = (port) ?
- NIG_REG_P1_RX_COS2_PRIORITY_MASK :
- NIG_REG_P0_RX_COS2_PRIORITY_MASK;
+ nig_reg_rx_priority_mask_add = (port) ?
+ NIG_REG_P1_RX_COS2_PRIORITY_MASK :
+ NIG_REG_P0_RX_COS2_PRIORITY_MASK;
break;
case 3:
if (port)
- return ELINK_STATUS_ERROR;
- nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
+ return ELINK_STATUS_ERROR;
+ nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
break;
case 4:
if (port)
- return ELINK_STATUS_ERROR;
- nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
+ return ELINK_STATUS_ERROR;
+ nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
break;
case 5:
if (port)
- return ELINK_STATUS_ERROR;
- nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
+ return ELINK_STATUS_ERROR;
+ nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
break;
}
@@ -1863,7 +2925,6 @@ static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,
return ELINK_STATUS_OK;
}
-
static void elink_update_mng(struct elink_params *params, uint32_t link_status)
{
struct bnx2x_softc *sc = params->sc;
@@ -1873,31 +2934,20 @@ static void elink_update_mng(struct elink_params *params, uint32_t link_status)
port_mb[params->port].link_status), link_status);
}
-static void elink_update_link_attr(struct elink_params *params,
- uint32_t link_attr)
-{
- struct bnx2x_softc *sc = params->sc;
-
- if (SHMEM2_HAS(sc, link_attr_sync))
- REG_WR(sc, params->shmem2_base +
- offsetof(struct shmem2_region,
- link_attr_sync[params->port]), link_attr);
-}
-
static void elink_update_pfc_nig(struct elink_params *params,
- struct elink_nig_brb_pfc_port_params
- *nig_params)
+ __rte_unused struct elink_vars *vars,
+ struct elink_nig_brb_pfc_port_params *nig_params)
{
- uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en =
- 0;
+ uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0;
+ uint32_t llfc_out_en = 0;
uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
uint32_t pkt_priority_to_cos = 0;
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
int set_pfc = params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED;
- PMD_DRV_LOG(DEBUG, sc, "updating pfc nig parameters");
+ ELINK_FEATURE_CONFIG_PFC_ENABLED;
+ ELINK_DEBUG_P0(sc, "updating pfc nig parameters");
/* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
* MAC control frames (that are not pause packets)
@@ -1917,19 +2967,19 @@ static void elink_update_pfc_nig(struct elink_params *params,
else
ppp_enable = 1;
xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
- NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
+ NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
xcm_out_en = 0;
hwpfc_enable = 1;
- } else {
+ } else {
if (nig_params) {
llfc_out_en = nig_params->llfc_out_en;
llfc_enable = nig_params->llfc_enable;
pause_enable = nig_params->pause_enable;
- } else /* Default non PFC mode - PAUSE */
+ } else /* Default non PFC mode - PAUSE */
pause_enable = 1;
xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
- NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
+ NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
xcm_out_en = 1;
}
@@ -1966,9 +3016,7 @@ static void elink_update_pfc_nig(struct elink_params *params,
for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
elink_pfc_nig_rx_priority_mask(sc, i,
- nig_params->
- rx_cos_priority_mask[i],
- port);
+ nig_params->rx_cos_priority_mask[i], port);
REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
@@ -1979,13 +3027,13 @@ static void elink_update_pfc_nig(struct elink_params *params,
nig_params->llfc_low_priority_classes);
}
REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
- NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos);
+ NIG_REG_P0_PKT_PRIORITY_TO_COS,
+ pkt_priority_to_cos);
}
elink_status_t elink_update_pfc(struct elink_params *params,
- struct elink_vars *vars,
- struct elink_nig_brb_pfc_port_params
- *pfc_params)
+ struct elink_vars *vars,
+ struct elink_nig_brb_pfc_port_params *pfc_params)
{
/* The PFC and pause are orthogonal to one another, meaning when
* PFC is enabled, the pause are disabled, and when PFC is
@@ -1993,7 +3041,6 @@ elink_status_t elink_update_pfc(struct elink_params *params,
*/
uint32_t val;
struct bnx2x_softc *sc = params->sc;
- elink_status_t elink_status = ELINK_STATUS_OK;
uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
@@ -2004,24 +3051,24 @@ elink_status_t elink_update_pfc(struct elink_params *params,
elink_update_mng(params, vars->link_status);
/* Update NIG params */
- elink_update_pfc_nig(params, pfc_params);
+ elink_update_pfc_nig(params, vars, pfc_params);
if (!vars->link_up)
- return elink_status;
+ return ELINK_STATUS_OK;
- PMD_DRV_LOG(DEBUG, sc, "About to update PFC in BMAC");
+ ELINK_DEBUG_P0(sc, "About to update PFC in BMAC");
if (CHIP_IS_E3(sc)) {
if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
- elink_update_pfc_xmac(params, vars);
+ elink_update_pfc_xmac(params, vars, 0);
} else {
val = REG_RD(sc, MISC_REG_RESET_REG_2);
if ((val &
(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
== 0) {
- PMD_DRV_LOG(DEBUG, sc, "About to update PFC in EMAC");
+ ELINK_DEBUG_P0(sc, "About to update PFC in EMAC");
elink_emac_enable(params, vars, 0);
- return elink_status;
+ return ELINK_STATUS_OK;
}
if (CHIP_IS_E2(sc))
elink_update_pfc_bmac2(params, vars, bmac_loopback);
@@ -2035,20 +3082,21 @@ elink_status_t elink_update_pfc(struct elink_params *params,
val = 1;
REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val);
}
- return elink_status;
+ return ELINK_STATUS_OK;
}
static elink_status_t elink_bmac1_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t is_lb)
+ struct elink_vars *vars,
+ uint8_t is_lb)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t wb_data[2];
uint32_t val;
- PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC1");
+ ELINK_DEBUG_P0(sc, "Enabling BigMAC1");
/* XGXS control */
wb_data[0] = 0x3c;
@@ -2058,16 +3106,18 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params,
/* TX MAC SA */
wb_data[0] = ((params->mac_addr[2] << 24) |
- (params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | params->mac_addr[5]);
- wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
+ (params->mac_addr[3] << 16) |
+ (params->mac_addr[4] << 8) |
+ params->mac_addr[5]);
+ wb_data[1] = ((params->mac_addr[0] << 8) |
+ params->mac_addr[1]);
REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
/* MAC control */
val = 0x3;
if (is_lb) {
val |= 0x4;
- PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
+ ELINK_DEBUG_P0(sc, "enable bmac loopback");
}
wb_data[0] = val;
wb_data[1] = 0;
@@ -2095,20 +3145,30 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params,
wb_data[1] = 0;
REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
wb_data, 2);
+#ifdef ELINK_INCLUDE_EMUL
+ /* Fix for emulation */
+ if (CHIP_REV_IS_EMUL(sc)) {
+ wb_data[0] = 0xf000;
+ wb_data[1] = 0;
+ REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
+ wb_data, 2);
+ }
+#endif
return ELINK_STATUS_OK;
}
static elink_status_t elink_bmac2_enable(struct elink_params *params,
- struct elink_vars *vars, uint8_t is_lb)
+ struct elink_vars *vars,
+ uint8_t is_lb)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t wb_data[2];
- PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC2");
+ ELINK_DEBUG_P0(sc, "Enabling BigMAC2");
wb_data[0] = 0;
wb_data[1] = 0;
@@ -2125,9 +3185,11 @@ static elink_status_t elink_bmac2_enable(struct elink_params *params,
/* TX MAC SA */
wb_data[0] = ((params->mac_addr[2] << 24) |
- (params->mac_addr[3] << 16) |
- (params->mac_addr[4] << 8) | params->mac_addr[5]);
- wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
+ (params->mac_addr[3] << 16) |
+ (params->mac_addr[4] << 8) |
+ params->mac_addr[5]);
+ wb_data[1] = ((params->mac_addr[0] << 8) |
+ params->mac_addr[1]);
REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
wb_data, 2);
@@ -2162,8 +3224,8 @@ static elink_status_t elink_bmac2_enable(struct elink_params *params,
}
static elink_status_t elink_bmac_enable(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t is_lb, uint8_t reset_bmac)
+ struct elink_vars *vars,
+ uint8_t is_lb, uint8_t reset_bmac)
{
elink_status_t rc = ELINK_STATUS_OK;
uint8_t port = params->port;
@@ -2182,7 +3244,7 @@ static elink_status_t elink_bmac_enable(struct elink_params *params,
/* Enable access for bmac registers */
REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
- /* Enable BMAC according to BMAC type */
+ /* Enable BMAC according to BMAC type*/
if (CHIP_IS_E2(sc))
rc = elink_bmac2_enable(params, vars, is_lb);
else
@@ -2192,7 +3254,7 @@ static elink_status_t elink_bmac_enable(struct elink_params *params,
REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);
val = 0;
if ((params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
+ ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
val = 1;
REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);
@@ -2206,13 +3268,15 @@ static elink_status_t elink_bmac_enable(struct elink_params *params,
return rc;
}
-static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
+static void elink_set_bmac_rx(struct bnx2x_softc *sc,
+ __rte_unused uint32_t chip_id,
+ uint8_t port, uint8_t en)
{
uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
uint32_t wb_data[2];
- uint32_t nig_bmac_enable =
- REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
+ uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN +
+ port * 4);
if (CHIP_IS_E2(sc))
bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
@@ -2220,7 +3284,8 @@ static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
/* Only if the bmac is out of reset */
if (REG_RD(sc, MISC_REG_RESET_REG_2) &
- (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {
+ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
+ nig_bmac_enable) {
/* Clear Rx Enable bit in BMAC_CONTROL register */
REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
if (en)
@@ -2233,7 +3298,8 @@ static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
}
static elink_status_t elink_pbf_update(struct elink_params *params,
- uint32_t flow_ctrl, uint32_t line_speed)
+ uint32_t flow_ctrl,
+ uint32_t line_speed)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
@@ -2246,7 +3312,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
/* Wait for init credit */
init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);
crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
- PMD_DRV_LOG(DEBUG, sc, "init_crd 0x%x crd 0x%x", init_crd, crd);
+ ELINK_DEBUG_P2(sc, "init_crd 0x%x crd 0x%x", init_crd, crd);
while ((init_crd != crd) && count) {
DELAY(1000 * 5);
@@ -2255,24 +3321,25 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
}
crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
if (init_crd != crd) {
- PMD_DRV_LOG(DEBUG, sc, "BUG! init_crd 0x%x != crd 0x%x",
- init_crd, crd);
+ ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x",
+ init_crd, crd);
return ELINK_STATUS_ERROR;
}
if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
line_speed == ELINK_SPEED_10 ||
line_speed == ELINK_SPEED_100 ||
- line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) {
+ line_speed == ELINK_SPEED_1000 ||
+ line_speed == ELINK_SPEED_2500) {
REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);
/* Update threshold */
REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);
/* Update init credit */
- init_crd = 778; /* (800-18-4) */
+ init_crd = 778; /* (800-18-4) */
} else {
uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
- ELINK_ETH_OVREHEAD) / 16;
+ ELINK_ETH_OVREHEAD) / 16;
REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
/* Update threshold */
REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);
@@ -2282,14 +3349,14 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
init_crd = thresh + 553 - 22;
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
- line_speed);
+ ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x",
+ line_speed);
return ELINK_STATUS_ERROR;
}
}
REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);
- PMD_DRV_LOG(DEBUG, sc, "PBF updated to speed %d credit %d",
- line_speed, init_crd);
+ ELINK_DEBUG_P2(sc, "PBF updated to speed %d credit %d",
+ line_speed, init_crd);
/* Probe the credit changes */
REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);
@@ -2317,7 +3384,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params,
* the emac_base for the CL45 read/writes operations
*/
static uint32_t elink_get_emac_base(struct bnx2x_softc *sc,
- uint32_t mdc_mdio_access, uint8_t port)
+ uint32_t mdc_mdio_access, uint8_t port)
{
uint32_t emac_base = 0;
switch (mdc_mdio_access) {
@@ -2365,7 +3432,8 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
/* Address */
tmp = ((phy->addr << 21) | (reg << 16) | val |
- EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY);
+ EMAC_MDIO_COMM_COMMAND_WRITE_22 |
+ EMAC_MDIO_COMM_START_BUSY);
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
for (i = 0; i < 50; i++) {
@@ -2378,7 +3446,7 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
}
}
if (tmp & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
+ ELINK_DEBUG_P0(sc, "write phy register failed");
rc = ELINK_STATUS_TIMEOUT;
}
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
@@ -2387,7 +3455,7 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
struct elink_phy *phy,
- uint16_t reg, uint16_t * ret_val)
+ uint16_t reg, uint16_t *ret_val)
{
uint32_t val, mode;
uint16_t i;
@@ -2400,7 +3468,8 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
/* Address */
val = ((phy->addr << 21) | (reg << 16) |
- EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY);
+ EMAC_MDIO_COMM_COMMAND_READ_22 |
+ EMAC_MDIO_COMM_START_BUSY);
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
for (i = 0; i < 50; i++) {
@@ -2408,13 +3477,13 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
- *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA);
+ *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
DELAY(5);
break;
}
}
if (val & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
+ ELINK_DEBUG_P0(sc, "read phy register failed");
*ret_val = 0;
rc = ELINK_STATUS_TIMEOUT;
@@ -2427,14 +3496,17 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
/* CL45 access functions */
/******************************************************************/
static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t devad,
- uint16_t reg, uint16_t * ret_val)
+ struct elink_phy *phy,
+ uint8_t devad, uint16_t reg, uint16_t *ret_val)
{
uint32_t val;
uint16_t i;
elink_status_t rc = ELINK_STATUS_OK;
+ uint32_t chip_id;
if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
- elink_set_mdio_clk(sc, phy->mdio_ctrl);
+ chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
+ ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
+ elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
}
if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
@@ -2442,7 +3514,8 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
EMAC_MDIO_STATUS_10MB);
/* Address */
val = ((phy->addr << 21) | (devad << 16) | reg |
- EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
+ EMAC_MDIO_COMM_COMMAND_ADDRESS |
+ EMAC_MDIO_COMM_START_BUSY);
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
for (i = 0; i < 50; i++) {
@@ -2455,8 +3528,9 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
}
}
if (val & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
- elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
+ ELINK_DEBUG_P0(sc, "read phy register failed");
+ elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);
+ /* "MDC/MDIO access timeout" */
*ret_val = 0;
rc = ELINK_STATUS_TIMEOUT;
@@ -2473,14 +3547,16 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
val = REG_RD(sc, phy->mdio_ctrl +
EMAC_REG_EMAC_MDIO_COMM);
if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
- *ret_val =
- (uint16_t) (val & EMAC_MDIO_COMM_DATA);
+ *ret_val = (uint16_t)
+ (val & EMAC_MDIO_COMM_DATA);
break;
}
}
if (val & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
- elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
+ ELINK_DEBUG_P0(sc, "read phy register failed");
+ elink_cb_event_log(sc,
+ ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);
+ /* "MDC/MDIO access timeout" */
*ret_val = 0;
rc = ELINK_STATUS_TIMEOUT;
@@ -2502,14 +3578,17 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
}
static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t devad,
- uint16_t reg, uint16_t val)
+ struct elink_phy *phy,
+ uint8_t devad, uint16_t reg, uint16_t val)
{
uint32_t tmp;
uint8_t i;
elink_status_t rc = ELINK_STATUS_OK;
+ uint32_t chip_id;
if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
- elink_set_mdio_clk(sc, phy->mdio_ctrl);
+ chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
+ ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
+ elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
}
if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
@@ -2518,7 +3597,8 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
/* Address */
tmp = ((phy->addr << 21) | (devad << 16) | reg |
- EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
+ EMAC_MDIO_COMM_COMMAND_ADDRESS |
+ EMAC_MDIO_COMM_START_BUSY);
REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
for (i = 0; i < 50; i++) {
@@ -2531,8 +3611,9 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
}
}
if (tmp & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
- elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
+ ELINK_DEBUG_P0(sc, "write phy register failed");
+ elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);
+ /* "MDC/MDIO access timeout" */
rc = ELINK_STATUS_TIMEOUT;
} else {
@@ -2553,8 +3634,10 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
}
}
if (tmp & EMAC_MDIO_COMM_START_BUSY) {
- PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
- elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
+ ELINK_DEBUG_P0(sc, "write phy register failed");
+ elink_cb_event_log(sc,
+ ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);
+ /* "MDC/MDIO access timeout" */
rc = ELINK_STATUS_TIMEOUT;
}
@@ -2581,14 +3664,14 @@ static uint8_t elink_eee_has_cap(struct elink_params *params)
struct bnx2x_softc *sc = params->sc;
if (REG_RD(sc, params->shmem2_base) <=
- offsetof(struct shmem2_region, eee_status[params->port]))
- return 0;
+ offsetof(struct shmem2_region, eee_status[params->port]))
+ return 0;
return 1;
}
static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,
- uint32_t * idle_timer)
+ uint32_t *idle_timer)
{
switch (nvram_mode) {
case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
@@ -2609,7 +3692,7 @@ static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,
}
static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer,
- uint32_t * nvram_mode)
+ uint32_t *nvram_mode)
{
switch (idle_timer) {
case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
@@ -2636,7 +3719,7 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params)
if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
- /* time value in eee_mode --> used directly */
+ /* time value in eee_mode --> used directly*/
eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
} else {
/* hsi value in eee_mode --> time */
@@ -2646,12 +3729,11 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params)
return 0;
}
} else {
- /* hsi values in nvram --> time */
+ /* hsi values in nvram --> time*/
eee_mode = ((REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config
- [params->
- port].eee_power_mode)) &
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].
+ eee_power_mode)) &
PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
@@ -2663,7 +3745,7 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params)
}
static elink_status_t elink_eee_set_timers(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
uint32_t eee_idle = 0, eee_mode;
struct bnx2x_softc *sc = params->sc;
@@ -2676,7 +3758,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,
} else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
(params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
(params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
- PMD_DRV_LOG(DEBUG, sc, "Error: Tx LPI is enabled with timer 0");
+ ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0");
return ELINK_STATUS_ERROR;
}
@@ -2685,7 +3767,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,
/* eee_idle in 1u --> eee_status in 16u */
eee_idle >>= 4;
vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
- SHMEM_EEE_TIME_OUTPUT_BIT;
+ SHMEM_EEE_TIME_OUTPUT_BIT;
} else {
if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
return ELINK_STATUS_ERROR;
@@ -2696,8 +3778,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params,
}
static elink_status_t elink_eee_initial_config(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t mode)
+ struct elink_vars *vars, uint8_t mode)
{
vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
@@ -2716,8 +3797,8 @@ static elink_status_t elink_eee_initial_config(struct elink_params *params,
}
static elink_status_t elink_eee_disable(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
@@ -2732,9 +3813,8 @@ static elink_status_t elink_eee_disable(struct elink_phy *phy,
}
static elink_status_t elink_eee_advertise(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars,
- uint8_t modes)
+ struct elink_params *params,
+ struct elink_vars *vars, uint8_t modes)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val = 0;
@@ -2743,11 +3823,11 @@ static elink_status_t elink_eee_advertise(struct elink_phy *phy,
REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
if (modes & SHMEM_EEE_10G_ADV) {
- PMD_DRV_LOG(DEBUG, sc, "Advertise 10GBase-T EEE");
+ ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE");
val |= 0x8;
}
if (modes & SHMEM_EEE_1G_ADV) {
- PMD_DRV_LOG(DEBUG, sc, "Advertise 1GBase-T EEE");
+ ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE");
val |= 0x4;
}
@@ -2771,8 +3851,8 @@ static void elink_update_mng_eee(struct elink_params *params,
}
static void elink_eee_an_resolve(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t adv = 0, lp = 0;
@@ -2787,7 +3867,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
if (adv & 0x2) {
if (vars->line_speed == ELINK_SPEED_100)
neg = 1;
- PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 100M");
+ ELINK_DEBUG_P0(sc, "EEE negotiated - 100M");
}
}
if (lp & 0x14) {
@@ -2795,7 +3875,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
if (adv & 0x14) {
if (vars->line_speed == ELINK_SPEED_1000)
neg = 1;
- PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 1G");
+ ELINK_DEBUG_P0(sc, "EEE negotiated - 1G");
}
}
if (lp & 0x68) {
@@ -2803,7 +3883,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
if (adv & 0x68) {
if (vars->line_speed == ELINK_SPEED_10000)
neg = 1;
- PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 10G");
+ ELINK_DEBUG_P0(sc, "EEE negotiated - 10G");
}
}
@@ -2811,7 +3891,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy,
vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
if (neg) {
- PMD_DRV_LOG(DEBUG, sc, "EEE is active");
+ ELINK_DEBUG_P0(sc, "EEE is active");
vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
}
}
@@ -2832,37 +3912,34 @@ static void elink_bsc_module_sel(struct elink_params *params)
dev_info.shared_hw_config.board));
i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
- SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
+ SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
/* Read I2C output value */
sfp_ctrl = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_cmn_pin_cfg));
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg));
i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
- PMD_DRV_LOG(DEBUG, sc, "Setting BSC switch");
+ ELINK_DEBUG_P0(sc, "Setting BSC switch");
for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
}
-static elink_status_t elink_bsc_read(struct elink_params *params,
- struct bnx2x_softc *sc,
- uint8_t sl_devid,
- uint16_t sl_addr,
- uint8_t lc_addr,
- uint8_t xfer_cnt, uint32_t * data_array)
+static elink_status_t elink_bsc_read(struct bnx2x_softc *sc,
+ uint8_t sl_devid,
+ uint16_t sl_addr,
+ uint8_t lc_addr,
+ uint8_t xfer_cnt,
+ uint32_t *data_array)
{
uint32_t val, i;
elink_status_t rc = ELINK_STATUS_OK;
if (xfer_cnt > 16) {
- PMD_DRV_LOG(DEBUG, sc, "invalid xfer_cnt %d. Max is 16 bytes",
- xfer_cnt);
+ ELINK_DEBUG_P1(sc, "invalid xfer_cnt %d. Max is 16 bytes",
+ xfer_cnt);
return ELINK_STATUS_ERROR;
}
- if (params)
- elink_bsc_module_sel(params);
xfer_cnt = 16 - lc_addr;
@@ -2875,11 +3952,11 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
val = (sl_devid << 16) | sl_addr;
REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
- /* Start xfer with 0 byte to update the address pointer ??? */
+ /* Start xfer with 0 byte to update the address pointer ???*/
val = (MCPR_IMC_COMMAND_ENABLE) |
- (MCPR_IMC_COMMAND_WRITE_OP <<
- MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
- (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
+ (MCPR_IMC_COMMAND_WRITE_OP <<
+ MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
+ (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
/* Poll for completion */
@@ -2889,8 +3966,8 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
DELAY(10);
val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
if (i++ > 1000) {
- PMD_DRV_LOG(DEBUG, sc, "wr 0 byte timed out after %d try",
- i);
+ ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try",
+ i);
rc = ELINK_STATUS_TIMEOUT;
break;
}
@@ -2900,10 +3977,10 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
/* Start xfer with read op */
val = (MCPR_IMC_COMMAND_ENABLE) |
- (MCPR_IMC_COMMAND_READ_OP <<
- MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
- (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
- (xfer_cnt);
+ (MCPR_IMC_COMMAND_READ_OP <<
+ MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
+ (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
+ (xfer_cnt);
REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
/* Poll for completion */
@@ -2913,8 +3990,7 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
DELAY(10);
val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
if (i++ > 1000) {
- PMD_DRV_LOG(DEBUG, sc,
- "rd op timed out after %d try", i);
+ ELINK_DEBUG_P1(sc, "rd op timed out after %d try", i);
rc = ELINK_STATUS_TIMEOUT;
break;
}
@@ -2926,17 +4002,18 @@ static elink_status_t elink_bsc_read(struct elink_params *params,
data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4));
#ifdef __BIG_ENDIAN
data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
- ((data_array[i] & 0x0000ff00) << 8) |
- ((data_array[i] & 0x00ff0000) >> 8) |
- ((data_array[i] & 0xff000000) >> 24);
+ ((data_array[i] & 0x0000ff00) << 8) |
+ ((data_array[i] & 0x00ff0000) >> 8) |
+ ((data_array[i] & 0xff000000) >> 24);
#endif
}
return rc;
}
static void elink_cl45_read_or_write(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t devad,
- uint16_t reg, uint16_t or_val)
+ struct elink_phy *phy,
+ uint8_t devad, uint16_t reg,
+ uint16_t or_val)
{
uint16_t val;
elink_cl45_read(sc, phy, devad, reg, &val);
@@ -2953,7 +4030,42 @@ static void elink_cl45_read_and_write(struct bnx2x_softc *sc,
elink_cl45_write(sc, phy, devad, reg, val & and_val);
}
-static uint8_t elink_get_warpcore_lane(struct elink_params *params)
+elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
+ uint8_t devad, uint16_t reg, uint16_t *ret_val)
+{
+ uint8_t phy_index;
+ /* Probe for the phy according to the given phy_addr, and execute
+ * the read request on it
+ */
+ for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
+ if (params->phy[phy_index].addr == phy_addr) {
+ return elink_cl45_read(params->sc,
+ ¶ms->phy[phy_index], devad,
+ reg, ret_val);
+ }
+ }
+ return ELINK_STATUS_ERROR;
+}
+
+elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
+ uint8_t devad, uint16_t reg, uint16_t val)
+{
+ uint8_t phy_index;
+ /* Probe for the phy according to the given phy_addr, and execute
+ * the write request on it
+ */
+ for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
+ if (params->phy[phy_index].addr == phy_addr) {
+ return elink_cl45_write(params->sc,
+ ¶ms->phy[phy_index], devad,
+ reg, val);
+ }
+ }
+ return ELINK_STATUS_ERROR;
+}
+
+static uint8_t elink_get_warpcore_lane(__rte_unused struct elink_phy *phy,
+ struct elink_params *params)
{
uint8_t lane = 0;
struct bnx2x_softc *sc = params->sc;
@@ -2987,14 +4099,16 @@ static uint8_t elink_get_warpcore_lane(struct elink_params *params)
port = port ^ 1;
lane = (port << 1) + path;
- } else { /* Two port mode - no port swap */
+ } else { /* Two port mode - no port swap */
/* Figure out path swap value */
- path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
+ path_swap_ovr =
+ REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
if (path_swap_ovr & 0x1) {
path_swap = (path_swap_ovr & 0x2);
} else {
- path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
+ path_swap =
+ REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
}
if (path_swap)
path = path ^ 1;
@@ -3004,6 +4118,7 @@ static uint8_t elink_get_warpcore_lane(struct elink_params *params)
return lane;
}
+
static void elink_set_aer_mmd(struct elink_params *params,
struct elink_phy *phy)
{
@@ -3012,13 +4127,13 @@ static void elink_set_aer_mmd(struct elink_params *params,
struct bnx2x_softc *sc = params->sc;
ser_lane = ((params->lane_config &
PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
- (phy->addr + ser_lane) : 0;
+ (phy->addr + ser_lane) : 0;
if (USES_WARPCORE(sc)) {
- aer_val = elink_get_warpcore_lane(params);
+ aer_val = elink_get_warpcore_lane(phy, params);
/* In Dual-lane mode, two lanes are joined together,
* so in order to configure them, the AER broadcast method is
* used here.
@@ -3051,7 +4166,7 @@ static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port)
DELAY(500);
REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
DELAY(500);
- /* Set Clause 45 */
+ /* Set Clause 45 */
REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0);
}
@@ -3059,7 +4174,7 @@ static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)
{
uint32_t val;
- PMD_DRV_LOG(DEBUG, sc, "elink_serdes_deassert");
+ ELINK_DEBUG_P0(sc, "elink_serdes_deassert");
val = ELINK_SERDES_RESET_BITS << (port * 16);
@@ -3094,7 +4209,7 @@ static void elink_xgxs_deassert(struct elink_params *params)
struct bnx2x_softc *sc = params->sc;
uint8_t port;
uint32_t val;
- PMD_DRV_LOG(DEBUG, sc, "elink_xgxs_deassert");
+ ELINK_DEBUG_P0(sc, "elink_xgxs_deassert");
port = params->port;
val = ELINK_XGXS_RESET_BITS << (port * 16);
@@ -3109,8 +4224,9 @@ static void elink_xgxs_deassert(struct elink_params *params)
static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
struct elink_params *params,
- uint16_t * ieee_fc)
+ uint16_t *ieee_fc)
{
+ struct bnx2x_softc *sc = params->sc;
*ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
/* Resolve pause mode and advertisement Please refer to Table
* 28B-3 of the 802.3ab-1999 spec
@@ -3120,12 +4236,12 @@ static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
case ELINK_FLOW_CTRL_AUTO:
switch (params->req_fc_auto_adv) {
case ELINK_FLOW_CTRL_BOTH:
+ case ELINK_FLOW_CTRL_RX:
*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
break;
- case ELINK_FLOW_CTRL_RX:
case ELINK_FLOW_CTRL_TX:
*ieee_fc |=
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
break;
default:
break;
@@ -3145,16 +4261,18 @@ static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
break;
}
- PMD_DRV_LOG(DEBUG, params->sc, "ieee_fc = 0x%x", *ieee_fc);
+ ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x", *ieee_fc);
}
-static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
+static void set_phy_vars(struct elink_params *params,
+ struct elink_vars *vars)
{
+ struct bnx2x_softc *sc = params->sc;
uint8_t actual_phy_idx, phy_index, link_cfg_idx;
uint8_t phy_config_swapped = params->multi_phy_config &
- PORT_HW_CFG_PHY_SWAPPED_ENABLED;
+ PORT_HW_CFG_PHY_SWAPPED_ENABLED;
for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
actual_phy_idx = phy_index;
if (phy_config_swapped) {
@@ -3164,26 +4282,26 @@ static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
actual_phy_idx = ELINK_EXT_PHY1;
}
params->phy[actual_phy_idx].req_flow_ctrl =
- params->req_flow_ctrl[link_cfg_idx];
+ params->req_flow_ctrl[link_cfg_idx];
params->phy[actual_phy_idx].req_line_speed =
- params->req_line_speed[link_cfg_idx];
+ params->req_line_speed[link_cfg_idx];
params->phy[actual_phy_idx].speed_cap_mask =
- params->speed_cap_mask[link_cfg_idx];
+ params->speed_cap_mask[link_cfg_idx];
params->phy[actual_phy_idx].req_duplex =
- params->req_duplex[link_cfg_idx];
+ params->req_duplex[link_cfg_idx];
if (params->req_line_speed[link_cfg_idx] ==
ELINK_SPEED_AUTO_NEG)
vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
- PMD_DRV_LOG(DEBUG, params->sc, "req_flow_ctrl %x, req_line_speed %x,"
- " speed_cap_mask %x",
- params->phy[actual_phy_idx].req_flow_ctrl,
- params->phy[actual_phy_idx].req_line_speed,
- params->phy[actual_phy_idx].speed_cap_mask);
+ ELINK_DEBUG_P3(sc, "req_flow_ctrl %x, req_line_speed %x,"
+ " speed_cap_mask %x",
+ params->phy[actual_phy_idx].req_flow_ctrl,
+ params->phy[actual_phy_idx].req_line_speed,
+ params->phy[actual_phy_idx].speed_cap_mask);
}
}
@@ -3201,38 +4319,57 @@ static void elink_ext_phy_set_pause(struct elink_params *params,
/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
}
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
}
- PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize 0x%x", val);
+ ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x", val);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
}
-static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
-{ /* LD LP */
- switch (pause_result) { /* ASYM P ASYM P */
- case 0xb: /* 1 0 1 1 */
+static void elink_pause_resolve(__rte_unused struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars,
+ uint32_t pause_result)
+{
+ struct bnx2x_softc *sc = params->sc;
+ /* LD LP */
+ switch (pause_result) { /* ASYM P ASYM P */
+ case 0xb: /* 1 0 1 1 */
+ ELINK_DEBUG_P0(sc, "Flow Control: TX only");
vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
break;
- case 0xe: /* 1 1 1 0 */
+ case 0xe: /* 1 1 1 0 */
+ ELINK_DEBUG_P0(sc, "Flow Control: RX only");
vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
break;
- case 0x5: /* 0 1 0 1 */
- case 0x7: /* 0 1 1 1 */
- case 0xd: /* 1 1 0 1 */
- case 0xf: /* 1 1 1 1 */
+ case 0x5: /* 0 1 0 1 */
+ case 0x7: /* 0 1 1 1 */
+ case 0xd: /* 1 1 0 1 */
+ case 0xf: /* 1 1 1 1 */
+ /* If the user selected to advertise RX ONLY,
+ * although we advertised both, need to enable
+ * RX only.
+ */
+
+ if (params->req_fc_auto_adv == ELINK_FLOW_CTRL_BOTH) {
+ ELINK_DEBUG_P0(sc, "Flow Control: RX & TX");
vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
+ } else {
+ ELINK_DEBUG_P0(sc, "Flow Control: RX only");
+ vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
+ }
break;
-
default:
+ ELINK_DEBUG_P0(sc, "Flow Control: None");
+ vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
break;
}
if (pause_result & (1 << 0))
@@ -3246,22 +4383,23 @@ static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
struct elink_params *params,
struct elink_vars *vars)
{
- uint16_t ld_pause; /* local */
- uint16_t lp_pause; /* link partner */
+ uint16_t ld_pause; /* local */
+ uint16_t lp_pause; /* link partner */
uint16_t pause_result;
struct bnx2x_softc *sc = params->sc;
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) {
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) {
elink_cl22_read(sc, phy, 0x4, &ld_pause);
elink_cl22_read(sc, phy, 0x5, &lp_pause);
- } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) {
- uint8_t lane = elink_get_warpcore_lane(params);
+ } else if (CHIP_IS_E3(sc) &&
+ ELINK_SINGLE_MEDIA_DIRECT(params)) {
+ uint8_t lane = elink_get_warpcore_lane(phy, params);
uint16_t gp_status, gp_mask;
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
&gp_status);
gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
- lane;
+ lane;
if ((gp_status & gp_mask) == gp_mask) {
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_ADV_PAUSE, &ld_pause);
@@ -3287,16 +4425,18 @@ static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
}
- pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
- pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
- PMD_DRV_LOG(DEBUG, sc, "Ext PHY pause result 0x%x", pause_result);
- elink_pause_resolve(vars, pause_result);
+ pause_result = (ld_pause &
+ MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
+ pause_result |= (lp_pause &
+ MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
+ ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x", pause_result);
+ elink_pause_resolve(phy, params, vars, pause_result);
}
static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint8_t ret = 0;
vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
@@ -3314,7 +4454,6 @@ static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
}
return ret;
}
-
/******************************************************************/
/* Warpcore section */
/******************************************************************/
@@ -3323,19 +4462,31 @@ static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
* init configuration, and set/clear SGMII flag. Internal
* phy init is done purely in phy_init stage.
*/
-#define WC_TX_DRIVER(post2, idriver, ipre) \
+#define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
(idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
- (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
+ (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
+ (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
#define WC_TX_FIR(post, main, pre) \
((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
(main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
(pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
+static void elink_update_link_attr(struct elink_params *params,
+ uint32_t link_attr)
+{
+ struct bnx2x_softc *sc = params->sc;
+
+ if (SHMEM2_HAS(sc, link_attr_sync))
+ REG_WR(sc, params->shmem2_base +
+ offsetof(struct shmem2_region,
+ link_attr_sync[params->port]), link_attr);
+}
+
static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars)
+ __rte_unused struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t i;
@@ -3358,7 +4509,7 @@ static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
};
- PMD_DRV_LOG(DEBUG, sc, "Enabling 20G-KR2");
+ ELINK_DEBUG_P0(sc, "Enabling 20G-KR2");
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));
@@ -3368,15 +4519,16 @@ static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
reg_set[i].val);
/* Start KR2 work-around timer which handles BNX2X8073 link-parner */
- vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
- elink_update_link_attr(params, vars->link_attr_sync);
+ params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
+ elink_update_link_attr(params, params->link_attr_sync);
}
static void elink_disable_kr2(struct elink_params *params,
- struct elink_vars *vars, struct elink_phy *phy)
+ struct elink_vars *vars,
+ struct elink_phy *phy)
{
struct bnx2x_softc *sc = params->sc;
- uint32_t i;
+ int i;
static struct elink_reg_set reg_set[] = {
/* Step 1 - Program the TX/RX alignment markers */
{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
@@ -3395,13 +4547,13 @@ static void elink_disable_kr2(struct elink_params *params,
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
};
- PMD_DRV_LOG(DEBUG, sc, "Disabling 20G-KR2");
+ ELINK_DEBUG_P0(sc, "Disabling 20G-KR2");
- for (i = 0; i < ARRAY_SIZE(reg_set); i++)
+ for (i = 0; i < (int)ARRAY_SIZE(reg_set); i++)
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
reg_set[i].val);
- vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
- elink_update_link_attr(params, vars->link_attr_sync);
+ params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
+ elink_update_link_attr(params, params->link_attr_sync);
vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
}
@@ -3411,7 +4563,7 @@ static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Configure WC for LPI pass through");
+ ELINK_DEBUG_P0(sc, "Configure WC for LPI pass through");
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
@@ -3423,7 +4575,7 @@ static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
{
/* Restart autoneg on the leading lane only */
struct bnx2x_softc *sc = params->sc;
- uint16_t lane = elink_get_warpcore_lane(params);
+ uint16_t lane = elink_get_warpcore_lane(phy, params);
CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
MDIO_AER_BLOCK_AER_REG, lane);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
@@ -3435,9 +4587,9 @@ static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars)
-{
- uint16_t lane, i, cl72_ctrl, an_adv = 0;
+ struct elink_vars *vars) {
+ uint16_t lane, i, cl72_ctrl, an_adv = 0, val;
+ uint32_t wc_lane_config;
struct bnx2x_softc *sc = params->sc;
static struct elink_reg_set reg_set[] = {
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
@@ -3449,7 +4601,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
{MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
};
- PMD_DRV_LOG(DEBUG, sc, "Enable Auto Negotiation for KR");
+ ELINK_DEBUG_P0(sc, "Enable Auto Negotiation for KR");
/* Set to default registers that may be overridden by 10G force */
for (i = 0; i < ARRAY_SIZE(reg_set); i++)
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
@@ -3471,11 +4623,11 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
/* Enable CL37 1G Parallel Detect */
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
- PMD_DRV_LOG(DEBUG, sc, "Advertize 1G");
+ ELINK_DEBUG_P0(sc, "Advertize 1G");
}
if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
- (vars->line_speed == ELINK_SPEED_10000)) {
+ (vars->line_speed == ELINK_SPEED_10000)) {
/* Check adding advertisement for 10G KR */
an_adv |= (1 << 7);
/* Enable 10G Parallel Detect */
@@ -3485,23 +4637,25 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
elink_set_aer_mmd(params, phy);
- PMD_DRV_LOG(DEBUG, sc, "Advertize 10G");
+ ELINK_DEBUG_P0(sc, "Advertize 10G");
}
/* Set Transmit PMD settings */
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
- WC_TX_DRIVER(0x02, 0x06, 0x09));
+ WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
/* Configure the next lane if dual mode */
if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1),
- WC_TX_DRIVER(0x02, 0x06, 0x09));
+ WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0);
+ MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
+ 0x03f0);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0);
+ MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
+ 0x03f0);
/* Advertised speeds */
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
@@ -3515,14 +4669,13 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
/* Enable CL37 BAM */
if (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- default_cfg)) &
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg)) &
PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
1);
- PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
+ ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR");
}
/* Advertise pause */
@@ -3533,7 +4686,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
/* Over 1G - AN local device user page 1 */
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
+ MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
@@ -3544,7 +4697,8 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_RX1_PCI_CTRL +
- (0x10 * lane), (1 << 11));
+ (0x10 * lane),
+ (1 << 11));
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
@@ -3552,6 +4706,31 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
elink_warpcore_enable_AN_KR2(phy, params, vars);
} else {
+ /* Enable Auto-Detect to support 1G over CL37 as well */
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
+ wc_lane_config = REG_RD(sc, params->shmem_base +
+ offsetof(struct shmem_region, dev_info.
+ shared_hw_config.wc_lane_config));
+ elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
+ /* Force cl48 sync_status LOW to avoid getting stuck in CL73
+ * parallel-detect loop when CL73 and CL37 are enabled.
+ */
+ val |= 1 << 11;
+
+ /* Restore Polarity settings in case it was run over by
+ * previous link owner
+ */
+ if (wc_lane_config &
+ (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
+ val |= 3 << 2;
+ else
+ val &= ~(3 << 2);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
+ val);
+
elink_disable_kr2(params, vars, phy);
}
@@ -3560,7 +4739,8 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
}
static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
- struct elink_params *params)
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val16, i, lane;
@@ -3568,7 +4748,7 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
/* Disable Autoneg */
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
- 0x3f00},
+ 0x3f00},
{MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
{MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
@@ -3581,7 +4761,7 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
reg_set[i].val);
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
/* Global registers */
CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
MDIO_AER_BLOCK_AER_REG, 0);
@@ -3611,7 +4791,8 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
/* Turn TX scramble payload only the 64/66 scrambler */
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_TX66_CONTROL, 0x9);
/* Turn RX scramble payload only the 64/66 scrambler */
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
@@ -3632,7 +4813,7 @@ static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
-
+ uint32_t ifir_val, ipost2_val, ipre_driver_val;
/* Hold rxSeqStart */
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
@@ -3677,38 +4858,59 @@ static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
if (is_xfi) {
misc1_val |= 0x5;
tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
- tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
+ tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
} else {
cfg_tap_val = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->
- port].sfi_tap_values));
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].
+ sfi_tap_values));
tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
- tx_drv_brdct = (cfg_tap_val &
- PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
- PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
-
misc1_val |= 0x9;
/* TAP values are controlled by nvram, if value there isn't 0 */
if (tx_equal)
- tap_val = (uint16_t) tx_equal;
+ tap_val = (uint16_t)tx_equal;
else
tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
- if (tx_drv_brdct)
- tx_driver_val =
- WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06);
- else
- tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
+ ifir_val = DEFAULT_TX_DRV_IFIR;
+ ipost2_val = DEFAULT_TX_DRV_POST2;
+ ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
+ tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
+
+ /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all
+ * configuration.
+ */
+ if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
+ PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
+ PORT_HW_CFG_TX_DRV_POST2_MASK)) {
+ ifir_val = (cfg_tap_val &
+ PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
+ PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
+ ipre_driver_val = (cfg_tap_val &
+ PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
+ >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
+ ipost2_val = (cfg_tap_val &
+ PORT_HW_CFG_TX_DRV_POST2_MASK) >>
+ PORT_HW_CFG_TX_DRV_POST2_SHIFT;
+ }
+
+ if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
+ tx_drv_brdct = (cfg_tap_val &
+ PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
+ PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
+ }
+
+ tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
+ ipre_driver_val, ifir_val);
}
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
/* Set Transmit PMD settings */
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX_FIR_TAP,
tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
@@ -3756,7 +4958,8 @@ static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1));
- elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
+ elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
+ MDIO_AN_REG_CTRL, 0);
/* Turn off CL73 */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_CL73_USERB0_CTRL, &val);
@@ -3792,7 +4995,8 @@ static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
}
static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint16_t lane)
+ struct elink_phy *phy,
+ uint16_t lane)
{
/* Rx0 anaRxControl1G */
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
@@ -3802,13 +5006,17 @@ static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX66_SCW0, 0xE070);
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX66_SCW1, 0xC0D0);
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX66_SCW2, 0xA0B0);
- elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090);
+ elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_RX66_SCW3, 0x8090);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
@@ -3837,7 +5045,7 @@ static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
MDIO_WC_REG_TX_FIR_TAP_ENABLE));
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
- WC_TX_DRIVER(0x02, 0x02, 0x02));
+ WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
}
static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
@@ -3859,7 +5067,7 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
0x1000);
- PMD_DRV_LOG(DEBUG, sc, "set SGMII AUTONEG");
+ ELINK_DEBUG_P0(sc, "set SGMII AUTONEG");
} else {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
@@ -3874,9 +5082,8 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
val16 |= 0x0040;
break;
default:
- PMD_DRV_LOG(DEBUG, sc,
- "Speed not supported: 0x%x",
- phy->req_line_speed);
+ ELINK_DEBUG_P1(sc,
+ "Speed not supported: 0x%x", phy->req_line_speed);
return;
}
@@ -3884,13 +5091,13 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
val16 |= 0x0100;
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
+ MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
- PMD_DRV_LOG(DEBUG, sc, "set SGMII force speed %d",
- phy->req_line_speed);
+ ELINK_DEBUG_P1(sc, "set SGMII force speed %d",
+ phy->req_line_speed);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
- PMD_DRV_LOG(DEBUG, sc, " (readback) %x", val16);
+ ELINK_DEBUG_P1(sc, " (readback) %x", val16);
}
/* SGMII Slave mode and disable signal detect */
@@ -3902,28 +5109,31 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
digctrl_kx1 &= 0xff4a;
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1);
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
+ digctrl_kx1);
/* Turn off parallel detect */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
- (digctrl_kx2 & ~(1 << 2)));
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
+ (digctrl_kx2 & ~(1 << 2)));
/* Re-enable parallel detect */
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
- (digctrl_kx2 | (1 << 2)));
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
+ (digctrl_kx2 | (1 << 2)));
/* Enable autodet */
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
- (digctrl_kx1 | 0x10));
+ MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
+ (digctrl_kx1 | 0x10));
}
+
static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t reset)
+ struct elink_phy *phy,
+ uint8_t reset)
{
uint16_t val;
/* Take lane out of reset after configuration is finished */
@@ -3936,7 +5146,7 @@ static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL5_MISC6, val);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_DIGITAL5_MISC6, &val);
+ MDIO_WC_REG_DIGITAL5_MISC6, &val);
}
/* Clear SFI/XFI link settings registers */
@@ -3952,11 +5162,11 @@ static void elink_warpcore_clear_regs(struct elink_phy *phy,
{MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
- 0x0195},
+ 0x0195},
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
- 0x0007},
+ 0x0007},
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
- 0x0002},
+ 0x0002},
{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
{MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
{MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
@@ -3970,28 +5180,28 @@ static void elink_warpcore_clear_regs(struct elink_phy *phy,
elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
wc_regs[i].val);
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990);
}
static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
+ __rte_unused uint32_t chip_id,
uint32_t shmem_base,
uint8_t port,
- uint8_t * gpio_num,
- uint8_t * gpio_port)
+ uint8_t *gpio_num,
+ uint8_t *gpio_port)
{
uint32_t cfg_pin;
*gpio_num = 0;
*gpio_port = 0;
if (CHIP_IS_E3(sc)) {
cfg_pin = (REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_sfp_ctrl)) &
- PORT_HW_CFG_E3_MOD_ABS_MASK) >>
- PORT_HW_CFG_E3_MOD_ABS_SHIFT;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].e3_sfp_ctrl)) &
+ PORT_HW_CFG_E3_MOD_ABS_MASK) >>
+ PORT_HW_CFG_E3_MOD_ABS_SHIFT;
/* Should not happen. This function called upon interrupt
* triggered by GPIO ( since EPIO can only generate interrupts
@@ -4001,9 +5211,9 @@ static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
*/
if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
(cfg_pin > PIN_CFG_GPIO3_P1)) {
- PMD_DRV_LOG(DEBUG, sc,
- "No cfg pin %x for module detect indication",
- cfg_pin);
+ ELINK_DEBUG_P1(sc,
+ "No cfg pin %x for module detect indication",
+ cfg_pin);
return ELINK_STATUS_ERROR;
}
@@ -4017,12 +5227,13 @@ static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
return ELINK_STATUS_OK;
}
-static int elink_is_sfp_module_plugged(struct elink_params *params)
+static int elink_is_sfp_module_plugged(__rte_unused struct elink_phy *phy,
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint8_t gpio_num, gpio_port;
uint32_t gpio_val;
- if (elink_get_mod_abs_int_cfg(sc,
+ if (elink_get_mod_abs_int_cfg(sc, params->chip_id,
params->shmem_base, params->port,
&gpio_num, &gpio_port) != ELINK_STATUS_OK)
return 0;
@@ -4034,17 +5245,16 @@ static int elink_is_sfp_module_plugged(struct elink_params *params)
else
return 0;
}
-
static int elink_warpcore_get_sigdet(struct elink_phy *phy,
struct elink_params *params)
{
uint16_t gp2_status_reg0, lane;
struct bnx2x_softc *sc = params->sc;
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
- &gp2_status_reg0);
+ &gp2_status_reg0);
return (gp2_status_reg0 >> (8 + lane)) & 0x1;
}
@@ -4063,38 +5273,35 @@ static void elink_warpcore_config_runtime(struct elink_phy *phy,
return;
if (vars->rx_tx_asic_rst) {
- uint16_t lane = elink_get_warpcore_lane(params);
+ uint16_t lane = elink_get_warpcore_lane(phy, params);
serdes_net_if = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config
- [params->port].
- default_cfg)) &
- PORT_HW_CFG_NET_SERDES_IF_MASK);
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg)) &
+ PORT_HW_CFG_NET_SERDES_IF_MASK);
switch (serdes_net_if) {
case PORT_HW_CFG_NET_SERDES_IF_KR:
/* Do we get link yet? */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
&gp_status1);
- lnkup = (gp_status1 >> (8 + lane)) & 0x1; /* 1G */
- /*10G KR */
+ lnkup = (gp_status1 >> (8 + lane)) & 0x1;/* 1G */
+ /*10G KR*/
lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1;
if (lnkup_kr || lnkup) {
vars->rx_tx_asic_rst = 0;
} else {
- /* Reset the lane to see if link comes up. */
+ /* Reset the lane to see if link comes up.*/
elink_warpcore_reset_lane(sc, phy, 1);
elink_warpcore_reset_lane(sc, phy, 0);
/* Restart Autoneg */
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
- MDIO_WC_REG_IEEE0BLK_MIICNTL,
- 0x1200);
+ MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
vars->rx_tx_asic_rst--;
- PMD_DRV_LOG(DEBUG, sc, "0x%x retry left",
- vars->rx_tx_asic_rst);
+ ELINK_DEBUG_P1(sc, "0x%x retry left",
+ vars->rx_tx_asic_rst);
}
break;
@@ -4102,29 +5309,29 @@ static void elink_warpcore_config_runtime(struct elink_phy *phy,
break;
}
- }
- /*params->rx_tx_asic_rst */
+ } /*params->rx_tx_asic_rst*/
}
static void elink_warpcore_config_sfi(struct elink_phy *phy,
struct elink_params *params)
{
- uint16_t lane = elink_get_warpcore_lane(params);
-
+ uint16_t lane = elink_get_warpcore_lane(phy, params);
+ struct bnx2x_softc *sc = params->sc;
elink_warpcore_clear_regs(phy, params, lane);
if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
ELINK_SPEED_10000) &&
(phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
- PMD_DRV_LOG(DEBUG, params->sc, "Setting 10G SFI");
+ ELINK_DEBUG_P0(sc, "Setting 10G SFI");
elink_warpcore_set_10G_XFI(phy, params, 0);
} else {
- PMD_DRV_LOG(DEBUG, params->sc, "Setting 1G Fiber");
+ ELINK_DEBUG_P0(sc, "Setting 1G Fiber");
elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
}
}
static void elink_sfp_e3_set_transmitter(struct elink_params *params,
- struct elink_phy *phy, uint8_t tx_en)
+ struct elink_phy *phy,
+ uint8_t tx_en)
{
struct bnx2x_softc *sc = params->sc;
uint32_t cfg_pin;
@@ -4133,9 +5340,9 @@ static void elink_sfp_e3_set_transmitter(struct elink_params *params,
cfg_pin = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
dev_info.port_hw_config[port].e3_sfp_ctrl)) &
- PORT_HW_CFG_E3_TX_LASER_MASK;
+ PORT_HW_CFG_E3_TX_LASER_MASK;
/* Set the !tx_en since this pin is DISABLE_TX_LASER */
- PMD_DRV_LOG(DEBUG, sc, "Setting WC TX to %d", tx_en);
+ ELINK_DEBUG_P1(sc, "Setting WC TX to %d", tx_en);
/* For 20G, the expected pin to be used is 3 pins after the current */
elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
@@ -4144,21 +5351,20 @@ static void elink_sfp_e3_set_transmitter(struct elink_params *params,
}
static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint32_t serdes_net_if;
uint8_t fiber_mode;
- uint16_t lane = elink_get_warpcore_lane(params);
+ uint16_t lane = elink_get_warpcore_lane(phy, params);
serdes_net_if = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- default_cfg)) &
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg)) &
PORT_HW_CFG_NET_SERDES_IF_MASK);
- PMD_DRV_LOG(DEBUG, sc,
- "Begin Warpcore init, link_speed %d, "
- "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if);
+ ELINK_DEBUG_P2(sc, "Begin Warpcore init, link_speed %d, "
+ "serdes_net_if = 0x%x",
+ vars->line_speed, serdes_net_if);
elink_set_aer_mmd(params, phy);
elink_warpcore_reset_lane(sc, phy, 1);
vars->phy_flags |= PHY_XGXS_FLAG;
@@ -4167,7 +5373,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
((phy->req_line_speed == ELINK_SPEED_100) ||
(phy->req_line_speed == ELINK_SPEED_10)))) {
vars->phy_flags |= PHY_SGMII_FLAG;
- PMD_DRV_LOG(DEBUG, sc, "Setting SGMII mode");
+ ELINK_DEBUG_P0(sc, "Setting SGMII mode");
elink_warpcore_clear_regs(phy, params, lane);
elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
} else {
@@ -4177,27 +5383,28 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
if (params->loopback_mode != ELINK_LOOPBACK_EXT)
elink_warpcore_enable_AN_KR(phy, params, vars);
else {
- PMD_DRV_LOG(DEBUG, sc, "Setting KR 10G-Force");
- elink_warpcore_set_10G_KR(phy, params);
+ ELINK_DEBUG_P0(sc, "Setting KR 10G-Force");
+ elink_warpcore_set_10G_KR(phy, params, vars);
}
break;
case PORT_HW_CFG_NET_SERDES_IF_XFI:
elink_warpcore_clear_regs(phy, params, lane);
if (vars->line_speed == ELINK_SPEED_10000) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 10G XFI");
+ ELINK_DEBUG_P0(sc, "Setting 10G XFI");
elink_warpcore_set_10G_XFI(phy, params, 1);
} else {
if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
- PMD_DRV_LOG(DEBUG, sc, "1G Fiber");
+ ELINK_DEBUG_P0(sc, "1G Fiber");
fiber_mode = 1;
} else {
- PMD_DRV_LOG(DEBUG, sc, "10/100/1G SGMII");
+ ELINK_DEBUG_P0(sc, "10/100/1G SGMII");
fiber_mode = 0;
}
elink_warpcore_set_sgmii_speed(phy,
- params,
- fiber_mode, 0);
+ params,
+ fiber_mode,
+ 0);
}
break;
@@ -4209,7 +5416,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
*/
if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
(params->loopback_mode == ELINK_LOOPBACK_EXT)) {
- if (elink_is_sfp_module_plugged(params))
+ if (elink_is_sfp_module_plugged(phy, params))
elink_sfp_module_detection(phy, params);
else
elink_sfp_e3_set_transmitter(params,
@@ -4221,10 +5428,10 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
if (vars->line_speed != ELINK_SPEED_20000) {
- PMD_DRV_LOG(DEBUG, sc, "Speed not supported yet");
+ ELINK_DEBUG_P0(sc, "Speed not supported yet");
return 0;
}
- PMD_DRV_LOG(DEBUG, sc, "Setting 20G DXGXS");
+ ELINK_DEBUG_P0(sc, "Setting 20G DXGXS");
elink_warpcore_set_20G_DXGXS(sc, phy, lane);
/* Issue Module detection */
@@ -4234,21 +5441,21 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
if (!params->loopback_mode) {
elink_warpcore_enable_AN_KR(phy, params, vars);
} else {
- PMD_DRV_LOG(DEBUG, sc, "Setting KR 20G-Force");
+ ELINK_DEBUG_P0(sc, "Setting KR 20G-Force");
elink_warpcore_set_20G_force_KR2(phy, params);
}
break;
default:
- PMD_DRV_LOG(DEBUG, sc,
- "Unsupported Serdes Net Interface 0x%x",
- serdes_net_if);
+ ELINK_DEBUG_P1(sc,
+ "Unsupported Serdes Net Interface 0x%x",
+ serdes_net_if);
return 0;
}
}
/* Take lane out of reset after configuration is finished */
elink_warpcore_reset_lane(sc, phy, 0);
- PMD_DRV_LOG(DEBUG, sc, "Exit config init");
+ ELINK_DEBUG_P0(sc, "Exit config init");
return 0;
}
@@ -4277,11 +5484,12 @@ static void elink_warpcore_link_reset(struct elink_phy *phy,
MDIO_AER_BLOCK_AER_REG, 0);
/* Enable 1G MDIO (1-copy) */
elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10);
+ MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
+ ~0x10);
elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
/* Disable CL36 PCS Tx */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
@@ -4313,8 +5521,8 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t val16;
uint32_t lane;
- PMD_DRV_LOG(DEBUG, sc, "Setting Warpcore loopback type %x, speed %d",
- params->loopback_mode, phy->req_line_speed);
+ ELINK_DEBUG_P2(sc, "Setting Warpcore loopback type %x, speed %d",
+ params->loopback_mode, phy->req_line_speed);
if (phy->req_line_speed < ELINK_SPEED_10000 ||
phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
@@ -4328,14 +5536,15 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,
MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
0x10);
/* Set 1G loopback based on lane (1-copy) */
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
val16 |= (1 << lane);
if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
val16 |= (2 << lane);
elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16);
+ MDIO_WC_REG_XGXSBLK1_LANECTRL2,
+ val16);
/* Switch back to 4-copy registers */
elink_set_aer_mmd(params, phy);
@@ -4349,8 +5558,10 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy,
}
}
+
+
static void elink_sync_link(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t link_10g_plus;
@@ -4358,21 +5569,23 @@ static void elink_sync_link(struct elink_params *params,
vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
if (vars->link_up) {
- PMD_DRV_LOG(DEBUG, sc, "phy link up");
+ ELINK_DEBUG_P0(sc, "phy link up");
+ ELINK_DEBUG_P1(sc, "link status = %x", vars->link_status);
vars->phy_link_up = 1;
vars->duplex = DUPLEX_FULL;
- switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
+ switch (vars->link_status &
+ LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
case ELINK_LINK_10THD:
vars->duplex = DUPLEX_HALF;
- /* Fall through */
+ /* Fall thru */
case ELINK_LINK_10TFD:
vars->line_speed = ELINK_SPEED_10;
break;
case ELINK_LINK_100TXHD:
vars->duplex = DUPLEX_HALF;
- /* Fall through */
+ /* Fall thru */
case ELINK_LINK_100T4:
case ELINK_LINK_100TXFD:
vars->line_speed = ELINK_SPEED_100;
@@ -4380,14 +5593,14 @@ static void elink_sync_link(struct elink_params *params,
case ELINK_LINK_1000THD:
vars->duplex = DUPLEX_HALF;
- /* Fall through */
+ /* Fall thru */
case ELINK_LINK_1000TFD:
vars->line_speed = ELINK_SPEED_1000;
break;
case ELINK_LINK_2500THD:
vars->duplex = DUPLEX_HALF;
- /* Fall through */
+ /* Fall thru */
case ELINK_LINK_2500TFD:
vars->line_speed = ELINK_SPEED_2500;
break;
@@ -4419,7 +5632,8 @@ static void elink_sync_link(struct elink_params *params,
vars->phy_flags &= ~PHY_SGMII_FLAG;
}
if (vars->line_speed &&
- USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000))
+ USES_WARPCORE(sc) &&
+ (vars->line_speed == ELINK_SPEED_1000))
vars->phy_flags |= PHY_SGMII_FLAG;
/* Anything 10 and over uses the bmac */
link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
@@ -4435,8 +5649,8 @@ static void elink_sync_link(struct elink_params *params,
else
vars->mac_type = ELINK_MAC_TYPE_EMAC;
}
- } else { /* Link down */
- PMD_DRV_LOG(DEBUG, sc, "phy link down");
+ } else { /* Link down */
+ ELINK_DEBUG_P0(sc, "phy link down");
vars->phy_link_up = 0;
@@ -4480,44 +5694,44 @@ void elink_link_status_update(struct elink_params *params,
elink_sync_link(params, vars);
/* Sync media type */
sync_offset = params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].media_type);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].media_type);
media_types = REG_RD(sc, sync_offset);
params->phy[ELINK_INT_PHY].media_type =
- (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
- PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
+ (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
+ PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
params->phy[ELINK_EXT_PHY1].media_type =
- (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
- PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
+ (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
+ PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
params->phy[ELINK_EXT_PHY2].media_type =
- (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
- PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
- PMD_DRV_LOG(DEBUG, sc, "media_types = 0x%x", media_types);
+ (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
+ PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
+ ELINK_DEBUG_P1(sc, "media_types = 0x%x", media_types);
/* Sync AEU offset */
sync_offset = params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].aeu_int_mask);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].aeu_int_mask);
vars->aeu_int_mask = REG_RD(sc, sync_offset);
/* Sync PFC status */
if (vars->link_status & LINK_STATUS_PFC_ENABLED)
params->feature_config_flags |=
- ELINK_FEATURE_CONFIG_PFC_ENABLED;
+ ELINK_FEATURE_CONFIG_PFC_ENABLED;
else
params->feature_config_flags &=
- ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
+ ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
if (SHMEM2_HAS(sc, link_attr_sync))
- vars->link_attr_sync = SHMEM2_RD(sc,
+ params->link_attr_sync = SHMEM2_RD(sc,
link_attr_sync[params->port]);
- PMD_DRV_LOG(DEBUG, sc, "link_status 0x%x phy_link_up %x int_mask 0x%x",
- vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
- PMD_DRV_LOG(DEBUG, sc, "line_speed %x duplex %x flow_ctrl 0x%x",
- vars->line_speed, vars->duplex, vars->flow_ctrl);
+ ELINK_DEBUG_P3(sc, "link_status 0x%x phy_link_up %x int_mask 0x%x",
+ vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
+ ELINK_DEBUG_P3(sc, "line_speed %x duplex %x flow_ctrl 0x%x",
+ vars->line_speed, vars->duplex, vars->flow_ctrl);
}
static void elink_set_master_ln(struct elink_params *params,
@@ -4532,7 +5746,8 @@ static void elink_set_master_ln(struct elink_params *params,
/* Set the master_ln for AN */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_XGXS_BLOCK2,
- MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln);
+ MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
+ &new_master_ln);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_XGXS_BLOCK2,
@@ -4541,8 +5756,8 @@ static void elink_set_master_ln(struct elink_params *params,
}
static elink_status_t elink_reset_unicore(struct elink_params *params,
- struct elink_phy *phy,
- uint8_t set_serdes)
+ struct elink_phy *phy,
+ uint8_t set_serdes)
{
struct bnx2x_softc *sc = params->sc;
uint16_t mii_control;
@@ -4555,7 +5770,8 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
MDIO_COMBO_IEEE0_MII_CONTROL,
- (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
+ (mii_control |
+ MDIO_COMBO_IEEO_MII_CONTROL_RESET));
if (set_serdes)
elink_set_serdes_access(sc, params->port);
@@ -4566,7 +5782,8 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,
/* The reset erased the previous bank value */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
DELAY(5);
@@ -4574,10 +5791,12 @@ static elink_status_t elink_reset_unicore(struct elink_params *params,
}
}
- elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
- // " Port %d",
+ elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port);
+ /* "Warning: PHY was not initialized,"
+ * " Port %d",
+ */
- PMD_DRV_LOG(DEBUG, sc, "BUG! XGXS is still in reset!");
+ ELINK_DEBUG_P0(sc, "BUG! XGXS is still in reset!");
return ELINK_STATUS_ERROR;
}
@@ -4631,31 +5850,35 @@ static void elink_set_parallel_detection(struct elink_phy *phy,
uint16_t control2;
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+ &control2);
if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
else
control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
- PMD_DRV_LOG(DEBUG, sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
- phy->speed_cap_mask, control2);
+ ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
+ phy->speed_cap_mask, control2);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+ control2);
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
- (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
- PMD_DRV_LOG(DEBUG, sc, "XGXS");
+ (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
+ ELINK_DEBUG_P0(sc, "XGXS");
CL22_WR_OVER_CL45(sc, phy,
- MDIO_REG_BANK_10G_PARALLEL_DETECT,
- MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
- MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
+ MDIO_REG_BANK_10G_PARALLEL_DETECT,
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_10G_PARALLEL_DETECT,
MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
&control2);
+
control2 |=
MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
@@ -4675,7 +5898,8 @@ static void elink_set_parallel_detection(struct elink_phy *phy,
static void elink_set_autoneg(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars, uint8_t enable_cl73)
+ struct elink_vars *vars,
+ uint8_t enable_cl73)
{
struct bnx2x_softc *sc = params->sc;
uint16_t reg_val;
@@ -4688,7 +5912,7 @@ static void elink_set_autoneg(struct elink_phy *phy,
/* CL37 Autoneg Enabled */
if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
- else /* CL37 Autoneg Disabled */
+ else /* CL37 Autoneg Disabled */
reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
@@ -4702,7 +5926,7 @@ static void elink_set_autoneg(struct elink_phy *phy,
MDIO_REG_BANK_SERDES_DIGITAL,
MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
@@ -4716,7 +5940,8 @@ static void elink_set_autoneg(struct elink_phy *phy,
/* Enable TetonII and BAM autoneg */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_BAM_NEXT_PAGE,
- MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val);
+ MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+ ®_val);
if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
/* Enable BAM aneg Mode and TetonII aneg Mode */
reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
@@ -4728,40 +5953,45 @@ static void elink_set_autoneg(struct elink_phy *phy,
}
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_BAM_NEXT_PAGE,
- MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val);
+ MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+ reg_val);
if (enable_cl73) {
/* Enable Cl73 FSM status bits */
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_USERB0,
- MDIO_CL73_USERB0_CL73_UCTRL, 0xe);
+ MDIO_CL73_USERB0_CL73_UCTRL,
+ 0xe);
- /* Enable BAM Station Manager */
+ /* Enable BAM Station Manager*/
CL22_WR_OVER_CL45(sc, phy,
- MDIO_REG_BANK_CL73_USERB0,
- MDIO_CL73_USERB0_CL73_BAM_CTRL1,
- MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
- MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
- |
- MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
+ MDIO_REG_BANK_CL73_USERB0,
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1,
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
/* Advertise CL73 link speeds */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB1,
- MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
- if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
+ MDIO_CL73_IEEEB1_AN_ADV2,
+ ®_val);
+ if (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
- if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
+ if (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB1,
- MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
+ MDIO_CL73_IEEEB1_AN_ADV2,
+ reg_val);
/* CL73 Autoneg Enabled */
reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
- } else /* CL73 Autoneg Disabled */
+ } else /* CL73 Autoneg Disabled */
reg_val = 0;
CL22_WR_OVER_CL45(sc, phy,
@@ -4777,7 +6007,7 @@ static void elink_program_serdes(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t reg_val;
- /* Program duplex, disable autoneg and sgmii */
+ /* Program duplex, disable autoneg and sgmii*/
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
@@ -4797,7 +6027,7 @@ static void elink_program_serdes(struct elink_phy *phy,
MDIO_REG_BANK_SERDES_DIGITAL,
MDIO_SERDES_DIGITAL_MISC1, ®_val);
/* Clearing the speed value before setting the right speed */
- PMD_DRV_LOG(DEBUG, sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
+ ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
@@ -4810,7 +6040,7 @@ static void elink_program_serdes(struct elink_phy *phy,
MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
if (vars->line_speed == ELINK_SPEED_10000)
reg_val |=
- MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
+ MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
}
CL22_WR_OVER_CL45(sc, phy,
@@ -4831,10 +6061,12 @@ static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
val |= MDIO_OVER_1G_UP1_10G;
CL22_WR_OVER_CL45(sc, phy,
- MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);
+ MDIO_REG_BANK_OVER_1G,
+ MDIO_OVER_1G_UP1, val);
CL22_WR_OVER_CL45(sc, phy,
- MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);
+ MDIO_REG_BANK_OVER_1G,
+ MDIO_OVER_1G_UP3, 0x400);
}
static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
@@ -4865,7 +6097,7 @@ static void elink_restart_autoneg(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t mii_control;
- PMD_DRV_LOG(DEBUG, sc, "elink_restart_autoneg");
+ ELINK_DEBUG_P0(sc, "elink_restart_autoneg");
/* Enable and restart BAM/CL37 aneg */
if (enable_cl73) {
@@ -4878,16 +6110,17 @@ static void elink_restart_autoneg(struct elink_phy *phy,
MDIO_REG_BANK_CL73_IEEEB0,
MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
(mii_control |
- MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
- MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
} else {
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
- PMD_DRV_LOG(DEBUG, sc,
- "elink_restart_autoneg mii_control before = 0x%x",
- mii_control);
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
+ ELINK_DEBUG_P1(sc,
+ "elink_restart_autoneg mii_control before = 0x%x",
+ mii_control);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
MDIO_COMBO_IEEE0_MII_CONTROL,
@@ -4908,7 +6141,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+ &control1);
control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
/* Set sgmii mode (and not fiber) */
control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
@@ -4916,7 +6150,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1);
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+ control1);
/* If forced speed */
if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
@@ -4925,7 +6160,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
@@ -4933,30 +6169,32 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
switch (vars->line_speed) {
case ELINK_SPEED_100:
mii_control |=
- MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
+ MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
break;
case ELINK_SPEED_1000:
mii_control |=
- MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
+ MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
break;
case ELINK_SPEED_10:
/* There is nothing to set for 10M */
break;
default:
/* Invalid speed for SGMII */
- PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
- vars->line_speed);
+ ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x",
+ vars->line_speed);
break;
}
/* Setting the full duplex */
if (phy->req_duplex == DUPLEX_FULL)
- mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
+ mii_control |=
+ MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_MII_CONTROL, mii_control);
+ MDIO_COMBO_IEEE0_MII_CONTROL,
+ mii_control);
- } else { /* AN mode */
+ } else { /* AN mode */
/* Enable and restart AN */
elink_restart_autoneg(phy, params, 0);
}
@@ -4965,8 +6203,7 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy,
/* Link management
*/
static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
- struct elink_params
- *params)
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint16_t pd_10g, status2_1000x;
@@ -4974,34 +6211,38 @@ static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
return ELINK_STATUS_OK;
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
+ MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
+ &status2_1000x);
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_SERDES_DIGITAL,
- MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
+ MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
+ &status2_1000x);
if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
- PMD_DRV_LOG(DEBUG, sc, "1G parallel detect link on port %d",
- params->port);
- return ELINK_STATUS_ERROR;
+ ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d",
+ params->port);
+ return 1;
}
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_10G_PARALLEL_DETECT,
- MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
+ &pd_10g);
if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
- PMD_DRV_LOG(DEBUG, sc, "10G parallel detect link on port %d",
- params->port);
- return ELINK_STATUS_ERROR;
+ ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d",
+ params->port);
+ return 1;
}
return ELINK_STATUS_OK;
}
static void elink_update_adv_fc(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars, uint32_t gp_status)
+ struct elink_vars *vars,
+ uint32_t gp_status)
{
- uint16_t ld_pause; /* local driver */
- uint16_t lp_pause; /* link partner */
+ uint16_t ld_pause; /* local driver */
+ uint16_t lp_pause; /* link partner */
uint16_t pause_result;
struct bnx2x_softc *sc = params->sc;
if ((gp_status &
@@ -5012,37 +6253,42 @@ static void elink_update_adv_fc(struct elink_phy *phy,
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB1,
- MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause);
+ MDIO_CL73_IEEEB1_AN_ADV1,
+ &ld_pause);
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB1,
- MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);
+ MDIO_CL73_IEEEB1_AN_LP_ADV1,
+ &lp_pause);
pause_result = (ld_pause &
MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
pause_result |= (lp_pause &
MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
- PMD_DRV_LOG(DEBUG, sc, "pause_result CL73 0x%x", pause_result);
+ ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x", pause_result);
} else {
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
+ &ld_pause);
CL22_RD_OVER_CL45(sc, phy,
- MDIO_REG_BANK_COMBO_IEEE0,
- MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
- &lp_pause);
+ MDIO_REG_BANK_COMBO_IEEE0,
+ MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
+ &lp_pause);
pause_result = (ld_pause &
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;
pause_result |= (lp_pause &
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;
- PMD_DRV_LOG(DEBUG, sc, "pause_result CL37 0x%x", pause_result);
+ ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x", pause_result);
}
- elink_pause_resolve(vars, pause_result);
+ elink_pause_resolve(phy, params, vars, pause_result);
}
static void elink_flow_ctrl_resolve(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars, uint32_t gp_status)
+ struct elink_vars *vars,
+ uint32_t gp_status)
{
+ struct bnx2x_softc *sc = params->sc;
vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
/* Resolve from gp_status in case of AN complete and not sgmii */
@@ -5062,7 +6308,7 @@ static void elink_flow_ctrl_resolve(struct elink_phy *phy,
}
elink_update_adv_fc(phy, params, vars, gp_status);
}
- PMD_DRV_LOG(DEBUG, params->sc, "flow_ctrl 0x%x", vars->flow_ctrl);
+ ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x", vars->flow_ctrl);
}
static void elink_check_fallback_to_cl37(struct elink_phy *phy,
@@ -5070,14 +6316,16 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
{
struct bnx2x_softc *sc = params->sc;
uint16_t rx_status, ustat_val, cl37_fsm_received;
- PMD_DRV_LOG(DEBUG, sc, "elink_check_fallback_to_cl37");
+ ELINK_DEBUG_P0(sc, "elink_check_fallback_to_cl37");
/* Step 1: Make sure signal is detected */
CL22_RD_OVER_CL45(sc, phy,
- MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);
+ MDIO_REG_BANK_RX0,
+ MDIO_RX0_RX_STATUS,
+ &rx_status);
if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
(MDIO_RX0_RX_STATUS_SIGDET)) {
- PMD_DRV_LOG(DEBUG, sc, "Signal is not detected. Restoring CL73."
- "rx_status(0x80b0) = 0x%x", rx_status);
+ ELINK_DEBUG_P1(sc, "Signal is not detected. Restoring CL73."
+ "rx_status(0x80b0) = 0x%x", rx_status);
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB0,
MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
@@ -5087,14 +6335,15 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
/* Step 2: Check CL73 state machine */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_USERB0,
- MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val);
+ MDIO_CL73_USERB0_CL73_USTAT1,
+ &ustat_val);
if ((ustat_val &
(MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
(MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
- MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
- PMD_DRV_LOG(DEBUG, sc, "CL73 state-machine is not stable. "
- "ustat_val(0x8371) = 0x%x", ustat_val);
+ MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
+ ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. "
+ "ustat_val(0x8371) = 0x%x", ustat_val);
return;
}
/* Step 3: Check CL37 Message Pages received to indicate LP
@@ -5102,14 +6351,16 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
*/
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_REMOTE_PHY,
- MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received);
+ MDIO_REMOTE_PHY_MISC_RX_STATUS,
+ &cl37_fsm_received);
if ((cl37_fsm_received &
(MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
- MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
+ MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
(MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
- MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
- PMD_DRV_LOG(DEBUG, sc, "No CL37 FSM were received. "
- "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received);
+ MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
+ ELINK_DEBUG_P1(sc, "No CL37 FSM were received. "
+ "misc_rx_status(0x8330) = 0x%x",
+ cl37_fsm_received);
return;
}
/* The combined cl37/cl73 fsm state information indicating that
@@ -5121,34 +6372,38 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy,
/* Disable CL73 */
CL22_WR_OVER_CL45(sc, phy,
MDIO_REG_BANK_CL73_IEEEB0,
- MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+ 0);
/* Restart CL37 autoneg */
elink_restart_autoneg(phy, params, 0);
- PMD_DRV_LOG(DEBUG, sc, "Disabling CL73, and restarting CL37 autoneg");
+ ELINK_DEBUG_P0(sc, "Disabling CL73, and restarting CL37 autoneg");
}
static void elink_xgxs_an_resolve(struct elink_phy *phy,
struct elink_params *params,
- struct elink_vars *vars, uint32_t gp_status)
+ struct elink_vars *vars,
+ uint32_t gp_status)
{
if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
- vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+ vars->link_status |=
+ LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
if (elink_direct_parallel_detect_used(phy, params))
- vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
+ vars->link_status |=
+ LINK_STATUS_PARALLEL_DETECTION_USED;
}
-
static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
- struct elink_params *params __rte_unused,
- struct elink_vars *vars,
- uint16_t is_link_up,
- uint16_t speed_mask,
- uint16_t is_duplex)
+ struct elink_params *params,
+ struct elink_vars *vars,
+ uint16_t is_link_up,
+ uint16_t speed_mask,
+ uint16_t is_duplex)
{
+ struct bnx2x_softc *sc = params->sc;
if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
if (is_link_up) {
- PMD_DRV_LOG(DEBUG, params->sc, "phy link up");
+ ELINK_DEBUG_P0(sc, "phy link up");
vars->phy_link_up = 1;
vars->link_status |= LINK_STATUS_LINK_UP;
@@ -5189,9 +6444,9 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
case ELINK_GP_STATUS_5G:
case ELINK_GP_STATUS_6G:
- PMD_DRV_LOG(DEBUG, params->sc,
- "link speed unsupported gp_status 0x%x",
- speed_mask);
+ ELINK_DEBUG_P1(sc,
+ "link speed unsupported gp_status 0x%x",
+ speed_mask);
return ELINK_STATUS_ERROR;
case ELINK_GP_STATUS_10G_KX4:
@@ -5209,13 +6464,13 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
vars->link_status |= ELINK_LINK_20GTFD;
break;
default:
- PMD_DRV_LOG(DEBUG, params->sc,
- "link speed unsupported gp_status 0x%x",
- speed_mask);
+ ELINK_DEBUG_P1(sc,
+ "link speed unsupported gp_status 0x%x",
+ speed_mask);
return ELINK_STATUS_ERROR;
}
- } else { /* link_down */
- PMD_DRV_LOG(DEBUG, params->sc, "phy link down");
+ } else { /* link_down */
+ ELINK_DEBUG_P0(sc, "phy link down");
vars->phy_link_up = 0;
@@ -5223,14 +6478,16 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
vars->mac_type = ELINK_MAC_TYPE_NONE;
}
- PMD_DRV_LOG(DEBUG, params->sc, " phy_link_up %x line_speed %d",
+ ELINK_DEBUG_P2(sc, " in elink_get_link_speed_duplex vars->link_status = %x, vars->duplex = %x",
+ vars->link_status, vars->duplex);
+ ELINK_DEBUG_P2(sc, " phy_link_up %x line_speed %d",
vars->phy_link_up, vars->line_speed);
return ELINK_STATUS_OK;
}
static uint8_t elink_link_settings_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
@@ -5240,14 +6497,23 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
/* Read gp_status */
CL22_RD_OVER_CL45(sc, phy,
MDIO_REG_BANK_GP_STATUS,
- MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);
- if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
+ MDIO_GP_STATUS_TOP_AN_STATUS1,
+ &gp_status);
+ if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) {
duplex = DUPLEX_FULL;
+ ELINK_DEBUG_P1(sc, "duplex status read from phy is = %x",
+ duplex);
+ } else {
+ ELINK_DEBUG_P1(sc, "phy status does not allow interface to be FULL_DUPLEX : %x",
+ gp_status);
+ }
+
+
if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
link_up = 1;
speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
- PMD_DRV_LOG(DEBUG, sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
- gp_status, link_up, speed_mask);
+ ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
+ gp_status, link_up, speed_mask);
rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
duplex);
if (rc == ELINK_STATUS_ERROR)
@@ -5261,7 +6527,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
elink_xgxs_an_resolve(phy, params, vars,
gp_status);
}
- } else { /* Link_down */
+ } else { /* Link_down */
if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
ELINK_SINGLE_MEDIA_DIRECT(params)) {
/* Check signal is detected */
@@ -5269,7 +6535,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
}
}
- /* Read LP advertised speeds */
+ /* Read LP advertised speeds*/
if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
(vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
uint16_t val;
@@ -5279,61 +6545,69 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy,
if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
MDIO_OVER_1G_LP_UP1, &val);
if (val & MDIO_OVER_1G_UP1_2_5G)
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
}
- PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
- vars->duplex, vars->flow_ctrl, vars->link_status);
+ ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
+ vars->duplex, vars->flow_ctrl, vars->link_status);
return rc;
}
static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t lane;
uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
elink_status_t rc = ELINK_STATUS_OK;
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
/* Read gp_status */
- if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
+ if ((params->loopback_mode) &&
+ (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
link_up &= 0x1;
+ ELINK_DEBUG_P1(sc, "params->loopback_mode link_up read = %x",
+ link_up);
} else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
- (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
+ (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
uint16_t temp_link_up;
- elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);
- elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);
- PMD_DRV_LOG(DEBUG, sc, "PCS RX link status = 0x%x-->0x%x",
- temp_link_up, link_up);
+ elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
+ 1, &temp_link_up);
+ elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
+ 1, &link_up);
+ ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x",
+ temp_link_up, link_up);
link_up &= (1 << 2);
if (link_up)
elink_ext_phy_resolve_fc(phy, params, vars);
} else {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
- MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
- PMD_DRV_LOG(DEBUG, sc, "0x81d1 = 0x%x", gp_status1);
+ MDIO_WC_REG_GP2_STATUS_GP_2_1,
+ &gp_status1);
+ ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x", gp_status1);
/* Check for either KR, 1G, or AN up. */
link_up = ((gp_status1 >> 8) |
- (gp_status1 >> 12) | (gp_status1)) & (1 << lane);
+ (gp_status1 >> 12) |
+ (gp_status1)) &
+ (1 << lane);
if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
uint16_t an_link;
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
@@ -5341,6 +6615,8 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_STATUS, &an_link);
link_up |= (an_link & (1 << 2));
+ ELINK_DEBUG_P2(sc, "an_link = %x, link_up = %x",
+ an_link, link_up);
}
if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
uint16_t pd, gp_status4;
@@ -5351,7 +6627,7 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
&gp_status4);
if (gp_status4 & ((1 << 12) << lane))
vars->link_status |=
- LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+ LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
/* Check parallel detect used */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
@@ -5359,13 +6635,19 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
&pd);
if (pd & (1 << 15))
vars->link_status |=
- LINK_STATUS_PARALLEL_DETECTION_USED;
+ LINK_STATUS_PARALLEL_DETECTION_USED;
+ ELINK_DEBUG_P2(sc, "pd = %x, link_status = %x",
+ pd, vars->link_status);
}
elink_ext_phy_resolve_fc(phy, params, vars);
vars->duplex = duplex;
+ ELINK_DEBUG_P3(sc, " ELINK_SINGLE_MEDIA_DIRECT duplex %x flow_ctrl 0x%x link_status 0x%x",
+ vars->duplex, vars->flow_ctrl,
+ vars->link_status);
}
}
-
+ ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
+ vars->duplex, vars->flow_ctrl, vars->link_status);
if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
ELINK_SINGLE_MEDIA_DIRECT(params)) {
uint16_t val;
@@ -5375,24 +6657,28 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
-
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ ELINK_DEBUG_P2(sc, "val = %x, link_status = %x",
+ val, vars->link_status);
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
if (val & MDIO_OVER_1G_UP1_2_5G)
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ ELINK_DEBUG_P2(sc, "val = %x, link_status = %x",
+ val, vars->link_status);
}
+
if (lane < 2) {
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
@@ -5400,12 +6686,12 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
}
- PMD_DRV_LOG(DEBUG, sc, "lane %d gp_speed 0x%x", lane, gp_speed);
+ ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x", lane, gp_speed);
if ((lane & 1) == 0)
gp_speed <<= 8;
gp_speed &= 0x3f00;
- link_up = ! !link_up;
+ link_up = !!link_up;
/* Reset the TX FIFO to fix SGMII issue */
rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
@@ -5416,11 +6702,10 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
(!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
- PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
- vars->duplex, vars->flow_ctrl, vars->link_status);
+ ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
+ vars->duplex, vars->flow_ctrl, vars->link_status);
return rc;
}
-
static void elink_set_gmii_tx_driver(struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
@@ -5431,7 +6716,8 @@ static void elink_set_gmii_tx_driver(struct elink_params *params)
/* Read precomp */
CL22_RD_OVER_CL45(sc, phy,
- MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);
+ MDIO_REG_BANK_OVER_1G,
+ MDIO_OVER_1G_LP_UP2, &lp_up2);
/* Bits [10:7] at lp_up2, positioned at [15:12] */
lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
@@ -5442,32 +6728,36 @@ static void elink_set_gmii_tx_driver(struct elink_params *params)
return;
for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
- bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
+ bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
CL22_RD_OVER_CL45(sc, phy,
- bank, MDIO_TX0_TX_DRIVER, &tx_driver);
+ bank,
+ MDIO_TX0_TX_DRIVER, &tx_driver);
/* Replace tx_driver bits [15:12] */
- if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
+ if (lp_up2 !=
+ (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
tx_driver |= lp_up2;
CL22_WR_OVER_CL45(sc, phy,
- bank, MDIO_TX0_TX_DRIVER, tx_driver);
+ bank,
+ MDIO_TX0_TX_DRIVER, tx_driver);
}
}
}
static elink_status_t elink_emac_program(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
uint16_t mode = 0;
- PMD_DRV_LOG(DEBUG, sc, "setting link speed & duplex");
+ ELINK_DEBUG_P0(sc, "setting link speed & duplex");
elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +
EMAC_REG_EMAC_MODE,
(EMAC_MODE_25G_MODE |
- EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX));
+ EMAC_MODE_PORT_MII_10M |
+ EMAC_MODE_HALF_DUPLEX));
switch (vars->line_speed) {
case ELINK_SPEED_10:
mode |= EMAC_MODE_PORT_MII_10M;
@@ -5487,15 +6777,16 @@ static elink_status_t elink_emac_program(struct elink_params *params,
default:
/* 10G not valid for EMAC */
- PMD_DRV_LOG(DEBUG, sc,
- "Invalid line_speed 0x%x", vars->line_speed);
+ ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x",
+ vars->line_speed);
return ELINK_STATUS_ERROR;
}
if (vars->duplex == DUPLEX_HALF)
mode |= EMAC_MODE_HALF_DUPLEX;
elink_bits_en(sc,
- GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode);
+ GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE,
+ mode);
elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
return ELINK_STATUS_OK;
@@ -5512,24 +6803,26 @@ static void elink_set_preemphasis(struct elink_phy *phy,
bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) {
CL22_WR_OVER_CL45(sc, phy,
bank,
- MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]);
+ MDIO_RX0_RX_EQ_BOOST,
+ phy->rx_preemphasis[i]);
}
for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
CL22_WR_OVER_CL45(sc, phy,
bank,
- MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]);
+ MDIO_TX0_TX_DRIVER,
+ phy->tx_preemphasis[i]);
}
}
static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
+ struct bnx2x_softc *sc = params->sc;
uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
- (params->loopback_mode == ELINK_LOOPBACK_XGXS));
-
+ (params->loopback_mode == ELINK_LOOPBACK_XGXS));
if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
(params->feature_config_flags &
@@ -5540,7 +6833,7 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
(ELINK_SINGLE_MEDIA_DIRECT(params) &&
params->loopback_mode == ELINK_LOOPBACK_EXT)) {
- PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, no AN");
+ ELINK_DEBUG_P0(sc, "not SGMII, no AN");
/* Disable autoneg */
elink_set_autoneg(phy, params, vars, 0);
@@ -5548,8 +6841,8 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
/* Program speed and duplex */
elink_program_serdes(phy, params, vars);
- } else { /* AN_mode */
- PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, AN");
+ } else { /* AN_mode */
+ ELINK_DEBUG_P0(sc, "not SGMII, AN");
/* AN enabled */
elink_set_brcm_cl37_advertisement(phy, params);
@@ -5565,8 +6858,8 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
elink_restart_autoneg(phy, params, enable_cl73);
}
- } else { /* SGMII mode */
- PMD_DRV_LOG(DEBUG, params->sc, "SGMII");
+ } else { /* SGMII mode */
+ ELINK_DEBUG_P0(sc, "SGMII");
elink_initialize_sgmii_process(phy, params, vars);
}
@@ -5575,8 +6868,8 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
}
static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
elink_status_t rc;
vars->phy_flags |= PHY_XGXS_FLAG;
@@ -5614,28 +6907,32 @@ static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
}
static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- struct elink_params *params)
+ struct elink_phy *phy,
+ struct elink_params *params)
{
uint16_t cnt, ctrl;
/* Wait for soft reset to get cleared up to 1 sec */
for (cnt = 0; cnt < 1000; cnt++) {
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
- elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl);
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE)
+ elink_cl22_read(sc, phy,
+ MDIO_PMA_REG_CTRL, &ctrl);
else
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_CTRL, &ctrl);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL, &ctrl);
if (!(ctrl & (1 << 15)))
break;
DELAY(1000 * 1);
}
if (cnt == 1000)
- elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
- // " Port %d",
+ elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED,
+ params->port);
+ /* "Warning: PHY was not initialized,"
+ * " Port %d",
+ */
- PMD_DRV_LOG(DEBUG, sc, "control reg 0x%x (after %d ms)", ctrl, cnt);
+ ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)", ctrl, cnt);
return cnt;
}
@@ -5653,37 +6950,38 @@ static void elink_link_int_enable(struct elink_params *params)
} else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
ELINK_NIG_MASK_XGXS0_LINK_STATUS);
- PMD_DRV_LOG(DEBUG, sc, "enabled XGXS interrupt");
+ ELINK_DEBUG_P0(sc, "enabled XGXS interrupt");
if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
- params->phy[ELINK_INT_PHY].type !=
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
+ params->phy[ELINK_INT_PHY].type !=
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
mask |= ELINK_NIG_MASK_MI_INT;
- PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
+ ELINK_DEBUG_P0(sc, "enabled external phy int");
}
- } else { /* SerDes */
+ } else { /* SerDes */
mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
- PMD_DRV_LOG(DEBUG, sc, "enabled SerDes interrupt");
+ ELINK_DEBUG_P0(sc, "enabled SerDes interrupt");
if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
- params->phy[ELINK_INT_PHY].type !=
- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
+ params->phy[ELINK_INT_PHY].type !=
+ PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
mask |= ELINK_NIG_MASK_MI_INT;
- PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
+ ELINK_DEBUG_P0(sc, "enabled external phy int");
}
}
- elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);
+ elink_bits_en(sc,
+ NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
+ mask);
- PMD_DRV_LOG(DEBUG, sc, "port %x, is_xgxs %x, int_status 0x%x", port,
- (params->switch_cfg == ELINK_SWITCH_CFG_10G),
- REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
- PMD_DRV_LOG(DEBUG, sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
- REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
- REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
- REG_RD(sc,
- NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
- PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
- REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
- REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
+ ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x", port,
+ (params->switch_cfg == ELINK_SWITCH_CFG_10G),
+ REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
+ ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
+ REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
+ REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
+ REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
+ ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x",
+ REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
+ REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
}
static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
@@ -5696,17 +6994,20 @@ static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
* so in this case we need to write the status to clear the XOR
*/
/* Read Latched signals */
- latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);
- PMD_DRV_LOG(DEBUG, sc, "latch_status = 0x%x", latch_status);
- /* Handle only those with latched-signal=up. */
+ latch_status = REG_RD(sc,
+ NIG_REG_LATCH_STATUS_0 + port * 8);
+ ELINK_DEBUG_P1(sc, "latch_status = 0x%x", latch_status);
+ /* Handle only those with latched-signal=up.*/
if (exp_mi_int)
elink_bits_en(sc,
NIG_REG_STATUS_INTERRUPT_PORT0
- + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
+ + port * 4,
+ ELINK_NIG_STATUS_EMAC0_MI_INT);
else
elink_bits_dis(sc,
NIG_REG_STATUS_INTERRUPT_PORT0
- + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
+ + port * 4,
+ ELINK_NIG_STATUS_EMAC0_MI_INT);
if (latch_status & 1) {
@@ -5741,23 +7042,24 @@ static void elink_link_int_ack(struct elink_params *params,
* the relevant lane in the status register
*/
uint32_t ser_lane =
- ((params->lane_config &
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+ ((params->lane_config &
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
mask = ((1 << ser_lane) <<
- ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
+ ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
} else
mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
}
- PMD_DRV_LOG(DEBUG, sc, "Ack link up interrupt with mask 0x%x",
- mask);
+ ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x",
+ mask);
elink_bits_en(sc,
- NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);
+ NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,
+ mask);
}
}
-static uint8_t elink_format_ver(uint32_t num, uint8_t * str,
- uint16_t * len)
+static elink_status_t elink_format_ver(uint32_t num, uint8_t *str,
+ uint16_t *len)
{
uint8_t *str_ptr = str;
uint32_t mask = 0xf0000000;
@@ -5795,14 +7097,57 @@ static uint8_t elink_format_ver(uint32_t num, uint8_t * str,
return ELINK_STATUS_OK;
}
-static uint8_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
- uint8_t * str, uint16_t * len)
+
+static elink_status_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
+ uint8_t *str,
+ uint16_t *len)
{
str[0] = '\0';
(*len)--;
return ELINK_STATUS_OK;
}
+elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params,
+ uint8_t *version,
+ uint16_t len)
+{
+ struct bnx2x_softc *sc;
+ uint32_t spirom_ver = 0;
+ elink_status_t status = ELINK_STATUS_OK;
+ uint8_t *ver_p = version;
+ uint16_t remain_len = len;
+ if (version == NULL || params == NULL)
+ return ELINK_STATUS_ERROR;
+ sc = params->sc;
+
+ /* Extract first external phy*/
+ version[0] = '\0';
+ spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);
+
+ if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {
+ status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,
+ ver_p,
+ &remain_len);
+ ver_p += (len - remain_len);
+ }
+ if ((params->num_phys == ELINK_MAX_PHYS) &&
+ (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {
+ spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);
+ if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {
+ *ver_p = '/';
+ ver_p++;
+ remain_len--;
+ status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(
+ spirom_ver,
+ ver_p,
+ &remain_len);
+ ver_p = version + (len - remain_len);
+ }
+ }
+ *ver_p = '\0';
+ return status;
+}
+
static void elink_set_xgxs_loopback(struct elink_phy *phy,
struct elink_params *params)
{
@@ -5812,7 +7157,7 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,
if (phy->req_line_speed != ELINK_SPEED_1000) {
uint32_t md_devad = 0;
- PMD_DRV_LOG(DEBUG, sc, "XGXS 10G loopback enable");
+ ELINK_DEBUG_P0(sc, "XGXS 10G loopback enable");
if (!CHIP_IS_E3(sc)) {
/* Change the uni_phy_addr in the nig */
@@ -5826,7 +7171,8 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,
elink_cl45_write(sc, phy,
5,
(MDIO_REG_BANK_AER_BLOCK +
- (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800);
+ (MDIO_AER_BLOCK_AER_REG & 0xf)),
+ 0x2800);
elink_cl45_write(sc, phy,
5,
@@ -5844,22 +7190,21 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy,
}
} else {
uint16_t mii_ctrl;
- PMD_DRV_LOG(DEBUG, sc, "XGXS 1G loopback enable");
+ ELINK_DEBUG_P0(sc, "XGXS 1G loopback enable");
elink_cl45_read(sc, phy, 5,
(MDIO_REG_BANK_COMBO_IEEE0 +
- (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
+ (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
&mii_ctrl);
elink_cl45_write(sc, phy, 5,
(MDIO_REG_BANK_COMBO_IEEE0 +
- (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
+ (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
mii_ctrl |
MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
}
}
elink_status_t elink_set_led(struct elink_params *params,
- struct elink_vars *vars, uint8_t mode,
- uint32_t speed)
+ struct elink_vars *vars, uint8_t mode, uint32_t speed)
{
uint8_t port = params->port;
uint16_t hw_led_mode = params->hw_led_mode;
@@ -5868,16 +7213,21 @@ elink_status_t elink_set_led(struct elink_params *params,
uint32_t tmp;
uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "elink_set_led: port %x, mode %d", port, mode);
- PMD_DRV_LOG(DEBUG, sc,
- "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode);
+ ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d", port, mode);
+ ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x",
+ speed, hw_led_mode);
/* In case */
for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
if (params->phy[phy_idx].set_link_led) {
- params->phy[phy_idx].set_link_led(¶ms->phy[phy_idx],
- params, mode);
+ params->phy[phy_idx].set_link_led(
+ ¶ms->phy[phy_idx], params, mode);
}
}
+#ifdef ELINK_INCLUDE_EMUL
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)
+ return rc;
+#endif
switch (mode) {
case ELINK_LED_MODE_FRONT_PANEL_OFF:
@@ -5888,10 +7238,10 @@ elink_status_t elink_set_led(struct elink_params *params,
tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
if (params->phy[ELINK_EXT_PHY1].type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
+ PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE)
tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
- EMAC_LED_100MB_OVERRIDE |
- EMAC_LED_10MB_OVERRIDE);
+ EMAC_LED_100MB_OVERRIDE |
+ EMAC_LED_10MB_OVERRIDE);
else
tmp |= EMAC_LED_OVERRIDE;
@@ -5904,25 +7254,22 @@ elink_status_t elink_set_led(struct elink_params *params,
*/
if (!vars->link_up)
break;
- /* fall-through */
+ /* fallthrough */
case ELINK_LED_MODE_ON:
if (((params->phy[ELINK_EXT_PHY1].type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||
- (params->phy[ELINK_EXT_PHY1].type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||
+ (params->phy[ELINK_EXT_PHY1].type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&
CHIP_IS_E2(sc) && params->num_phys == 2) {
- /* This is a work-around for E2+8727 Configurations */
+ /* This is a work-around for E2 + 8727 Configurations */
if (mode == ELINK_LED_MODE_ON ||
- speed == ELINK_SPEED_10000) {
+ speed == ELINK_SPEED_10000){
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
- tmp =
- elink_cb_reg_read(sc,
- emac_base +
- EMAC_REG_EMAC_LED);
- elink_cb_reg_write(sc,
- emac_base +
+ tmp = elink_cb_reg_read(sc, emac_base +
+ EMAC_REG_EMAC_LED);
+ elink_cb_reg_write(sc, emac_base +
EMAC_REG_EMAC_LED,
(tmp | EMAC_LED_OVERRIDE));
/* Return here without enabling traffic
@@ -5938,22 +7285,23 @@ elink_status_t elink_set_led(struct elink_params *params,
* is up in CL73
*/
if ((!CHIP_IS_E3(sc)) ||
- (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON))
+ (CHIP_IS_E3(sc) &&
+ mode == ELINK_LED_MODE_ON))
REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
if (CHIP_IS_E1x(sc) ||
- CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON))
+ CHIP_IS_E2(sc) ||
+ (mode == ELINK_LED_MODE_ON))
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
else
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
hw_led_mode);
} else if ((params->phy[ELINK_EXT_PHY1].type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) &&
+ PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) &&
(mode == ELINK_LED_MODE_ON)) {
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
- tmp =
- elink_cb_reg_read(sc,
- emac_base + EMAC_REG_EMAC_LED);
+ tmp = elink_cb_reg_read(sc, emac_base +
+ EMAC_REG_EMAC_LED);
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
tmp | EMAC_LED_OVERRIDE |
EMAC_LED_1000MB_OVERRIDE);
@@ -5963,11 +7311,10 @@ elink_status_t elink_set_led(struct elink_params *params,
break;
} else {
uint32_t nig_led_mode = ((params->hw_led_mode <<
- SHARED_HW_CFG_LED_MODE_SHIFT)
- ==
- SHARED_HW_CFG_LED_EXTPHY2)
- ? (SHARED_HW_CFG_LED_PHY1 >>
- SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
+ SHARED_HW_CFG_LED_MODE_SHIFT) ==
+ SHARED_HW_CFG_LED_EXTPHY2) ?
+ (SHARED_HW_CFG_LED_PHY1 >>
+ SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
nig_led_mode);
}
@@ -5981,27 +7328,133 @@ elink_status_t elink_set_led(struct elink_params *params,
else
REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
LED_BLINK_RATE_VAL_E1X_E2);
- REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);
+ REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
+ port * 4, 1);
tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
- (tmp & (~EMAC_LED_OVERRIDE)));
+ (tmp & (~EMAC_LED_OVERRIDE)));
+ if (CHIP_IS_E1(sc) &&
+ ((speed == ELINK_SPEED_2500) ||
+ (speed == ELINK_SPEED_1000) ||
+ (speed == ELINK_SPEED_100) ||
+ (speed == ELINK_SPEED_10))) {
+ /* For speeds less than 10G LED scheme is different */
+ REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+ + port * 4, 1);
+ REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
+ port * 4, 0);
+ REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
+ port * 4, 1);
+ }
break;
default:
rc = ELINK_STATUS_ERROR;
- PMD_DRV_LOG(DEBUG, sc,
- "elink_set_led: Invalid led mode %d", mode);
+ ELINK_DEBUG_P1(sc, "elink_set_led: Invalid led mode %d",
+ mode);
break;
}
return rc;
}
+/* This function comes to reflect the actual link state read DIRECTLY from the
+ * HW
+ */
+elink_status_t elink_test_link(struct elink_params *params,
+ __rte_unused struct elink_vars *vars,
+ uint8_t is_serdes)
+{
+ struct bnx2x_softc *sc = params->sc;
+ uint16_t gp_status = 0, phy_index = 0;
+ uint8_t ext_phy_link_up = 0, serdes_phy_type;
+ struct elink_vars temp_vars;
+ struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
+#ifdef ELINK_INCLUDE_FPGA
+ if (CHIP_REV_IS_FPGA(sc))
+ return ELINK_STATUS_OK;
+#endif
+#ifdef ELINK_INCLUDE_EMUL
+ if (CHIP_REV_IS_EMUL(sc))
+ return ELINK_STATUS_OK;
+#endif
+
+ if (CHIP_IS_E3(sc)) {
+ uint16_t link_up;
+ if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)]
+ > ELINK_SPEED_10000) {
+ /* Check 20G link */
+ elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
+ 1, &link_up);
+ elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
+ 1, &link_up);
+ link_up &= (1 << 2);
+ } else {
+ /* Check 10G link and below*/
+ uint8_t lane = elink_get_warpcore_lane(int_phy, params);
+ elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_GP2_STATUS_GP_2_1,
+ &gp_status);
+ gp_status = ((gp_status >> 8) & 0xf) |
+ ((gp_status >> 12) & 0xf);
+ link_up = gp_status & (1 << lane);
+ }
+ if (!link_up)
+ return ELINK_STATUS_NO_LINK;
+ } else {
+ CL22_RD_OVER_CL45(sc, int_phy,
+ MDIO_REG_BANK_GP_STATUS,
+ MDIO_GP_STATUS_TOP_AN_STATUS1,
+ &gp_status);
+ /* Link is up only if both local phy and external phy are up */
+ if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
+ return ELINK_STATUS_NO_LINK;
+ }
+ /* In XGXS loopback mode, do not check external PHY */
+ if (params->loopback_mode == ELINK_LOOPBACK_XGXS)
+ return ELINK_STATUS_OK;
+
+ switch (params->num_phys) {
+ case 1:
+ /* No external PHY */
+ return ELINK_STATUS_OK;
+ case 2:
+ ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(
+ ¶ms->phy[ELINK_EXT_PHY1],
+ params, &temp_vars);
+ break;
+ case 3: /* Dual Media */
+ for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
+ phy_index++) {
+ serdes_phy_type = ((params->phy[phy_index].media_type ==
+ ELINK_ETH_PHY_SFPP_10G_FIBER) ||
+ (params->phy[phy_index].media_type ==
+ ELINK_ETH_PHY_SFP_1G_FIBER) ||
+ (params->phy[phy_index].media_type ==
+ ELINK_ETH_PHY_XFP_FIBER) ||
+ (params->phy[phy_index].media_type ==
+ ELINK_ETH_PHY_DA_TWINAX));
+
+ if (is_serdes != serdes_phy_type)
+ continue;
+ if (params->phy[phy_index].read_status) {
+ ext_phy_link_up |=
+ params->phy[phy_index].read_status(
+ ¶ms->phy[phy_index],
+ params, &temp_vars);
+ }
+ }
+ break;
+ }
+ if (ext_phy_link_up)
+ return ELINK_STATUS_OK;
+ return ELINK_STATUS_NO_LINK;
+}
+
static elink_status_t elink_link_initialize(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
- elink_status_t rc = ELINK_STATUS_OK;
uint8_t phy_index, non_ext_phy;
struct bnx2x_softc *sc = params->sc;
/* In case of external phy existence, the line speed would be the
@@ -6026,11 +7479,12 @@ static elink_status_t elink_link_initialize(struct elink_params *params,
(params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
- (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)))
+ (CHIP_IS_E1x(sc) ||
+ CHIP_IS_E2(sc)))
elink_set_parallel_detection(phy, params);
if (params->phy[ELINK_INT_PHY].config_init)
- params->phy[ELINK_INT_PHY].config_init(phy,
- params, vars);
+ params->phy[ELINK_INT_PHY].config_init(phy, params,
+ vars);
}
/* Re-read this value in case it was changed inside config_init due to
@@ -6038,14 +7492,14 @@ static elink_status_t elink_link_initialize(struct elink_params *params,
*/
vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
- /* Init external phy */
+ /* Init external phy*/
if (non_ext_phy) {
if (params->phy[ELINK_INT_PHY].supported &
ELINK_SUPPORTED_FIBRE)
vars->link_status |= LINK_STATUS_SERDES_LINK;
} else {
for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
/* No need to initialize second phy in case of first
* phy only selection. In case of second phy, we do
* need to initialize the first phy, since they are
@@ -6058,13 +7512,13 @@ static elink_status_t elink_link_initialize(struct elink_params *params,
if (phy_index == ELINK_EXT_PHY2 &&
(elink_phy_selection(params) ==
PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
- PMD_DRV_LOG(DEBUG, sc,
- "Not initializing second phy");
+ ELINK_DEBUG_P0(sc,
+ "Not initializing second phy");
continue;
}
- params->phy[phy_index].config_init(¶ms->
- phy[phy_index],
- params, vars);
+ params->phy[phy_index].config_init(
+ ¶ms->phy[phy_index],
+ params, vars);
}
}
/* Reset the interrupt indication after phy was initialized */
@@ -6074,7 +7528,7 @@ static elink_status_t elink_link_initialize(struct elink_params *params,
ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
ELINK_NIG_MASK_MI_INT));
- return rc;
+ return ELINK_STATUS_OK;
}
static void elink_int_link_reset(__rte_unused struct elink_phy *phy,
@@ -6096,19 +7550,21 @@ static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,
else
gpio_port = params->port;
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ gpio_port);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
- PMD_DRV_LOG(DEBUG, sc, "reset external PHY");
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ gpio_port);
+ ELINK_DEBUG_P0(sc, "reset external PHY");
}
static elink_status_t elink_update_link_down(struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port = params->port;
- PMD_DRV_LOG(DEBUG, sc, "Port %x: Link is down", port);
+ ELINK_DEBUG_P1(sc, "Port %x: Link is down", port);
elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
/* Indicate no mac active */
@@ -6128,8 +7584,9 @@ static elink_status_t elink_update_link_down(struct elink_params *params,
DELAY(1000 * 10);
/* Reset BigMac/Xmac */
- if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))
- elink_set_bmac_rx(sc, params->port, 0);
+ if (CHIP_IS_E1x(sc) ||
+ CHIP_IS_E2(sc))
+ elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
if (CHIP_IS_E3(sc)) {
/* Prevent LPI Generation by chip */
@@ -6149,8 +7606,8 @@ static elink_status_t elink_update_link_down(struct elink_params *params,
}
static elink_status_t elink_update_link_up(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t link_10g)
+ struct elink_vars *vars,
+ uint8_t link_10g)
{
struct bnx2x_softc *sc = params->sc;
uint8_t phy_idx, port = params->port;
@@ -6161,15 +7618,17 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
- vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
+ vars->link_status |=
+ LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
- vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
+ vars->link_status |=
+ LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
if (USES_WARPCORE(sc)) {
if (link_10g) {
if (elink_xmac_enable(params, vars, 0) ==
ELINK_STATUS_NO_LINK) {
- PMD_DRV_LOG(DEBUG, sc, "Found errors on XMAC");
+ ELINK_DEBUG_P0(sc, "Found errors on XMAC");
vars->link_up = 0;
vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
vars->link_status &= ~LINK_STATUS_LINK_UP;
@@ -6181,7 +7640,7 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
(vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
- PMD_DRV_LOG(DEBUG, sc, "Enabling LPI assertion");
+ ELINK_DEBUG_P0(sc, "Enabling LPI assertion");
REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
(params->port << 2), 1);
REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
@@ -6189,11 +7648,12 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
(params->port << 2), 0xfc20);
}
}
- if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) {
+ if ((CHIP_IS_E1x(sc) ||
+ CHIP_IS_E2(sc))) {
if (link_10g) {
if (elink_bmac_enable(params, vars, 0, 1) ==
ELINK_STATUS_NO_LINK) {
- PMD_DRV_LOG(DEBUG, sc, "Found errors on BMAC");
+ ELINK_DEBUG_P0(sc, "Found errors on BMAC");
vars->link_up = 0;
vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
vars->link_status &= ~LINK_STATUS_LINK_UP;
@@ -6236,6 +7696,24 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
return rc;
}
+static void elink_chng_link_count(struct elink_params *params, uint8_t clear)
+{
+ struct bnx2x_softc *sc = params->sc;
+ uint32_t addr, val;
+
+ /* Verify the link_change_count is supported by the MFW */
+ if (!(SHMEM2_HAS(sc, link_change_count)))
+ return;
+
+ addr = params->shmem2_base +
+ offsetof(struct shmem2_region, link_change_count[params->port]);
+ if (clear)
+ val = 0;
+ else
+ val = REG_RD(sc, addr) + 1;
+ REG_WR(sc, addr, val);
+}
+
/* The elink_link_update function should be called upon link
* interrupt.
* Link is considered up as follows:
@@ -6248,24 +7726,24 @@ static elink_status_t elink_update_link_up(struct elink_params *params,
* external phy needs to be up, and at least one of the 2
* external phy link must be up.
*/
-elink_status_t elink_link_update(struct elink_params * params,
- struct elink_vars * vars)
+elink_status_t elink_link_update(struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
struct elink_vars phy_vars[ELINK_MAX_PHYS];
uint8_t port = params->port;
uint8_t link_10g_plus, phy_index;
+ uint32_t prev_link_status = vars->link_status;
uint8_t ext_phy_link_up = 0, cur_link_up;
elink_status_t rc = ELINK_STATUS_OK;
- __rte_unused uint8_t is_mi_int = 0;
uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
uint8_t active_external_phy = ELINK_INT_PHY;
vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
phy_vars[phy_index].flow_ctrl = 0;
- phy_vars[phy_index].link_status = ETH_LINK_DOWN;
+ phy_vars[phy_index].link_status = 0;
phy_vars[phy_index].line_speed = 0;
phy_vars[phy_index].duplex = DUPLEX_FULL;
phy_vars[phy_index].phy_link_up = 0;
@@ -6278,21 +7756,18 @@ elink_status_t elink_link_update(struct elink_params * params,
if (USES_WARPCORE(sc))
elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
- PMD_DRV_LOG(DEBUG, sc, "port %x, XGXS?%x, int_status 0x%x",
- port, (vars->phy_flags & PHY_XGXS_FLAG),
- REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
+ ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x",
+ port, (vars->phy_flags & PHY_XGXS_FLAG),
+ REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
- is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
- port * 0x18) > 0);
- PMD_DRV_LOG(DEBUG, sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
- REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
- is_mi_int,
- REG_RD(sc,
- NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
+ ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
+ REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
+ REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18) > 0,
+ REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
- PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
- REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
- REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
+ ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x",
+ REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
+ REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
/* Disable emac */
if (!CHIP_IS_E3(sc))
@@ -6306,7 +7781,7 @@ elink_status_t elink_link_update(struct elink_params * params,
* speed/duplex result
*/
for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
struct elink_phy *phy = ¶ms->phy[phy_index];
if (!phy->read_status)
continue;
@@ -6314,11 +7789,11 @@ elink_status_t elink_link_update(struct elink_params * params,
cur_link_up = phy->read_status(phy, params,
&phy_vars[phy_index]);
if (cur_link_up) {
- PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is up",
- phy_index);
+ ELINK_DEBUG_P1(sc, "phy in index %d link is up",
+ phy_index);
} else {
- PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is down",
- phy_index);
+ ELINK_DEBUG_P1(sc, "phy in index %d link is down",
+ phy_index);
continue;
}
@@ -6329,30 +7804,30 @@ elink_status_t elink_link_update(struct elink_params * params,
switch (elink_phy_selection(params)) {
case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
- /* In this option, the first PHY makes sure to pass the
- * traffic through itself only.
- * Its not clear how to reset the link on the second phy
- */
+ /* In this option, the first PHY makes sure to pass the
+ * traffic through itself only.
+ * Its not clear how to reset the link on the second phy
+ */
active_external_phy = ELINK_EXT_PHY1;
break;
case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
- /* In this option, the first PHY makes sure to pass the
- * traffic through the second PHY.
- */
+ /* In this option, the first PHY makes sure to pass the
+ * traffic through the second PHY.
+ */
active_external_phy = ELINK_EXT_PHY2;
break;
default:
- /* Link indication on both PHYs with the following cases
- * is invalid:
- * - FIRST_PHY means that second phy wasn't initialized,
- * hence its link is expected to be down
- * - SECOND_PHY means that first phy should not be able
- * to link up by itself (using configuration)
- * - DEFAULT should be overridden during initialization
- */
- PMD_DRV_LOG(DEBUG, sc, "Invalid link indication"
- "mpc=0x%x. DISABLING LINK !!!",
- params->multi_phy_config);
+ /* Link indication on both PHYs with the following cases
+ * is invalid:
+ * - FIRST_PHY means that second phy wasn't initialized,
+ * hence its link is expected to be down
+ * - SECOND_PHY means that first phy should not be able
+ * to link up by itself (using configuration)
+ * - DEFAULT should be overridden during initialiazation
+ */
+ ELINK_DEBUG_P1(sc, "Invalid link indication"
+ " mpc=0x%x. DISABLING LINK !!!",
+ params->multi_phy_config);
ext_phy_link_up = 0;
break;
}
@@ -6366,9 +7841,9 @@ elink_status_t elink_link_update(struct elink_params * params,
* external phy
*/
if (params->phy[ELINK_INT_PHY].read_status)
- params->phy[ELINK_INT_PHY].read_status(¶ms->
- phy[ELINK_INT_PHY],
- params, vars);
+ params->phy[ELINK_INT_PHY].read_status(
+ ¶ms->phy[ELINK_INT_PHY],
+ params, vars);
/* The INT_PHY flow control reside in the vars. This include the
* case where the speed or flow control are not set to AUTO.
* Otherwise, the active external phy flow control result is set
@@ -6388,11 +7863,11 @@ elink_status_t elink_link_update(struct elink_params * params,
*/
if (active_external_phy == ELINK_EXT_PHY1) {
if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
- PMD_DRV_LOG(DEBUG, sc, "Disabling TX on EXT_PHY2");
- params->phy[ELINK_EXT_PHY2].
- phy_specific_func(¶ms->
- phy[ELINK_EXT_PHY2],
- params, ELINK_DISABLE_TX);
+ ELINK_DEBUG_P0(sc,
+ "Disabling TX on EXT_PHY2");
+ params->phy[ELINK_EXT_PHY2].phy_specific_func(
+ ¶ms->phy[ELINK_EXT_PHY2],
+ params, ELINK_DISABLE_TX);
}
}
@@ -6406,12 +7881,27 @@ elink_status_t elink_link_update(struct elink_params * params,
vars->eee_status = phy_vars[active_external_phy].eee_status;
- PMD_DRV_LOG(DEBUG, sc, "Active external phy selected: %x",
- active_external_phy);
- }
+ ELINK_DEBUG_P1(sc, "Active external phy selected: %x",
+ active_external_phy);
+ }
+
+ ELINK_DEBUG_P3(sc, "vars : phy_flags = %x, mac_type = %x, phy_link_up = %x",
+ vars->phy_flags, vars->mac_type, vars->phy_link_up);
+ ELINK_DEBUG_P3(sc, "vars : link_up = %x, line_speed = %x, duplex = %x",
+ vars->link_up, vars->line_speed, vars->duplex);
+ ELINK_DEBUG_P3(sc, "vars : flow_ctrl = %x, ieee_fc = %x, link_status = %x",
+ vars->flow_ctrl, vars->ieee_fc, vars->link_status);
+ ELINK_DEBUG_P3(sc, "vars : eee_status = %x, fault_detected = %x, check_kr2_recovery_cnt = %x",
+ vars->eee_status, vars->fault_detected,
+ vars->check_kr2_recovery_cnt);
+ ELINK_DEBUG_P3(sc, "vars : periodic_flags = %x, aeu_int_mask = %x, rx_tx_asic_rst = %x",
+ vars->periodic_flags, vars->aeu_int_mask,
+ vars->rx_tx_asic_rst);
+ ELINK_DEBUG_P2(sc, "vars : turn_to_run_wc_rt = %x, rsrv2 = %x",
+ vars->turn_to_run_wc_rt, vars->rsrv2);
for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
if (params->phy[phy_index].flags &
ELINK_FLAGS_REARM_LATCH_SIGNAL) {
elink_rearm_latch_signal(sc, port,
@@ -6420,9 +7910,9 @@ elink_status_t elink_link_update(struct elink_params * params,
break;
}
}
- PMD_DRV_LOG(DEBUG, sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
- " ext_phy_line_speed = %d", vars->flow_ctrl,
- vars->link_status, ext_phy_line_speed);
+ ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
+ " ext_phy_line_speed = %d", vars->flow_ctrl,
+ vars->link_status, ext_phy_line_speed);
/* Upon link speed change set the NIG into drain mode. Comes to
* deals with possible FIFO glitch due to clk change when speed
* is decreased without link down indicator
@@ -6431,15 +7921,15 @@ elink_status_t elink_link_update(struct elink_params * params,
if (vars->phy_link_up) {
if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
(ext_phy_line_speed != vars->line_speed)) {
- PMD_DRV_LOG(DEBUG, sc, "Internal link speed %d is"
- " different than the external"
- " link speed %d", vars->line_speed,
- ext_phy_line_speed);
+ ELINK_DEBUG_P2(sc, "Internal link speed %d is"
+ " different than the external"
+ " link speed %d", vars->line_speed,
+ ext_phy_line_speed);
vars->phy_link_up = 0;
+ ELINK_DEBUG_P0(sc, "phy_link_up set to 0");
} else if (prev_line_speed != vars->line_speed) {
- REG_WR(sc,
- NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4,
- 0);
+ REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE +
+ params->port * 4, 0);
DELAY(1000 * 1);
}
}
@@ -6457,11 +7947,11 @@ elink_status_t elink_link_update(struct elink_params * params,
* initialize it
*/
if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
- PMD_DRV_LOG(DEBUG, sc, "ext_phy_link_up = %d, int_link_up = %d,"
- " init_preceding = %d", ext_phy_link_up,
- vars->phy_link_up,
- params->phy[ELINK_EXT_PHY1].flags &
- ELINK_FLAGS_INIT_XGXS_FIRST);
+ ELINK_DEBUG_P3(sc, "ext_phy_link_up = %d, int_link_up = %d,"
+ " init_preceding = %d", ext_phy_link_up,
+ vars->phy_link_up,
+ params->phy[ELINK_EXT_PHY1].flags &
+ ELINK_FLAGS_INIT_XGXS_FIRST);
if (!(params->phy[ELINK_EXT_PHY1].flags &
ELINK_FLAGS_INIT_XGXS_FIRST)
&& ext_phy_link_up && !vars->phy_link_up) {
@@ -6472,11 +7962,9 @@ elink_status_t elink_link_update(struct elink_params * params,
vars->phy_flags &= ~PHY_SGMII_FLAG;
if (params->phy[ELINK_INT_PHY].config_init)
- params->phy[ELINK_INT_PHY].config_init(¶ms->
- phy
- [ELINK_INT_PHY],
- params,
- vars);
+ params->phy[ELINK_INT_PHY].config_init(
+ ¶ms->phy[ELINK_INT_PHY], params,
+ vars);
}
}
/* Link is up only if both local phy and external phy (in case of
@@ -6487,6 +7975,11 @@ elink_status_t elink_link_update(struct elink_params * params,
ELINK_SINGLE_MEDIA_DIRECT(params)) &&
(phy_vars[active_external_phy].fault_detected == 0));
+ if (vars->link_up)
+ ELINK_DEBUG_P0(sc, "local phy and external phy are up");
+ else
+ ELINK_DEBUG_P0(sc, "either local phy or external phy or both are down");
+
/* Update the PFC configuration in case it was changed */
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
vars->link_status |= LINK_STATUS_PFC_ENABLED;
@@ -6498,9 +7991,12 @@ elink_status_t elink_link_update(struct elink_params * params,
else
rc = elink_update_link_down(params, vars);
+ if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
+ elink_chng_link_count(params, 0);
+
/* Update MCP link status was changed */
- if (params->
- feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
return rc;
@@ -6509,28 +8005,28 @@ elink_status_t elink_link_update(struct elink_params * params,
/*****************************************************************************/
/* External Phy section */
/*****************************************************************************/
-static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)
+void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)
{
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
DELAY(1000 * 1);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
}
-static void elink_save_spirom_version(struct bnx2x_softc *sc,
- __rte_unused uint8_t port,
+static void elink_save_spirom_version(struct bnx2x_softc *sc, uint8_t port,
uint32_t spirom_ver, uint32_t ver_addr)
{
- PMD_DRV_LOG(DEBUG, sc, "FW version 0x%x:0x%x for port %d",
- (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);
+ ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d",
+ (uint16_t)(spirom_ver >> 16), (uint16_t)spirom_ver, port);
if (ver_addr)
REG_WR(sc, ver_addr, spirom_ver);
}
static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t port)
+ struct elink_phy *phy,
+ uint8_t port)
{
uint16_t fw_ver1, fw_ver2;
@@ -6538,18 +8034,21 @@ static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,
MDIO_PMA_REG_ROM_VER1, &fw_ver1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
MDIO_PMA_REG_ROM_VER2, &fw_ver2);
- elink_save_spirom_version(sc, port,
- (uint32_t) (fw_ver1 << 16 | fw_ver2),
+ elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1 << 16 | fw_ver2),
phy->ver_addr);
}
static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- struct elink_vars *vars)
+ struct elink_phy *phy,
+ struct elink_vars *vars)
{
uint16_t val;
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_STATUS, &val);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_STATUS, &val);
if (val & (1 << 5))
vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
if ((val & (1 << 0)) == 0)
@@ -6573,8 +8072,8 @@ static void elink_8073_resolve_fc(struct elink_phy *phy,
if (elink_ext_phy_resolve_fc(phy, params, vars) &&
(vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
uint16_t pause_result;
- uint16_t ld_pause; /* local */
- uint16_t lp_pause; /* link partner */
+ uint16_t ld_pause; /* local */
+ uint16_t lp_pause; /* link partner */
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_CL37_FC_LD, &ld_pause);
@@ -6587,31 +8086,35 @@ static void elink_8073_resolve_fc(struct elink_phy *phy,
pause_result |= (lp_pause &
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
- elink_pause_resolve(vars, pause_result);
- PMD_DRV_LOG(DEBUG, sc, "Ext PHY CL37 pause result 0x%x",
- pause_result);
+ elink_pause_resolve(phy, params, vars, pause_result);
+ ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x",
+ pause_result);
}
}
-
static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- uint8_t port)
+ struct elink_phy *phy,
+ uint8_t port)
{
uint32_t count = 0;
- uint16_t fw_ver1 = 0, fw_msgout;
+ uint16_t fw_ver1, fw_msgout;
elink_status_t rc = ELINK_STATUS_OK;
/* Boot port from external ROM */
/* EDC grst */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_GEN_CTRL,
+ 0x0001);
/* Ucode reboot and rst */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_GEN_CTRL,
+ 0x008c);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_MISC_CTRL1, 0x0001);
/* Reset internal microprocessor */
elink_cl45_write(sc, phy,
@@ -6632,10 +8135,10 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
do {
count++;
if (count > 300) {
- PMD_DRV_LOG(DEBUG, sc,
- "elink_8073_8727_external_rom_boot port %x:"
- "Download failed. fw version = 0x%x",
- port, fw_ver1);
+ ELINK_DEBUG_P2(sc,
+ "elink_8073_8727_external_rom_boot port %x:"
+ "Download failed. fw version = 0x%x",
+ port, fw_ver1);
rc = ELINK_STATUS_ERROR;
break;
}
@@ -6649,17 +8152,19 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
DELAY(1000 * 1);
} while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
- ((fw_msgout & 0xff) != 0x03 && (phy->type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));
+ ((fw_msgout & 0xff) != 0x03 && (phy->type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));
/* Clear ser_boot_ctl bit */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_MISC_CTRL1, 0x0000);
elink_save_bnx2x_spirom_ver(sc, phy, port);
- PMD_DRV_LOG(DEBUG, sc,
- "elink_8073_8727_external_rom_boot port %x:"
- "Download complete. fw version = 0x%x", port, fw_ver1);
+ ELINK_DEBUG_P2(sc,
+ "elink_8073_8727_external_rom_boot port %x:"
+ "Download complete. fw version = 0x%x",
+ port, fw_ver1);
return rc;
}
@@ -6673,22 +8178,25 @@ static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc,
/* This is only required for 8073A1, version 102 only */
uint16_t val;
- /* Read 8073 HW revision */
+ /* Read 8073 HW revision*/
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8073_CHIP_REV, &val);
if (val != 1) {
/* No need to workaround in 8073 A1 */
return ELINK_STATUS_OK;
}
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_ROM_VER2, &val);
/* SNR should be applied only for version 0x102 */
if (val != 0x102)
return ELINK_STATUS_OK;
- return ELINK_STATUS_ERROR;
+ return 1;
}
static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
@@ -6697,7 +8205,8 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
uint16_t val, cnt, cnt1;
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8073_CHIP_REV, &val);
if (val > 0) {
/* No need to workaround in 8073 A1 */
@@ -6712,16 +8221,17 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
for (cnt = 0; cnt < 1000; cnt++) {
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);
- /* If bit [14] = 0 or bit [13] = 0, continue on with
- * system initialization (XAUI work-around not required, as
- * these bits indicate 2.5G or 1G link up).
- */
+ MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
+ &val);
+ /* If bit [14] = 0 or bit [13] = 0, continue on with
+ * system initialization (XAUI work-around not required, as
+ * these bits indicate 2.5G or 1G link up).
+ */
if (!(val & (1 << 14)) || !(val & (1 << 13))) {
- PMD_DRV_LOG(DEBUG, sc, "XAUI work-around not required");
+ ELINK_DEBUG_P0(sc, "XAUI work-around not required");
return ELINK_STATUS_OK;
} else if (!(val & (1 << 15))) {
- PMD_DRV_LOG(DEBUG, sc, "bit 15 went off");
+ ELINK_DEBUG_P0(sc, "bit 15 went off");
/* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
* MSB (bit15) goes to 1 (indicating that the XAUI
* workaround has completed), then continue on with
@@ -6729,12 +8239,11 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
*/
for (cnt1 = 0; cnt1 < 1000; cnt1++) {
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8073_XAUI_WA,
- &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8073_XAUI_WA, &val);
if (val & (1 << 15)) {
- PMD_DRV_LOG(DEBUG, sc,
- "XAUI workaround has completed");
+ ELINK_DEBUG_P0(sc,
+ "XAUI workaround has completed");
return ELINK_STATUS_OK;
}
DELAY(1000 * 3);
@@ -6743,19 +8252,21 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
}
DELAY(1000 * 3);
}
- PMD_DRV_LOG(DEBUG, sc, "Warning: XAUI work-around timeout !!!");
+ ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!");
return ELINK_STATUS_ERROR;
}
static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy)
{
/* Force KR or KX */
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000);
- elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
+ elink_cl45_write(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
}
static void elink_8073_set_pause_cl37(struct elink_params *params,
@@ -6771,21 +8282,22 @@ static void elink_8073_set_pause_cl37(struct elink_params *params,
/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
- cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
+ cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
}
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
- cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+ cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
}
if ((vars->ieee_fc &
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
}
- PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize cl37 0x%x", cl37_val);
+ ELINK_DEBUG_P1(sc,
+ "Ext phy AN advertize cl37 0x%x", cl37_val);
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
@@ -6803,31 +8315,31 @@ static void elink_8073_specific_func(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
(1 << 2));
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
- 0x0004);
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
break;
}
}
static uint8_t elink_8073_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val = 0, tmp1;
uint8_t gpio_port;
- PMD_DRV_LOG(DEBUG, sc, "Init 8073");
+ ELINK_DEBUG_P0(sc, "Init 8073");
if (CHIP_IS_E2(sc))
gpio_port = SC_PATH(sc);
else
gpio_port = params->port;
- /* Restore normal power mode */
+ /* Restore normal power mode*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
elink_8073_set_pause_cl37(params, phy, vars);
@@ -6835,14 +8347,15 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
- PMD_DRV_LOG(DEBUG, sc, "Before rom RX_ALARM(port1): 0x%x", tmp1);
+ ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x", tmp1);
/* Swap polarity if required - Must be done only in non-1G mode */
if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
/* Configure the 8073 to swap _P and _N of the KR lines */
- PMD_DRV_LOG(DEBUG, sc, "Swapping polarity for the 8073");
+ ELINK_DEBUG_P0(sc, "Swapping polarity for the 8073");
/* 10G Rx/Tx and 1G Tx signal polarity swap */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
@@ -6853,31 +8366,33 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
(val | (3 << 9)));
}
+
/* Enable CL37 BAM */
if (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- default_cfg)) &
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg)) &
PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
elink_cl45_read(sc, phy,
- MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8073_BAM, &val);
elink_cl45_write(sc, phy,
- MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);
- PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8073_BAM, val | 1);
+ ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR");
}
if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
elink_807x_force_10G(sc, phy);
- PMD_DRV_LOG(DEBUG, sc, "Forced speed 10G on 807X");
+ ELINK_DEBUG_P0(sc, "Forced speed 10G on 807X");
return ELINK_STATUS_OK;
} else {
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
}
if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
if (phy->req_line_speed == ELINK_SPEED_10000) {
val = (1 << 7);
- } else if (phy->req_line_speed == ELINK_SPEED_2500) {
+ } else if (phy->req_line_speed == ELINK_SPEED_2500) {
val = (1 << 5);
/* Note that 2.5G works only when used with 1G
* advertisement
@@ -6886,15 +8401,16 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
val = (1 << 5);
} else {
val = 0;
- if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
+ if (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
val |= (1 << 7);
/* Note that 2.5G works only when used with 1G advertisement */
if (phy->speed_cap_mask &
- (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
- PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
+ (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
val |= (1 << 5);
- PMD_DRV_LOG(DEBUG, sc, "807x autoneg val = 0x%x", val);
+ ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x", val);
}
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
@@ -6908,13 +8424,13 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
&phy_ver);
- PMD_DRV_LOG(DEBUG, sc, "Add 2.5G");
+ ELINK_DEBUG_P0(sc, "Add 2.5G");
if (phy_ver > 0)
tmp1 |= 1;
else
tmp1 &= 0xfffe;
} else {
- PMD_DRV_LOG(DEBUG, sc, "Disable 2.5G");
+ ELINK_DEBUG_P0(sc, "Disable 2.5G");
tmp1 &= 0xfffe;
}
@@ -6948,14 +8464,14 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy,
/* Restart autoneg */
DELAY(1000 * 500);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
- PMD_DRV_LOG(DEBUG, sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
- ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
+ ELINK_DEBUG_P2(sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
+ ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
return ELINK_STATUS_OK;
}
static uint8_t elink_8073_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t link_up = 0;
@@ -6963,33 +8479,41 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
uint16_t link_status = 0;
uint16_t an1000_status = 0;
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8703 LASI status 0x%x", val1);
+ ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x", val1);
/* Clear the interrupt LASI status register */
- elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "807x PCS status 0x%x->0x%x", val2, val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
+ ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x", val2, val1);
/* Clear MSG-OUT */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
/* Check the LASI */
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
- PMD_DRV_LOG(DEBUG, sc, "KR 0x9003 0x%x", val2);
+ ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x", val2);
/* Check the link status */
- elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
- PMD_DRV_LOG(DEBUG, sc, "KR PCS status 0x%x", val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
+ ELINK_DEBUG_P1(sc, "KR PCS status 0x%x", val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
link_up = ((val1 & 4) == 4);
- PMD_DRV_LOG(DEBUG, sc, "PMA_REG_STATUS=0x%x", val1);
+ ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x", val1);
- if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {
+ if (link_up &&
+ ((phy->req_line_speed != ELINK_SPEED_10000))) {
if (elink_8073_xaui_wa(sc, phy) != 0)
return 0;
}
@@ -6999,10 +8523,12 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
/* Check the link status on 1.1.2 */
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "KR PMA status 0x%x->0x%x,"
- "an_link_status=0x%x", val2, val1, an1000_status);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
+ ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x,"
+ "an_link_status=0x%x", val2, val1, an1000_status);
link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));
if (link_up && elink_8073_is_snr_needed(sc, phy)) {
@@ -7027,27 +8553,28 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_10000;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 10G",
+ params->port);
} else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_2500;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 2.5G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G",
+ params->port);
} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_1000;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 1G",
+ params->port);
} else {
link_up = 0;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link is down",
+ params->port);
}
if (link_up) {
/* Swap polarity if required */
- if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
+ if (params->lane_config &
+ PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
/* Configure the 8073 to swap P and N of the KR lines */
elink_cl45_read(sc, phy,
MDIO_XS_DEVAD,
@@ -7056,15 +8583,16 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
* when it`s in 10G mode.
*/
if (vars->line_speed == ELINK_SPEED_1000) {
- PMD_DRV_LOG(DEBUG, sc, "Swapping 1G polarity for"
- "the 8073");
+ ELINK_DEBUG_P0(sc, "Swapping 1G polarity for"
+ " the 8073");
val1 |= (1 << 3);
} else
val1 &= ~(1 << 3);
elink_cl45_write(sc, phy,
MDIO_XS_DEVAD,
- MDIO_XS_REG_8073_RX_CTRL_PCIE, val1);
+ MDIO_XS_REG_8073_RX_CTRL_PCIE,
+ val1);
}
elink_ext_phy_10G_an_resolve(sc, phy, vars);
elink_8073_resolve_fc(phy, params, vars);
@@ -7077,10 +8605,10 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy,
if (val1 & (1 << 5))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
if (val1 & (1 << 7))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
}
return link_up;
@@ -7095,25 +8623,25 @@ static void elink_8073_link_reset(__rte_unused struct elink_phy *phy,
gpio_port = SC_PATH(sc);
else
gpio_port = params->port;
- PMD_DRV_LOG(DEBUG, sc, "Setting 8073 port %d into low power mode",
- gpio_port);
+ ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode",
+ gpio_port);
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ gpio_port);
}
/******************************************************************/
/* BNX2X8705 PHY SECTION */
/******************************************************************/
static uint8_t elink_8705_config_init(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars
- *vars)
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "init 8705");
- /* Restore normal power mode */
+ ELINK_DEBUG_P0(sc, "init 8705");
+ /* Restore normal power mode*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
/* HW reset */
elink_ext_phy_hw_reset(sc, params->port);
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
@@ -7125,36 +8653,40 @@ static uint8_t elink_8705_config_init(struct elink_phy *phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
- elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
+ elink_cl45_write(sc, phy,
+ MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
/* BNX2X8705 doesn't have microcode, hence the 0 */
elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
return ELINK_STATUS_OK;
}
static uint8_t elink_8705_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint8_t link_up = 0;
uint16_t val1, rx_sd;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "read status 8705");
+ ELINK_DEBUG_P0(sc, "read status 8705");
elink_cl45_read(sc, phy,
- MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
+ MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
+ ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x", val1);
elink_cl45_read(sc, phy,
- MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
+ MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
+ ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x", val1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, 0xc809, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, 0xc809, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8705 1.c809 val=0x%x", val1);
- link_up = ((rx_sd & 0x1) && (val1 & (1 << 9))
- && ((val1 & (1 << 8)) == 0));
+ ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x", val1);
+ link_up = ((rx_sd & 0x1) && (val1 & (1 << 9)) &&
+ ((val1 & (1 << 8)) == 0));
if (link_up) {
vars->line_speed = ELINK_SPEED_10000;
elink_ext_phy_resolve_fc(phy, params, vars);
@@ -7175,17 +8707,17 @@ static void elink_set_disable_pmd_transmit(struct elink_params *params,
*/
if (pmd_dis) {
if (params->feature_config_flags &
- ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
- PMD_DRV_LOG(DEBUG, sc, "Disabling PMD transmitter");
+ ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
+ ELINK_DEBUG_P0(sc, "Disabling PMD transmitter");
} else {
- PMD_DRV_LOG(DEBUG, sc, "NOT disabling PMD transmitter");
+ ELINK_DEBUG_P0(sc, "NOT disabling PMD transmitter");
return;
}
- } else {
- PMD_DRV_LOG(DEBUG, sc, "Enabling PMD transmitter");
- }
+ } else
+ ELINK_DEBUG_P0(sc, "Enabling PMD transmitter");
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_TX_DISABLE, pmd_dis);
}
static uint8_t elink_get_gpio_port(struct elink_params *params)
@@ -7193,37 +8725,38 @@ static uint8_t elink_get_gpio_port(struct elink_params *params)
uint8_t gpio_port;
uint32_t swap_val, swap_override;
struct bnx2x_softc *sc = params->sc;
- if (CHIP_IS_E2(sc)) {
+ if (CHIP_IS_E2(sc))
gpio_port = SC_PATH(sc);
- } else {
+ else
gpio_port = params->port;
- }
swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
return gpio_port ^ (swap_val && swap_override);
}
static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
- struct elink_phy *phy, uint8_t tx_en)
+ struct elink_phy *phy,
+ uint8_t tx_en)
{
uint16_t val;
uint8_t port = params->port;
struct bnx2x_softc *sc = params->sc;
uint32_t tx_en_mode;
- /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */
+ /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
tx_en_mode = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
dev_info.port_hw_config[port].sfp_ctrl)) &
- PORT_HW_CFG_TX_LASER_MASK;
- PMD_DRV_LOG(DEBUG, sc, "Setting transmitter tx_en=%x for port %x "
- "mode = %x", tx_en, port, tx_en_mode);
+ PORT_HW_CFG_TX_LASER_MASK;
+ ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x "
+ "mode = %x", tx_en, port, tx_en_mode);
switch (tx_en_mode) {
case PORT_HW_CFG_TX_LASER_MDIO:
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, &val);
+ MDIO_PMA_REG_PHY_IDENTIFIER,
+ &val);
if (tx_en)
val &= ~(1 << 15);
@@ -7232,37 +8765,38 @@ static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, val);
- break;
+ MDIO_PMA_REG_PHY_IDENTIFIER,
+ val);
+ break;
case PORT_HW_CFG_TX_LASER_GPIO0:
case PORT_HW_CFG_TX_LASER_GPIO1:
case PORT_HW_CFG_TX_LASER_GPIO2:
case PORT_HW_CFG_TX_LASER_GPIO3:
- {
- uint16_t gpio_pin;
- uint8_t gpio_port, gpio_mode;
- if (tx_en)
- gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
- else
- gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
+ {
+ uint16_t gpio_pin;
+ uint8_t gpio_port, gpio_mode;
+ if (tx_en)
+ gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
+ else
+ gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
- gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
- gpio_port = elink_get_gpio_port(params);
- elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
- break;
- }
+ gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
+ gpio_port = elink_get_gpio_port(params);
+ elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
+ break;
+ }
default:
- PMD_DRV_LOG(DEBUG, sc,
- "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
+ ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
break;
}
}
static void elink_sfp_set_transmitter(struct elink_params *params,
- struct elink_phy *phy, uint8_t tx_en)
+ struct elink_phy *phy,
+ uint8_t tx_en)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ transmitter to %d", tx_en);
+ ELINK_DEBUG_P1(sc, "Setting SFP+ transmitter to %d", tx_en);
if (CHIP_IS_E3(sc))
elink_sfp_e3_set_transmitter(params, phy, tx_en);
else
@@ -7270,20 +8804,17 @@ static void elink_sfp_set_transmitter(struct elink_params *params,
}
static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
- struct elink_params
- *params,
- uint8_t dev_addr,
- uint16_t addr,
- uint8_t byte_cnt,
- uint8_t * o_buf,
- __rte_unused uint8_t
- is_init)
+ struct elink_params *params,
+ uint8_t dev_addr, uint16_t addr,
+ uint8_t byte_cnt,
+ uint8_t *o_buf, __rte_unused uint8_t is_init)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val = 0;
uint16_t i;
if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
- PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
+ ELINK_DEBUG_P0(sc,
+ "Reading from eeprom is limited to 0xf");
return ELINK_STATUS_ERROR;
}
/* Set the read command byte count */
@@ -7313,10 +8844,10 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
}
if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
- MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
- PMD_DRV_LOG(DEBUG, sc,
- "Got bad status 0x%x when reading from SFP+ EEPROM",
- (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
+ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
+ ELINK_DEBUG_P1(sc,
+ "Got bad status 0x%x when reading from SFP+ EEPROM",
+ (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
return ELINK_STATUS_ERROR;
}
@@ -7325,8 +8856,8 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
- o_buf[i] =
- (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
+ o_buf[i] = (uint8_t)
+ (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
}
for (i = 0; i < 100; i++) {
@@ -7349,29 +8880,27 @@ static void elink_warpcore_power_module(struct elink_params *params,
pin_cfg = (REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK)
- >> PORT_HW_CFG_E3_PWR_DIS_SHIFT;
+ dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
+ PORT_HW_CFG_E3_PWR_DIS_MASK) >>
+ PORT_HW_CFG_E3_PWR_DIS_SHIFT;
if (pin_cfg == PIN_CFG_NA)
return;
- PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ module power to %d using pin cfg %d",
- power, pin_cfg);
+ ELINK_DEBUG_P2(sc, "Setting SFP+ module power to %d using pin cfg %d",
+ power, pin_cfg);
/* Low ==> corresponding SFP+ module is powered
* high ==> the SFP+ module is powered down
*/
elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
}
-
-static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
- elink_phy *phy,
- struct elink_params
- *params,
- uint8_t dev_addr,
- uint16_t addr,
- uint8_t byte_cnt,
- uint8_t * o_buf,
- uint8_t is_init)
+static elink_status_t elink_warpcore_read_sfp_module_eeprom(
+ __rte_unused struct elink_phy *phy,
+ struct elink_params *params,
+ uint8_t dev_addr,
+ uint16_t addr,
+ uint8_t byte_cnt,
+ uint8_t *o_buf,
+ uint8_t is_init)
{
elink_status_t rc = ELINK_STATUS_OK;
uint8_t i, j = 0, cnt = 0;
@@ -7380,8 +8909,8 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
struct bnx2x_softc *sc = params->sc;
if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
- PMD_DRV_LOG(DEBUG, sc,
- "Reading from eeprom is limited to 16 bytes");
+ ELINK_DEBUG_P0(sc,
+ "Reading from eeprom is limited to 16 bytes");
return ELINK_STATUS_ERROR;
}
@@ -7394,13 +8923,15 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
DELAY(1000 * 1);
elink_warpcore_power_module(params, 1);
}
- rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
+
+ elink_bsc_module_sel(params);
+ rc = elink_bsc_read(sc, dev_addr, addr32, 0, byte_cnt,
data_array);
} while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
if (rc == ELINK_STATUS_OK) {
for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
- o_buf[j] = *((uint8_t *) data_array + i);
+ o_buf[j] = *((uint8_t *)data_array + i);
j++;
}
}
@@ -7409,20 +8940,18 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
}
static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
- struct elink_params
- *params,
- uint8_t dev_addr,
- uint16_t addr,
- uint8_t byte_cnt,
- uint8_t * o_buf,
- __rte_unused uint8_t
- is_init)
+ struct elink_params *params,
+ uint8_t dev_addr, uint16_t addr,
+ uint8_t byte_cnt,
+ uint8_t *o_buf,
+ __rte_unused uint8_t is_init)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val, i;
if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
- PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
+ ELINK_DEBUG_P0(sc,
+ "Reading from eeprom is limited to 0xf");
return ELINK_STATUS_ERROR;
}
@@ -7437,7 +8966,9 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
/* Need to read from 1.8000 to clear it */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
+ &val);
/* Set the read command byte count */
elink_cl45_write(sc, phy,
@@ -7448,16 +8979,19 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
/* Set the read command address */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);
+ MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
+ addr);
/* Set the destination address */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
+ 0x8004,
+ MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
/* Activate read command */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);
+ MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
+ 0x8002);
/* Wait appropriate time for two-wire command to finish before
* polling the status register
*/
@@ -7475,10 +9009,10 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
}
if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
- MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
- PMD_DRV_LOG(DEBUG, sc,
- "Got bad status 0x%x when reading from SFP+ EEPROM",
- (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
+ MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
+ ELINK_DEBUG_P1(sc,
+ "Got bad status 0x%x when reading from SFP+ EEPROM",
+ (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
return ELINK_STATUS_TIMEOUT;
}
@@ -7487,8 +9021,8 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
- o_buf[i] =
- (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
+ o_buf[i] = (uint8_t)
+ (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
}
for (i = 0; i < 100; i++) {
@@ -7503,22 +9037,18 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
return ELINK_STATUS_ERROR;
}
-
-static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
- struct elink_params *params,
- uint8_t dev_addr,
- uint16_t addr,
- uint16_t byte_cnt,
- uint8_t * o_buf)
+elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
+ struct elink_params *params, uint8_t dev_addr,
+ uint16_t addr, uint16_t byte_cnt,
+ uint8_t *o_buf)
{
- elink_status_t rc = ELINK_STATUS_OK;
+ elink_status_t rc = 0;
+ struct bnx2x_softc *sc = params->sc;
uint8_t xfer_size;
uint8_t *user_data = o_buf;
read_sfp_module_eeprom_func_p read_func;
-
if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
- PMD_DRV_LOG(DEBUG, params->sc,
- "invalid dev_addr 0x%x", dev_addr);
+ ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x", dev_addr);
return ELINK_STATUS_ERROR;
}
@@ -7539,7 +9069,7 @@ static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
while (!rc && (byte_cnt > 0)) {
xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
- ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
+ ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
rc = read_func(phy, params, dev_addr, addr, xfer_size,
user_data, 0);
byte_cnt -= xfer_size;
@@ -7550,91 +9080,105 @@ static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
}
static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
- struct elink_params *params,
- uint16_t * edc_mode)
+ struct elink_params *params,
+ uint16_t *edc_mode)
{
struct bnx2x_softc *sc = params->sc;
uint32_t sync_offset = 0, phy_idx, media_types;
- uint8_t gport, val[2], check_limiting_mode = 0;
+ uint8_t val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1];
+ uint8_t check_limiting_mode = 0;
*edc_mode = ELINK_EDC_MODE_LIMITING;
phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
/* First check for copper cable */
if (elink_read_sfp_module_eeprom(phy,
params,
ELINK_I2C_DEV_ADDR_A0,
- ELINK_SFP_EEPROM_CON_TYPE_ADDR,
- 2, (uint8_t *) val) != 0) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to read from SFP+ module EEPROM");
+ 0,
+ ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1,
+ (uint8_t *)val) != 0) {
+ ELINK_DEBUG_P0(sc, "Failed to read from SFP+ module EEPROM");
return ELINK_STATUS_ERROR;
}
-
- switch (val[0]) {
+ params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
+ params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] <<
+ LINK_SFP_EEPROM_COMP_CODE_SHIFT;
+ elink_update_link_attr(params, params->link_attr_sync);
+ switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) {
case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
- {
- uint8_t copper_module_type;
- phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
- /* Check if its active cable (includes SFP+ module)
- * of passive cable
+ {
+ uint8_t copper_module_type;
+ phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
+ /* Check if its active cable (includes SFP+ module)
+ * of passive cable
+ */
+ copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR];
+ if (copper_module_type &
+ ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
+ ELINK_DEBUG_P0(sc, "Active Copper cable detected");
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
+ *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
+ else
+ check_limiting_mode = 1;
+ } else {
+ *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
+ /* Even in case PASSIVE_DAC indication is not set,
+ * treat it as a passive DAC cable, since some cables
+ * don't have this indication.
*/
- if (elink_read_sfp_module_eeprom(phy,
- params,
- ELINK_I2C_DEV_ADDR_A0,
- ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
- 1,
- &copper_module_type) !=
- 0) {
- PMD_DRV_LOG(DEBUG, sc,
- "Failed to read copper-cable-type"
- " from SFP+ EEPROM");
- return ELINK_STATUS_ERROR;
- }
-
if (copper_module_type &
- ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
- PMD_DRV_LOG(DEBUG, sc,
- "Active Copper cable detected");
- if (phy->type ==
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
- *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
- else
- check_limiting_mode = 1;
- } else if (copper_module_type &
- ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)
- {
- PMD_DRV_LOG(DEBUG, sc,
- "Passive Copper cable detected");
- *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
+ ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
+ ELINK_DEBUG_P0(sc,
+ "Passive Copper cable detected");
} else {
- PMD_DRV_LOG(DEBUG, sc,
- "Unknown copper-cable-type 0x%x !!!",
- copper_module_type);
- return ELINK_STATUS_ERROR;
+ ELINK_DEBUG_P0(sc,
+ "Unknown copper-cable-type");
}
- break;
}
+ break;
+ }
+ case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
check_limiting_mode = 1;
- if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
- ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
- ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
- PMD_DRV_LOG(DEBUG, sc, "1G SFP module detected");
- gport = params->port;
+ /* Module is considered as 1G in case it's NOT compliant with
+ * any 10G ethernet protocol, but is 1G Ethernet compliant.
+ */
+ if (((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] &
+ (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK |
+ ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK |
+ ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
+ (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
+ ELINK_DEBUG_P0(sc, "1G SFP module detected");
phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
if (phy->req_line_speed != ELINK_SPEED_1000) {
+ uint8_t gport = params->port;
phy->req_line_speed = ELINK_SPEED_1000;
if (!CHIP_IS_E1x(sc)) {
gport = SC_PATH(sc) +
- (params->port << 1);
+ (params->port << 1);
}
- elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
- // " Current SFP module in port %d is not"
- // " compliant with 10G Ethernet",
+ elink_cb_event_log(sc,
+ ELINK_LOG_ID_NON_10G_MODULE,
+ gport);
+ /*"Warning: Link speed was forced to 1000Mbps."
+ *" Current SFP module in port %d is not"
+ *" compliant with 10G Ethernet",
+ */
+ }
+ if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] &
+ ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) {
+ /* Some 1G-baseT modules will not link up,
+ * unless TX_EN is toggled with long delay in
+ * between.
+ */
+ elink_sfp_set_transmitter(params, phy, 0);
+ DELAY(1000 * 40);
+ elink_sfp_set_transmitter(params, phy, 1);
}
} else {
int idx, cfg_idx = 0;
- PMD_DRV_LOG(DEBUG, sc, "10G Optic module detected");
+ ELINK_DEBUG_P0(sc, "10G Optic module detected");
for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
if (params->phy[idx].type == phy->type) {
cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
@@ -7646,24 +9190,22 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
}
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Unable to determine module type 0x%x !!!",
- val[0]);
+ ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!",
+ val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]);
return ELINK_STATUS_ERROR;
}
sync_offset = params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].media_type);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[params->port].media_type);
media_types = REG_RD(sc, sync_offset);
/* Update media type for non-PMF sync */
for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
if (&(params->phy[phy_idx]) == phy) {
media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
- (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
- phy_idx));
- media_types |=
- ((phy->
- media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
- (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
+ (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
+ media_types |= ((phy->media_type &
+ PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
+ (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
break;
}
}
@@ -7676,8 +9218,8 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
ELINK_SFP_EEPROM_OPTIONS_ADDR,
ELINK_SFP_EEPROM_OPTIONS_SIZE,
options) != 0) {
- PMD_DRV_LOG(DEBUG, sc,
- "Failed to read Option field from module EEPROM");
+ ELINK_DEBUG_P0(sc,
+ "Failed to read Option field from module EEPROM");
return ELINK_STATUS_ERROR;
}
if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
@@ -7685,15 +9227,14 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
else
*edc_mode = ELINK_EDC_MODE_LIMITING;
}
- PMD_DRV_LOG(DEBUG, sc, "EDC mode is set to 0x%x", *edc_mode);
+ ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x", *edc_mode);
return ELINK_STATUS_OK;
}
-
/* This function read the relevant field from the module (SFP+), and verify it
* is compliant with this board
*/
static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
- struct elink_params *params)
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint32_t val, cmd;
@@ -7702,12 +9243,11 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1];
phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
val = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config[params->port].
- config));
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].config));
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
- PMD_DRV_LOG(DEBUG, sc, "NOT enforcing module verification");
+ ELINK_DEBUG_P0(sc, "NOT enforcing module verification");
return ELINK_STATUS_OK;
}
@@ -7717,23 +9257,24 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
} else if (params->feature_config_flags &
ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
- /* Use first phy request only in case of non-dual media */
+ /* Use first phy request only in case of non-dual media*/
if (ELINK_DUAL_MEDIA(params)) {
- PMD_DRV_LOG(DEBUG, sc,
- "FW does not support OPT MDL verification");
+ ELINK_DEBUG_P0(sc,
+ "FW does not support OPT MDL verification");
return ELINK_STATUS_ERROR;
}
cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
} else {
/* No support in OPT MDL detection */
- PMD_DRV_LOG(DEBUG, sc, "FW does not support OPT MDL verification");
+ ELINK_DEBUG_P0(sc,
+ "FW does not support OPT MDL verification");
return ELINK_STATUS_ERROR;
}
fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
- PMD_DRV_LOG(DEBUG, sc, "Approved module");
+ ELINK_DEBUG_P0(sc, "Approved module");
return ELINK_STATUS_OK;
}
@@ -7743,7 +9284,7 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
ELINK_I2C_DEV_ADDR_A0,
ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
- (uint8_t *) vendor_name))
+ (uint8_t *)vendor_name))
vendor_name[0] = '\0';
else
vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
@@ -7752,13 +9293,16 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
ELINK_I2C_DEV_ADDR_A0,
ELINK_SFP_EEPROM_PART_NO_ADDR,
ELINK_SFP_EEPROM_PART_NO_SIZE,
- (uint8_t *) vendor_pn))
+ (uint8_t *)vendor_pn))
vendor_pn[0] = '\0';
else
vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
- elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
- // " Port %d from %s part number %s",
+ elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port,
+ vendor_name, vendor_pn);
+ /* "Warning: Unqualified SFP+ module detected,"
+ * " Port %d from %s part number %s",
+ */
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
@@ -7766,13 +9310,14 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
return ELINK_STATUS_ERROR;
}
-static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
- *phy,
- struct elink_params
- *params)
+static elink_status_t elink_wait_for_sfp_module_initialized(
+ struct elink_phy *phy,
+ struct elink_params *params)
+
{
uint8_t val;
elink_status_t rc;
+ struct bnx2x_softc *sc = params->sc;
uint16_t timeout;
/* Initialization time after hot-plug may take up to 300ms for
* some phys type ( e.g. JDSU )
@@ -7780,18 +9325,17 @@ static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
for (timeout = 0; timeout < 60; timeout++) {
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
- rc = elink_warpcore_read_sfp_module_eeprom(phy, params,
- ELINK_I2C_DEV_ADDR_A0,
- 1, 1, &val,
- 1);
+ rc = elink_warpcore_read_sfp_module_eeprom(
+ phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,
+ 1);
else
rc = elink_read_sfp_module_eeprom(phy, params,
ELINK_I2C_DEV_ADDR_A0,
1, 1, &val);
if (rc == 0) {
- PMD_DRV_LOG(DEBUG, params->sc,
- "SFP+ module initialization took %d ms",
- timeout * 5);
+ ELINK_DEBUG_P1(sc,
+ "SFP+ module initialization took %d ms",
+ timeout * 5);
return ELINK_STATUS_OK;
}
DELAY(1000 * 5);
@@ -7802,8 +9346,8 @@ static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
}
static void elink_8727_power_module(struct bnx2x_softc *sc,
- struct elink_phy *phy, uint8_t is_power_up)
-{
+ struct elink_phy *phy,
+ uint8_t is_power_up) {
/* Make sure GPIOs are not using for LED mode */
uint16_t val;
/* In the GPIO register, bit 4 is use to determine if the GPIOs are
@@ -7828,30 +9372,33 @@ static void elink_8727_power_module(struct bnx2x_softc *sc,
val = (1 << 1);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_GPIO_CTRL,
+ val);
}
static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- uint16_t edc_mode)
+ struct elink_phy *phy,
+ uint16_t edc_mode)
{
uint16_t cur_limiting_mode;
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);
- PMD_DRV_LOG(DEBUG, sc,
- "Current Limiting mode is 0x%x", cur_limiting_mode);
+ MDIO_PMA_REG_ROM_VER2,
+ &cur_limiting_mode);
+ ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x",
+ cur_limiting_mode);
if (edc_mode == ELINK_EDC_MODE_LIMITING) {
- PMD_DRV_LOG(DEBUG, sc, "Setting LIMITING MODE");
+ ELINK_DEBUG_P0(sc, "Setting LIMITING MODE");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_ROM_VER2,
ELINK_EDC_MODE_LIMITING);
- } else { /* LRM mode ( default ) */
+ } else { /* LRM mode ( default )*/
- PMD_DRV_LOG(DEBUG, sc, "Setting LRM MODE");
+ ELINK_DEBUG_P0(sc, "Setting LRM MODE");
/* Changing to LRM mode takes quite few seconds. So do it only
* if current mode is limiting (default is LRM)
@@ -7860,27 +9407,35 @@ static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
return ELINK_STATUS_OK;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_LRM_MODE,
+ 0);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_ROM_VER2,
+ 0x128);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_MISC_CTRL0, 0x4008);
+ MDIO_PMA_REG_MISC_CTRL0,
+ 0x4008);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_LRM_MODE,
+ 0xaaaa);
}
return ELINK_STATUS_OK;
}
static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,
- struct elink_phy *phy,
- uint16_t edc_mode)
+ struct elink_phy *phy,
+ uint16_t edc_mode)
{
uint16_t phy_identifier;
uint16_t rom_ver2_val;
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier);
+ MDIO_PMA_REG_PHY_IDENTIFIER,
+ &phy_identifier);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -7888,7 +9443,9 @@ static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,
(phy_identifier & ~(1 << 9)));
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_ROM_VER2,
+ &rom_ver2_val);
/* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -7922,12 +9479,14 @@ static void elink_8727_specific_func(struct elink_phy *phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
(1 << 2) | (1 << 5));
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
+ 0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
/* Make MOD_ABS give interrupt on change */
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
+ MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+ &val);
val |= (1 << 12);
if (phy->flags & ELINK_FLAGS_NOC)
val |= (3 << 5);
@@ -7935,29 +9494,27 @@ static void elink_8727_specific_func(struct elink_phy *phy,
* status which reflect SFP+ module over-current
*/
if (!(phy->flags & ELINK_FLAGS_NOC))
- val &= 0xff8f; /* Reset bits 4-6 */
+ val &= 0xff8f; /* Reset bits 4-6 */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
val);
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Function 0x%x not supported by 8727",
- action);
+ ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727",
+ action);
return;
}
}
static void elink_set_e1e2_module_fault_led(struct elink_params *params,
- uint8_t gpio_mode)
+ uint8_t gpio_mode)
{
struct bnx2x_softc *sc = params->sc;
uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[params->port].
- sfp_ctrl)) &
- PORT_HW_CFG_FAULT_MODULE_LED_MASK;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[params->port].sfp_ctrl)) &
+ PORT_HW_CFG_FAULT_MODULE_LED_MASK;
switch (fault_led_gpio) {
case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
return;
@@ -7965,19 +9522,19 @@ static void elink_set_e1e2_module_fault_led(struct elink_params *params,
case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
- {
- uint8_t gpio_port = elink_get_gpio_port(params);
- uint16_t gpio_pin = fault_led_gpio -
- PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
- PMD_DRV_LOG(DEBUG, sc, "Set fault module-detected led "
- "pin %x port %x mode %x",
- gpio_pin, gpio_port, gpio_mode);
- elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
- }
- break;
+ {
+ uint8_t gpio_port = elink_get_gpio_port(params);
+ uint16_t gpio_pin = fault_led_gpio -
+ PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
+ ELINK_DEBUG_P3(sc, "Set fault module-detected led "
+ "pin %x port %x mode %x",
+ gpio_pin, gpio_port, gpio_mode);
+ elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
+ }
+ break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Error: Invalid fault led mode 0x%x",
- fault_led_gpio);
+ ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x",
+ fault_led_gpio);
}
}
@@ -7988,12 +9545,12 @@ static void elink_set_e3_module_fault_led(struct elink_params *params,
uint8_t port = params->port;
struct bnx2x_softc *sc = params->sc;
pin_cfg = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].e3_sfp_ctrl)) &
- PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
- PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
- PMD_DRV_LOG(DEBUG, sc, "Setting Fault LED to %d using pin cfg %d",
- gpio_mode, pin_cfg);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].e3_sfp_ctrl)) &
+ PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
+ PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
+ ELINK_DEBUG_P2(sc, "Setting Fault LED to %d using pin cfg %d",
+ gpio_mode, pin_cfg);
elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
}
@@ -8001,8 +9558,7 @@ static void elink_set_sfp_module_fault_led(struct elink_params *params,
uint8_t gpio_mode)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc,
- "Setting SFP+ module fault LED to %d", gpio_mode);
+ ELINK_DEBUG_P1(sc, "Setting SFP+ module fault LED to %d", gpio_mode);
if (CHIP_IS_E3(sc)) {
/* Low ==> if SFP+ module is supported otherwise
* High ==> if SFP+ module is not on the approved vendor list
@@ -8027,9 +9583,11 @@ static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,
}
static void elink_power_sfp_module(struct elink_params *params,
- struct elink_phy *phy, uint8_t power)
+ struct elink_phy *phy,
+ uint8_t power)
{
- PMD_DRV_LOG(DEBUG, params->sc, "Setting SFP+ power to %x", power);
+ struct bnx2x_softc *sc = params->sc;
+ ELINK_DEBUG_P1(sc, "Setting SFP+ power to %x", power);
switch (phy->type) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
@@ -8043,7 +9601,6 @@ static void elink_power_sfp_module(struct elink_params *params,
break;
}
}
-
static void elink_warpcore_set_limiting_mode(struct elink_params *params,
struct elink_phy *phy,
uint16_t edc_mode)
@@ -8052,7 +9609,7 @@ static void elink_warpcore_set_limiting_mode(struct elink_params *params,
uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
struct bnx2x_softc *sc = params->sc;
- uint8_t lane = elink_get_warpcore_lane(params);
+ uint8_t lane = elink_get_warpcore_lane(phy, params);
/* This is a global register which controls all lanes */
elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
@@ -8085,7 +9642,8 @@ static void elink_warpcore_set_limiting_mode(struct elink_params *params,
}
static void elink_set_limiting_mode(struct elink_params *params,
- struct elink_phy *phy, uint16_t edc_mode)
+ struct elink_phy *phy,
+ uint16_t edc_mode)
{
switch (phy->type) {
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
@@ -8101,30 +9659,28 @@ static void elink_set_limiting_mode(struct elink_params *params,
}
}
-static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
- struct elink_params *params)
+elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint16_t edc_mode;
elink_status_t rc = ELINK_STATUS_OK;
uint32_t val = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config[params->
- port].
- config));
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].config));
/* Enabled transmitter by default */
elink_sfp_set_transmitter(params, phy, 1);
- PMD_DRV_LOG(DEBUG, sc, "SFP+ module plugged in/out detected on port %d",
- params->port);
+ ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d",
+ params->port);
/* Power up module */
elink_power_sfp_module(params, phy, 1);
if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to get valid module type");
+ ELINK_DEBUG_P0(sc, "Failed to get valid module type");
return ELINK_STATUS_ERROR;
} else if (elink_verify_sfp_module(phy, params) != 0) {
/* Check SFP+ module compatibility */
- PMD_DRV_LOG(DEBUG, sc, "Module verification failed!!");
+ ELINK_DEBUG_P0(sc, "Module verification failed!!");
rc = ELINK_STATUS_ERROR;
/* Turn on fault module-detected led */
elink_set_sfp_module_fault_led(params,
@@ -8132,8 +9688,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
/* Check if need to power down the SFP+ module */
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
- PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
- PMD_DRV_LOG(DEBUG, sc, "Shutdown SFP+ module!!");
+ PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
+ ELINK_DEBUG_P0(sc, "Shutdown SFP+ module!!");
elink_power_sfp_module(params, phy, 0);
return rc;
}
@@ -8166,22 +9722,22 @@ void elink_handle_module_detect_int(struct elink_params *params)
uint8_t gpio_num, gpio_port;
if (CHIP_IS_E3(sc)) {
phy = ¶ms->phy[ELINK_INT_PHY];
- /* Always enable TX laser,will be disabled in case of fault */
+ /* Always enable TX laser, will be disabled in case of fault */
elink_sfp_set_transmitter(params, phy, 1);
} else {
phy = ¶ms->phy[ELINK_EXT_PHY1];
}
- if (elink_get_mod_abs_int_cfg(sc, params->shmem_base,
+ if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base,
params->port, &gpio_num, &gpio_port) ==
ELINK_STATUS_ERROR) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to get MOD_ABS interrupt config");
+ ELINK_DEBUG_P0(sc, "Failed to get MOD_ABS interrupt config");
return;
}
/* Set valid module led off */
elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
- /* Get current gpio val reflecting module plugged in / out */
+ /* Get current gpio val reflecting module plugged in / out*/
gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
/* Call the handling function in case module is detected */
@@ -8191,8 +9747,8 @@ void elink_handle_module_detect_int(struct elink_params *params)
elink_power_sfp_module(params, phy, 1);
elink_cb_gpio_int_write(sc, gpio_num,
- MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
- gpio_port);
+ MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
+ gpio_port);
if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
elink_sfp_module_detection(phy, params);
if (CHIP_IS_E3(sc)) {
@@ -8214,12 +9770,12 @@ void elink_handle_module_detect_int(struct elink_params *params)
}
}
} else {
- PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
+ ELINK_DEBUG_P0(sc, "SFP+ module is not initialized");
}
} else {
elink_cb_gpio_int_write(sc, gpio_num,
- MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
- gpio_port);
+ MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
+ gpio_port);
/* Module was plugged out.
* Disable transmit for this module
*/
@@ -8237,9 +9793,11 @@ static void elink_sfp_mask_fault(struct bnx2x_softc *sc,
{
uint16_t alarm_status, val;
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
+ MDIO_PMA_DEVAD, alarm_status_offset,
+ &alarm_status);
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
+ MDIO_PMA_DEVAD, alarm_status_offset,
+ &alarm_status);
/* Mask or enable the fault event. */
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
if (alarm_status & (1 << 0))
@@ -8248,38 +9806,42 @@ static void elink_sfp_mask_fault(struct bnx2x_softc *sc,
val |= (1 << 0);
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
}
-
/******************************************************************/
/* common BNX2X8706/BNX2X8726 PHY SECTION */
/******************************************************************/
static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint8_t link_up = 0;
uint16_t val1, val2, rx_sd, pcs_status;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "XGXS 8706/8726");
- /* Clear RX Alarm */
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
+ ELINK_DEBUG_P0(sc, "XGXS 8706/8726");
+ /* Clear RX Alarm*/
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
MDIO_PMA_LASI_TXCTRL);
- /* Clear LASI indication */
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
- PMD_DRV_LOG(DEBUG, sc,
- "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
+ /* Clear LASI indication*/
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
+ ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
elink_cl45_read(sc, phy,
MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
- PMD_DRV_LOG(DEBUG, sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
- " link_status 0x%x", rx_sd, pcs_status, val2);
+ ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
+ " link_status 0x%x", rx_sd, pcs_status, val2);
/* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
* are set, or if the autoneg bit 1 is set
*/
@@ -8296,9 +9858,9 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
/* Capture 10G link fault. Read twice to clear stale value. */
if (vars->line_speed == ELINK_SPEED_10000) {
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_TXSTAT, &val1);
+ MDIO_PMA_LASI_TXSTAT, &val1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_TXSTAT, &val1);
+ MDIO_PMA_LASI_TXSTAT, &val1);
if (val1 & (1 << 0))
vars->fault_detected = 1;
}
@@ -8310,15 +9872,15 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
/* BNX2X8706 PHY SECTION */
/******************************************************************/
static uint8_t elink_8706_config_init(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars *vars)
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
uint32_t tx_en_mode;
uint16_t cnt, val, tmp1;
struct bnx2x_softc *sc = params->sc;
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
/* HW reset */
elink_ext_phy_hw_reset(sc, params->port);
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
@@ -8332,34 +9894,35 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
break;
DELAY(1000 * 10);
}
- PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 is initialized after %d ms", cnt);
+ ELINK_DEBUG_P1(sc, "XGXS 8706 is initialized after %d ms", cnt);
if ((params->feature_config_flags &
ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
uint8_t i;
uint16_t reg;
for (i = 0; i < 4; i++) {
reg = MDIO_XS_8706_REG_BANK_RX0 +
- i * (MDIO_XS_8706_REG_BANK_RX1 -
- MDIO_XS_8706_REG_BANK_RX0);
+ i * (MDIO_XS_8706_REG_BANK_RX1 -
+ MDIO_XS_8706_REG_BANK_RX0);
elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
/* Clear first 3 bits of the control */
val &= ~0x7;
/* Set control bits according to configuration */
val |= (phy->rx_preemphasis[i] & 0x7);
- PMD_DRV_LOG(DEBUG, sc, "Setting RX Equalizer to BNX2X8706"
- " reg 0x%x <-- val 0x%x", reg, val);
+ ELINK_DEBUG_P2(sc, "Setting RX Equalizer to BNX2X8706"
+ " reg 0x%x <-- val 0x%x", reg, val);
elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
}
}
/* Force speed */
if (phy->req_line_speed == ELINK_SPEED_10000) {
- PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 force 10Gbps");
+ ELINK_DEBUG_P0(sc, "XGXS 8706 force 10Gbps");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
+ 0);
/* Arm LASI for link and Tx fault. */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
@@ -8367,7 +9930,7 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
/* Force 1Gbps using autoneg with 1G advertisement */
/* Allow CL37 through CL73 */
- PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 AutoNeg");
+ ELINK_DEBUG_P0(sc, "XGXS 8706 AutoNeg");
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
@@ -8385,9 +9948,11 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
+ 0x0400);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
+ 0x0004);
}
elink_save_bnx2x_spirom_ver(sc, phy, params->port);
@@ -8397,27 +9962,24 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy,
tx_en_mode = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- sfp_ctrl))
- & PORT_HW_CFG_TX_LASER_MASK;
+ dev_info.port_hw_config[params->port].sfp_ctrl))
+ & PORT_HW_CFG_TX_LASER_MASK;
if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
- PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
+ ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS");
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
- &tmp1);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
tmp1 |= 0x1;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
- tmp1);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
}
return ELINK_STATUS_OK;
}
static uint8_t elink_8706_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
return elink_8706_8726_read_status(phy, params, vars);
}
@@ -8429,7 +9991,7 @@ static void elink_8726_config_loopback(struct elink_phy *phy,
struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "PMA/PMD ext_phy_loopback: 8726");
+ ELINK_DEBUG_P0(sc, "PMA/PMD ext_phy_loopback: 8726");
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
}
@@ -8451,7 +10013,8 @@ static void elink_8726_external_rom_boot(struct elink_phy *phy,
MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_MISC_CTRL1, 0x0001);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -8463,15 +10026,16 @@ static void elink_8726_external_rom_boot(struct elink_phy *phy,
/* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_MISC_CTRL1, 0x0000);
DELAY(1000 * 200);
elink_save_bnx2x_spirom_ver(sc, phy, params->port);
}
static uint8_t elink_8726_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val1;
@@ -8481,7 +10045,7 @@ static uint8_t elink_8726_read_status(struct elink_phy *phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
&val1);
if (val1 & (1 << 15)) {
- PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
+ ELINK_DEBUG_P0(sc, "Tx is disabled");
link_up = 0;
vars->line_speed = 0;
}
@@ -8489,12 +10053,13 @@ static uint8_t elink_8726_read_status(struct elink_phy *phy,
return link_up;
}
+
static uint8_t elink_8726_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8726");
+ ELINK_DEBUG_P0(sc, "Initializing BNX2X8726");
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
elink_wait_reset_complete(sc, phy, params);
@@ -8509,7 +10074,7 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
elink_sfp_module_detection(phy, params);
if (phy->req_line_speed == ELINK_SPEED_1000) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
+ ELINK_DEBUG_P0(sc, "Setting 1G force");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
elink_cl45_write(sc, phy,
@@ -8517,17 +10082,19 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
+ 0x400);
} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
((phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
+ ELINK_DEBUG_P0(sc, "Setting 1G clause37");
/* Set Flow control */
elink_ext_phy_set_pause(params, phy, vars);
- elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
+ elink_cl45_write(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
elink_cl45_write(sc, phy,
@@ -8535,16 +10102,17 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
elink_cl45_write(sc, phy,
- MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
/* Enable RX-ALARM control to receive interrupt for 1G speed
* change
*/
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
+ 0x400);
- } else { /* Default 10G. Set only LASI control */
+ } else { /* Default 10G. Set only LASI control */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
}
@@ -8552,9 +10120,10 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy,
/* Set TX PreEmphasis if needed */
if ((params->feature_config_flags &
ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
- PMD_DRV_LOG(DEBUG, sc,
- "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
- phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
+ ELINK_DEBUG_P2(sc,
+ "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
+ phy->tx_preemphasis[0],
+ phy->tx_preemphasis[1]);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8726_TX_CTRL1,
@@ -8574,10 +10143,11 @@ static void elink_8726_link_reset(struct elink_phy *phy,
struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "elink_8726_link_reset port %d", params->port);
+ ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d", params->port);
/* Set serial boot control for external load */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_GEN_CTRL, 0x0001);
}
/******************************************************************/
@@ -8610,22 +10180,28 @@ static void elink_8727_set_link_led(struct elink_phy *phy,
break;
}
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+ &val);
val &= 0xff8f;
val |= led_mode_bitmask;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+ val);
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_GPIO_CTRL,
+ &val);
val &= 0xffe0;
val |= gpio_pins_bitmask;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8727_GPIO_CTRL,
+ val);
}
-
static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,
- struct elink_params *params)
-{
+ struct elink_params *params) {
uint32_t swap_val, swap_override;
uint8_t port;
/* The PHY reset is controlled by GPIO 1. Fake the port number
@@ -8636,7 +10212,7 @@ static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,
swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
port = (swap_val && swap_override) ^ 1;
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
}
static void elink_8727_config_speed(struct elink_phy *phy,
@@ -8647,14 +10223,14 @@ static void elink_8727_config_speed(struct elink_phy *phy,
/* Set option 1G speed */
if ((phy->req_line_speed == ELINK_SPEED_1000) ||
(phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
+ ELINK_DEBUG_P0(sc, "Setting 1G force");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
- PMD_DRV_LOG(DEBUG, sc, "1.7 = 0x%x", tmp1);
+ ELINK_DEBUG_P1(sc, "1.7 = 0x%x", tmp1);
/* Power down the XAUI until link is up in case of dual-media
* and 1G
*/
@@ -8671,10 +10247,10 @@ static void elink_8727_config_speed(struct elink_phy *phy,
((phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
((phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
- PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
+ ELINK_DEBUG_P0(sc, "Setting 1G clause37");
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
elink_cl45_write(sc, phy,
@@ -8697,9 +10273,8 @@ static void elink_8727_config_speed(struct elink_phy *phy,
}
static uint8_t elink_8727_config_init(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars
- *vars)
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
uint32_t tx_en_mode;
uint16_t tmp1, mod_abs, tmp2;
@@ -8708,7 +10283,7 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,
elink_wait_reset_complete(sc, phy, params);
- PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8727");
+ ELINK_DEBUG_P0(sc, "Initializing BNX2X8727");
elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
/* Initially configure MOD_ABS to interrupt when module is
@@ -8734,15 +10309,18 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
elink_8727_config_speed(phy, params);
+
/* Set TX PreEmphasis if needed */
if ((params->feature_config_flags &
ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
- PMD_DRV_LOG(DEBUG, sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
- phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
+ ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
+ phy->tx_preemphasis[0],
+ phy->tx_preemphasis[1]);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
phy->tx_preemphasis[0]);
@@ -8757,25 +10335,24 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy,
*/
tx_en_mode = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- sfp_ctrl))
- & PORT_HW_CFG_TX_LASER_MASK;
+ dev_info.port_hw_config[params->port].sfp_ctrl))
+ & PORT_HW_CFG_TX_LASER_MASK;
if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
- PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
+ ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS");
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
- &tmp2);
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
tmp2 |= 0x1000;
tmp2 &= 0xFFEF;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
- tmp2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2);
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff));
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
+ &tmp2);
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
+ (tmp2 & 0x7fff));
}
return ELINK_STATUS_OK;
@@ -8787,15 +10364,17 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
uint16_t mod_abs, rx_alarm_status;
uint32_t val = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config[params->
- port].config));
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
- &mod_abs);
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].
+ config));
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
if (mod_abs & (1 << 8)) {
/* Module is absent */
- PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is absent");
+ ELINK_DEBUG_P0(sc,
+ "MOD_ABS indication show module is absent");
phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
/* 1. Set mod_abs to detect next module
* presence event
@@ -8820,7 +10399,8 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,
} else {
/* Module is present */
- PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is present");
+ ELINK_DEBUG_P0(sc,
+ "MOD_ABS indication show module is present");
/* First disable transmitter, and if the module is ok, the
* module_detection will enable it
* 1. Set mod_abs to detect next module absent event ( bit 8)
@@ -8844,51 +10424,56 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy,
MDIO_PMA_DEVAD,
MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
+
if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
elink_sfp_set_transmitter(params, phy, 0);
- if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
+ if (elink_wait_for_sfp_module_initialized(phy, params) == 0)
elink_sfp_module_detection(phy, params);
- } else {
- PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
- }
+ else
+ ELINK_DEBUG_P0(sc, "SFP+ module is not initialized");
/* Reconfigure link speed based on module type limitations */
elink_8727_config_speed(phy, params);
}
- PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
+ ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x",
+ rx_alarm_status);
/* No need to check link status in case of module plugged in/out */
}
static uint8_t elink_8727_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
+
{
struct bnx2x_softc *sc = params->sc;
- uint8_t link_up = 0, oc_port = params->port;
+ uint8_t link_up = 0;
uint16_t link_status = 0;
uint16_t rx_alarm_status, lasi_ctrl, val1;
/* If PHY is not initialized, do not check link status */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
+ &lasi_ctrl);
if (!lasi_ctrl)
return 0;
/* Check the LASI on Rx */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
+ &rx_alarm_status);
vars->line_speed = 0;
- PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
+ ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
MDIO_PMA_LASI_TXCTRL);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- PMD_DRV_LOG(DEBUG, sc, "8727 LASI status 0x%x", val1);
+ ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x", val1);
/* Clear MSG-OUT */
elink_cl45_read(sc, phy,
@@ -8898,24 +10483,28 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
* for over current
*/
if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) {
- /* Check over-current using 8727 GPIO0 input */
+ /* Check over-current using 8727 GPIO0 input*/
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
&val1);
if ((val1 & (1 << 8)) == 0) {
+ uint8_t oc_port = params->port;
if (!CHIP_IS_E1x(sc))
oc_port = SC_PATH(sc) + (params->port << 1);
- PMD_DRV_LOG(DEBUG, sc,
- "8727 Power fault has been detected on port %d",
- oc_port);
- elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
- // "been detected and the power to "
- // "that SFP+ module has been removed "
- // "to prevent failure of the card. "
- // "Please remove the SFP+ module and "
- // "restart the system to clear this "
- // "error.",
+ ELINK_DEBUG_P1(sc,
+ "8727 Power fault has been detected on port %d",
+ oc_port);
+ elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT,
+ oc_port);
+ /* "Error: Power fault on Port %d has "
+ * "been detected and the power to "
+ * "that SFP+ module has been removed "
+ * "to prevent failure of the card. "
+ * "Please remove the SFP+ module and "
+ * "restart the system to clear this "
+ * "error.",
+ */
/* Disable all RX_ALARMs except for mod_abs */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -8931,14 +10520,13 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
MDIO_PMA_REG_PHY_IDENTIFIER, val1);
/* Clear RX alarm */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
elink_8727_power_module(params->sc, phy, 0);
return 0;
}
- }
+ } /* Over current check */
- /* Over current check */
/* When module absent bit is set, check module */
if (rx_alarm_status & (1 << 5)) {
elink_8727_handle_mod_abs(phy, params);
@@ -8949,10 +10537,10 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
}
if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
- PMD_DRV_LOG(DEBUG, sc, "Enabling 8727 TX laser");
+ ELINK_DEBUG_P0(sc, "Enabling 8727 TX laser");
elink_sfp_set_transmitter(params, phy, 1);
} else {
- PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
+ ELINK_DEBUG_P0(sc, "Tx is disabled");
return 0;
}
@@ -8966,26 +10554,26 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_10000;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 10G",
+ params->port);
} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
link_up = 1;
vars->line_speed = ELINK_SPEED_1000;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link up in 1G",
+ params->port);
} else {
link_up = 0;
- PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
- params->port);
+ ELINK_DEBUG_P1(sc, "port %x: External link is down",
+ params->port);
}
/* Capture 10G link fault. */
if (vars->line_speed == ELINK_SPEED_10000) {
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_TXSTAT, &val1);
+ MDIO_PMA_LASI_TXSTAT, &val1);
elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
- MDIO_PMA_LASI_TXSTAT, &val1);
+ MDIO_PMA_LASI_TXSTAT, &val1);
if (val1 & (1 << 0)) {
vars->fault_detected = 1;
@@ -8995,7 +10583,7 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy,
if (link_up) {
elink_ext_phy_resolve_fc(phy, params, vars);
vars->duplex = DUPLEX_FULL;
- PMD_DRV_LOG(DEBUG, sc, "duplex = 0x%x", vars->duplex);
+ ELINK_DEBUG_P1(sc, "duplex = 0x%x", vars->duplex);
}
if ((ELINK_DUAL_MEDIA(params)) &&
@@ -9035,8 +10623,16 @@ static void elink_8727_link_reset(struct elink_phy *phy,
/******************************************************************/
/* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */
/******************************************************************/
+static int elink_is_8483x_8485x(struct elink_phy *phy)
+{
+ return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
+ (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) ||
+ (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858));
+}
+
static void elink_save_848xx_spirom_version(struct elink_phy *phy,
- struct bnx2x_softc *sc, uint8_t port)
+ struct bnx2x_softc *sc,
+ uint8_t port)
{
uint16_t val, fw_ver2, cnt, i;
static struct elink_reg_set reg_set[] = {
@@ -9048,11 +10644,10 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
};
uint16_t fw_ver1;
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
+ if (elink_is_8483x_8485x(phy)) {
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
- phy->ver_addr);
+ phy->ver_addr);
} else {
/* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
/* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
@@ -9067,12 +10662,14 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
DELAY(5);
}
if (cnt == 100) {
- PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx "
- "phy fw version(1)");
- elink_save_spirom_version(sc, port, 0, phy->ver_addr);
+ ELINK_DEBUG_P0(sc, "Unable to read 848xx "
+ "phy fw version(1)");
+ elink_save_spirom_version(sc, port, 0,
+ phy->ver_addr);
return;
}
+
/* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
@@ -9084,9 +10681,10 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
DELAY(5);
}
if (cnt == 100) {
- PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx phy fw "
- "version(2)");
- elink_save_spirom_version(sc, port, 0, phy->ver_addr);
+ ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw "
+ "version(2)");
+ elink_save_spirom_version(sc, port, 0,
+ phy->ver_addr);
return;
}
@@ -9100,8 +10698,8 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy,
}
}
-
-static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)
+static void elink_848xx_set_led(struct bnx2x_softc *sc,
+ struct elink_phy *phy)
{
uint16_t val, offset, i;
static struct elink_reg_set reg_set[] = {
@@ -9110,29 +10708,30 @@ static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)
{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
{MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
- MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
+ MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
{MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
};
/* PHYC_CTL_LED_CTL */
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
val &= 0xFE00;
val |= 0x0092;
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LINK_SIGNAL, val);
for (i = 0; i < ARRAY_SIZE(reg_set); i++)
elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
reg_set[i].val);
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
+ if (elink_is_8483x_8485x(phy))
offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
else
offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
- /* stretch_en for LED3 */
+ /* stretch_en for LED3*/
elink_cl45_read_or_write(sc, phy,
MDIO_PMA_DEVAD, offset,
MDIO_PMA_REG_84823_LED3_STRETCH_EN);
@@ -9145,8 +10744,7 @@ static void elink_848xx_specific_func(struct elink_phy *phy,
struct bnx2x_softc *sc = params->sc;
switch (action) {
case ELINK_PHY_INIT:
- if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
- (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
+ if (!elink_is_8483x_8485x(phy)) {
/* Save spirom version */
elink_save_848xx_spirom_version(phy, sc, params->port);
}
@@ -9163,14 +10761,15 @@ static void elink_848xx_specific_func(struct elink_phy *phy,
}
static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t autoneg_val, an_1000_val, an_10_100_val;
elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
/* set 1000 speed advertisement */
elink_cl45_read(sc, phy,
@@ -9180,24 +10779,25 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
elink_ext_phy_set_pause(params, phy, vars);
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val);
+ MDIO_AN_REG_8481_LEGACY_AN_ADV,
+ &an_10_100_val);
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
&autoneg_val);
/* Disable forced speed */
- autoneg_val &=
- ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
+ autoneg_val &= ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) |
+ (1 << 13));
an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));
if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
(phy->req_line_speed == ELINK_SPEED_1000)) {
an_1000_val |= (1 << 8);
autoneg_val |= (1 << 9 | 1 << 12);
if (phy->req_duplex == DUPLEX_FULL)
an_1000_val |= (1 << 9);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
+ ELINK_DEBUG_P0(sc, "Advertising 1G");
} else
an_1000_val &= ~((1 << 8) | (1 << 9));
@@ -9213,7 +10813,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
*/
autoneg_val |= (1 << 9 | 1 << 12);
an_10_100_val |= (1 << 8);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
+ ELINK_DEBUG_P0(sc, "Advertising 100M-FD");
}
if (phy->speed_cap_mask &
@@ -9222,7 +10822,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
*/
autoneg_val |= (1 << 9 | 1 << 12);
an_10_100_val |= (1 << 7);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
+ ELINK_DEBUG_P0(sc, "Advertising 100M-HD");
}
if ((phy->speed_cap_mask &
@@ -9230,7 +10830,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
an_10_100_val |= (1 << 6);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
+ ELINK_DEBUG_P0(sc, "Advertising 10M-FD");
}
if ((phy->speed_cap_mask &
@@ -9238,14 +10838,15 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
an_10_100_val |= (1 << 5);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
+ ELINK_DEBUG_P0(sc, "Advertising 10M-HD");
}
}
/* Only 10/100 are allowed to work in FORCE mode */
if ((phy->req_line_speed == ELINK_SPEED_100) &&
(phy->supported &
- (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) {
+ (ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full))) {
autoneg_val |= (1 << 13);
/* Enabled AUTO-MDIX when autoneg is disabled */
elink_cl45_write(sc, phy,
@@ -9253,16 +10854,17 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
(1 << 15 | 1 << 9 | 7 << 0));
/* The PHY needs this set even for forced link. */
an_10_100_val |= (1 << 8) | (1 << 7);
- PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
+ ELINK_DEBUG_P0(sc, "Setting 100M force");
}
if ((phy->req_line_speed == ELINK_SPEED_10) &&
(phy->supported &
- (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) {
+ (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full))) {
/* Enabled AUTO-MDIX when autoneg is disabled */
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
(1 << 15 | 1 << 9 | 7 << 0));
- PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
+ ELINK_DEBUG_P0(sc, "Setting 10M force");
}
elink_cl45_write(sc, phy,
@@ -9275,42 +10877,44 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
/* Always write this if this is not 84833/4.
* For 84833/4, write it only when it's a forced speed.
*/
- if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
- (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) ||
+ if (!elink_is_8483x_8485x(phy) ||
((autoneg_val & (1 << 12)) == 0))
elink_cl45_write(sc, phy,
- MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
(phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
(phy->req_line_speed == ELINK_SPEED_10000)) {
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10G");
- /* Restart autoneg for 10G */
+ ELINK_DEBUG_P0(sc, "Advertising 10G");
+ /* Restart autoneg for 10G*/
- elink_cl45_read_or_write(sc, phy,
- MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
- 0x1000);
+ elink_cl45_read_or_write(
+ sc, phy,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
+ 0x1000);
elink_cl45_write(sc, phy,
- MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200);
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
+ 0x3200);
} else
elink_cl45_write(sc, phy,
MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1);
+ MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
+ 1);
return ELINK_STATUS_OK;
}
static uint8_t elink_8481_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
- /* Restore normal power mode */
+ /* Restore normal power mode*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
/* HW reset */
elink_ext_phy_hw_reset(sc, params->port);
@@ -9320,101 +10924,219 @@ static uint8_t elink_8481_config_init(struct elink_phy *phy,
return elink_848xx_cmn_config_init(phy, params, vars);
}
-#define PHY84833_CMDHDLR_WAIT 300
-#define PHY84833_CMDHDLR_MAX_ARGS 5
-static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
+#define PHY848xx_CMDHDLR_WAIT 300
+#define PHY848xx_CMDHDLR_MAX_ARGS 5
+
+static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy,
struct elink_params *params,
- uint16_t fw_cmd, uint16_t cmd_args[],
- int argc)
+ uint16_t fw_cmd,
+ uint16_t cmd_args[], int argc)
+{
+ int idx;
+ uint16_t val;
+ struct bnx2x_softc *sc = params->sc;
+
+ /* Step 1: Poll the STATUS register to see whether the previous command
+ * is in progress or the system is busy (CMD_IN_PROGRESS or
+ * SYSTEM_BUSY). If previous command is in progress or system is busy,
+ * check again until the previous command finishes execution and the
+ * system is available for taking command
+ */
+
+ for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
+ elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_STATUS, &val);
+ if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
+ (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
+ break;
+ DELAY(1000 * 1);
+ }
+ if (idx >= PHY848xx_CMDHDLR_WAIT) {
+ ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.");
+ return ELINK_STATUS_ERROR;
+ }
+
+ /* Step2: If any parameters are required for the function, write them
+ * to the required DATA registers
+ */
+
+ for (idx = 0; idx < argc; idx++) {
+ elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_DATA1 + idx,
+ cmd_args[idx]);
+ }
+
+ /* Step3: When the firmware is ready for commands, write the 'Command
+ * code' to the CMD register
+ */
+ elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
+
+ /* Step4: Once the command has been written, poll the STATUS register
+ * to check whether the command has completed (CMD_COMPLETED_PASS/
+ * CMD_FOR_CMDS or CMD_COMPLETED_ERROR).
+ */
+
+ for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
+ elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_STATUS, &val);
+ if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
+ (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
+ break;
+ DELAY(1000 * 1);
+ }
+ if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
+ (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
+ ELINK_DEBUG_P0(sc, "FW cmd failed.");
+ return ELINK_STATUS_ERROR;
+ }
+ /* Step5: Once the command has completed, read the specficied DATA
+ * registers for any saved results for the command, if applicable
+ */
+
+ /* Gather returning data */
+ for (idx = 0; idx < argc; idx++) {
+ elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_DATA1 + idx,
+ &cmd_args[idx]);
+ }
+
+ return ELINK_STATUS_OK;
+}
+
+static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
+ struct elink_params *params, uint16_t fw_cmd,
+ uint16_t cmd_args[], int argc, int process)
{
int idx;
uint16_t val;
struct bnx2x_softc *sc = params->sc;
+ elink_status_t rc = ELINK_STATUS_OK;
+
+ if (process == PHY84833_MB_PROCESS2) {
/* Write CMD_OPEN_OVERRIDE to STATUS reg */
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_STATUS,
- PHY84833_STATUS_CMD_OPEN_OVERRIDE);
- for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
+ MDIO_848xx_CMD_HDLR_STATUS,
+ PHY84833_STATUS_CMD_OPEN_OVERRIDE);
+ }
+
+ for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_STATUS, &val);
+ MDIO_848xx_CMD_HDLR_STATUS, &val);
if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
break;
DELAY(1000 * 1);
}
- if (idx >= PHY84833_CMDHDLR_WAIT) {
- PMD_DRV_LOG(DEBUG, sc, "FW cmd: FW not ready.");
+ if (idx >= PHY848xx_CMDHDLR_WAIT) {
+ ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.");
+ /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR
+ * clear the status to CMD_CLEAR_COMPLETE
+ */
+ if (val == PHY84833_STATUS_CMD_COMPLETE_PASS ||
+ val == PHY84833_STATUS_CMD_COMPLETE_ERROR) {
+ elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
+ MDIO_848xx_CMD_HDLR_STATUS,
+ PHY84833_STATUS_CMD_CLEAR_COMPLETE);
+ }
return ELINK_STATUS_ERROR;
}
-
- /* Prepare argument(s) and issue command */
+ if (process == PHY84833_MB_PROCESS1 ||
+ process == PHY84833_MB_PROCESS2) {
+ /* Prepare argument(s) */
for (idx = 0; idx < argc; idx++) {
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_DATA1 + idx,
- cmd_args[idx]);
+ MDIO_848xx_CMD_HDLR_DATA1 + idx,
+ cmd_args[idx]);
}
+ }
+
+ /* Issue command */
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
- for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
+ MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
+ for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_STATUS, &val);
+ MDIO_848xx_CMD_HDLR_STATUS, &val);
if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
- (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
+ (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
break;
DELAY(1000 * 1);
}
- if ((idx >= PHY84833_CMDHDLR_WAIT) ||
- (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
- PMD_DRV_LOG(DEBUG, sc, "FW cmd failed.");
- return ELINK_STATUS_ERROR;
+ if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
+ (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
+ ELINK_DEBUG_P0(sc, "FW cmd failed.");
+ rc = ELINK_STATUS_ERROR;
}
+ if (process == PHY84833_MB_PROCESS3 && rc == ELINK_STATUS_OK) {
/* Gather returning data */
for (idx = 0; idx < argc; idx++) {
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_DATA1 + idx,
+ MDIO_848xx_CMD_HDLR_DATA1 + idx,
&cmd_args[idx]);
}
+ }
+ if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR ||
+ val == PHY84833_STATUS_CMD_COMPLETE_PASS) {
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
- MDIO_84833_CMD_HDLR_STATUS,
- PHY84833_STATUS_CMD_CLEAR_COMPLETE);
- return ELINK_STATUS_OK;
+ MDIO_848xx_CMD_HDLR_STATUS,
+ PHY84833_STATUS_CMD_CLEAR_COMPLETE);
+ }
+ return rc;
+}
+
+static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy,
+ struct elink_params *params,
+ uint16_t fw_cmd,
+ uint16_t cmd_args[], int argc,
+ int process)
+{
+ struct bnx2x_softc *sc = params->sc;
+
+ if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858) ||
+ (REG_RD(sc, params->shmem2_base +
+ offsetof(struct shmem2_region,
+ link_attr_sync[params->port])) &
+ LINK_ATTR_84858)) {
+ return elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
+ argc);
+ } else {
+ return elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
+ argc, process);
+ }
}
-static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars
- *vars)
+static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy,
+ struct elink_params *params,
+ __rte_unused struct elink_vars *vars)
{
uint32_t pair_swap;
- uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
+ uint16_t data[PHY848xx_CMDHDLR_MAX_ARGS];
elink_status_t status;
struct bnx2x_softc *sc = params->sc;
/* Check for configuration. */
pair_swap = REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- xgbt_phy_cfg)) &
- PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
+ dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
+ PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
if (pair_swap == 0)
return ELINK_STATUS_OK;
/* Only the second argument is used for this command */
- data[1] = (uint16_t) pair_swap;
+ data[1] = (uint16_t)pair_swap;
- status = elink_84833_cmd_hdlr(phy, params,
- PHY84833_CMD_SET_PAIR_SWAP, data,
- PHY84833_CMDHDLR_MAX_ARGS);
- if (status == ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Pairswap OK, val=0x%x", data[1]);
- }
+ status = elink_848xx_cmd_hdlr(phy, params,
+ PHY848xx_CMD_SET_PAIR_SWAP, data,
+ 2, PHY84833_MB_PROCESS2);
+ if (status == ELINK_STATUS_OK)
+ ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x", data[1]);
return status;
}
static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- __rte_unused uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ __rte_unused uint32_t chip_id)
{
uint32_t reset_pin[2];
uint32_t idx;
@@ -9424,54 +11146,50 @@ static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,
for (idx = 0; idx < 2; idx++) {
/* Map config param to register bit. */
reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[0].
- e3_cmn_pin_cfg));
- reset_pin[idx] =
- (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >>
- PORT_HW_CFG_E3_PHY_RESET_SHIFT;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[0].e3_cmn_pin_cfg));
+ reset_pin[idx] = (reset_pin[idx] &
+ PORT_HW_CFG_E3_PHY_RESET_MASK) >>
+ PORT_HW_CFG_E3_PHY_RESET_SHIFT;
reset_pin[idx] -= PIN_CFG_GPIO0_P0;
reset_pin[idx] = (1 << reset_pin[idx]);
}
- reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
+ reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
} else {
/* E2, look from diff place of shmem. */
for (idx = 0; idx < 2; idx++) {
reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[0].
- default_cfg));
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[0].default_cfg));
reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
reset_pin[idx] = (1 << reset_pin[idx]);
}
- reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
+ reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
}
return reset_gpios;
}
static void elink_84833_hw_reset_phy(struct elink_phy *phy,
- struct elink_params *params)
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint8_t reset_gpios;
uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
- offsetof(struct shmem2_region,
- other_shmem_base_addr));
+ offsetof(struct shmem2_region,
+ other_shmem_base_addr));
uint32_t shmem_base_path[2];
/* Work around for 84833 LED failure inside RESET status */
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_LEGACY_MII_CTRL,
- MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
+ MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+ MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
- MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
- MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
+ MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
+ MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
shmem_base_path[0] = params->shmem_base;
shmem_base_path[1] = other_shmem_base_addr;
@@ -9482,24 +11200,25 @@ static void elink_84833_hw_reset_phy(struct elink_phy *phy,
elink_cb_gpio_mult_write(sc, reset_gpios,
MISC_REGISTERS_GPIO_OUTPUT_LOW);
DELAY(10);
- PMD_DRV_LOG(DEBUG, sc,
- "84833 hw reset on pin values 0x%x", reset_gpios);
+ ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x",
+ reset_gpios);
}
static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
elink_status_t rc;
+ struct bnx2x_softc *sc = params->sc;
uint16_t cmd_args = 0;
- PMD_DRV_LOG(DEBUG, params->sc, "Don't Advertise 10GBase-T EEE");
+ ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE");
/* Prevent Phy from working in EEE and advertising it */
- rc = elink_84833_cmd_hdlr(phy, params,
- PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
+ rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
+ &cmd_args, 1, PHY84833_MB_PROCESS1);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, params->sc, "EEE disable failed.");
+ ELINK_DEBUG_P0(sc, "EEE disable failed.");
return rc;
}
@@ -9507,16 +11226,17 @@ static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
}
static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
elink_status_t rc;
+ struct bnx2x_softc *sc = params->sc;
uint16_t cmd_args = 1;
- rc = elink_84833_cmd_hdlr(phy, params,
- PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
+ rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
+ &cmd_args, 1, PHY84833_MB_PROCESS1);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, params->sc, "EEE enable failed.");
+ ELINK_DEBUG_P0(sc, "EEE enable failed.");
return rc;
}
@@ -9525,14 +11245,14 @@ static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
#define PHY84833_CONSTANT_LATENCY 1193
static uint8_t elink_848x3_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port, initialize = 1;
uint16_t val;
uint32_t actual_phy_selection;
- uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
+ uint16_t cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
elink_status_t rc = ELINK_STATUS_OK;
DELAY(1000 * 1);
@@ -9544,19 +11264,20 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+ port);
} else {
/* MDIO reset */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL, 0x8000);
}
elink_wait_reset_complete(sc, phy, params);
/* Wait for GPHY to come out of reset */
DELAY(1000 * 50);
- if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
- (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
+ if (!elink_is_8483x_8485x(phy)) {
/* BNX2X84823 requires that XGXS links up first @ 10G for normal
* behavior.
*/
@@ -9567,7 +11288,19 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
vars->line_speed = temp;
}
+ /* Check if this is actually BNX2X84858 */
+ if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858) {
+ uint16_t hw_rev;
+
+ elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
+ MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
+ if (hw_rev == BNX2X84858_PHY_ID) {
+ params->link_attr_sync |= LINK_ATTR_84858;
+ elink_update_link_attr(params, params->link_attr_sync);
+ }
+ }
+ /* Set dual-media configuration according to configuration */
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
MDIO_CTL_REG_84823_MEDIA, &val);
val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
@@ -9609,39 +11342,33 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
MDIO_CTL_REG_84823_MEDIA, val);
- PMD_DRV_LOG(DEBUG, sc, "Multi_phy config = 0x%x, Media control = 0x%x",
- params->multi_phy_config, val);
+ ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x",
+ params->multi_phy_config, val);
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
- elink_84833_pair_swap_cfg(phy, params, vars);
+ if (elink_is_8483x_8485x(phy)) {
+ elink_848xx_pair_swap_cfg(phy, params, vars);
/* Keep AutogrEEEn disabled. */
cmd_args[0] = 0x0;
cmd_args[1] = 0x0;
cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
cmd_args[3] = PHY84833_CONSTANT_LATENCY;
- rc = elink_84833_cmd_hdlr(phy, params,
- PHY84833_CMD_SET_EEE_MODE, cmd_args,
- PHY84833_CMDHDLR_MAX_ARGS);
- if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Cfg AutogrEEEn failed.");
- }
+ rc = elink_848xx_cmd_hdlr(phy, params,
+ PHY848xx_CMD_SET_EEE_MODE, cmd_args,
+ 4, PHY84833_MB_PROCESS1);
+ if (rc != ELINK_STATUS_OK)
+ ELINK_DEBUG_P0(sc, "Cfg AutogrEEEn failed.");
}
- if (initialize) {
+ if (initialize)
rc = elink_848xx_cmn_config_init(phy, params, vars);
- } else {
+ else
elink_save_848xx_spirom_version(phy, sc, params->port);
- }
/* 84833 PHY has a better feature and doesn't need to support this. */
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
uint32_t cms_enable = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[params->
- port].
- default_cfg)) &
- PORT_HW_CFG_ENABLE_CMS_MASK;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[params->port].default_cfg)) &
+ PORT_HW_CFG_ENABLE_CMS_MASK;
elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
@@ -9662,7 +11389,7 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
elink_eee_has_cap(params)) {
rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
+ ELINK_DEBUG_P0(sc, "Failed to configure EEE timers");
elink_8483x_disable_eee(phy, params, vars);
return rc;
}
@@ -9675,39 +11402,40 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy,
else
rc = elink_8483x_disable_eee(phy, params, vars);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to set EEE advertisement");
+ ELINK_DEBUG_P0(sc, "Failed to set EEE advertisement");
return rc;
}
} else {
vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
}
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
+ if (elink_is_8483x_8485x(phy)) {
/* Bring PHY out of super isolate mode as the final step. */
elink_cl45_read_and_write(sc, phy,
MDIO_CTL_DEVAD,
MDIO_84833_TOP_CFG_XGPHY_STRAP1,
- (uint16_t) ~
- MDIO_84833_SUPER_ISOLATE);
+ (uint16_t)~MDIO_84833_SUPER_ISOLATE);
}
return rc;
}
static uint8_t elink_848xx_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val, val1, val2;
uint8_t link_up = 0;
+
/* Check 10G-BaseT link status */
/* Check PMD signal ok */
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);
elink_cl45_read(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);
- PMD_DRV_LOG(DEBUG, sc, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
+ MDIO_AN_DEVAD, 0xFFFA, &val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
+ &val2);
+ ELINK_DEBUG_P1(sc, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
/* Check link 10G */
if (val2 & (1 << 11)) {
@@ -9715,8 +11443,8 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
vars->duplex = DUPLEX_FULL;
link_up = 1;
elink_ext_phy_10G_an_resolve(sc, phy, vars);
- } else { /* Check Legacy speed link */
- uint16_t legacy_status, legacy_speed, mii_ctrl;
+ } else { /* Check Legacy speed link */
+ uint16_t legacy_status, legacy_speed;
/* Enable expansion register 0x42 (Operation mode status) */
elink_cl45_write(sc, phy,
@@ -9729,8 +11457,8 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
&legacy_status);
- PMD_DRV_LOG(DEBUG, sc,
- "Legacy speed status = 0x%x", legacy_status);
+ ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x",
+ legacy_status);
link_up = ((legacy_status & (1 << 11)) == (1 << 11));
legacy_speed = (legacy_status & (3 << 9));
if (legacy_speed == (0 << 9))
@@ -9739,13 +11467,15 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
vars->line_speed = ELINK_SPEED_100;
else if (legacy_speed == (2 << 9))
vars->line_speed = ELINK_SPEED_1000;
- else { /* Should not happen: Treat as link down */
+ else { /* Should not happen: Treat as link down */
vars->line_speed = 0;
link_up = 0;
}
if (params->feature_config_flags &
- ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
+ ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
+ uint16_t mii_ctrl;
+
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_8481_LEGACY_MII_CTRL,
@@ -9760,10 +11490,10 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
else
vars->duplex = DUPLEX_HALF;
- PMD_DRV_LOG(DEBUG, sc,
- "Link is up in %dMbps, is_duplex_full= %d",
- vars->line_speed,
- (vars->duplex == DUPLEX_FULL));
+ ELINK_DEBUG_P2(sc,
+ "Link is up in %dMbps, is_duplex_full= %d",
+ vars->line_speed,
+ (vars->duplex == DUPLEX_FULL));
/* Check legacy speed AN resolution */
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
@@ -9771,19 +11501,19 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
&val);
if (val & (1 << 5))
vars->link_status |=
- LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+ LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
elink_cl45_read(sc, phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
&val);
if ((val & (1 << 0)) == 0)
vars->link_status |=
- LINK_STATUS_PARALLEL_DETECTION_USED;
+ LINK_STATUS_PARALLEL_DETECTION_USED;
}
}
if (link_up) {
- PMD_DRV_LOG(DEBUG, sc, "BNX2X848x3: link speed is %d",
- vars->line_speed);
+ ELINK_DEBUG_P1(sc, "BNX2X848x3: link speed is %d",
+ vars->line_speed);
elink_ext_phy_resolve_fc(phy, params, vars);
/* Read LP advertised speeds */
@@ -9791,48 +11521,47 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy,
MDIO_AN_REG_CL37_FC_LP, &val);
if (val & (1 << 5))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
if (val & (1 << 6))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
if (val & (1 << 7))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
if (val & (1 << 8))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
if (val & (1 << 9))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_1000T_STATUS, &val);
if (val & (1 << 10))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
if (val & (1 << 11))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_MASTER_STATUS, &val);
if (val & (1 << 11))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
/* Determine if EEE was negotiated */
- if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
+ if (elink_is_8483x_8485x(phy))
elink_eee_an_resolve(phy, params, vars);
}
return link_up;
}
-static uint8_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,
- uint16_t * len)
+static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str,
+ uint16_t *len)
{
elink_status_t status = ELINK_STATUS_OK;
uint32_t spirom_ver;
@@ -9845,17 +11574,18 @@ static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy,
struct elink_params *params)
{
elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
}
static void elink_8481_link_reset(struct elink_phy *phy,
- struct elink_params *params)
+ struct elink_params *params)
{
elink_cl45_write(params->sc, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
- elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
+ elink_cl45_write(params->sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
}
static void elink_848x3_link_reset(struct elink_phy *phy,
@@ -9872,7 +11602,8 @@ static void elink_848x3_link_reset(struct elink_phy *phy,
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ port);
} else {
elink_cl45_read(sc, phy,
MDIO_CTL_DEVAD,
@@ -9889,48 +11620,52 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
{
struct bnx2x_softc *sc = params->sc;
uint16_t val;
- __rte_unused uint8_t port;
+ uint8_t port;
if (!(CHIP_IS_E1x(sc)))
port = SC_PATH(sc);
else
port = params->port;
-
switch (mode) {
case ELINK_LED_MODE_OFF:
- PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OFF", port);
+ ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
/* Set LED masks */
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED2_MASK, 0x0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED2_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED3_MASK, 0x0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED3_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED5_MASK, 0x0);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_8481_LED5_MASK,
+ 0x0);
} else {
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
}
break;
case ELINK_LED_MODE_FRONT_PANEL_OFF:
- PMD_DRV_LOG(DEBUG, sc,
- "Port 0x%x: LED MODE FRONT PANEL OFF", port);
+ ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF",
+ port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
@@ -9938,25 +11673,31 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
/* Set LED masks */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED2_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED2_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED3_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED3_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED5_MASK, 0x20);
+ MDIO_PMA_REG_8481_LED5_MASK,
+ 0x20);
} else {
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
+ if (phy->type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
/* Disable MI_INT interrupt before setting LED4
* source to constant off.
*/
@@ -9964,12 +11705,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
params->port * 4) &
ELINK_NIG_MASK_MI_INT) {
params->link_flags |=
- ELINK_LINK_FLAGS_INT_DISABLED;
+ ELINK_LINK_FLAGS_INT_DISABLED;
- elink_bits_dis(sc,
- NIG_REG_MASK_INTERRUPT_PORT0
- + params->port * 4,
- ELINK_NIG_MASK_MI_INT);
+ elink_bits_dis(
+ sc,
+ NIG_REG_MASK_INTERRUPT_PORT0 +
+ params->port * 4,
+ ELINK_NIG_MASK_MI_INT);
}
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -9980,42 +11722,50 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
break;
case ELINK_LED_MODE_ON:
- PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE ON", port);
+ ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
/* Set control reg */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ &val);
val &= 0x8000;
val |= 0x2492;
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, val);
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ val);
/* Set LED masks */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x0);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED2_MASK, 0x20);
+ MDIO_PMA_REG_8481_LED2_MASK,
+ 0x20);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED3_MASK, 0x20);
+ MDIO_PMA_REG_8481_LED3_MASK,
+ 0x20);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED5_MASK, 0x0);
+ MDIO_PMA_REG_8481_LED5_MASK,
+ 0x0);
} else {
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x20);
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x20);
+ if (phy->type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
/* Disable MI_INT interrupt before setting LED4
* source to constant on.
*/
@@ -10023,12 +11773,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
params->port * 4) &
ELINK_NIG_MASK_MI_INT) {
params->link_flags |=
- ELINK_LINK_FLAGS_INT_DISABLED;
+ ELINK_LINK_FLAGS_INT_DISABLED;
- elink_bits_dis(sc,
- NIG_REG_MASK_INTERRUPT_PORT0
- + params->port * 4,
- ELINK_NIG_MASK_MI_INT);
+ elink_bits_dis(
+ sc,
+ NIG_REG_MASK_INTERRUPT_PORT0 +
+ params->port * 4,
+ ELINK_NIG_MASK_MI_INT);
}
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
@@ -10040,7 +11791,7 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
case ELINK_LED_MODE_OPER:
- PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OPER", port);
+ ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER", port);
if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
SHARED_HW_CFG_LED_EXTPHY1) {
@@ -10048,14 +11799,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
/* Set control reg */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ &val);
if (!((val &
MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
- >>
- MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))
- {
- PMD_DRV_LOG(DEBUG, sc, "Setting LINK_SIGNAL");
+ >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
+ ELINK_DEBUG_P0(sc, "Setting LINK_SIGNAL");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8481_LINK_SIGNAL,
@@ -10065,19 +11815,23 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
/* Set LED masks */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, 0x10);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ 0x10);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED2_MASK, 0x80);
+ MDIO_PMA_REG_8481_LED2_MASK,
+ 0x80);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED3_MASK, 0x98);
+ MDIO_PMA_REG_8481_LED3_MASK,
+ 0x98);
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED5_MASK, 0x40);
+ MDIO_PMA_REG_8481_LED5_MASK,
+ 0x40);
} else {
/* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
@@ -10090,18 +11844,22 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LED1_MASK, val);
+ MDIO_PMA_REG_8481_LED1_MASK,
+ val);
/* Tell LED3 to blink on source */
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ &val);
val &= ~(7 << 6);
- val |= (1 << 6); /* A83B[8:6]= 1 */
+ val |= (1 << 6); /* A83B[8:6]= 1 */
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_8481_LINK_SIGNAL, val);
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
+ MDIO_PMA_REG_8481_LINK_SIGNAL,
+ val);
+ if (phy->type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
/* Restore LED4 source to external link,
* and re-enable interrupts.
*/
@@ -10113,14 +11871,14 @@ static void elink_848xx_set_link_led(struct elink_phy *phy,
ELINK_LINK_FLAGS_INT_DISABLED) {
elink_link_int_enable(params);
params->link_flags &=
- ~ELINK_LINK_FLAGS_INT_DISABLED;
+ ~ELINK_LINK_FLAGS_INT_DISABLED;
}
}
}
break;
}
- /* This is a workaround for E3+84833 until autoneg
+ /* This is a workaround for E3 + 84833 until autoneg
* restart is fixed in f/w
*/
if (CHIP_IS_E3(sc)) {
@@ -10145,7 +11903,9 @@ static void elink_54618se_specific_func(struct elink_phy *phy,
elink_cl22_write(sc, phy,
MDIO_REG_GPHY_SHADOW,
MDIO_REG_GPHY_SHADOW_LED_SEL2);
- elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_GPHY_SHADOW,
+ &temp);
temp &= ~(0xf << 4);
temp |= (0x6 << 4);
elink_cl22_write(sc, phy,
@@ -10160,15 +11920,15 @@ static void elink_54618se_specific_func(struct elink_phy *phy,
}
static uint8_t elink_54618se_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port;
uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
uint32_t cfg_pin;
- PMD_DRV_LOG(DEBUG, sc, "54618SE cfg init");
+ ELINK_DEBUG_P0(sc, "54618SE cfg init");
DELAY(1000 * 1);
/* This works with E3 only, no need to check the chip
@@ -10177,11 +11937,10 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
port = params->port;
cfg_pin = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_cmn_pin_cfg)) &
- PORT_HW_CFG_E3_PHY_RESET_MASK) >>
- PORT_HW_CFG_E3_PHY_RESET_SHIFT;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
+ PORT_HW_CFG_E3_PHY_RESET_MASK) >>
+ PORT_HW_CFG_E3_PHY_RESET_SHIFT;
/* Drive pin high to bring the GPHY out of reset. */
elink_set_cfg_pin(sc, cfg_pin, 1);
@@ -10190,63 +11949,76 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
DELAY(1000 * 50);
/* reset phy */
- elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000);
+ elink_cl22_write(sc, phy,
+ MDIO_PMA_REG_CTRL, 0x8000);
elink_wait_reset_complete(sc, phy, params);
/* Wait for GPHY to reset */
DELAY(1000 * 50);
+
elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
/* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
elink_cl22_write(sc, phy,
- MDIO_REG_GPHY_SHADOW,
- MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
- elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
+ MDIO_REG_GPHY_SHADOW,
+ MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_GPHY_SHADOW,
+ &temp);
temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
elink_cl22_write(sc, phy,
- MDIO_REG_GPHY_SHADOW,
- MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
+ MDIO_REG_GPHY_SHADOW,
+ MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
/* Set up fc */
/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
fc_val = 0;
if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
- MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
/* Read all advertisement */
- elink_cl22_read(sc, phy, 0x09, &an_1000_val);
+ elink_cl22_read(sc, phy,
+ 0x09,
+ &an_1000_val);
- elink_cl22_read(sc, phy, 0x04, &an_10_100_val);
+ elink_cl22_read(sc, phy,
+ 0x04,
+ &an_10_100_val);
- elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val);
+ elink_cl22_read(sc, phy,
+ MDIO_PMA_REG_CTRL,
+ &autoneg_val);
/* Disable forced speed */
- autoneg_val &=
- ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
- an_10_100_val &=
- ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |
- (1 << 11));
+ autoneg_val &= ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) |
+ (1 << 13));
+ an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) |
+ (1 << 10) | (1 << 11));
if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
- (phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
- (phy->req_line_speed == ELINK_SPEED_1000)) {
+ (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
+ (phy->req_line_speed == ELINK_SPEED_1000)) {
an_1000_val |= (1 << 8);
autoneg_val |= (1 << 9 | 1 << 12);
if (phy->req_duplex == DUPLEX_FULL)
an_1000_val |= (1 << 9);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
+ ELINK_DEBUG_P0(sc, "Advertising 1G");
} else
an_1000_val &= ~((1 << 8) | (1 << 9));
- elink_cl22_write(sc, phy, 0x09, an_1000_val);
- elink_cl22_read(sc, phy, 0x09, &an_1000_val);
+ elink_cl22_write(sc, phy,
+ 0x09,
+ an_1000_val);
+ elink_cl22_read(sc, phy,
+ 0x09,
+ &an_1000_val);
/* Advertise 10/100 link speed */
if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
@@ -10254,25 +12026,25 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
an_10_100_val |= (1 << 5);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
+ ELINK_DEBUG_P0(sc, "Advertising 10M-HD");
}
if (phy->speed_cap_mask &
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
an_10_100_val |= (1 << 6);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
+ ELINK_DEBUG_P0(sc, "Advertising 10M-FD");
}
if (phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
an_10_100_val |= (1 << 7);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
+ ELINK_DEBUG_P0(sc, "Advertising 100M-HD");
}
if (phy->speed_cap_mask &
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
an_10_100_val |= (1 << 8);
autoneg_val |= (1 << 9 | 1 << 12);
- PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
+ ELINK_DEBUG_P0(sc, "Advertising 100M-FD");
}
}
@@ -10280,13 +12052,17 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
if (phy->req_line_speed == ELINK_SPEED_100) {
autoneg_val |= (1 << 13);
/* Enabled AUTO-MDIX when autoneg is disabled */
- elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
- PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
+ elink_cl22_write(sc, phy,
+ 0x18,
+ (1 << 15 | 1 << 9 | 7 << 0));
+ ELINK_DEBUG_P0(sc, "Setting 100M force");
}
if (phy->req_line_speed == ELINK_SPEED_10) {
/* Enabled AUTO-MDIX when autoneg is disabled */
- elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
- PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
+ elink_cl22_write(sc, phy,
+ 0x18,
+ (1 << 15 | 1 << 9 | 7 << 0));
+ ELINK_DEBUG_P0(sc, "Setting 10M force");
}
if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
@@ -10301,7 +12077,7 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
if (rc != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
+ ELINK_DEBUG_P0(sc, "Failed to configure EEE timers");
elink_eee_disable(phy, params, vars);
} else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
(phy->req_duplex == DUPLEX_FULL) &&
@@ -10315,38 +12091,42 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy,
elink_eee_advertise(phy, params, vars,
SHMEM_EEE_1G_ADV);
} else {
- PMD_DRV_LOG(DEBUG, sc, "Don't Advertise 1GBase-T EEE");
+ ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE");
elink_eee_disable(phy, params, vars);
}
} else {
- vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
- SHMEM_EEE_SUPPORTED_SHIFT;
+ vars->eee_status &= ((uint32_t)(~SHMEM_EEE_1G_ADV) <<
+ SHMEM_EEE_SUPPORTED_SHIFT);
if (phy->flags & ELINK_FLAGS_EEE) {
/* Handle legacy auto-grEEEn */
if (params->feature_config_flags &
ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
temp = 6;
- PMD_DRV_LOG(DEBUG, sc, "Enabling Auto-GrEEEn");
+ ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn");
} else {
temp = 0;
- PMD_DRV_LOG(DEBUG, sc, "Don't Adv. EEE");
+ ELINK_DEBUG_P0(sc, "Don't Adv. EEE");
}
elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
MDIO_AN_REG_EEE_ADV, temp);
}
}
- elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val);
+ elink_cl22_write(sc, phy,
+ 0x04,
+ an_10_100_val | fc_val);
if (phy->req_duplex == DUPLEX_FULL)
autoneg_val |= (1 << 8);
- elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val);
+ elink_cl22_write(sc, phy,
+ MDIO_PMA_REG_CTRL, autoneg_val);
return ELINK_STATUS_OK;
}
+
static void elink_5461x_set_link_led(struct elink_phy *phy,
struct elink_params *params, uint8_t mode)
{
@@ -10354,11 +12134,14 @@ static void elink_5461x_set_link_led(struct elink_phy *phy,
uint16_t temp;
elink_cl22_write(sc, phy,
- MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1);
- elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
+ MDIO_REG_GPHY_SHADOW,
+ MDIO_REG_GPHY_SHADOW_LED_SEL1);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_GPHY_SHADOW,
+ &temp);
temp &= 0xff00;
- PMD_DRV_LOG(DEBUG, sc, "54618x set link led (mode=%x)", mode);
+ ELINK_DEBUG_P1(sc, "54618x set link led (mode=%x)", mode);
switch (mode) {
case ELINK_LED_MODE_FRONT_PANEL_OFF:
case ELINK_LED_MODE_OFF:
@@ -10374,11 +12157,12 @@ static void elink_5461x_set_link_led(struct elink_phy *phy,
break;
}
elink_cl22_write(sc, phy,
- MDIO_REG_GPHY_SHADOW,
- MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
+ MDIO_REG_GPHY_SHADOW,
+ MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
return;
}
+
static void elink_54618se_link_reset(struct elink_phy *phy,
struct elink_params *params)
{
@@ -10395,19 +12179,18 @@ static void elink_54618se_link_reset(struct elink_phy *phy,
*/
port = params->port;
cfg_pin = (REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_cmn_pin_cfg)) &
- PORT_HW_CFG_E3_PHY_RESET_MASK) >>
- PORT_HW_CFG_E3_PHY_RESET_SHIFT;
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
+ PORT_HW_CFG_E3_PHY_RESET_MASK) >>
+ PORT_HW_CFG_E3_PHY_RESET_SHIFT;
/* Drive pin low to put GPHY in reset. */
elink_set_cfg_pin(sc, cfg_pin, 0);
}
static uint8_t elink_54618se_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val;
@@ -10415,11 +12198,15 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,
uint16_t legacy_status, legacy_speed;
/* Get speed operation status */
- elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);
- PMD_DRV_LOG(DEBUG, sc, "54618SE read_status: 0x%x", legacy_status);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_GPHY_AUX_STATUS,
+ &legacy_status);
+ ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x", legacy_status);
/* Read status to clear the PHY interrupt. */
- elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);
+ elink_cl22_read(sc, phy,
+ MDIO_REG_INTR_STATUS,
+ &val);
link_up = ((legacy_status & (1 << 2)) == (1 << 2));
@@ -10445,25 +12232,30 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,
} else if (legacy_speed == (1 << 8)) {
vars->line_speed = ELINK_SPEED_10;
vars->duplex = DUPLEX_HALF;
- } else /* Should not happen */
+ } else /* Should not happen */
vars->line_speed = 0;
- PMD_DRV_LOG(DEBUG, sc,
- "Link is up in %dMbps, is_duplex_full= %d",
- vars->line_speed, (vars->duplex == DUPLEX_FULL));
+ ELINK_DEBUG_P2(sc,
+ "Link is up in %dMbps, is_duplex_full= %d",
+ vars->line_speed,
+ (vars->duplex == DUPLEX_FULL));
/* Check legacy speed AN resolution */
- elink_cl22_read(sc, phy, 0x01, &val);
+ elink_cl22_read(sc, phy,
+ 0x01,
+ &val);
if (val & (1 << 5))
vars->link_status |=
- LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
- elink_cl22_read(sc, phy, 0x06, &val);
+ LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+ elink_cl22_read(sc, phy,
+ 0x06,
+ &val);
if ((val & (1 << 0)) == 0)
vars->link_status |=
- LINK_STATUS_PARALLEL_DETECTION_USED;
+ LINK_STATUS_PARALLEL_DETECTION_USED;
- PMD_DRV_LOG(DEBUG, sc, "BNX2X54618SE: link speed is %d",
- vars->line_speed);
+ ELINK_DEBUG_P1(sc, "BNX2X4618SE: link speed is %d",
+ vars->line_speed);
elink_ext_phy_resolve_fc(phy, params, vars);
@@ -10473,27 +12265,27 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy,
if (val & (1 << 5))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
if (val & (1 << 6))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
if (val & (1 << 7))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
if (val & (1 << 8))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
if (val & (1 << 9))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
elink_cl22_read(sc, phy, 0xa, &val);
if (val & (1 << 10))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
if (val & (1 << 11))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
if ((phy->flags & ELINK_FLAGS_EEE) &&
elink_eee_has_cap(params))
@@ -10510,7 +12302,7 @@ static void elink_54618se_config_loopback(struct elink_phy *phy,
uint16_t val;
uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
- PMD_DRV_LOG(DEBUG, sc, "2PMA/PMD ext_phy_loopback: 54618se");
+ ELINK_DEBUG_P0(sc, "2PMA/PMD ext_phy_loopback: 54618se");
/* Enable master/slave manual mmode and set to master */
/* mii write 9 [bits set 11 12] */
@@ -10556,30 +12348,33 @@ static void elink_7101_config_loopback(struct elink_phy *phy,
}
static uint8_t elink_7101_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint16_t fw_ver1, fw_ver2, val;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LASI indication");
+ ELINK_DEBUG_P0(sc, "Setting the SFX7101 LASI indication");
- /* Restore normal power mode */
+ /* Restore normal power mode*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
/* HW reset */
elink_ext_phy_hw_reset(sc, params->port);
elink_wait_reset_complete(sc, phy, params);
- elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
- PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LED to blink on traffic");
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
+ ELINK_DEBUG_P0(sc, "Setting the SFX7101 LED to blink on traffic");
elink_cl45_write(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));
elink_ext_phy_set_pause(params, phy, vars);
/* Restart autoneg */
- elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
+ elink_cl45_read(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
val |= 0x200;
- elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
+ elink_cl45_write(sc, phy,
+ MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
/* Save spirom version */
elink_cl45_read(sc, phy,
@@ -10588,24 +12383,30 @@ static uint8_t elink_7101_config_init(struct elink_phy *phy,
elink_cl45_read(sc, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
elink_save_spirom_version(sc, params->port,
- (uint32_t) (fw_ver1 << 16 | fw_ver2),
+ (uint32_t)(fw_ver1 << 16 | fw_ver2),
phy->ver_addr);
return ELINK_STATUS_OK;
}
static uint8_t elink_7101_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t link_up;
uint16_t val1, val2;
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
- PMD_DRV_LOG(DEBUG, sc, "10G-base-T LASI status 0x%x->0x%x", val2, val1);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
- elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
- PMD_DRV_LOG(DEBUG, sc, "10G-base-T PMA status 0x%x->0x%x", val2, val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
+ ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x",
+ val2, val1);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
+ ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x",
+ val2, val1);
link_up = ((val1 & 4) == 4);
/* If link is up print the AN outcome of the SFX7101 PHY */
if (link_up) {
@@ -10614,21 +12415,21 @@ static uint8_t elink_7101_read_status(struct elink_phy *phy,
&val2);
vars->line_speed = ELINK_SPEED_10000;
vars->duplex = DUPLEX_FULL;
- PMD_DRV_LOG(DEBUG, sc, "SFX7101 AN status 0x%x->Master=%x",
- val2, (val2 & (1 << 14)));
+ ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x",
+ val2, (val2 & (1 << 14)));
elink_ext_phy_10G_an_resolve(sc, phy, vars);
elink_ext_phy_resolve_fc(phy, params, vars);
/* Read LP advertised speeds */
if (val2 & (1 << 11))
vars->link_status |=
- LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
+ LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
}
return link_up;
}
-static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
- uint16_t * len)
+static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str,
+ uint16_t *len)
{
if (*len < 5)
return ELINK_STATUS_ERROR;
@@ -10641,15 +12442,39 @@ static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
return ELINK_STATUS_OK;
}
-static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,
- struct elink_params *params)
+void elink_sfx7101_sp_sw_reset(struct bnx2x_softc *sc, struct elink_phy *phy)
{
+ uint16_t val, cnt;
+
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_7101_RESET, &val);
+
+ for (cnt = 0; cnt < 10; cnt++) {
+ DELAY(1000 * 50);
+ /* Writes a self-clearing reset */
+ elink_cl45_write(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_7101_RESET,
+ (val | (1 << 15)));
+ /* Wait for clear */
+ elink_cl45_read(sc, phy,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_7101_RESET, &val);
+
+ if ((val & (1 << 15)) == 0)
+ break;
+ }
+}
+
+static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,
+ struct elink_params *params) {
/* Low power mode is controlled by GPIO 2 */
elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
/* The PHY reset is controlled by GPIO 1 */
elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
}
static void elink_7101_set_link_led(struct elink_phy *phy,
@@ -10670,7 +12495,9 @@ static void elink_7101_set_link_led(struct elink_phy *phy,
break;
}
elink_cl45_write(sc, phy,
- MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_7107_LINK_LED_CNTL,
+ val);
}
/******************************************************************/
@@ -10678,482 +12505,532 @@ static void elink_7101_set_link_led(struct elink_phy *phy,
/******************************************************************/
static const struct elink_phy phy_null = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
- .addr = 0,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = 0,
- .media_type = ELINK_ETH_PHY_NOT_PRESENT,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = NULL,
- .read_status = NULL,
- .link_reset = NULL,
- .config_loopback = NULL,
- .format_fw_ver = NULL,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
+ .addr = 0,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = 0,
+ .media_type = ELINK_ETH_PHY_NOT_PRESENT,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)NULL,
+ .read_status = (read_status_t)NULL,
+ .link_reset = (link_reset_t)NULL,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_serdes = {
- .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = 0,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_2500baseX_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_xgxs_config_init,
- .read_status = elink_link_settings_status,
- .link_reset = elink_int_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = NULL,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = 0,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_2500baseX_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_xgxs_config_init,
+ .read_status = (read_status_t)elink_link_settings_status,
+ .link_reset = (link_reset_t)elink_int_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_xgxs = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = 0,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_2500baseX_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_CX4,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_xgxs_config_init,
- .read_status = elink_link_settings_status,
- .link_reset = elink_int_link_reset,
- .config_loopback = elink_set_xgxs_loopback,
- .format_fw_ver = NULL,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = elink_xgxs_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = 0,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_2500baseX_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_CX4,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_xgxs_config_init,
+ .read_status = (read_status_t)elink_link_settings_status,
+ .link_reset = (link_reset_t)elink_int_link_reset,
+ .config_loopback = (config_loopback_t)elink_set_xgxs_loopback,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func
};
-
static const struct elink_phy phy_warpcore = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_TX_ERROR_CHECK,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_20000baseKR2_Full |
- ELINK_SUPPORTED_20000baseMLD2_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_UNSPECIFIED,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- /* req_duplex = */ 0,
- /* rsrv = */ 0,
- .config_init = elink_warpcore_config_init,
- .read_status = elink_warpcore_read_status,
- .link_reset = elink_warpcore_link_reset,
- .config_loopback = elink_set_warpcore_loopback,
- .format_fw_ver = NULL,
- .hw_reset = elink_warpcore_hw_reset,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_TX_ERROR_CHECK,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_1000baseKX_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_10000baseKR_Full |
+ ELINK_SUPPORTED_20000baseKR2_Full |
+ ELINK_SUPPORTED_20000baseMLD2_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_UNSPECIFIED,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ /* req_duplex = */0,
+ /* rsrv = */0,
+ .config_init = (config_init_t)elink_warpcore_config_init,
+ .read_status = (read_status_t)elink_warpcore_read_status,
+ .link_reset = (link_reset_t)elink_warpcore_link_reset,
+ .config_loopback = (config_loopback_t)elink_set_warpcore_loopback,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)elink_warpcore_hw_reset,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
+
static const struct elink_phy phy_7101 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_7101_config_init,
- .read_status = elink_7101_read_status,
- .link_reset = elink_common_ext_link_reset,
- .config_loopback = elink_7101_config_loopback,
- .format_fw_ver = elink_7101_format_ver,
- .hw_reset = elink_7101_hw_reset,
- .set_link_led = elink_7101_set_link_led,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_7101_config_init,
+ .read_status = (read_status_t)elink_7101_read_status,
+ .link_reset = (link_reset_t)elink_common_ext_link_reset,
+ .config_loopback = (config_loopback_t)elink_7101_config_loopback,
+ .format_fw_ver = (format_fw_ver_t)elink_7101_format_ver,
+ .hw_reset = (hw_reset_t)elink_7101_hw_reset,
+ .set_link_led = (set_link_led_t)elink_7101_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
-
static const struct elink_phy phy_8073 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = 0,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_2500baseX_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_KR,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8073_config_init,
- .read_status = elink_8073_read_status,
- .link_reset = elink_8073_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_format_ver,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = elink_8073_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = 0,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_2500baseX_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_KR,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8073_config_init,
+ .read_status = (read_status_t)elink_8073_read_status,
+ .link_reset = (link_reset_t)elink_8073_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)elink_8073_specific_func
};
-
static const struct elink_phy phy_8705 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_XFP_FIBER,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8705_config_init,
- .read_status = elink_8705_read_status,
- .link_reset = elink_common_ext_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_null_format_ver,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_XFP_FIBER,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8705_config_init,
+ .read_status = (read_status_t)elink_8705_read_status,
+ .link_reset = (link_reset_t)elink_common_ext_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_null_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
-
static const struct elink_phy phy_8706 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8706_config_init,
- .read_status = elink_8706_read_status,
- .link_reset = elink_common_ext_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_format_ver,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8706_config_init,
+ .read_status = (read_status_t)elink_8706_read_status,
+ .link_reset = (link_reset_t)elink_common_ext_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_8726 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK),
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_NOT_PRESENT,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8726_config_init,
- .read_status = elink_8726_read_status,
- .link_reset = elink_8726_link_reset,
- .config_loopback = elink_8726_config_loopback,
- .format_fw_ver = elink_format_ver,
- .hw_reset = NULL,
- .set_link_led = NULL,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = (ELINK_FLAGS_INIT_XGXS_FIRST |
+ ELINK_FLAGS_TX_ERROR_CHECK),
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_NOT_PRESENT,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8726_config_init,
+ .read_status = (read_status_t)elink_8726_read_status,
+ .link_reset = (link_reset_t)elink_8726_link_reset,
+ .config_loopback = (config_loopback_t)elink_8726_config_loopback,
+ .format_fw_ver = (format_fw_ver_t)elink_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)NULL,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_8727 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK),
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_FIBRE |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_NOT_PRESENT,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8727_config_init,
- .read_status = elink_8727_read_status,
- .link_reset = elink_8727_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_format_ver,
- .hw_reset = elink_8727_hw_reset,
- .set_link_led = elink_8727_set_link_led,
- .phy_specific_func = elink_8727_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_TX_ERROR_CHECK),
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_FIBRE |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_NOT_PRESENT,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8727_config_init,
+ .read_status = (read_status_t)elink_8727_read_status,
+ .link_reset = (link_reset_t)elink_8727_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_format_ver,
+ .hw_reset = (hw_reset_t)elink_8727_hw_reset,
+ .set_link_led = (set_link_led_t)elink_8727_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_8727_specific_func
};
-
static const struct elink_phy phy_8481 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
- ELINK_FLAGS_REARM_LATCH_SIGNAL,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_8481_config_init,
- .read_status = elink_848xx_read_status,
- .link_reset = elink_8481_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_848xx_format_ver,
- .hw_reset = elink_8481_hw_reset,
- .set_link_led = elink_848xx_set_link_led,
- .phy_specific_func = NULL
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_8481_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_8481_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)elink_8481_hw_reset,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)NULL
};
static const struct elink_phy phy_84823 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
- ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK),
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_848x3_config_init,
- .read_status = elink_848xx_read_status,
- .link_reset = elink_848x3_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_848xx_format_ver,
- .hw_reset = NULL,
- .set_link_led = elink_848xx_set_link_led,
- .phy_specific_func = elink_848xx_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL |
+ ELINK_FLAGS_TX_ERROR_CHECK),
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_848x3_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_848x3_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
};
static const struct elink_phy phy_84833 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
- ELINK_FLAGS_REARM_LATCH_SIGNAL |
- ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE),
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_848x3_config_init,
- .read_status = elink_848xx_read_status,
- .link_reset = elink_848x3_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_848xx_format_ver,
- .hw_reset = elink_84833_hw_reset_phy,
- .set_link_led = elink_848xx_set_link_led,
- .phy_specific_func = elink_848xx_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL |
+ ELINK_FLAGS_TX_ERROR_CHECK |
+ ELINK_FLAGS_TEMPERATURE),
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_848x3_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_848x3_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
};
static const struct elink_phy phy_84834 = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
- ELINK_FLAGS_REARM_LATCH_SIGNAL,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- .req_duplex = 0,
- .rsrv = 0,
- .config_init = elink_848x3_config_init,
- .read_status = elink_848xx_read_status,
- .link_reset = elink_848x3_link_reset,
- .config_loopback = NULL,
- .format_fw_ver = elink_848xx_format_ver,
- .hw_reset = elink_84833_hw_reset_phy,
- .set_link_led = elink_848xx_set_link_led,
- .phy_specific_func = elink_848xx_specific_func
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_848x3_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_848x3_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
};
-static const struct elink_phy phy_54618se = {
- .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE,
- .addr = 0xff,
- .def_md_devad = 0,
- .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
- .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
- .mdio_ctrl = 0,
- .supported = (ELINK_SUPPORTED_10baseT_Half |
- ELINK_SUPPORTED_10baseT_Full |
- ELINK_SUPPORTED_100baseT_Half |
- ELINK_SUPPORTED_100baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_TP |
- ELINK_SUPPORTED_Autoneg |
- ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
- .media_type = ELINK_ETH_PHY_BASE_T,
- .ver_addr = 0,
- .req_flow_ctrl = 0,
- .req_line_speed = 0,
- .speed_cap_mask = 0,
- /* req_duplex = */ 0,
- /* rsrv = */ 0,
- .config_init = elink_54618se_config_init,
- .read_status = elink_54618se_read_status,
- .link_reset = elink_54618se_link_reset,
- .config_loopback = elink_54618se_config_loopback,
- .format_fw_ver = NULL,
- .hw_reset = NULL,
- .set_link_led = elink_5461x_set_link_led,
- .phy_specific_func = elink_54618se_specific_func
+static const struct elink_phy phy_84858 = {
+ .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
+ ELINK_FLAGS_REARM_LATCH_SIGNAL,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ .req_duplex = 0,
+ .rsrv = 0,
+ .config_init = (config_init_t)elink_848x3_config_init,
+ .read_status = (read_status_t)elink_848xx_read_status,
+ .link_reset = (link_reset_t)elink_848x3_link_reset,
+ .config_loopback = (config_loopback_t)NULL,
+ .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
+ .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
+ .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
};
+
+static const struct elink_phy phy_54618se = {
+ .type = PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE,
+ .addr = 0xff,
+ .def_md_devad = 0,
+ .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
+ .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
+ .mdio_ctrl = 0,
+ .supported = (ELINK_SUPPORTED_10baseT_Half |
+ ELINK_SUPPORTED_10baseT_Full |
+ ELINK_SUPPORTED_100baseT_Half |
+ ELINK_SUPPORTED_100baseT_Full |
+ ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_TP |
+ ELINK_SUPPORTED_Autoneg |
+ ELINK_SUPPORTED_Pause |
+ ELINK_SUPPORTED_Asym_Pause),
+ .media_type = ELINK_ETH_PHY_BASE_T,
+ .ver_addr = 0,
+ .req_flow_ctrl = 0,
+ .req_line_speed = 0,
+ .speed_cap_mask = 0,
+ /* req_duplex = */0,
+ /* rsrv = */0,
+ .config_init = (config_init_t)elink_54618se_config_init,
+ .read_status = (read_status_t)elink_54618se_read_status,
+ .link_reset = (link_reset_t)elink_54618se_link_reset,
+ .config_loopback = (config_loopback_t)elink_54618se_config_loopback,
+ .format_fw_ver = (format_fw_ver_t)NULL,
+ .hw_reset = (hw_reset_t)NULL,
+ .set_link_led = (set_link_led_t)elink_5461x_set_link_led,
+ .phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func
+};
/*****************************************************************/
/* */
/* Populate the phy according. Main function: elink_populate_phy */
@@ -11161,9 +13038,9 @@ static void elink_7101_set_link_led(struct elink_phy *phy,
/*****************************************************************/
static void elink_populate_preemphasis(struct bnx2x_softc *sc,
- uint32_t shmem_base,
- struct elink_phy *phy, uint8_t port,
- uint8_t phy_index)
+ uint32_t shmem_base,
+ struct elink_phy *phy, uint8_t port,
+ uint8_t phy_index)
{
/* Get the 4 lanes xgxs config rx and tx */
uint32_t rx = 0, tx = 0, i;
@@ -11175,23 +13052,19 @@ static void elink_populate_preemphasis(struct bnx2x_softc *sc,
if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
rx = REG_RD(sc, shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- xgxs_config_rx[i << 1]));
+ dev_info.port_hw_config[port].xgxs_config_rx[i << 1]));
tx = REG_RD(sc, shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- xgxs_config_tx[i << 1]));
+ dev_info.port_hw_config[port].xgxs_config_tx[i << 1]));
} else {
rx = REG_RD(sc, shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- xgxs_config2_rx[i << 1]));
+ dev_info.port_hw_config[port].xgxs_config2_rx[i << 1]));
tx = REG_RD(sc, shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- xgxs_config2_rx[i << 1]));
+ dev_info.port_hw_config[port].xgxs_config2_rx[i << 1]));
}
phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff);
@@ -11199,65 +13072,62 @@ static void elink_populate_preemphasis(struct bnx2x_softc *sc,
phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff);
phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
+ ELINK_DEBUG_P2(sc, "phy->rx_preemphasis = %x, phy->tx_preemphasis = %x",
+ phy->rx_preemphasis[i << 1],
+ phy->tx_preemphasis[i << 1]);
}
}
static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,
- uint32_t shmem_base, uint8_t phy_index,
- uint8_t port)
+ uint32_t shmem_base,
+ uint8_t phy_index, uint8_t port)
{
uint32_t ext_phy_config = 0;
switch (phy_index) {
case ELINK_EXT_PHY1:
ext_phy_config = REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- external_phy_config));
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].external_phy_config));
break;
case ELINK_EXT_PHY2:
ext_phy_config = REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- external_phy_config2));
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].external_phy_config2));
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Invalid phy_index %d", phy_index);
+ ELINK_DEBUG_P1(sc, "Invalid phy_index %d", phy_index);
return ELINK_STATUS_ERROR;
}
return ext_phy_config;
}
-
static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base, uint8_t port,
- struct elink_phy *phy)
+ uint32_t shmem_base, uint8_t port,
+ struct elink_phy *phy)
{
uint32_t phy_addr;
- __rte_unused uint32_t chip_id;
+ uint32_t chip_id;
uint32_t switch_cfg = (REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.
- port_feature_config[port].
- link_config)) &
- PORT_FEATURE_CONNECTED_SWITCH_MASK);
- chip_id =
- (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
- ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
-
- PMD_DRV_LOG(DEBUG, sc, ":chip_id = 0x%x", chip_id);
+ offsetof(struct shmem_region,
+ dev_info.port_feature_config[port].link_config)) &
+ PORT_FEATURE_CONNECTED_SWITCH_MASK);
+ chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
+ ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
+
+ ELINK_DEBUG_P1(sc, ":chip_id = 0x%x", chip_id);
if (USES_WARPCORE(sc)) {
uint32_t serdes_net_if;
- phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
+ phy_addr = REG_RD(sc,
+ MISC_REG_WC0_CTRL_PHY_ADDR);
*phy = phy_warpcore;
if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
phy->flags |= ELINK_FLAGS_4_PORT_MODE;
else
phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
- /* Check Dual mode */
+ /* Check Dual mode */
serdes_net_if = (REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- default_cfg)) &
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[port].default_cfg)) &
PORT_HW_CFG_NET_SERDES_IF_MASK);
/* Set the appropriate supported and flags indications per
* interface type of the chip
@@ -11293,8 +13163,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
break;
case PORT_HW_CFG_NET_SERDES_IF_KR:
phy->media_type = ELINK_ETH_PHY_KR;
- phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
- ELINK_SUPPORTED_10000baseT_Full |
+ phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full |
+ ELINK_SUPPORTED_10000baseKR_Full |
ELINK_SUPPORTED_FIBRE |
ELINK_SUPPORTED_Autoneg |
ELINK_SUPPORTED_Pause |
@@ -11312,8 +13182,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
phy->media_type = ELINK_ETH_PHY_KR;
phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
- ELINK_SUPPORTED_10000baseT_Full |
- ELINK_SUPPORTED_1000baseT_Full |
+ ELINK_SUPPORTED_10000baseKR_Full |
+ ELINK_SUPPORTED_1000baseKX_Full |
ELINK_SUPPORTED_Autoneg |
ELINK_SUPPORTED_FIBRE |
ELINK_SUPPORTED_Pause |
@@ -11321,8 +13191,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Unknown WC interface type 0x%x",
- serdes_net_if);
+ ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x",
+ serdes_net_if);
break;
}
@@ -11334,6 +13204,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
else
phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
+ ELINK_DEBUG_P3(sc, "media_type = %x, flags = %x, supported = %x",
+ phy->media_type, phy->flags, phy->supported);
} else {
switch (switch_cfg) {
case ELINK_SWITCH_CFG_1G:
@@ -11349,32 +13221,32 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
*phy = phy_xgxs;
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Invalid switch_cfg");
+ ELINK_DEBUG_P0(sc, "Invalid switch_cfg");
return ELINK_STATUS_ERROR;
}
}
- phy->addr = (uint8_t) phy_addr;
+ phy->addr = (uint8_t)phy_addr;
phy->mdio_ctrl = elink_get_emac_base(sc,
- SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
- port);
+ SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
+ port);
if (CHIP_IS_E2(sc))
phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
else
phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
- PMD_DRV_LOG(DEBUG, sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
- port, phy->addr, phy->mdio_ctrl);
+ ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
+ port, phy->addr, phy->mdio_ctrl);
elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
return ELINK_STATUS_OK;
}
static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
- uint8_t phy_index,
- uint32_t shmem_base,
- uint32_t shmem2_base,
- uint8_t port,
- struct elink_phy *phy)
+ uint8_t phy_index,
+ uint32_t shmem_base,
+ uint32_t shmem2_base,
+ uint8_t port,
+ struct elink_phy *phy)
{
uint32_t ext_phy_config, phy_type, config2;
uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
@@ -11420,10 +13292,13 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
*phy = phy_84834;
break;
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858:
+ *phy = phy_84858;
+ break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616:
- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE:
+ case PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE:
*phy = phy_54618se;
- if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
+ if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE)
phy->flags |= ELINK_FLAGS_EEE;
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
@@ -11449,21 +13324,20 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
* the address
*/
config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
- dev_info.shared_hw_config.
- config2));
+ dev_info.shared_hw_config.config2));
if (phy_index == ELINK_EXT_PHY1) {
phy->ver_addr = shmem_base + offsetof(struct shmem_region,
- port_mb[port].
- ext_phy_fw_version);
+ port_mb[port].ext_phy_fw_version);
/* Check specific mdc mdio settings */
if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
mdc_mdio_access = config2 &
- SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
+ SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
} else {
uint32_t size = REG_RD(sc, shmem2_base);
- if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) {
+ if (size >
+ offsetof(struct shmem2_region, ext_phy_fw_version2)) {
phy->ver_addr = shmem2_base +
offsetof(struct shmem2_region,
ext_phy_fw_version2[port]);
@@ -11471,35 +13345,34 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
/* Check specific mdc mdio settings */
if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
mdc_mdio_access = (config2 &
- SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
- >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
- SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
+ SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
+ (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
+ SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
}
phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
- if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
- (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) &&
- (phy->ver_addr)) {
+ if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) {
/* Remove 100Mb link supported for BNX2X84833/4 when phy fw
* version lower than or equal to 1.39
*/
uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
- if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1))
+ if (((raw_ver & 0x7F) <= 39) &&
+ (((raw_ver & 0xF80) >> 7) <= 1))
phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
ELINK_SUPPORTED_100baseT_Full);
}
- PMD_DRV_LOG(DEBUG, sc, "phy_type 0x%x port %d found in index %d",
- phy_type, port, phy_index);
- PMD_DRV_LOG(DEBUG, sc, " addr=0x%x, mdio_ctl=0x%x",
- phy->addr, phy->mdio_ctrl);
+ ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d",
+ phy_type, port, phy_index);
+ ELINK_DEBUG_P2(sc, " addr=0x%x, mdio_ctl=0x%x",
+ phy->addr, phy->mdio_ctrl);
return ELINK_STATUS_OK;
}
static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,
- uint8_t phy_index, uint32_t shmem_base,
- uint32_t shmem2_base, uint8_t port,
- struct elink_phy *phy)
+ uint8_t phy_index, uint32_t shmem_base,
+ uint32_t shmem2_base, uint8_t port,
+ struct elink_phy *phy)
{
elink_status_t status = ELINK_STATUS_OK;
phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
@@ -11511,50 +13384,44 @@ static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,
}
static void elink_phy_def_cfg(struct elink_params *params,
- struct elink_phy *phy, uint8_t phy_index)
+ struct elink_phy *phy,
+ uint8_t phy_index)
{
struct bnx2x_softc *sc = params->sc;
uint32_t link_config;
/* Populate the default phy configuration for MF mode */
if (phy_index == ELINK_EXT_PHY2) {
link_config = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config
- [params->port].link_config2));
- phy->speed_cap_mask =
- REG_RD(sc,
- params->shmem_base + offsetof(struct shmem_region,
- dev_info.port_hw_config
- [params->port].
- speed_capability_mask2));
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].link_config2));
+ phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
+ offsetof(struct shmem_region,
+ dev_info.
+ port_hw_config[params->port].speed_capability_mask2));
} else {
link_config = REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_feature_config
- [params->port].link_config));
- phy->speed_cap_mask =
- REG_RD(sc,
- params->shmem_base + offsetof(struct shmem_region,
- dev_info.port_hw_config
- [params->port].
- speed_capability_mask));
+ offsetof(struct shmem_region, dev_info.
+ port_feature_config[params->port].link_config));
+ phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
+ offsetof(struct shmem_region,
+ dev_info.
+ port_hw_config[params->port].speed_capability_mask));
}
-
- PMD_DRV_LOG(DEBUG, sc,
- "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
- phy_index, link_config, phy->speed_cap_mask);
+ ELINK_DEBUG_P3(sc,
+ "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
+ phy_index, link_config, phy->speed_cap_mask);
phy->req_duplex = DUPLEX_FULL;
- switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
+ switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
case PORT_FEATURE_LINK_SPEED_10M_HALF:
phy->req_duplex = DUPLEX_HALF;
- /* fall-through */
+ /* fallthrough */
case PORT_FEATURE_LINK_SPEED_10M_FULL:
phy->req_line_speed = ELINK_SPEED_10;
break;
case PORT_FEATURE_LINK_SPEED_100M_HALF:
phy->req_duplex = DUPLEX_HALF;
- /* fall-through */
+ /* fallthrough */
case PORT_FEATURE_LINK_SPEED_100M_FULL:
phy->req_line_speed = ELINK_SPEED_100;
break;
@@ -11572,7 +13439,10 @@ static void elink_phy_def_cfg(struct elink_params *params,
break;
}
- switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
+ ELINK_DEBUG_P2(sc, "Default config phy idx %x, req_duplex config %x",
+ phy_index, phy->req_duplex);
+
+ switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
case PORT_FEATURE_FLOW_CONTROL_AUTO:
phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
break;
@@ -11589,6 +13459,9 @@ static void elink_phy_def_cfg(struct elink_params *params,
phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
break;
}
+ ELINK_DEBUG_P3(sc, "Requested Duplex = %x, line_speed = %x, flow_ctrl = %x",
+ phy->req_duplex, phy->req_line_speed,
+ phy->req_flow_ctrl);
}
uint32_t elink_phy_selection(struct elink_params *params)
@@ -11597,25 +13470,24 @@ uint32_t elink_phy_selection(struct elink_params *params)
uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
phy_config_swapped = params->multi_phy_config &
- PORT_HW_CFG_PHY_SWAPPED_ENABLED;
+ PORT_HW_CFG_PHY_SWAPPED_ENABLED;
- prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK;
+ prio_cfg = params->multi_phy_config &
+ PORT_HW_CFG_PHY_SELECTION_MASK;
if (phy_config_swapped) {
switch (prio_cfg) {
case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
- return_cfg =
- PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
+ return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
break;
case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
- return_cfg =
- PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
+ return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
break;
case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
- return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
+ return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
break;
case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
- return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
+ return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
break;
}
} else
@@ -11624,19 +13496,23 @@ uint32_t elink_phy_selection(struct elink_params *params)
return return_cfg;
}
-elink_status_t elink_phy_probe(struct elink_params * params)
+elink_status_t elink_phy_probe(struct elink_params *params)
{
uint8_t phy_index, actual_phy_idx;
uint32_t phy_config_swapped, sync_offset, media_types;
struct bnx2x_softc *sc = params->sc;
struct elink_phy *phy;
params->num_phys = 0;
- PMD_DRV_LOG(DEBUG, sc, "Begin phy probe");
-
+ ELINK_DEBUG_P0(sc, "Begin phy probe");
+#ifdef ELINK_INCLUDE_EMUL
+ if (CHIP_REV_IS_EMUL(sc))
+ return ELINK_STATUS_OK;
+#endif
phy_config_swapped = params->multi_phy_config &
- PORT_HW_CFG_PHY_SWAPPED_ENABLED;
+ PORT_HW_CFG_PHY_SWAPPED_ENABLED;
- for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
+ for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
+ phy_index++) {
actual_phy_idx = phy_index;
if (phy_config_swapped) {
if (phy_index == ELINK_EXT_PHY1)
@@ -11644,18 +13520,19 @@ elink_status_t elink_phy_probe(struct elink_params * params)
else if (phy_index == ELINK_EXT_PHY2)
actual_phy_idx = ELINK_EXT_PHY1;
}
- PMD_DRV_LOG(DEBUG, sc, "phy_config_swapped %x, phy_index %x,"
- " actual_phy_idx %x", phy_config_swapped,
- phy_index, actual_phy_idx);
+ ELINK_DEBUG_P3(sc, "phy_config_swapped %x, phy_index %x,"
+ " actual_phy_idx %x", phy_config_swapped,
+ phy_index, actual_phy_idx);
phy = ¶ms->phy[actual_phy_idx];
if (elink_populate_phy(sc, phy_index, params->shmem_base,
params->shmem2_base, params->port,
phy) != ELINK_STATUS_OK) {
params->num_phys = 0;
- PMD_DRV_LOG(DEBUG, sc, "phy probe failed in phy index %d",
- phy_index);
+ ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d",
+ phy_index);
for (phy_index = ELINK_INT_PHY;
- phy_index < ELINK_MAX_PHYS; phy_index++)
+ phy_index < ELINK_MAX_PHYS;
+ phy_index++)
*phy = phy_null;
return ELINK_STATUS_ERROR;
}
@@ -11671,8 +13548,8 @@ elink_status_t elink_phy_probe(struct elink_params * params)
phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
sync_offset = params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].media_type);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[params->port].media_type);
media_types = REG_RD(sc, sync_offset);
/* Update media type for non-PMF sync only for the first time
@@ -11683,9 +13560,9 @@ elink_status_t elink_phy_probe(struct elink_params * params)
(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
actual_phy_idx))) == 0) {
media_types |= ((phy->media_type &
- PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
- (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
- actual_phy_idx));
+ PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
+ (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
+ actual_phy_idx));
}
REG_WR(sc, sync_offset, media_types);
@@ -11693,48 +13570,231 @@ elink_status_t elink_phy_probe(struct elink_params * params)
params->num_phys++;
}
- PMD_DRV_LOG(DEBUG, sc,
- "End phy probe. #phys found %x", params->num_phys);
+ ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x", params->num_phys);
return ELINK_STATUS_OK;
}
-static void elink_init_bmac_loopback(struct elink_params *params,
- struct elink_vars *vars)
+#ifdef ELINK_INCLUDE_EMUL
+static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
+ struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+ vars->line_speed = params->req_line_speed[0];
+ /* In case link speed is auto, set speed the highest as possible */
+ if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)
+ vars->line_speed = ELINK_SPEED_2500;
+ else if (elink_is_4_port_mode(sc))
+ vars->line_speed = ELINK_SPEED_10000;
+ else
+ vars->line_speed = ELINK_SPEED_20000;
+ }
+ if (vars->line_speed < ELINK_SPEED_10000) {
+ if ((params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {
+ ELINK_DEBUG_P1(sc, "Invalid line speed %d while UMAC is"
+ " disabled!", params->req_line_speed[0]);
+ return ELINK_STATUS_ERROR;
+ }
+ switch (vars->line_speed) {
+ case ELINK_SPEED_10:
+ vars->link_status = ELINK_LINK_10TFD;
+ break;
+ case ELINK_SPEED_100:
+ vars->link_status = ELINK_LINK_100TXFD;
+ break;
+ case ELINK_SPEED_1000:
+ vars->link_status = ELINK_LINK_1000TFD;
+ break;
+ case ELINK_SPEED_2500:
+ vars->link_status = ELINK_LINK_2500TFD;
+ break;
+ default:
+ ELINK_DEBUG_P1(sc, "Invalid line speed %d for UMAC",
+ vars->line_speed);
+ return ELINK_STATUS_ERROR;
+ }
+ vars->link_status |= LINK_STATUS_LINK_UP;
+
+ if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
+ elink_umac_enable(params, vars, 1);
+ else
+ elink_umac_enable(params, vars, 0);
+ } else {
+ /* Link speed >= 10000 requires XMAC enabled */
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {
+ ELINK_DEBUG_P1(sc, "Invalid line speed %d while XMAC is"
+ " disabled!", params->req_line_speed[0]);
+ return ELINK_STATUS_ERROR;
+ }
+ /* Check link speed */
+ switch (vars->line_speed) {
+ case ELINK_SPEED_10000:
+ vars->link_status = ELINK_LINK_10GTFD;
+ break;
+ case ELINK_SPEED_20000:
+ vars->link_status = ELINK_LINK_20GTFD;
+ break;
+ default:
+ ELINK_DEBUG_P1(sc, "Invalid line speed %d for XMAC",
+ vars->line_speed);
+ return ELINK_STATUS_ERROR;
+ }
+ vars->link_status |= LINK_STATUS_LINK_UP;
+ if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
+ elink_xmac_enable(params, vars, 1);
+ else
+ elink_xmac_enable(params, vars, 0);
+ }
+ return ELINK_STATUS_OK;
+}
+
+static elink_status_t elink_init_emul(struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
+ if (CHIP_IS_E3(sc)) {
+ if (elink_init_e3_emul_mac(params, vars) !=
+ ELINK_STATUS_OK)
+ return ELINK_STATUS_ERROR;
+ } else {
+ if (params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {
+ vars->line_speed = ELINK_SPEED_1000;
+ vars->link_status = (LINK_STATUS_LINK_UP |
+ ELINK_LINK_1000XFD);
+ if (params->loopback_mode ==
+ ELINK_LOOPBACK_EMAC)
+ elink_emac_enable(params, vars, 1);
+ else
+ elink_emac_enable(params, vars, 0);
+ } else {
+ vars->line_speed = ELINK_SPEED_10000;
+ vars->link_status = (LINK_STATUS_LINK_UP |
+ ELINK_LINK_10GTFD);
+ if (params->loopback_mode ==
+ ELINK_LOOPBACK_BMAC)
+ elink_bmac_enable(params, vars, 1, 1);
+ else
+ elink_bmac_enable(params, vars, 0, 1);
+ }
+ }
vars->link_up = 1;
- vars->line_speed = ELINK_SPEED_10000;
vars->duplex = DUPLEX_FULL;
vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
- vars->mac_type = ELINK_MAC_TYPE_BMAC;
-
- vars->phy_flags = PHY_XGXS_FLAG;
- elink_xgxs_deassert(params);
+ if (CHIP_IS_E1x(sc))
+ elink_pbf_update(params, vars->flow_ctrl,
+ vars->line_speed);
+ /* Disable drain */
+ REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
- /* Set bmac loopback */
- elink_bmac_enable(params, vars, 1, 1);
+ /* update shared memory */
+ elink_update_mng(params, vars->link_status);
+ return ELINK_STATUS_OK;
+}
+#endif
+#ifdef ELINK_INCLUDE_FPGA
+static elink_status_t elink_init_fpga(struct elink_params *params,
+ struct elink_vars *vars)
+{
+ /* Enable on E1.5 FPGA */
+ struct bnx2x_softc *sc = params->sc;
+ vars->duplex = DUPLEX_FULL;
+ vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
+ if (!(CHIP_IS_E1(sc))) {
+ vars->flow_ctrl = (ELINK_FLOW_CTRL_TX |
+ ELINK_FLOW_CTRL_RX);
+ vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
+ LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
+ }
+ if (CHIP_IS_E3(sc)) {
+ vars->line_speed = params->req_line_speed[0];
+ switch (vars->line_speed) {
+ case ELINK_SPEED_AUTO_NEG:
+ vars->line_speed = ELINK_SPEED_2500;
+ case ELINK_SPEED_2500:
+ vars->link_status = ELINK_LINK_2500TFD;
+ break;
+ case ELINK_SPEED_1000:
+ vars->link_status = ELINK_LINK_1000XFD;
+ break;
+ case ELINK_SPEED_100:
+ vars->link_status = ELINK_LINK_100TXFD;
+ break;
+ case ELINK_SPEED_10:
+ vars->link_status = ELINK_LINK_10TFD;
+ break;
+ default:
+ ELINK_DEBUG_P1(sc, "Invalid link speed %d",
+ params->req_line_speed[0]);
+ return ELINK_STATUS_ERROR;
+ }
+ vars->link_status |= LINK_STATUS_LINK_UP;
+ if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
+ elink_umac_enable(params, vars, 1);
+ else
+ elink_umac_enable(params, vars, 0);
+ } else {
+ vars->line_speed = ELINK_SPEED_10000;
+ vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
+ if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
+ elink_emac_enable(params, vars, 1);
+ else
+ elink_emac_enable(params, vars, 0);
+ }
+ vars->link_up = 1;
+ if (CHIP_IS_E1x(sc))
+ elink_pbf_update(params, vars->flow_ctrl,
+ vars->line_speed);
+ /* Disable drain */
REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
+
+ /* Update shared memory */
+ elink_update_mng(params, vars->link_status);
+ return ELINK_STATUS_OK;
+}
+#endif
+static void elink_init_bmac_loopback(struct elink_params *params,
+ struct elink_vars *vars)
+{
+ struct bnx2x_softc *sc = params->sc;
+ vars->link_up = 1;
+ vars->line_speed = ELINK_SPEED_10000;
+ vars->duplex = DUPLEX_FULL;
+ vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
+ vars->mac_type = ELINK_MAC_TYPE_BMAC;
+
+ vars->phy_flags = PHY_XGXS_FLAG;
+
+ elink_xgxs_deassert(params);
+
+ /* Set bmac loopback */
+ elink_bmac_enable(params, vars, 1, 1);
+
+ REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
}
static void elink_init_emac_loopback(struct elink_params *params,
struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
- vars->link_up = 1;
- vars->line_speed = ELINK_SPEED_1000;
- vars->duplex = DUPLEX_FULL;
- vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
- vars->mac_type = ELINK_MAC_TYPE_EMAC;
+ vars->link_up = 1;
+ vars->line_speed = ELINK_SPEED_1000;
+ vars->duplex = DUPLEX_FULL;
+ vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
+ vars->mac_type = ELINK_MAC_TYPE_EMAC;
- vars->phy_flags = PHY_XGXS_FLAG;
+ vars->phy_flags = PHY_XGXS_FLAG;
- elink_xgxs_deassert(params);
- /* Set bmac loopback */
- elink_emac_enable(params, vars, 1);
- elink_emac_program(params, vars);
- REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
+ elink_xgxs_deassert(params);
+ /* Set bmac loopback */
+ elink_emac_enable(params, vars, 1);
+ elink_emac_program(params, vars);
+ REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
}
static void elink_init_xmac_loopback(struct elink_params *params,
@@ -11755,8 +13815,9 @@ static void elink_init_xmac_loopback(struct elink_params *params,
*/
elink_set_aer_mmd(params, ¶ms->phy[0]);
elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
- params->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY],
- params);
+ params->phy[ELINK_INT_PHY].config_loopback(
+ ¶ms->phy[ELINK_INT_PHY],
+ params);
elink_xmac_enable(params, vars, 1);
REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
@@ -11818,12 +13879,11 @@ static void elink_init_xgxs_loopback(struct elink_params *params,
/* Set external phy loopback */
uint8_t phy_index;
for (phy_index = ELINK_EXT_PHY1;
- phy_index < params->num_phys; phy_index++)
+ phy_index < params->num_phys; phy_index++)
if (params->phy[phy_index].config_loopback)
- params->phy[phy_index].config_loopback(¶ms->
- phy
- [phy_index],
- params);
+ params->phy[phy_index].config_loopback(
+ ¶ms->phy[phy_index],
+ params);
}
REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
@@ -11840,12 +13900,14 @@ void elink_set_rx_filter(struct elink_params *params, uint8_t en)
val |= en * 0x20;
REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val);
- REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3);
+ if (!CHIP_IS_E1(sc)) {
+ REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4,
+ en * 0x3);
+ }
REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
NIG_REG_LLH0_BRB1_NOT_MCP), en);
}
-
static elink_status_t elink_avoid_link_flap(struct elink_params *params,
struct elink_vars *vars)
{
@@ -11853,6 +13915,7 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,
uint32_t dont_clear_stat, lfa_sts;
struct bnx2x_softc *sc = params->sc;
+ elink_set_mdio_emac_per_phy(sc, params);
/* Sync the link parameters */
elink_link_status_update(params, vars);
@@ -11864,7 +13927,7 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,
for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
struct elink_phy *phy = ¶ms->phy[phy_idx];
if (phy->phy_specific_func) {
- PMD_DRV_LOG(DEBUG, sc, "Calling PHY specific func");
+ ELINK_DEBUG_P0(sc, "Calling PHY specific func");
phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
}
if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
@@ -11873,7 +13936,8 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params,
elink_verify_sfp_module(phy, params);
}
lfa_sts = REG_RD(sc, params->lfa_base +
- offsetof(struct shmem_lfa, lfa_sts));
+ offsetof(struct shmem_lfa,
+ lfa_sts));
dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
@@ -11984,13 +14048,12 @@ elink_status_t elink_phy_init(struct elink_params *params,
{
int lfa_status;
struct bnx2x_softc *sc = params->sc;
- PMD_DRV_LOG(DEBUG, sc, "Phy Initialization started");
- PMD_DRV_LOG(DEBUG, sc, "(1) req_speed %d, req_flowctrl %d",
- params->req_line_speed[0], params->req_flow_ctrl[0]);
- PMD_DRV_LOG(DEBUG, sc, "(2) req_speed %d, req_flowctrl %d",
- params->req_line_speed[1], params->req_flow_ctrl[1]);
- PMD_DRV_LOG(DEBUG, sc,
- "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
+ ELINK_DEBUG_P0(sc, "Phy Initialization started");
+ ELINK_DEBUG_P2(sc, "(1) req_speed %d, req_flowctrl %d",
+ params->req_line_speed[0], params->req_flow_ctrl[0]);
+ ELINK_DEBUG_P2(sc, "(2) req_speed %d, req_flowctrl %d",
+ params->req_line_speed[1], params->req_flow_ctrl[1]);
+ ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
vars->link_status = 0;
vars->phy_link_up = 0;
vars->link_up = 0;
@@ -12003,17 +14066,33 @@ elink_status_t elink_phy_init(struct elink_params *params,
params->link_flags = ELINK_PHY_INITIALIZED;
/* Driver opens NIG-BRB filters */
elink_set_rx_filter(params, 1);
+ elink_chng_link_count(params, 1);
/* Check if link flap can be avoided */
lfa_status = elink_check_lfa(params);
+ ELINK_DEBUG_P3(sc, " params : port = %x, loopback_mode = %x req_duplex = %x",
+ params->port, params->loopback_mode,
+ params->req_duplex[0]);
+ ELINK_DEBUG_P3(sc, " params : switch_cfg = %x, lane_config = %x req_duplex[1] = %x",
+ params->switch_cfg, params->lane_config,
+ params->req_duplex[1]);
+ ELINK_DEBUG_P3(sc, " params : chip_id = %x, feature_config_flags = %x, num_phys = %x",
+ params->chip_id, params->feature_config_flags,
+ params->num_phys);
+ ELINK_DEBUG_P3(sc, " params : rsrv = %x, eee_mode = %x, hw_led_mode = %x",
+ params->rsrv, params->eee_mode, params->hw_led_mode);
+ ELINK_DEBUG_P3(sc, " params : multi_phy = %x, req_fc_auto_adv = %x, link_flags = %x",
+ params->multi_phy_config, params->req_fc_auto_adv,
+ params->link_flags);
+ ELINK_DEBUG_P2(sc, " params : lfa_base = %x, link_attr = %x",
+ params->lfa_base, params->link_attr_sync);
if (lfa_status == 0) {
- PMD_DRV_LOG(DEBUG, sc,
- "Link Flap Avoidance in progress");
+ ELINK_DEBUG_P0(sc, "Link Flap Avoidance in progress");
return elink_avoid_link_flap(params, vars);
}
- PMD_DRV_LOG(DEBUG, sc,
- "Cannot avoid link flap lfa_sta=0x%x", lfa_status);
+ ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x",
+ lfa_status);
elink_cannot_avoid_link_flap(params, vars, lfa_status);
/* Disable attentions */
@@ -12022,20 +14101,34 @@ elink_status_t elink_phy_init(struct elink_params *params,
ELINK_NIG_MASK_XGXS0_LINK10G |
ELINK_NIG_MASK_SERDES0_LINK_STATUS |
ELINK_NIG_MASK_MI_INT));
+#ifdef ELINK_INCLUDE_EMUL
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))
+#endif
- elink_emac_init(params);
+ elink_emac_init(params, vars);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
vars->link_status |= LINK_STATUS_PFC_ENABLED;
- if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {
- PMD_DRV_LOG(DEBUG, sc, "No phy found for initialization !!");
+ if ((params->num_phys == 0) &&
+ !CHIP_REV_IS_SLOW(sc)) {
+ ELINK_DEBUG_P0(sc, "No phy found for initialization !!");
return ELINK_STATUS_ERROR;
}
set_phy_vars(params, vars);
- PMD_DRV_LOG(DEBUG, sc, "Num of phys on board: %d", params->num_phys);
-
+ ELINK_DEBUG_P1(sc, "Num of phys on board: %d", params->num_phys);
+#ifdef ELINK_INCLUDE_FPGA
+ if (CHIP_REV_IS_FPGA(sc)) {
+ return elink_init_fpga(params, vars);
+ } else
+#endif
+#ifdef ELINK_INCLUDE_EMUL
+ if (CHIP_REV_IS_EMUL(sc)) {
+ return elink_init_emul(params, vars);
+ } else
+#endif
switch (params->loopback_mode) {
case ELINK_LOOPBACK_BMAC:
elink_init_bmac_loopback(params, vars);
@@ -12071,15 +14164,16 @@ elink_status_t elink_phy_init(struct elink_params *params,
return ELINK_STATUS_OK;
}
-static elink_status_t elink_link_reset(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t reset_ext_phy)
+elink_status_t elink_link_reset(struct elink_params *params,
+ struct elink_vars *vars,
+ uint8_t reset_ext_phy)
{
struct bnx2x_softc *sc = params->sc;
uint8_t phy_index, port = params->port, clear_latch_ind = 0;
- PMD_DRV_LOG(DEBUG, sc, "Resetting the link of port %d", port);
+ ELINK_DEBUG_P1(sc, "Resetting the link of port %d", port);
/* Disable attentions */
vars->link_status = 0;
+ elink_chng_link_count(params, 1);
elink_update_mng(params, vars->link_status);
vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
SHMEM_EEE_ACTIVE_BIT);
@@ -12098,12 +14192,24 @@ static elink_status_t elink_link_reset(struct elink_params *params,
REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
}
- if (!CHIP_IS_E3(sc))
- elink_set_bmac_rx(sc, port, 0);
- if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {
- elink_set_xmac_rxtx(params, 0);
- elink_set_umac_rxtx(params, 0);
- }
+
+#ifdef ELINK_INCLUDE_EMUL
+ /* Stop BigMac rx */
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))
+#endif
+ if (!CHIP_IS_E3(sc))
+ elink_set_bmac_rx(sc, params->chip_id, port, 0);
+#ifdef ELINK_INCLUDE_EMUL
+ /* Stop XMAC/UMAC rx */
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))
+#endif
+ if (CHIP_IS_E3(sc) &&
+ !CHIP_REV_IS_FPGA(sc)) {
+ elink_set_xmac_rxtx(params, 0);
+ elink_set_umac_rxtx(params, 0);
+ }
/* Disable emac */
if (!CHIP_IS_E3(sc))
REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
@@ -12112,20 +14218,19 @@ static elink_status_t elink_link_reset(struct elink_params *params,
/* The PHY reset is controlled by GPIO 1
* Hold it as vars low
*/
- /* Clear link led */
+ /* Clear link led */
elink_set_mdio_emac_per_phy(sc, params);
elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
- phy_index++) {
+ phy_index++) {
if (params->phy[phy_index].link_reset) {
elink_set_aer_mmd(params,
¶ms->phy[phy_index]);
- params->phy[phy_index].link_reset(¶ms->
- phy
- [phy_index],
- params);
+ params->phy[phy_index].link_reset(
+ ¶ms->phy[phy_index],
+ params);
}
if (params->phy[phy_index].flags &
ELINK_FLAGS_REARM_LATCH_SIGNAL)
@@ -12139,11 +14244,12 @@ static elink_status_t elink_link_reset(struct elink_params *params,
elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,
1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
}
+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
+ if (!CHIP_REV_IS_SLOW(sc))
+#endif
if (params->phy[ELINK_INT_PHY].link_reset)
- params->phy[ELINK_INT_PHY].link_reset(¶ms->
- phy
- [ELINK_INT_PHY],
- params);
+ params->phy[ELINK_INT_PHY].link_reset(
+ ¶ms->phy[ELINK_INT_PHY], params);
/* Disable nig ingress interface */
if (!CHIP_IS_E3(sc)) {
@@ -12153,8 +14259,8 @@ static elink_status_t elink_link_reset(struct elink_params *params,
REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);
REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);
} else {
- uint32_t xmac_base =
- (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
+ uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 :
+ GRCBASE_XMAC0;
elink_set_xumac_nig(params, 0, 0);
if (REG_RD(sc, MISC_REG_RESET_REG_2) &
MISC_REGISTERS_RESET_REG_2_XMAC)
@@ -12165,9 +14271,8 @@ static elink_status_t elink_link_reset(struct elink_params *params,
vars->phy_flags = 0;
return ELINK_STATUS_OK;
}
-
-elink_status_t elink_lfa_reset(struct elink_params * params,
- struct elink_vars * vars)
+elink_status_t elink_lfa_reset(struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
vars->link_up = 0;
@@ -12186,13 +14291,13 @@ elink_status_t elink_lfa_reset(struct elink_params * params,
* are passed.
*/
if (!CHIP_IS_E3(sc))
- elink_set_bmac_rx(sc, params->port, 0);
+ elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
if (CHIP_IS_E3(sc)) {
elink_set_xmac_rxtx(params, 0);
elink_set_umac_rxtx(params, 0);
}
- /* Wait 10ms for the pipe to clean up */
+ /* Wait 10ms for the pipe to clean up*/
DELAY(1000 * 10);
/* Clean the NIG-BRB using the network filters in a way that will
@@ -12207,7 +14312,7 @@ elink_status_t elink_lfa_reset(struct elink_params * params,
* minimum management protocol down time.
*/
if (!CHIP_IS_E3(sc))
- elink_set_bmac_rx(sc, params->port, 1);
+ elink_set_bmac_rx(sc, params->chip_id, params->port, 1);
if (CHIP_IS_E3(sc)) {
elink_set_xmac_rxtx(params, 1);
@@ -12222,10 +14327,10 @@ elink_status_t elink_lfa_reset(struct elink_params * params,
/* Common function */
/****************************************************************************/
static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint8_t phy_index,
- __rte_unused uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[],
+ uint8_t phy_index,
+ __rte_unused uint32_t chip_id)
{
struct elink_phy phy[PORT_MAX];
struct elink_phy *phy_blk[PORT_MAX];
@@ -12233,8 +14338,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
int8_t port = 0;
int8_t port_of_path = 0;
uint32_t swap_val, swap_override;
- swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
- swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
+ swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
+ swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
port ^= (swap_val && swap_override);
elink_ext_phy_hw_reset(sc, port);
/* PART1 - Reset both phys */
@@ -12255,7 +14360,7 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port_of_path, &phy[port]) !=
ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate_phy failed");
+ ELINK_DEBUG_P0(sc, "populate_phy failed");
return ELINK_STATUS_ERROR;
}
/* Disable attentions */
@@ -12270,11 +14375,14 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
* to write to access its registers
*/
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
+ MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+ port);
/* Reset the phy */
elink_cl45_write(sc, &phy[port],
- MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL,
+ 1 << 15);
}
/* Add delay of 150ms after reset */
@@ -12295,8 +14403,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
else
port_of_path = 0;
- PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
- phy_blk[port]->addr);
+ ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x",
+ phy_blk[port]->addr);
if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
port_of_path))
return ELINK_STATUS_ERROR;
@@ -12309,7 +14417,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
/* Phase1 of TX_POWER_DOWN reset */
elink_cl45_write(sc, phy_blk[port],
MDIO_PMA_DEVAD,
- MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));
+ MDIO_PMA_REG_TX_POWER_DOWN,
+ (val | 1 << 10));
}
/* Toggle Transmitter: Power down and then up with 600ms delay
@@ -12326,9 +14435,9 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
MDIO_PMA_REG_TX_POWER_DOWN, &val);
elink_cl45_write(sc, phy_blk[port],
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_TX_POWER_DOWN,
- (val & (~(1 << 10))));
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_TX_POWER_DOWN,
+ (val & (~(1 << 10))));
DELAY(1000 * 15);
/* Read modify write the SPI-ROM version select register */
@@ -12341,16 +14450,15 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
/* set GPIO2 back to LOW */
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
- MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+ MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
}
return ELINK_STATUS_OK;
}
-
static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint8_t phy_index,
- __rte_unused uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[],
+ uint8_t phy_index,
+ __rte_unused uint32_t chip_id)
{
uint32_t val;
int8_t port;
@@ -12359,8 +14467,8 @@ static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
/* Enable the module detection interrupt */
val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
val |= ((1 << MISC_REGISTERS_GPIO_3) |
- (1 <<
- (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
+ (1 << (MISC_REGISTERS_GPIO_3 +
+ MISC_REGISTERS_GPIO_PORT_SHIFT)));
REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
elink_ext_phy_hw_reset(sc, 0);
@@ -12378,33 +14486,33 @@ static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
}
/* Extract the ext phy address for the port */
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
- port, &phy) != ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
+ port, &phy) !=
+ ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc, "populate phy failed");
return ELINK_STATUS_ERROR;
}
- /* Reset phy */
+ /* Reset phy*/
elink_cl45_write(sc, &phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
+
/* Set fault module detected LED on */
elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
- MISC_REGISTERS_GPIO_HIGH, port);
+ MISC_REGISTERS_GPIO_HIGH,
+ port);
}
return ELINK_STATUS_OK;
}
-
static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,
- uint32_t shmem_base, uint8_t * io_gpio,
- uint8_t * io_port)
+ uint32_t shmem_base,
+ uint8_t *io_gpio, uint8_t *io_port)
{
uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
- offsetof(struct shmem_region,
- dev_info.
- port_hw_config[PORT_0].
- default_cfg));
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[PORT_0].default_cfg));
switch (phy_gpio_reset) {
case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
*io_gpio = 0;
@@ -12445,10 +14553,10 @@ static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,
}
static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint8_t phy_index,
- __rte_unused uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[],
+ uint8_t phy_index,
+ __rte_unused uint32_t chip_id)
{
int8_t port, reset_gpio;
uint32_t swap_val, swap_override;
@@ -12465,18 +14573,17 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
* Default is GPIO1, PORT1
*/
elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
- (uint8_t *) & reset_gpio,
- (uint8_t *) & port);
+ (uint8_t *)&reset_gpio, (uint8_t *)&port);
/* Calculate the port based on port swap */
port ^= (swap_val && swap_override);
- /* Initiate PHY reset */
+ /* Initiate PHY reset*/
elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
- port);
+ port);
DELAY(1000 * 1);
elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
- port);
+ port);
DELAY(1000 * 5);
@@ -12498,8 +14605,8 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
/* Extract the ext phy address for the port */
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port_of_path, &phy[port]) !=
- ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
+ ELINK_STATUS_OK) {
+ ELINK_DEBUG_P0(sc, "populate phy failed");
return ELINK_STATUS_ERROR;
}
/* disable attentions */
@@ -12510,6 +14617,7 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
ELINK_NIG_MASK_SERDES0_LINK_STATUS |
ELINK_NIG_MASK_MI_INT));
+
/* Reset the phy */
elink_cl45_write(sc, &phy[port],
MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
@@ -12530,25 +14638,25 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
port_of_path = port;
else
port_of_path = 0;
- PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
- phy_blk[port]->addr);
+ ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x",
+ phy_blk[port]->addr);
if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
port_of_path))
return ELINK_STATUS_ERROR;
/* Disable PHY transmitter output */
elink_cl45_write(sc, phy_blk[port],
- MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1);
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_TX_DISABLE, 1);
}
return ELINK_STATUS_OK;
}
static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- __rte_unused uint32_t
- shmem2_base_path[],
- __rte_unused uint8_t
- phy_index, uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ __rte_unused uint32_t shmem2_base_path[],
+ __rte_unused uint8_t phy_index,
+ uint32_t chip_id)
{
uint8_t reset_gpios;
reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
@@ -12557,17 +14665,15 @@ static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
DELAY(10);
elink_cb_gpio_mult_write(sc, reset_gpios,
MISC_REGISTERS_GPIO_OUTPUT_HIGH);
- PMD_DRV_LOG(DEBUG, sc,
- "84833 reset pulse on pin values 0x%x", reset_gpios);
+ ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x",
+ reset_gpios);
return ELINK_STATUS_OK;
}
-
static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint8_t phy_index,
- uint32_t ext_phy_type,
- uint32_t chip_id)
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[],
+ uint8_t phy_index,
+ uint32_t ext_phy_type, uint32_t chip_id)
{
elink_status_t rc = ELINK_STATUS_OK;
@@ -12595,44 +14701,50 @@ static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858:
/* GPIO3's are linked, and so both need to be toggled
* to obtain required 2us pulse.
*/
rc = elink_84833_common_init_phy(sc, shmem_base_path,
- shmem2_base_path,
- phy_index, chip_id);
+ shmem2_base_path,
+ phy_index, chip_id);
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
rc = ELINK_STATUS_ERROR;
break;
default:
- PMD_DRV_LOG(DEBUG, sc,
- "ext_phy 0x%x common init not required",
- ext_phy_type);
+ ELINK_DEBUG_P1(sc,
+ "ext_phy 0x%x common init not required",
+ ext_phy_type);
break;
}
if (rc != ELINK_STATUS_OK)
- elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
- // " Port %d",
+ elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0);
+ /* "Warning: PHY was not initialized,"
+ * " Port %d",
+ */
return rc;
}
-elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
- uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[],
- uint32_t chip_id,
- __rte_unused uint8_t one_port_enabled)
+elink_status_t elink_common_init_phy(struct bnx2x_softc *sc,
+ uint32_t shmem_base_path[],
+ uint32_t shmem2_base_path[], uint32_t chip_id,
+ __rte_unused uint8_t one_port_enabled)
{
elink_status_t rc = ELINK_STATUS_OK;
uint32_t phy_ver, val;
uint8_t phy_index = 0;
uint32_t ext_phy_type, ext_phy_config;
+#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
+ if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))
+ return ELINK_STATUS_OK;
+#endif
- elink_set_mdio_clk(sc, GRCBASE_EMAC0);
- elink_set_mdio_clk(sc, GRCBASE_EMAC1);
- PMD_DRV_LOG(DEBUG, sc, "Begin common phy init");
+ elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0);
+ elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1);
+ ELINK_DEBUG_P0(sc, "Begin common phy init");
if (CHIP_IS_E3(sc)) {
/* Enable EPIO */
val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
@@ -12643,14 +14755,14 @@ elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
offsetof(struct shmem_region,
port_mb[PORT_0].ext_phy_fw_version));
if (phy_ver) {
- PMD_DRV_LOG(DEBUG, sc, "Not doing common init; phy ver is 0x%x",
- phy_ver);
+ ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x",
+ phy_ver);
return ELINK_STATUS_OK;
}
/* Read the ext_phy_type for arbitrary port(0) */
for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
- phy_index++) {
+ phy_index++) {
ext_phy_config = elink_get_ext_phy_config(sc,
shmem_base_path[0],
phy_index, 0);
@@ -12673,10 +14785,9 @@ static void elink_check_over_curr(struct elink_params *params,
cfg_pin = (REG_RD(sc, params->shmem_base +
offsetof(struct shmem_region,
- dev_info.port_hw_config[port].
- e3_cmn_pin_cfg1)) &
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
- PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
+ PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
/* Ignore check if no external input PIN available */
if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
@@ -12684,13 +14795,16 @@ static void elink_check_over_curr(struct elink_params *params,
if (!pin_val) {
if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
- elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
- // " been detected and the power to "
- // "that SFP+ module has been removed"
- // " to prevent failure of the card."
- // " Please remove the SFP+ module and"
- // " restart the system to clear this"
- // " error.",
+ elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT,
+ params->port);
+ /* "Error: Power fault on Port %d has"
+ * " been detected and the power to "
+ * "that SFP+ module has been removed"
+ * " to prevent failure of the card."
+ * " Please remove the SFP+ module and"
+ * " restart the system to clear this"
+ * " error.",
+ */
vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
elink_warpcore_power_module(params, 0);
}
@@ -12700,9 +14814,9 @@ static void elink_check_over_curr(struct elink_params *params,
/* Returns 0 if no change occurred since last check; 1 otherwise. */
static uint8_t elink_analyze_link_error(struct elink_params *params,
- struct elink_vars *vars,
- uint32_t status, uint32_t phy_flag,
- uint32_t link_flag, uint8_t notify)
+ struct elink_vars *vars, uint32_t status,
+ uint32_t phy_flag, uint32_t link_flag,
+ uint8_t notify)
{
struct bnx2x_softc *sc = params->sc;
/* Compare new value with previous value */
@@ -12715,16 +14829,20 @@ static uint8_t elink_analyze_link_error(struct elink_params *params,
/* If values differ */
switch (phy_flag) {
case PHY_HALF_OPEN_CONN_FLAG:
- PMD_DRV_LOG(DEBUG, sc, "Analyze Remote Fault");
+ ELINK_DEBUG_P0(sc, "Analyze Remote Fault");
break;
case PHY_SFP_TX_FAULT_FLAG:
- PMD_DRV_LOG(DEBUG, sc, "Analyze TX Fault");
+ ELINK_DEBUG_P0(sc, "Analyze TX Fault");
break;
default:
- PMD_DRV_LOG(DEBUG, sc, "Analyze UNKNOWN");
+ ELINK_DEBUG_P0(sc, "Analyze UNKNOWN");
}
- PMD_DRV_LOG(DEBUG, sc, "Link changed:[%x %x]->%x", vars->link_up,
- old_status, status);
+ ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x", vars->link_up,
+ old_status, status);
+
+ /* Do not touch the link in case physical link down */
+ if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
+ return 1;
/* a. Update shmem->link_status accordingly
* b. Update elink_vars->link_up
@@ -12767,17 +14885,18 @@ static uint8_t elink_analyze_link_error(struct elink_params *params,
}
/******************************************************************************
-* Description:
-* This function checks for half opened connection change indication.
-* When such change occurs, it calls the elink_analyze_link_error
-* to check if Remote Fault is set or cleared. Reception of remote fault
-* status message in the MAC indicates that the peer's MAC has detected
-* a fault, for example, due to break in the TX side of fiber.
-*
-******************************************************************************/
-static elink_status_t elink_check_half_open_conn(struct elink_params *params,
- struct elink_vars *vars,
- uint8_t notify)
+ * Description:
+ * This function checks for half opened connection change indication.
+ * When such change occurs, it calls the elink_analyze_link_error
+ * to check if Remote Fault is set or cleared. Reception of remote fault
+ * status message in the MAC indicates that the peer's MAC has detected
+ * a fault, for example, due to break in the TX side of fiber.
+ *
+ ******************************************************************************/
+static
+elink_status_t elink_check_half_open_conn(struct elink_params *params,
+ struct elink_vars *vars,
+ uint8_t notify)
{
struct bnx2x_softc *sc = params->sc;
uint32_t lss_status = 0;
@@ -12789,7 +14908,7 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params,
if (CHIP_IS_E3(sc) &&
(REG_RD(sc, MISC_REG_RESET_REG_2) &
- (MISC_REGISTERS_RESET_REG_2_XMAC))) {
+ (MISC_REGISTERS_RESET_REG_2_XMAC))) {
/* Check E3 XMAC */
/* Note that link speed cannot be queried here, since it may be
* zero while link is down. In case UMAC is active, LSS will
@@ -12814,7 +14933,7 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params,
uint32_t lss_status_reg;
uint32_t wb_data[2];
mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
- NIG_REG_INGRESS_BMAC0_MEM;
+ NIG_REG_INGRESS_BMAC0_MEM;
/* Read BIGMAC_REGISTER_RX_LSS_STATUS */
if (CHIP_IS_E2(sc))
lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
@@ -12830,7 +14949,6 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params,
}
return ELINK_STATUS_OK;
}
-
static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
struct elink_params *params,
struct elink_vars *vars)
@@ -12841,15 +14959,12 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
/* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
- dev_info.
- port_hw_config
- [port].
- e3_cmn_pin_cfg)) &
+ dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
PORT_HW_CFG_E3_TX_FAULT_MASK) >>
- PORT_HW_CFG_E3_TX_FAULT_SHIFT;
+ PORT_HW_CFG_E3_TX_FAULT_SHIFT;
if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
- PMD_DRV_LOG(DEBUG, sc, "Failed to read pin 0x%02x", cfg_pin);
+ ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x", cfg_pin);
return;
}
@@ -12871,24 +14986,25 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
/* If module is unapproved, led should be on regardless */
if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
- PMD_DRV_LOG(DEBUG, sc, "Change TX_Fault LED: ->%x",
- led_mode);
+ ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x",
+ led_mode);
elink_set_e3_module_fault_led(params, led_mode);
}
}
}
-
static void elink_kr2_recovery(struct elink_params *params,
- struct elink_vars *vars, struct elink_phy *phy)
+ struct elink_vars *vars,
+ struct elink_phy *phy)
{
- PMD_DRV_LOG(DEBUG, params->sc, "KR2 recovery");
-
+ struct bnx2x_softc *sc = params->sc;
+ ELINK_DEBUG_P0(sc, "KR2 recovery");
elink_warpcore_enable_AN_KR2(phy, params, vars);
elink_warpcore_restart_AN_KR(phy, params);
}
static void elink_check_kr2_wa(struct elink_params *params,
- struct elink_vars *vars, struct elink_phy *phy)
+ struct elink_vars *vars,
+ struct elink_phy *phy)
{
struct bnx2x_softc *sc = params->sc;
uint16_t base_page, next_page, not_kr2_device, lane;
@@ -12906,14 +15022,14 @@ static void elink_check_kr2_wa(struct elink_params *params,
sigdet = elink_warpcore_get_sigdet(phy, params);
if (!sigdet) {
- if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
+ if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
elink_kr2_recovery(params, vars, phy);
- PMD_DRV_LOG(DEBUG, sc, "No sigdet");
+ ELINK_DEBUG_P0(sc, "No sigdet");
}
return;
}
- lane = elink_get_warpcore_lane(params);
+ lane = elink_get_warpcore_lane(phy, params);
CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
MDIO_AER_BLOCK_AER_REG, lane);
elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
@@ -12924,9 +15040,9 @@ static void elink_check_kr2_wa(struct elink_params *params,
/* CL73 has not begun yet */
if (base_page == 0) {
- if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
+ if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
elink_kr2_recovery(params, vars, phy);
- PMD_DRV_LOG(DEBUG, sc, "No BP");
+ ELINK_DEBUG_P0(sc, "No BP");
}
return;
}
@@ -12940,10 +15056,10 @@ static void elink_check_kr2_wa(struct elink_params *params,
((next_page & 0xe0) == 0x20))));
/* In case KR2 is already disabled, check if we need to re-enable it */
- if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
+ if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
if (!not_kr2_device) {
- PMD_DRV_LOG(DEBUG, sc, "BP=0x%x, NP=0x%x", base_page,
- next_page);
+ ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x", base_page,
+ next_page);
elink_kr2_recovery(params, vars, phy);
}
return;
@@ -12951,8 +15067,7 @@ static void elink_check_kr2_wa(struct elink_params *params,
/* KR2 is enabled, but not KR2 device */
if (not_kr2_device) {
/* Disable KR2 on both lanes */
- PMD_DRV_LOG(DEBUG, sc,
- "BP=0x%x, NP=0x%x", base_page, next_page);
+ ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x", base_page, next_page);
elink_disable_kr2(params, vars, phy);
/* Restart AN on leading lane */
elink_warpcore_restart_AN_KR(phy, params);
@@ -12968,9 +15083,8 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)
if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
if (elink_check_half_open_conn(params, vars, 1) !=
- ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "Fault detection failed");
- }
+ ELINK_STATUS_OK)
+ ELINK_DEBUG_P0(sc, "Fault detection failed");
break;
}
}
@@ -12978,22 +15092,24 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)
if (CHIP_IS_E3(sc)) {
struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
elink_set_aer_mmd(params, phy);
- if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
- (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
+ if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
+ (phy->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
+ (phy->req_line_speed == ELINK_SPEED_20000))
elink_check_kr2_wa(params, vars, phy);
elink_check_over_curr(params, vars);
if (vars->rx_tx_asic_rst)
elink_warpcore_config_runtime(phy, params, vars);
if ((REG_RD(sc, params->shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[params->port].
- default_cfg))
- & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
+ offsetof(struct shmem_region, dev_info.
+ port_hw_config[params->port].default_cfg))
+ & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
PORT_HW_CFG_NET_SERDES_IF_SFI) {
- if (elink_is_sfp_module_plugged(params)) {
+ if (elink_is_sfp_module_plugged(phy, params)) {
elink_sfp_tx_fault_detection(phy, params, vars);
- } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) {
+ } else if (vars->link_status &
+ LINK_STATUS_SFP_TX_FAULT) {
/* Clean trail, interrupt corrects the leds */
vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
@@ -13005,17 +15121,18 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars)
}
uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,
- uint32_t shmem_base,
- uint32_t shmem2_base, uint8_t port)
+ uint32_t shmem_base,
+ uint32_t shmem2_base,
+ uint8_t port)
{
uint8_t phy_index, fan_failure_det_req = 0;
struct elink_phy phy;
for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
- phy_index++) {
+ phy_index++) {
if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
port, &phy)
!= ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
+ ELINK_DEBUG_P0(sc, "populate phy failed");
return 0;
}
fan_failure_det_req |= (phy.flags &
@@ -13035,24 +15152,27 @@ void elink_hw_reset_phy(struct elink_params *params)
ELINK_NIG_MASK_SERDES0_LINK_STATUS |
ELINK_NIG_MASK_MI_INT));
- for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
+ for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
+ phy_index++) {
if (params->phy[phy_index].hw_reset) {
- params->phy[phy_index].hw_reset(¶ms->phy[phy_index],
- params);
+ params->phy[phy_index].hw_reset(
+ ¶ms->phy[phy_index],
+ params);
params->phy[phy_index] = phy_null;
}
}
}
void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
- __rte_unused uint32_t chip_id, uint32_t shmem_base,
- uint32_t shmem2_base, uint8_t port)
+ uint32_t chip_id, uint32_t shmem_base,
+ uint32_t shmem2_base,
+ uint8_t port)
{
uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
uint32_t val;
uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
if (CHIP_IS_E3(sc)) {
- if (elink_get_mod_abs_int_cfg(sc,
+ if (elink_get_mod_abs_int_cfg(sc, chip_id,
shmem_base,
port,
&gpio_num,
@@ -13061,11 +15181,11 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
} else {
struct elink_phy phy;
for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
- phy_index++) {
+ phy_index++) {
if (elink_populate_phy(sc, phy_index, shmem_base,
shmem2_base, port, &phy)
!= ELINK_STATUS_OK) {
- PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
+ ELINK_DEBUG_P0(sc, "populate phy failed");
return;
}
if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {
@@ -13088,15 +15208,15 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
gpio_port ^= (swap_val && swap_override);
vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
- (gpio_num + (gpio_port << 2));
+ (gpio_num + (gpio_port << 2));
sync_offset = shmem_base +
- offsetof(struct shmem_region,
- dev_info.port_hw_config[port].aeu_int_mask);
+ offsetof(struct shmem_region,
+ dev_info.port_hw_config[port].aeu_int_mask);
REG_WR(sc, sync_offset, vars->aeu_int_mask);
- PMD_DRV_LOG(DEBUG, sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
- gpio_num, gpio_port, vars->aeu_int_mask);
+ ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
+ gpio_num, gpio_port, vars->aeu_int_mask);
if (port == 0)
offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
diff --git a/drivers/net/bnx2x/elink.h b/drivers/net/bnx2x/elink.h
index 40000c2..c8b08bc 100644
--- a/drivers/net/bnx2x/elink.h
+++ b/drivers/net/bnx2x/elink.h
@@ -14,7 +14,7 @@
#ifndef ELINK_H
#define ELINK_H
-#define ELINK_DEBUG
+#include "bnx2x_logs.h"
@@ -29,6 +29,11 @@
extern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr);
extern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val);
+/* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/
+extern void elink_cb_reg_wb_write(struct bnx2x_softc *sc, uint32_t offset,
+ uint32_t *wb_write, uint16_t len);
+extern void elink_cb_reg_wb_read(struct bnx2x_softc *sc, uint32_t offset,
+ uint32_t *wb_write, uint16_t len);
/* mode - 0( LOW ) /1(HIGH)*/
extern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc,
@@ -45,6 +50,9 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
extern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param);
+/* Delay */
+extern void elink_cb_udelay(struct bnx2x_softc *sc, uint32_t microsecond);
+
/* This function is called every 1024 bytes downloading of phy firmware.
Driver can use it to print to screen indication for download progress */
extern void elink_cb_download_progress(struct bnx2x_softc *sc, uint32_t cur, uint32_t total);
@@ -69,6 +77,8 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
extern void elink_cb_event_log(struct bnx2x_softc *sc, const elink_log_id_t log_id, ...);
extern void elink_cb_load_warpcore_microcode(void);
+extern uint8_t elink_cb_path_id(struct bnx2x_softc *sc);
+
extern void elink_cb_notify_link_changed(struct bnx2x_softc *sc);
#define ELINK_EVENT_LOG_LEVEL_ERROR 1
@@ -78,6 +88,32 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
/* Debug prints */
+#ifdef ELINK_DEBUG
+
+extern void elink_cb_dbg(struct bnx2x_softc *sc, const char *fmt);
+extern void elink_cb_dbg1(struct bnx2x_softc *sc, const char *fmt,
+ uint32_t arg1);
+extern void elink_cb_dbg2(struct bnx2x_softc *sc, const char *fmt,
+ uint32_t arg1, uint32_t arg2);
+extern void elink_cb_dbg3(struct bnx2x_softc *sc, const char *fmt,
+ uint32_t arg1, uint32_t arg2,
+ uint32_t arg3);
+
+#define ELINK_DEBUG_P0(sc, fmt) elink_cb_dbg(sc, fmt)
+#define ELINK_DEBUG_P1(sc, fmt, arg1) elink_cb_dbg1(sc, fmt, arg1)
+#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) \
+ elink_cb_dbg2(sc, fmt, arg1, arg2)
+#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \
+ elink_cb_dbg3(sc, fmt, arg1, arg2, arg3)
+#else
+#define ELINK_DEBUG_P0(sc, fmt) PMD_DRV_LOG(DEBUG, sc, fmt)
+#define ELINK_DEBUG_P1(sc, fmt, arg1) \
+ PMD_DRV_LOG(DEBUG, sc, fmt, arg1)
+#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) \
+ PMD_DRV_LOG(DEBUG, sc, fmt, arg1, arg2)
+#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \
+ PMD_DRV_LOG(DEBUG, sc, fmt, arg1, arg2, arg3)
+#endif
/***********************************************************/
/* Defines */
@@ -126,9 +162,12 @@ extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
#define ELINK_SFP_EEPROM_DATE_SIZE 6
#define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
#define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1
-#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2)
+#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1 << 2)
#define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
#define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1
+#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR 0x60
+#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE 16
+
#define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e
#define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f
@@ -199,7 +238,7 @@ typedef void (*link_reset_t)(struct elink_phy *phy,
struct elink_params *params);
typedef void (*config_loopback_t)(struct elink_phy *phy,
struct elink_params *params);
-typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);
+typedef elink_status_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);
typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);
typedef void (*set_link_led_t)(struct elink_phy *phy,
struct elink_params *params, uint8_t mode);
@@ -219,23 +258,23 @@ struct elink_phy {
uint8_t def_md_devad;
uint16_t flags;
/* No Over-Current detection */
-#define ELINK_FLAGS_NOC (1<<1)
+#define ELINK_FLAGS_NOC (1 << 1)
/* Fan failure detection required */
-#define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2)
+#define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1 << 2)
/* Initialize first the XGXS and only then the phy itself */
-#define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3)
-#define ELINK_FLAGS_WC_DUAL_MODE (1<<4)
-#define ELINK_FLAGS_4_PORT_MODE (1<<5)
-#define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6)
-#define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7)
-#define ELINK_FLAGS_MDC_MDIO_WA (1<<8)
-#define ELINK_FLAGS_DUMMY_READ (1<<9)
-#define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10)
-#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11)
-#define ELINK_FLAGS_TX_ERROR_CHECK (1<<12)
-#define ELINK_FLAGS_EEE (1<<13)
-#define ELINK_FLAGS_TEMPERATURE (1<<14)
-#define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15)
+#define ELINK_FLAGS_INIT_XGXS_FIRST (1 << 3)
+#define ELINK_FLAGS_WC_DUAL_MODE (1 << 4)
+#define ELINK_FLAGS_4_PORT_MODE (1 << 5)
+#define ELINK_FLAGS_REARM_LATCH_SIGNAL (1 << 6)
+#define ELINK_FLAGS_SFP_NOT_APPROVED (1 << 7)
+#define ELINK_FLAGS_MDC_MDIO_WA (1 << 8)
+#define ELINK_FLAGS_DUMMY_READ (1 << 9)
+#define ELINK_FLAGS_MDC_MDIO_WA_B0 (1 << 10)
+#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1 << 11)
+#define ELINK_FLAGS_TX_ERROR_CHECK (1 << 12)
+#define ELINK_FLAGS_EEE (1 << 13)
+#define ELINK_FLAGS_TEMPERATURE (1 << 14)
+#define ELINK_FLAGS_MDC_MDIO_WA_G (1 << 15)
/* preemphasis values for the rx side */
uint16_t rx_preemphasis[4];
@@ -247,20 +286,22 @@ struct elink_phy {
uint32_t mdio_ctrl;
uint32_t supported;
-#define ELINK_SUPPORTED_10baseT_Half (1<<0)
-#define ELINK_SUPPORTED_10baseT_Full (1<<1)
-#define ELINK_SUPPORTED_100baseT_Half (1<<2)
-#define ELINK_SUPPORTED_100baseT_Full (1<<3)
-#define ELINK_SUPPORTED_1000baseT_Full (1<<4)
-#define ELINK_SUPPORTED_2500baseX_Full (1<<5)
-#define ELINK_SUPPORTED_10000baseT_Full (1<<6)
-#define ELINK_SUPPORTED_TP (1<<7)
-#define ELINK_SUPPORTED_FIBRE (1<<8)
-#define ELINK_SUPPORTED_Autoneg (1<<9)
-#define ELINK_SUPPORTED_Pause (1<<10)
-#define ELINK_SUPPORTED_Asym_Pause (1<<11)
-#define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21)
-#define ELINK_SUPPORTED_20000baseKR2_Full (1<<22)
+#define ELINK_SUPPORTED_10baseT_Half (1 << 0)
+#define ELINK_SUPPORTED_10baseT_Full (1 << 1)
+#define ELINK_SUPPORTED_100baseT_Half (1 << 2)
+#define ELINK_SUPPORTED_100baseT_Full (1 << 3)
+#define ELINK_SUPPORTED_1000baseT_Full (1 << 4)
+#define ELINK_SUPPORTED_2500baseX_Full (1 << 5)
+#define ELINK_SUPPORTED_10000baseT_Full (1 << 6)
+#define ELINK_SUPPORTED_TP (1 << 7)
+#define ELINK_SUPPORTED_FIBRE (1 << 8)
+#define ELINK_SUPPORTED_Autoneg (1 << 9)
+#define ELINK_SUPPORTED_Pause (1 << 10)
+#define ELINK_SUPPORTED_Asym_Pause (1 << 11)
+#define ELINK_SUPPORTED_1000baseKX_Full (1 << 17)
+#define ELINK_SUPPORTED_10000baseKR_Full (1 << 19)
+#define ELINK_SUPPORTED_20000baseMLD2_Full (1 << 21)
+#define ELINK_SUPPORTED_20000baseKR2_Full (1 << 22)
uint32_t media_type;
#define ELINK_ETH_PHY_UNSPECIFIED 0x0
@@ -353,17 +394,22 @@ struct elink_params {
/* features */
uint32_t feature_config_flags;
-#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
-#define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1)
-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
-#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
-#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
-#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
-#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12)
-#define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13)
-#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
+#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1 << 0)
+#define ELINK_FEATURE_CONFIG_PFC_ENABLED (1 << 1)
+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1 << 2)
+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1 << 3)
+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1 << 4)
+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1 << 5)
+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1 << 6)
+#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1 << 7)
+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1 << 8)
+#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1 << 9)
+#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1 << 10)
+#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1 << 11)
+#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1 << 12)
+#define ELINK_FEATURE_CONFIG_MT_SUPPORT (1 << 13)
+#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1 << 14)
+#define ELINK_FEATURE_CONFIG_DISABLE_PD (1 << 15)
/* Will be populated during common init */
struct elink_phy phy[ELINK_MAX_PHYS];
@@ -391,10 +437,10 @@ struct elink_params {
#define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
#define ELINK_EEE_MODE_NVRAM_MASK (0x3)
#define ELINK_EEE_MODE_TIMER_MASK (0xfffff)
-#define ELINK_EEE_MODE_OUTPUT_TIME (1<<28)
-#define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29)
-#define ELINK_EEE_MODE_ENABLE_LPI (1<<30)
-#define ELINK_EEE_MODE_ADV_LPI (1<<31)
+#define ELINK_EEE_MODE_OUTPUT_TIME (1 << 28)
+#define ELINK_EEE_MODE_OVERRIDE_NVRAM (1 << 29)
+#define ELINK_EEE_MODE_ENABLE_LPI (1 << 30)
+#define ELINK_EEE_MODE_ADV_LPI (1 << 31)
uint16_t hw_led_mode; /* part of the hw_config read from the shmem */
uint32_t multi_phy_config;
@@ -404,20 +450,23 @@ struct elink_params {
uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when
req_flow_ctrl is set to AUTO */
uint16_t link_flags;
-#define ELINK_LINK_FLAGS_INT_DISABLED (1<<0)
-#define ELINK_PHY_INITIALIZED (1<<1)
+#define ELINK_LINK_FLAGS_INT_DISABLED (1 << 0)
+#define ELINK_PHY_INITIALIZED (1 << 1)
uint32_t lfa_base;
+
+ /* The same definitions as the shmem2 parameter */
+ uint32_t link_attr_sync;
};
/* Output parameters */
struct elink_vars {
uint8_t phy_flags;
-#define PHY_XGXS_FLAG (1<<0)
-#define PHY_SGMII_FLAG (1<<1)
-#define PHY_PHYSICAL_LINK_FLAG (1<<2)
-#define PHY_HALF_OPEN_CONN_FLAG (1<<3)
-#define PHY_OVER_CURRENT_FLAG (1<<4)
-#define PHY_SFP_TX_FAULT_FLAG (1<<5)
+#define PHY_XGXS_FLAG (1 << 0)
+#define PHY_SGMII_FLAG (1 << 1)
+#define PHY_PHYSICAL_LINK_FLAG (1 << 2)
+#define PHY_HALF_OPEN_CONN_FLAG (1 << 3)
+#define PHY_OVER_CURRENT_FLAG (1 << 4)
+#define PHY_SFP_TX_FAULT_FLAG (1 << 5)
uint8_t mac_type;
#define ELINK_MAC_TYPE_NONE 0
@@ -448,8 +497,7 @@ struct elink_vars {
uint8_t rx_tx_asic_rst;
uint8_t turn_to_run_wc_rt;
uint16_t rsrv2;
- /* The same definitions as the shmem2 parameter */
- uint32_t link_attr_sync;
+
};
/***********************************************************/
@@ -460,14 +508,32 @@ struct elink_vars {
/* Reset the link. Should be called when driver or interface goes down
Before calling phy firmware upgrade, the reset_ext_phy should be set
to 0 */
+elink_status_t elink_link_reset(struct elink_params *params,
+ struct elink_vars *vars,
+ uint8_t reset_ext_phy);
elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
/* elink_link_update should be called upon link interrupt */
elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
+/* use the following phy functions to read/write from external_phy
+ * In order to use it to read/write internal phy registers, use
+ * ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
+ * the register
+ */
+elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
+ uint8_t devad, uint16_t reg, uint16_t *ret_val);
+
+elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
+ uint8_t devad, uint16_t reg, uint16_t val);
+
/* Reads the link_status from the shmem,
and update the link vars accordingly */
void elink_link_status_update(struct elink_params *input,
struct elink_vars *output);
+/* returns string representing the fw_version of the external phy */
+elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params,
+ uint8_t *version,
+ uint16_t len);
/* Set/Unset the led
Basically, the CLC takes care of the led for the link, but in case one needs
@@ -481,12 +547,34 @@ elink_status_t elink_set_led(struct elink_params *params,
#define ELINK_LED_MODE_FRONT_PANEL_OFF 3
/* elink_handle_module_detect_int should be called upon module detection
- interrupt */
+ * interrupt
+ */
void elink_handle_module_detect_int(struct elink_params *params);
+/* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up,
+ * otherwise link is down
+ */
+elink_status_t elink_test_link(struct elink_params *params,
+ struct elink_vars *vars,
+ uint8_t is_serdes);
+
+
/* One-time initialization for external phy after power up */
elink_status_t elink_common_init_phy(struct bnx2x_softc *sc, uint32_t shmem_base_path[],
- uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);
+ uint32_t shmem2_base_path[], uint32_t chip_id,
+ uint8_t one_port_enabled);
+
+/* Reset the external PHY using GPIO */
+void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port);
+
+/* Reset the external of SFX7101 */
+void elink_sfx7101_sp_sw_reset(struct bnx2x_softc *sc, struct elink_phy *phy);
+
+/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
+elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
+ struct elink_params *params, uint8_t dev_addr,
+ uint16_t addr, uint16_t byte_cnt,
+ uint8_t *o_buf);
void elink_hw_reset_phy(struct elink_params *params);
@@ -569,12 +657,42 @@ elink_status_t elink_update_pfc(struct elink_params *params,
struct elink_vars *vars,
struct elink_nig_brb_pfc_port_params *pfc_params);
+
+/* Used to configure the ETS to disable */
+elink_status_t elink_ets_disabled(struct elink_params *params,
+ struct elink_vars *vars);
+
+/* Used to configure the ETS to BW limited */
+void elink_ets_bw_limit(const struct elink_params *params,
+ const uint32_t cos0_bw,
+ const uint32_t cos1_bw);
+
+/* Used to configure the ETS to strict */
+elink_status_t elink_ets_strict(const struct elink_params *params,
+ const uint8_t strict_cos);
+
+
+/* Configure the COS to ETS according to BW and SP settings.*/
+elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
+ const struct elink_vars *vars,
+ struct elink_ets_params *ets_params);
+/* Read pfc statistic*/
+void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
+ uint32_t pfc_frames_sent[2],
+ uint32_t pfc_frames_received[2]);
void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
uint8_t port);
+/* elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
+ * struct elink_params *params);
+ */
void elink_period_func(struct elink_params *params, struct elink_vars *vars);
+/*elink_status_t elink_check_half_open_conn(struct elink_params *params,
+ * struct elink_vars *vars, uint8_t notify);
+ */
+
void elink_enable_pmd_tx(struct elink_params *params);
--
1.7.10.3
^ permalink raw reply [flat|nested] 13+ messages in thread* [dpdk-dev] [PATCH v2 3/5] net/bnx2x: fix to disable further interrupts
2018-09-19 21:59 [dpdk-dev] [PATCH 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
` (5 preceding siblings ...)
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 2/5] net/bnx2x: update link/PHY management Mody, Rasesh
@ 2018-09-29 5:42 ` Mody, Rasesh
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 4/5] net/bnx2x: fix call to link handling periodic function Mody, Rasesh
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 5/5] net/bnx2x: fix to add phy lock Mody, Rasesh
8 siblings, 0 replies; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-29 5:42 UTC (permalink / raw)
To: dev; +Cc: Mody, Rasesh, ferruh.yigit, Dept-Eng DPDK Dev, stable
Fix to disable further fastpath/slowpath interrupts. These will be
enabled again by their respective handlers
Fixes: 540a211084a7 ("bnx2x: driver core")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 93f8586..0225bea 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -4553,12 +4553,18 @@ int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
fp = &sc->fp[i];
mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
if (status & mask) {
+ /* acknowledge and disable further fastpath interrupts */
+ bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
+ 0, IGU_INT_DISABLE, 0);
bnx2x_handle_fp_tq(fp, scan_fp);
status &= ~mask;
}
}
if (unlikely(status & 0x1)) {
+ /* acknowledge and disable further slowpath interrupts */
+ bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
+ 0, IGU_INT_DISABLE, 0);
rc = bnx2x_handle_sp_tq(sc);
status &= ~0x1;
}
--
1.7.10.3
^ permalink raw reply [flat|nested] 13+ messages in thread* [dpdk-dev] [PATCH v2 4/5] net/bnx2x: fix call to link handling periodic function
2018-09-19 21:59 [dpdk-dev] [PATCH 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
` (6 preceding siblings ...)
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 3/5] net/bnx2x: fix to disable further interrupts Mody, Rasesh
@ 2018-09-29 5:42 ` Mody, Rasesh
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 5/5] net/bnx2x: fix to add phy lock Mody, Rasesh
8 siblings, 0 replies; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-29 5:42 UTC (permalink / raw)
To: dev; +Cc: Mody, Rasesh, ferruh.yigit, Dept-Eng DPDK Dev, stable
If link handling periodic function is allowed to be called in interrupt
context, the periodic function can get called too frequently and exhaust
the retry credits to check link status.
This change makes sure link handling periodic function is not called in
interrupt context.
Fixes: 540a211084a7 ("bnx2x: driver core")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x_ethdev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/bnx2x/bnx2x_ethdev.c b/drivers/net/bnx2x/bnx2x_ethdev.c
index ae2e60a..0057843 100644
--- a/drivers/net/bnx2x/bnx2x_ethdev.c
+++ b/drivers/net/bnx2x/bnx2x_ethdev.c
@@ -131,7 +131,9 @@ struct rte_bnx2x_xstats_name_off {
PMD_DEBUG_PERIODIC_LOG(INFO, sc, "Interrupt handled");
+ atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
bnx2x_interrupt_action(dev);
+ atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
rte_intr_enable(&sc->pci_dev->intr_handle);
}
--
1.7.10.3
^ permalink raw reply [flat|nested] 13+ messages in thread* [dpdk-dev] [PATCH v2 5/5] net/bnx2x: fix to add phy lock
2018-09-19 21:59 [dpdk-dev] [PATCH 1/5] net/bnx2x: fix logging to include dev name Mody, Rasesh
` (7 preceding siblings ...)
2018-09-29 5:42 ` [dpdk-dev] [PATCH v2 4/5] net/bnx2x: fix call to link handling periodic function Mody, Rasesh
@ 2018-09-29 5:42 ` Mody, Rasesh
8 siblings, 0 replies; 13+ messages in thread
From: Mody, Rasesh @ 2018-09-29 5:42 UTC (permalink / raw)
To: dev; +Cc: Mody, Rasesh, ferruh.yigit, Dept-Eng DPDK Dev, stable
This patch adds phy_lock, acquire/release the lock when performing
PHY transactions. Without this fix driver can run into synchronization
issues with management FW when modifying PHY settings.
Fixes: 540a211084a7 ("bnx2x: driver core")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x.c | 59 ++++++++++++++++++++++++++++++++++++-----
drivers/net/bnx2x/bnx2x.h | 7 +++++
drivers/net/bnx2x/ecore_reg.h | 1 +
3 files changed, 60 insertions(+), 7 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 0225bea..2797593 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -112,6 +112,7 @@ static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod);
+static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
static void bnx2x_link_report(struct bnx2x_softc *sc);
void bnx2x_link_status_update(struct bnx2x_softc *sc);
static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
@@ -198,7 +199,8 @@ static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
uint32_t hw_lock_control_reg;
int cnt;
- PMD_INIT_FUNC_TRACE(sc);
+ if (resource)
+ PMD_INIT_FUNC_TRACE(sc);
/* validate the resource is within range */
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
@@ -234,7 +236,8 @@ static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
DELAY(5000);
}
- PMD_DRV_LOG(NOTICE, sc, "Resource lock timeout!");
+ PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
+ resource, resource_bit);
return -1;
}
@@ -245,13 +248,14 @@ static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
int func = SC_FUNC(sc);
uint32_t hw_lock_control_reg;
- PMD_INIT_FUNC_TRACE(sc);
+ if (resource)
+ PMD_INIT_FUNC_TRACE(sc);
/* validate the resource is within range */
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
PMD_DRV_LOG(NOTICE, sc,
- "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
- resource);
+ "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
+ " resource_bit 0x%x", resource, resource_bit);
return -1;
}
@@ -275,6 +279,18 @@ static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
return 0;
}
+static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
+{
+ BNX2X_PHY_LOCK(sc);
+ bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
+}
+
+static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
+{
+ bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
+ BNX2X_PHY_UNLOCK(sc);
+}
+
/* copy command into DMAE command memory and set DMAE command Go */
void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
{
@@ -2903,7 +2919,7 @@ static void bnx2x_link_attn(struct bnx2x_softc *sc)
}
}
- bnx2x_link_report(sc);
+ bnx2x_link_report_locked(sc);
if (IS_MF(sc)) {
bnx2x_link_sync_notify(sc);
@@ -2942,6 +2958,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
if (asserted & ATTN_HARD_WIRED_MASK) {
if (asserted & ATTN_NIG_FOR_FUNC) {
+ bnx2x_acquire_phy_lock(sc);
/* save nig interrupt mask */
nig_mask = REG_RD(sc, nig_int_mask_addr);
@@ -3039,6 +3056,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
REG_WR(sc, nig_int_mask_addr, nig_mask);
+ bnx2x_release_phy_lock(sc);
}
}
@@ -3838,8 +3856,10 @@ static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
if (sc->link_vars.periodic_flags &
ELINK_PERIODIC_FLAGS_LINK_EVENT) {
/* sync with link */
+ bnx2x_acquire_phy_lock(sc);
sc->link_vars.periodic_flags &=
~ELINK_PERIODIC_FLAGS_LINK_EVENT;
+ bnx2x_release_phy_lock(sc);
if (IS_MF(sc)) {
bnx2x_link_sync_notify(sc);
}
@@ -4029,7 +4049,9 @@ static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
}
if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
+ bnx2x_acquire_phy_lock(sc);
elink_handle_module_detect_int(&sc->link_params);
+ bnx2x_release_phy_lock(sc);
}
if (attn & HW_INTERRUT_ASSERT_SET_0) {
@@ -6867,7 +6889,7 @@ static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
}
/* report link status to OS, should be called under phy_lock */
-static void bnx2x_link_report(struct bnx2x_softc *sc)
+static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
{
struct bnx2x_link_report_data cur_data;
@@ -6888,8 +6910,13 @@ static void bnx2x_link_report(struct bnx2x_softc *sc)
return;
}
+ PMD_DRV_LOG(INFO, sc, "Change in link status : cur_data = %lx, last_reported_link = %lx\n",
+ cur_data.link_report_flags,
+ sc->last_reported_link.link_report_flags);
+
sc->link_cnt++;
+ PMD_DRV_LOG(INFO, sc, "link status change count = %x\n", sc->link_cnt);
/* report new link params and remember the state for the next time */
rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
@@ -6941,6 +6968,14 @@ static void bnx2x_link_report(struct bnx2x_softc *sc)
}
}
+static void
+bnx2x_link_report(struct bnx2x_softc *sc)
+{
+ bnx2x_acquire_phy_lock(sc);
+ bnx2x_link_report_locked(sc);
+ bnx2x_release_phy_lock(sc);
+}
+
void bnx2x_link_status_update(struct bnx2x_softc *sc)
{
if (sc->state != BNX2X_STATE_OPEN) {
@@ -7019,6 +7054,8 @@ static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
bnx2x_set_requested_fc(sc);
+ bnx2x_acquire_phy_lock(sc);
+
if (load_mode == LOAD_DIAG) {
lp->loopback_mode = ELINK_LOOPBACK_XGXS;
/* Prefer doing PHY loopback at 10G speed, if possible */
@@ -7038,6 +7075,8 @@ static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
rc = elink_phy_init(&sc->link_params, &sc->link_vars);
+ bnx2x_release_phy_lock(sc);
+
bnx2x_calc_fc_adv(sc);
if (sc->link_vars.link_up) {
@@ -7088,7 +7127,9 @@ void bnx2x_periodic_callout(struct bnx2x_softc *sc)
*/
mb();
if (sc->port.pmf) {
+ bnx2x_acquire_phy_lock(sc);
elink_period_func(&sc->link_params, &sc->link_vars);
+ bnx2x_release_phy_lock(sc);
}
}
#ifdef BNX2X_PULSE
@@ -9840,8 +9881,10 @@ static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
}
+ bnx2x_acquire_phy_lock(sc);
elink_common_init_phy(sc, shmem_base, shmem2_base,
sc->devinfo.chip_id, 0);
+ bnx2x_release_phy_lock(sc);
}
static void bnx2x_pf_disable(struct bnx2x_softc *sc)
@@ -11320,7 +11363,9 @@ static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
static void bnx2x_link_reset(struct bnx2x_softc *sc)
{
if (!BNX2X_NOMCP(sc)) {
+ bnx2x_acquire_phy_lock(sc);
elink_lfa_reset(&sc->link_params, &sc->link_vars);
+ bnx2x_release_phy_lock(sc);
} else {
if (!CHIP_REV_IS_SLOW(sc)) {
PMD_DRV_LOG(WARNING, sc,
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 1cc5a6b..7478072 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -725,6 +725,13 @@ struct bnx2x_port {
uint32_t phy_addr;
+ /* Used to synchronize phy accesses. */
+ rte_spinlock_t phy_mtx;
+ char phy_mtx_name[32];
+
+#define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx)
+#define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx)
+
/*
* MCP scratchpad address for port specific statistics.
* The device is responsible for writing statistcss
diff --git a/drivers/net/bnx2x/ecore_reg.h b/drivers/net/bnx2x/ecore_reg.h
index ae8a93b..d69e857 100644
--- a/drivers/net/bnx2x/ecore_reg.h
+++ b/drivers/net/bnx2x/ecore_reg.h
@@ -1967,6 +1967,7 @@
#define HW_LOCK_MAX_RESOURCE_VALUE 31
#define HW_LOCK_RESOURCE_DRV_FLAGS 10
#define HW_LOCK_RESOURCE_GPIO 1
+#define HW_LOCK_RESOURCE_MDIO 0
#define HW_LOCK_RESOURCE_NVRAM 12
#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
--
1.7.10.3
^ permalink raw reply [flat|nested] 13+ messages in thread