From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
To: Akhil Goyal <akhil.goyal@nxp.com>,
Pablo de Lara <pablo.de.lara.guarch@intel.com>,
Thomas Monjalon <thomas@monjalon.net>
Cc: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>,
Jerin Jacob <jerin.jacob@caviumnetworks.com>,
Narayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,
dev@dpdk.org, Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,
Anoob Joseph <anoob.joseph@caviumnetworks.com>,
Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>,
Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,
Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>,
Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
Subject: [dpdk-dev] [PATCH v3 23/32] common/cpt: add support for zuc and snow3g
Date: Fri, 5 Oct 2018 18:29:14 +0530 [thread overview]
Message-ID: <1538744363-30340-24-git-send-email-anoob.joseph@caviumnetworks.com> (raw)
In-Reply-To: <1538744363-30340-1-git-send-email-anoob.joseph@caviumnetworks.com>
From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Adding microcode interface for supporting ZUC and SNOW3G.
Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
---
drivers/common/cpt/cpt_ucode.h | 596 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 596 insertions(+)
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 9085667..5d7743c 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -1226,6 +1226,596 @@ cpt_dec_hmac_prep(uint32_t flags,
return 0;
}
+static __rte_always_inline int
+cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
+ uint64_t d_offs,
+ uint64_t d_lens,
+ fc_params_t *params,
+ void *op,
+ void **prep_req)
+{
+ uint32_t size;
+ int32_t inputlen, outputlen;
+ struct cpt_ctx *cpt_ctx;
+ uint32_t mac_len = 0;
+ uint8_t snow3g, j;
+ struct cpt_request_info *req;
+ buf_ptr_t *buf_p;
+ uint32_t encr_offset = 0, auth_offset = 0;
+ uint32_t encr_data_len = 0, auth_data_len = 0;
+ int flags, iv_len = 16, m_size;
+ void *m_vaddr, *c_vaddr;
+ uint64_t m_dma, c_dma, offset_ctrl;
+ uint64_t *offset_vaddr, offset_dma;
+ uint32_t *iv_s, iv[4];
+ vq_cmd_word0_t vq_cmd_w0;
+ vq_cmd_word3_t vq_cmd_w3;
+ opcode_info_t opcode;
+
+ buf_p = ¶ms->meta_buf;
+ m_vaddr = buf_p->vaddr;
+ m_dma = buf_p->dma_addr;
+ m_size = buf_p->size;
+
+ cpt_ctx = params->ctx_buf.vaddr;
+ flags = cpt_ctx->zsk_flags;
+ mac_len = cpt_ctx->mac_len;
+ snow3g = cpt_ctx->snow3g;
+
+ /*
+ * Save initial space that followed app data for completion code &
+ * alternate completion code to fall in same cache line as app data
+ */
+ m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+ m_dma += COMPLETION_CODE_SIZE;
+ size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+ (uint8_t *)m_vaddr;
+
+ c_vaddr = (uint8_t *)m_vaddr + size;
+ c_dma = m_dma + size;
+ size += sizeof(cpt_res_s_t);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* Reserve memory for cpt request info */
+ req = m_vaddr;
+
+ size = sizeof(struct cpt_request_info);
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+ /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+ opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+ (0 << 3) | (flags & 0x7));
+
+ if (flags == 0x1) {
+ /*
+ * Microcode expects offsets in bytes
+ * TODO: Rounding off
+ */
+ auth_data_len = AUTH_DLEN(d_lens);
+
+ /* EIA3 or UIA2 */
+ auth_offset = AUTH_OFFSET(d_offs);
+ auth_offset = auth_offset / 8;
+
+ /* consider iv len */
+ auth_offset += iv_len;
+
+ inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
+ outputlen = mac_len;
+
+ offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
+
+ } else {
+ /* EEA3 or UEA2 */
+ /*
+ * Microcode expects offsets in bytes
+ * TODO: Rounding off
+ */
+ encr_data_len = ENCR_DLEN(d_lens);
+
+ encr_offset = ENCR_OFFSET(d_offs);
+ encr_offset = encr_offset / 8;
+ /* consider iv len */
+ encr_offset += iv_len;
+
+ inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
+ outputlen = inputlen;
+
+ /* iv offset is 0 */
+ offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+ }
+
+ /* IV */
+ iv_s = (flags == 0x1) ? params->auth_iv_buf :
+ params->iv_buf;
+
+ if (snow3g) {
+ /*
+ * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+ * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+ */
+
+ for (j = 0; j < 4; j++)
+ iv[j] = iv_s[3 - j];
+ } else {
+ /* ZUC doesn't need a swap */
+ for (j = 0; j < 4; j++)
+ iv[j] = iv_s[j];
+ }
+
+ /*
+ * GP op header, lengths are expected in bits.
+ */
+ vq_cmd_w0.u64 = 0;
+ vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+ vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
+
+ /*
+ * In 83XX since we have a limitation of
+ * IV & Offset control word not part of instruction
+ * and need to be part of Data Buffer, we check if
+ * head room is there and then only do the Direct mode processing
+ */
+ if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+ (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+ void *dm_vaddr = params->bufs[0].vaddr;
+ uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+ /*
+ * This flag indicates that there is 24 bytes head room and
+ * 8 bytes tail room available, so that we get to do
+ * DIRECT MODE with limitation
+ */
+
+ offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+ OFF_CTRL_LEN - iv_len);
+ offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+ /* DPTR */
+ req->ist.ei1 = offset_dma;
+ /* RPTR should just exclude offset control word */
+ req->ist.ei2 = dm_dma_addr - iv_len;
+ req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+ + outputlen - iv_len);
+
+ vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+ vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+ if (likely(iv_len)) {
+ uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+ + OFF_CTRL_LEN);
+ memcpy(iv_d, iv, 16);
+ }
+
+ *offset_vaddr = offset_ctrl;
+ } else {
+ uint32_t i, g_size_bytes, s_size_bytes;
+ uint64_t dptr_dma, rptr_dma;
+ sg_comp_t *gather_comp;
+ sg_comp_t *scatter_comp;
+ uint8_t *in_buffer;
+ uint32_t *iv_d;
+
+ /* save space for iv */
+ offset_vaddr = m_vaddr;
+ offset_dma = m_dma;
+
+ m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+ m_dma += OFF_CTRL_LEN + iv_len;
+ m_size -= OFF_CTRL_LEN + iv_len;
+
+ opcode.s.major |= CPT_DMA_MODE;
+
+ vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+ /* DPTR has SG list */
+ in_buffer = m_vaddr;
+ dptr_dma = m_dma;
+
+ ((uint16_t *)in_buffer)[0] = 0;
+ ((uint16_t *)in_buffer)[1] = 0;
+
+ /* TODO Add error check if space will be sufficient */
+ gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+ /*
+ * Input Gather List
+ */
+ i = 0;
+
+ /* Offset control word followed by iv */
+
+ i = fill_sg_comp(gather_comp, i, offset_dma,
+ OFF_CTRL_LEN + iv_len);
+
+ /* iv offset is 0 */
+ *offset_vaddr = offset_ctrl;
+
+ iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+ memcpy(iv_d, iv, 16);
+
+ /* input data */
+ size = inputlen - iv_len;
+ if (size) {
+ i = fill_sg_comp_from_iov(gather_comp, i,
+ params->src_iov,
+ 0, &size, NULL, 0);
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+ g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ /*
+ * Output Scatter List
+ */
+
+ i = 0;
+ scatter_comp =
+ (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+ if (flags == 0x1) {
+ /* IV in SLIST only for EEA3 & UEA2 */
+ iv_len = 0;
+ }
+
+ if (iv_len) {
+ i = fill_sg_comp(scatter_comp, i,
+ offset_dma + OFF_CTRL_LEN, iv_len);
+ }
+
+ /* Add output data */
+ if (req_flags & VALID_MAC_BUF) {
+ size = outputlen - iv_len - mac_len;
+ if (size) {
+ i = fill_sg_comp_from_iov(scatter_comp, i,
+ params->dst_iov, 0,
+ &size, NULL, 0);
+
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+
+ /* mac data */
+ if (mac_len) {
+ i = fill_sg_comp_from_buf(scatter_comp, i,
+ ¶ms->mac_buf);
+ }
+ } else {
+ /* Output including mac */
+ size = outputlen - iv_len;
+ if (size) {
+ i = fill_sg_comp_from_iov(scatter_comp, i,
+ params->dst_iov, 0,
+ &size, NULL, 0);
+
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ }
+ ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+ s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+ /* This is DPTR len incase of SG mode */
+ vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* cpt alternate completion address saved earlier */
+ req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+ *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+ rptr_dma = c_dma - 8;
+
+ req->ist.ei1 = dptr_dma;
+ req->ist.ei2 = rptr_dma;
+ }
+
+ /* First 16-bit swap then 64-bit swap */
+ /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+ * to eliminate all the swapping
+ */
+ vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+ /* vq command w3 */
+ vq_cmd_w3.u64 = 0;
+ vq_cmd_w3.s.grp = 0;
+ vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+ offsetof(struct cpt_ctx, zs_ctx);
+
+ /* 16 byte aligned cpt res address */
+ req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+ *req->completion_addr = COMPLETION_CODE_INIT;
+ req->comp_baddr = c_dma;
+
+ /* Fill microcode part of instruction */
+ req->ist.ei0 = vq_cmd_w0.u64;
+ req->ist.ei3 = vq_cmd_w3.u64;
+
+ req->op = op;
+
+ *prep_req = req;
+ return 0;
+}
+
+static __rte_always_inline int
+cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
+ uint64_t d_offs,
+ uint64_t d_lens,
+ fc_params_t *params,
+ void *op,
+ void **prep_req)
+{
+ uint32_t size;
+ int32_t inputlen = 0, outputlen;
+ struct cpt_ctx *cpt_ctx;
+ uint8_t snow3g, iv_len = 16;
+ struct cpt_request_info *req;
+ buf_ptr_t *buf_p;
+ uint32_t encr_offset;
+ uint32_t encr_data_len;
+ int flags, m_size;
+ void *m_vaddr, *c_vaddr;
+ uint64_t m_dma, c_dma;
+ uint64_t *offset_vaddr, offset_dma;
+ uint32_t *iv_s, iv[4], j;
+ vq_cmd_word0_t vq_cmd_w0;
+ vq_cmd_word3_t vq_cmd_w3;
+ opcode_info_t opcode;
+
+ buf_p = ¶ms->meta_buf;
+ m_vaddr = buf_p->vaddr;
+ m_dma = buf_p->dma_addr;
+ m_size = buf_p->size;
+
+ /*
+ * Microcode expects offsets in bytes
+ * TODO: Rounding off
+ */
+ encr_offset = ENCR_OFFSET(d_offs) / 8;
+ encr_data_len = ENCR_DLEN(d_lens);
+
+ cpt_ctx = params->ctx_buf.vaddr;
+ flags = cpt_ctx->zsk_flags;
+ snow3g = cpt_ctx->snow3g;
+ /*
+ * Save initial space that followed app data for completion code &
+ * alternate completion code to fall in same cache line as app data
+ */
+ m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+ m_dma += COMPLETION_CODE_SIZE;
+ size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+ (uint8_t *)m_vaddr;
+
+ c_vaddr = (uint8_t *)m_vaddr + size;
+ c_dma = m_dma + size;
+ size += sizeof(cpt_res_s_t);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* Reserve memory for cpt request info */
+ req = m_vaddr;
+
+ size = sizeof(struct cpt_request_info);
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
+
+ /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
+ opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+ (0 << 3) | (flags & 0x7));
+
+ /* consider iv len */
+ encr_offset += iv_len;
+
+ inputlen = encr_offset +
+ (RTE_ALIGN(encr_data_len, 8) / 8);
+ outputlen = inputlen;
+
+ /* IV */
+ iv_s = params->iv_buf;
+ if (snow3g) {
+ /*
+ * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
+ * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
+ */
+
+ for (j = 0; j < 4; j++)
+ iv[j] = iv_s[3 - j];
+ } else {
+ /* ZUC doesn't need a swap */
+ for (j = 0; j < 4; j++)
+ iv[j] = iv_s[j];
+ }
+
+ /*
+ * GP op header, lengths are expected in bits.
+ */
+ vq_cmd_w0.u64 = 0;
+ vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
+
+ /*
+ * In 83XX since we have a limitation of
+ * IV & Offset control word not part of instruction
+ * and need to be part of Data Buffer, we check if
+ * head room is there and then only do the Direct mode processing
+ */
+ if (likely((req_flags & SINGLE_BUF_INPLACE) &&
+ (req_flags & SINGLE_BUF_HEADTAILROOM))) {
+ void *dm_vaddr = params->bufs[0].vaddr;
+ uint64_t dm_dma_addr = params->bufs[0].dma_addr;
+ /*
+ * This flag indicates that there is 24 bytes head room and
+ * 8 bytes tail room available, so that we get to do
+ * DIRECT MODE with limitation
+ */
+
+ offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
+ OFF_CTRL_LEN - iv_len);
+ offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+ /* DPTR */
+ req->ist.ei1 = offset_dma;
+ /* RPTR should just exclude offset control word */
+ req->ist.ei2 = dm_dma_addr - iv_len;
+ req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+ + outputlen - iv_len);
+
+ vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
+
+ vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+ if (likely(iv_len)) {
+ uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
+ + OFF_CTRL_LEN);
+ memcpy(iv_d, iv, 16);
+ }
+
+ /* iv offset is 0 */
+ *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+ } else {
+ uint32_t i, g_size_bytes, s_size_bytes;
+ uint64_t dptr_dma, rptr_dma;
+ sg_comp_t *gather_comp;
+ sg_comp_t *scatter_comp;
+ uint8_t *in_buffer;
+ uint32_t *iv_d;
+
+ /* save space for offset and iv... */
+ offset_vaddr = m_vaddr;
+ offset_dma = m_dma;
+
+ m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
+ m_dma += OFF_CTRL_LEN + iv_len;
+ m_size -= OFF_CTRL_LEN + iv_len;
+
+ opcode.s.major |= CPT_DMA_MODE;
+
+ vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
+
+ /* DPTR has SG list */
+ in_buffer = m_vaddr;
+ dptr_dma = m_dma;
+
+ ((uint16_t *)in_buffer)[0] = 0;
+ ((uint16_t *)in_buffer)[1] = 0;
+
+ /* TODO Add error check if space will be sufficient */
+ gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+ /*
+ * Input Gather List
+ */
+ i = 0;
+
+ /* Offset control word */
+
+ /* iv offset is 0 */
+ *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
+
+ i = fill_sg_comp(gather_comp, i, offset_dma,
+ OFF_CTRL_LEN + iv_len);
+
+ iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
+ memcpy(iv_d, iv, 16);
+
+ /* Add input data */
+ size = inputlen - iv_len;
+ if (size) {
+ i = fill_sg_comp_from_iov(gather_comp, i,
+ params->src_iov,
+ 0, &size, NULL, 0);
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+ g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ /*
+ * Output Scatter List
+ */
+
+ i = 0;
+ scatter_comp =
+ (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+ /* IV */
+ i = fill_sg_comp(scatter_comp, i,
+ offset_dma + OFF_CTRL_LEN,
+ iv_len);
+
+ /* Add output data */
+ size = outputlen - iv_len;
+ if (size) {
+ i = fill_sg_comp_from_iov(scatter_comp, i,
+ params->dst_iov, 0,
+ &size, NULL, 0);
+
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+ s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+ /* This is DPTR len incase of SG mode */
+ vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* cpt alternate completion address saved earlier */
+ req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+ *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+ rptr_dma = c_dma - 8;
+
+ req->ist.ei1 = dptr_dma;
+ req->ist.ei2 = rptr_dma;
+ }
+
+ /* First 16-bit swap then 64-bit swap */
+ /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+ * to eliminate all the swapping
+ */
+ vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
+
+ /* vq command w3 */
+ vq_cmd_w3.u64 = 0;
+ vq_cmd_w3.s.grp = 0;
+ vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
+ offsetof(struct cpt_ctx, zs_ctx);
+
+ /* 16 byte aligned cpt res address */
+ req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+ *req->completion_addr = COMPLETION_CODE_INIT;
+ req->comp_baddr = c_dma;
+
+ /* Fill microcode part of instruction */
+ req->ist.ei0 = vq_cmd_w0.u64;
+ req->ist.ei3 = vq_cmd_w3.u64;
+
+ req->op = op;
+
+ *prep_req = req;
+ return 0;
+}
+
static __rte_always_inline void *
cpt_fc_dec_hmac_prep(uint32_t flags,
uint64_t d_offs,
@@ -1243,6 +1833,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,
if (likely(fc_type == FC_GEN)) {
ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
fc_params, op, &prep_req);
+ } else if (fc_type == ZUC_SNOW3G) {
+ ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
+ fc_params, op, &prep_req);
} else {
/*
* For AUTH_ONLY case,
@@ -1273,6 +1866,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
if (likely(fc_type == FC_GEN)) {
ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
fc_params, op, &prep_req);
+ } else if (fc_type == ZUC_SNOW3G) {
+ ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
+ fc_params, op, &prep_req);
} else {
ret = ERR_EIO;
}
--
2.7.4
next prev parent reply other threads:[~2018-10-05 13:02 UTC|newest]
Thread overview: 185+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-08 16:45 [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 01/16] config: add Cavium CPT PMD skeleton Anoob Joseph
2018-06-14 2:56 ` Jerin Jacob
2018-06-19 13:39 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 02/16] crypto/cpt/base: add hardware definitions Cavium CPT Anoob Joseph
2018-06-14 3:02 ` Jerin Jacob
2018-06-08 16:45 ` [dpdk-dev] [PATCH 03/16] crypto/cpt/base: add hardware initialization API for CPT Anoob Joseph
2018-06-14 3:13 ` Jerin Jacob
2018-06-19 13:56 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 04/16] crypto/cpt/base: add hardware enq/deq " Anoob Joseph
2018-06-14 3:20 ` Jerin Jacob
2018-06-19 14:36 ` De Lara Guarch, Pablo
2018-06-19 15:08 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 05/16] crypto/cpt/base: add sym crypto session init " Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 06/16] crypto/cpt/base: add sym crypto request prepare " Anoob Joseph
2018-06-14 3:24 ` Jerin Jacob
2018-06-08 16:45 ` [dpdk-dev] [PATCH 07/16] crypto/cpt/base: add request prepare API for ZUC and SNOW3G Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 08/16] crypto/cpt/base: add request prepare API for Kasumi Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 09/16] crypto/cpt/base: add prepare request API for HASH and HMAC Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 10/16] crypto/cpt: add driver initializations Anoob Joseph
2018-06-19 15:25 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 11/16] crypto/cpt: add the basic device callback functions Anoob Joseph
2018-06-19 15:58 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 12/16] crypto/cpt: adds some more callback functions for CPT Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 13/16] crypto/cpt: adds the session related function callbacks Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 14/16] crypto/cpt: adds the enqueue and dequeue callbacks Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 15/16] doc: add Cavium's CPT guide Anoob Joseph
2018-06-19 16:10 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 16/16] crypto/cpt: build with meson Anoob Joseph
2018-06-18 14:54 ` De Lara Guarch, Pablo
2018-06-18 13:02 ` [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver Anoob Joseph
2018-06-18 14:29 ` De Lara Guarch, Pablo
2018-07-09 22:55 ` De Lara Guarch, Pablo
2018-07-10 3:41 ` Anoob Joseph
2018-07-10 8:11 ` De Lara Guarch, Pablo
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 00/33] Adding Cavium's OcteonTX crypto PMD Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton Anoob Joseph
2018-09-14 12:11 ` Akhil Goyal
2018-09-17 4:22 ` Joseph, Anoob
2018-09-17 10:37 ` Akhil Goyal
2018-09-17 11:42 ` Joseph, Anoob
2018-09-17 12:20 ` Akhil Goyal
2018-09-17 14:13 ` Joseph, Anoob
2018-09-17 14:36 ` Thomas Monjalon
2018-09-17 14:50 ` Joseph, Anoob
2018-09-18 12:31 ` Akhil Goyal
2018-09-18 12:40 ` Joseph
2018-09-18 12:44 ` Akhil Goyal
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 02/33] common/cpt: add common logging support Anoob Joseph
2018-09-14 12:29 ` Akhil Goyal
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 03/33] crypto/octeontx: add PCI probe and remove Anoob Joseph
2018-09-14 12:39 ` Akhil Goyal
2018-09-17 4:40 ` Joseph, Anoob
2018-09-17 10:34 ` Akhil Goyal
2018-09-17 10:38 ` Joseph, Anoob
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 04/33] crypto/octeontx: add register addresses Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 05/33] common/cpt: add common code for init routine Anoob Joseph
2018-09-17 10:45 ` Akhil Goyal
2018-09-17 11:46 ` Thomas Monjalon
2018-09-17 12:29 ` Joseph, Anoob
2018-09-17 12:32 ` Akhil Goyal
2018-09-17 12:51 ` Thomas Monjalon
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 06/33] crypto/octeontx: add hardware " Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 07/33] common/cpt: add hardware register defines Anoob Joseph
2018-09-17 11:18 ` Akhil Goyal
2018-09-17 14:15 ` Joseph, Anoob
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 08/33] crypto/octeontx: add hardware register access for misc poll Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities Anoob Joseph
2018-09-17 12:01 ` Akhil Goyal
2018-09-17 12:35 ` Joseph, Anoob
2018-09-24 11:36 ` Joseph, Anoob
2018-09-28 11:14 ` Joseph, Anoob
2018-10-01 10:05 ` Thomas Monjalon
2018-10-08 15:59 ` Trahe, Fiona
2018-10-08 20:27 ` Thomas Monjalon
2018-10-10 5:39 ` Joseph, Anoob
2018-10-17 5:40 ` Joseph, Anoob
2018-10-19 21:09 ` Trahe, Fiona
2018-10-22 3:49 ` Joseph, Anoob
2018-10-22 6:51 ` Thomas Monjalon
2018-10-23 8:48 ` Joseph, Anoob
2018-10-23 9:03 ` Thomas Monjalon
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 10/33] common/cpt: add PMD ops helper functions Anoob Joseph
2018-09-17 12:47 ` Akhil Goyal
2018-09-17 14:17 ` Joseph, Anoob
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 11/33] crypto/octeontx: add global resource init Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 12/33] crypto/octeontx: add mailbox routines Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 13/33] crypto/octeontx: add basic dev ops Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 14/33] common/cpt: add common macros for queue pair ops Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 15/33] crypto/octeontx: add queue pair functions Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 16/33] common/cpt: add common code required for session management Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 17/33] crypto/octeontx: add session management ops Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 18/33] common/cpt: add common code for fill session data Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 19/33] crypto/octeontx: add supported sessions Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 20/33] common/cpt: add common defines for microcode Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 21/33] common/cpt: add microcode interface for encryption Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 22/33] common/cpt: add microcode interface for decryption Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 23/33] common/cpt: add crypo op enqueue request manager framework Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 24/33] common/cpt: add support for zuc and snow3g Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 25/33] common/cpt: add support for kasumi Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 26/33] common/cpt: add support for hash Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 27/33] crypto/octeontx: add routines to prepare instructions Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 28/33] common/cpt: add common code for enqueuing cpt instruction Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 29/33] crypto/octeontx: add enqueue burst op Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 30/33] common/cpt: add common code for cpt dequeue Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 31/33] crypto/octeontx: add dequeue burst op Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 32/33] test: adds validation test Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 33/33] doc: adds doc file Anoob Joseph
2018-09-17 13:30 ` Akhil Goyal
2018-09-14 9:16 ` [dpdk-dev] [PATCH v2 00/33] Adding Cavium's OcteonTX crypto PMD Joseph, Anoob
2018-09-14 9:42 ` Akhil Goyal
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX " Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 01/32] common/cpt: add common logging support Anoob Joseph
2018-10-08 12:27 ` Thomas Monjalon
2018-10-08 13:07 ` Joseph, Anoob
2018-10-08 13:37 ` Thomas Monjalon
2018-10-08 14:39 ` Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 02/32] config: add Cavium OCTEONTX crypto PMD skeleton Anoob Joseph
2018-10-08 12:28 ` Thomas Monjalon
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 03/32] crypto/octeontx: add register addresses Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 04/32] common/cpt: add common code for init routine Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 05/32] crypto/octeontx: add hardware " Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 06/32] common/cpt: add hardware register defines Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 07/32] crypto/octeontx: add hardware register access for misc poll Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 08/32] crypto/octeontx: adds symmetric capabilities Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 09/32] common/cpt: add PMD ops helper functions Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 10/32] crypto/octeontx: add global resource init Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 11/32] crypto/octeontx: add mailbox routines Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 12/32] crypto/octeontx: add basic dev ops Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 13/32] common/cpt: add common macros for queue pair ops Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 14/32] crypto/octeontx: add queue pair functions Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 15/32] common/cpt: add common code required for session management Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 16/32] crypto/octeontx: add session management ops Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 17/32] common/cpt: add common code for fill session data Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 18/32] crypto/octeontx: add supported sessions Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 19/32] common/cpt: add common defines for microcode Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 20/32] common/cpt: add microcode interface for encryption Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 21/32] common/cpt: add microcode interface for decryption Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 22/32] common/cpt: add crypo op enqueue request manager framework Anoob Joseph
2018-10-05 12:59 ` Anoob Joseph [this message]
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 24/32] common/cpt: add support for kasumi Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 25/32] common/cpt: add support for hash Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 26/32] crypto/octeontx: add routines to prepare instructions Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 27/32] common/cpt: add common code for enqueuing cpt instruction Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 28/32] crypto/octeontx: add enqueue burst op Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 29/32] common/cpt: add common code for cpt dequeue Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 30/32] crypto/octeontx: add dequeue burst op Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 31/32] test: adds validation test Anoob Joseph
2018-10-08 12:33 ` Akhil Goyal
2018-10-08 12:56 ` Akhil Goyal
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 32/32] doc: adds doc file Anoob Joseph
2018-10-08 12:31 ` Thomas Monjalon
2018-10-05 13:04 ` [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD Akhil Goyal
2018-10-05 13:13 ` Joseph, Anoob
2018-10-05 13:14 ` Akhil Goyal
2018-10-05 13:35 ` Joseph, Anoob
2018-10-08 12:33 ` Thomas Monjalon
2018-10-08 12:58 ` Joseph, Anoob
2018-10-08 13:06 ` Thomas Monjalon
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 00/23] Adding Cavium's OCTEON TX " Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 01/23] crypto/octeontx: add PMD skeleton Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 02/23] crypto/octeontx: add hardware init routine Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 03/23] crypto/octeontx: add hardware register access for misc poll Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 04/23] crypto/octeontx: add symmetric capabilities Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 05/23] common/cpt: add PMD ops helper functions Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 06/23] crypto/octeontx: add global resource init Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 07/23] crypto/octeontx: add mailbox routines Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 08/23] crypto/octeontx: add basic dev ops Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 09/23] crypto/octeontx: add queue pair functions Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 10/23] crypto/octeontx: add session management ops Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 11/23] crypto/octeontx: add supported sessions Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 12/23] common/cpt: add common defines for microcode Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 13/23] common/cpt: add microcode interface for encryption Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 14/23] common/cpt: add microcode interface for decryption Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 15/23] common/cpt: add crypo op enqueue request manager framework Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 16/23] common/cpt: support zuc and snow3g Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 17/23] common/cpt: support kasumi Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 18/23] common/cpt: support hash Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 19/23] crypto/octeontx: add routines to prepare instructions Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 20/23] crypto/octeontx: add enqueue burst op Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 21/23] crypto/octeontx: add dequeue " Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 22/23] test/crypto: add OCTEON TX unit tests Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 23/23] doc: add documentation for OCTEON TX crypto Anoob Joseph
2018-10-09 9:56 ` [dpdk-dev] [PATCH v4 00/23] Adding Cavium's OCTEON TX crypto PMD Thomas Monjalon
2018-10-09 10:29 ` Akhil Goyal
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