* [dpdk-dev] [PATCH v3 4/4] test: fix memory barrier test failure on power CPUs
@ 2019-05-08 21:02 David Christensen
2019-05-08 21:02 ` David Christensen
0 siblings, 1 reply; 2+ messages in thread
From: David Christensen @ 2019-05-08 21:02 UTC (permalink / raw)
To: dev; +Cc: David Christensen
The memory barrier test fails on IBM Power 9 systems. Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
---
v2:
* Removed ifdef's for PPC since the rte_smp_*mb() macros are already
customized for each CPU architecture
v3:
* None
---
app/test/test_barrier.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index a0b4704..43b5f62 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -92,12 +92,14 @@ struct lcore_plock_test {
other = self ^ 1;
l->flag[self] = 1;
+ rte_smp_wmb();
l->victim = self;
store_load_barrier(l->utype);
while (l->flag[other] == 1 && l->victim == self)
rte_pause();
+ rte_smp_rmb();
}
static void
--
1.8.3.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* [dpdk-dev] [PATCH v3 4/4] test: fix memory barrier test failure on power CPUs
2019-05-08 21:02 [dpdk-dev] [PATCH v3 4/4] test: fix memory barrier test failure on power CPUs David Christensen
@ 2019-05-08 21:02 ` David Christensen
0 siblings, 0 replies; 2+ messages in thread
From: David Christensen @ 2019-05-08 21:02 UTC (permalink / raw)
To: dev; +Cc: David Christensen
The memory barrier test fails on IBM Power 9 systems. Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
---
v2:
* Removed ifdef's for PPC since the rte_smp_*mb() macros are already
customized for each CPU architecture
v3:
* None
---
app/test/test_barrier.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index a0b4704..43b5f62 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -92,12 +92,14 @@ struct lcore_plock_test {
other = self ^ 1;
l->flag[self] = 1;
+ rte_smp_wmb();
l->victim = self;
store_load_barrier(l->utype);
while (l->flag[other] == 1 && l->victim == self)
rte_pause();
+ rte_smp_rmb();
}
static void
--
1.8.3.1
^ permalink raw reply [flat|nested] 2+ messages in thread
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