From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 282EEA0487 for ; Sun, 30 Jun 2019 18:21:51 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2CB1D1B955; Sun, 30 Jun 2019 18:21:45 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 34DC91B945 for ; Sun, 30 Jun 2019 18:21:42 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B06FCFC; Sun, 30 Jun 2019 09:21:41 -0700 (PDT) Received: from net-arm-thunderx2.shanghai.arm.com (net-arm-thunderx2.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 97B063F718; Sun, 30 Jun 2019 09:21:39 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: thomas@monjalon.net, jerinj@marvell.com, hemant.agrawal@nxp.com, bruce.richardson@intel.com, chaozhu@linux.vnet.ibm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com, gavin.hu@arm.com Date: Mon, 1 Jul 2019 00:21:12 +0800 Message-Id: <1561911676-37718-2-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [RFC 1/5] eal: add the APIs to wait until equal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The rte_wait_until_equal_xxx APIs abstract the functionality of 'polling for a memory location to become equal to a given value'. Signed-off-by: Gavin Hu Reviewed-by: Ruifeng Wang Reviewed-by: Steve Capper Reviewed-by: Ola Liljedahl Reviewed-by: Honnappa Nagarahalli --- .../common/include/arch/arm/rte_pause_64.h | 143 +++++++++++++++++++++ lib/librte_eal/common/include/generic/rte_pause.h | 20 +++ 2 files changed, 163 insertions(+) diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h index 93895d3..0095da6 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h @@ -17,6 +17,149 @@ static inline void rte_pause(void) asm volatile("yield" ::: "memory"); } +#ifdef RTE_USE_WFE +#define rte_wait_until_equal_relaxed(addr, expected) do {\ + typeof(*addr) tmp; \ + if (__builtin_constant_p((expected))) \ + do { \ + if (sizeof(*(addr)) == 16)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxrh %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 32)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxr %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 64)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxr %x0, %1\n" \ + "cmp %x0, %x2\n" \ + "bne 1b\n" \ + : "=&r" (tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + } while (0); \ + else \ + do { \ + if (sizeof(*(addr)) == 16)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxrh %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 32)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxr %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 64)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldxr %x0, %1\n" \ + "cmp %x0, %x2\n" \ + "bne 1b\n" \ + : "=&r" (tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + } while (0); \ +} while (0) + +#define rte_wait_until_equal_acquire(addr, expected) do {\ + typeof(*addr) tmp; \ + if (__builtin_constant_p((expected))) \ + do { \ + if (sizeof(*(addr)) == 16)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxrh %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 32)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxr %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 64)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxr %x0, %1\n" \ + "cmp %x0, %x2\n" \ + "bne 1b\n" \ + : "=&r" (tmp) \ + : "Q"(*addr), "i"(expected) \ + : "cc", "memory"); \ + } while (0); \ + else \ + do { \ + if (sizeof(*(addr)) == 16)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxrh %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 32)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxr %w0, %1\n" \ + "cmp %w0, %w2\n" \ + "bne 1b\n" \ + : "=&r"(tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + else if (sizeof(*(addr)) == 64)\ + asm volatile( \ + "sevl\n" \ + "1: wfe\n" \ + "ldaxr %x0, %1\n" \ + "cmp %x0, %x2\n" \ + "bne 1b\n" \ + : "=&r" (tmp) \ + : "Q"(*addr), "r"(expected) \ + : "cc", "memory"); \ + } while (0); \ +} while (0) + +#endif + #ifdef __cplusplus } #endif diff --git a/lib/librte_eal/common/include/generic/rte_pause.h b/lib/librte_eal/common/include/generic/rte_pause.h index 52bd4db..c115b61 100644 --- a/lib/librte_eal/common/include/generic/rte_pause.h +++ b/lib/librte_eal/common/include/generic/rte_pause.h @@ -20,4 +20,24 @@ */ static inline void rte_pause(void); +#if !defined(RTE_USE_WFE) +#define rte_wait_until_equal_relaxed(addr, expected) do {\ + rte_pause(); \ + } while (*(addr) != (expected)) + +#ifdef RTE_USE_C11_MEM_MODEL +#define rte_wait_until_equal_acquire(addr, expected) do {\ + rte_pause(); \ + } while (__atomic_load_n((addr), __ATOMIC_ACQUIRE) != (expected)) +#else +#define rte_wait_until_equal_acquire(addr, expected) do {\ + do {\ + rte_pause(); \ + } while (*(addr) != (expected)); \ + rte_smp_rmb(); \ + } while (0) +#endif +#endif + + #endif /* _RTE_PAUSE_H_ */ -- 2.7.4