Re: [dpdk-dev] [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD

[Thomas Monjalon <thomas@monjalon.net>]

22/09/2017 15:06, Shreyansh Jain:
> On Friday 22 September 2017 03:40 AM, Thomas Monjalon wrote:
> > 09/09/2017 13:20, Shreyansh Jain:
> >> DPAA, or Datapath Acceleration Architecture [R2], is a set of hardware
> >> components designed for high-speed network packet processing. This
> >> architecture provides the infrastructure to support simplified sharing of
> >> networking interfaces and accelerators by multiple CPU cores, and the
> >> accelerators themselves.
> >>
> >> This patchset introduces the following:
> >> 1. DPAA Bus (drivers/bus/dpaa)
> >>   The core of DPAA bus is implemented using 3 main hardware blocks: QMan,
> >>   or Queue Manager; BMan, or Buffer Manager and FMan, or Frame Manager.
> >>   The patches introduce necessary layers to expose the DPAA hardware
> >>   blocks for interfacing with RTE framework.
> > 
> > I guess these are the same blocks as for DPAA2?
> > They are in drivers/bus/fslmc/
> > Why introducing yet another bus driver?
> > The fslmc one was supposed to cover any Freescale (NXP (Qualcomm)) SoC.
> 
> Forgot to reply to this in previous email:
> 
> No, fslmc is not compatible with DPAA. They are completely different 
> architectures.
> I am not sure why you have the notion "fslmc one was supposed to cover 
> any Freescale (NXP (Qualcomm)) SoC". That is not correct - FSLMC was 
> always for supporting DPAA2 which is based on VFIO. DPAA is more closer 
> to a platform layout.
> 
> And I don't think we should have single "bus/fslmc" just so that it can 
> encompass all NXP SoC. I am assuming you didn't mean this :P.

At the beginning of fslmc work, I had understood that every NXP SoC were
connecting components with the same principle which we could call the
"Freescale bus".
Then you came with this bus named bus/fslmc, not bus/dpaa2.
Now I am confused. What is the exact scope of fslmc? Is it just DPAA2?