From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by dpdk.org (Postfix) with ESMTP id A3B3C7CDE for ; Fri, 22 Sep 2017 15:13:29 +0200 (CEST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 3E0B320BA6; Fri, 22 Sep 2017 09:13:29 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute1.internal (MEProxy); Fri, 22 Sep 2017 09:13:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=Qr7Dy5jgccR68Zl ah6V+uRiT4SgUE99c9rHZkej1ia0=; b=m8XPMcLbFvLp3lSku+vDNKj9ERDRU6G 8W4pAT2KnX1b+y/HyE4AC5SnVApg5Fv6sBndqk+vQKsQk3rvf43gl91Bd8EavEUI 5PgbaSU8tJncTcLKXJ2vx6A1xIvf3V2wDGHq1un47/+JDgX++vzltdHoJ3Mg9FaA HuZdiB0QkzJM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=Qr7Dy5jgccR68Zlah6V+uRiT4SgUE99c9rHZkej1ia0=; b=GDvFqZBn VqWyyBHKVn7DXXUYGh+IJRK0g/gYb6B9GoC3cJT8nD1GIW8SFK7HzeM9eGeQmyJe WEjtG9nAI+ABH5nDWuwvSGnZUDJLsnOfJ5Y5B8/pIWaEGqgO8U5mLkifBX++KVbF k/6Bghqdxc5EpErGYQhf7g7f6mCXgDBjqMcx4UtNCUg1kh47FlmsQwHxTTYrWX6Z OundfE7v7KWk+e7pCNgzH1yJgDGwuYT2nzlD70OnRNHNbkPGDrldsPjY+QFdzkmx 7sW9ME/ZsjgRKePxdLN75SNIrG3PIzHJwiNlBzdrwfcfPZJR17xHW27ukvNjAswy 761Jm0Gp+uZzDA== X-ME-Sender: X-Sasl-enc: Ct93/nRgnpBVgPIoMw3u7mHXaW6g5xWBIP33oxqcdcn0 1506086009 Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 043657E808; Fri, 22 Sep 2017 09:13:29 -0400 (EDT) From: Thomas Monjalon To: Shreyansh Jain Cc: dev@dpdk.org, ferruh.yigit@intel.com, hemant.agrawal@nxp.com Date: Fri, 22 Sep 2017 15:13:27 +0200 Message-ID: <1563275.iJklTzZNDB@xps> In-Reply-To: References: <20170823141213.25476-1-shreyansh.jain@nxp.com> <25531756.sobbYYJFMz@xps> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Sep 2017 13:13:29 -0000 22/09/2017 15:06, Shreyansh Jain: > On Friday 22 September 2017 03:40 AM, Thomas Monjalon wrote: > > 09/09/2017 13:20, Shreyansh Jain: > >> DPAA, or Datapath Acceleration Architecture [R2], is a set of hardware > >> components designed for high-speed network packet processing. This > >> architecture provides the infrastructure to support simplified sharing of > >> networking interfaces and accelerators by multiple CPU cores, and the > >> accelerators themselves. > >> > >> This patchset introduces the following: > >> 1. DPAA Bus (drivers/bus/dpaa) > >> The core of DPAA bus is implemented using 3 main hardware blocks: QMan, > >> or Queue Manager; BMan, or Buffer Manager and FMan, or Frame Manager. > >> The patches introduce necessary layers to expose the DPAA hardware > >> blocks for interfacing with RTE framework. > > > > I guess these are the same blocks as for DPAA2? > > They are in drivers/bus/fslmc/ > > Why introducing yet another bus driver? > > The fslmc one was supposed to cover any Freescale (NXP (Qualcomm)) SoC. > > Forgot to reply to this in previous email: > > No, fslmc is not compatible with DPAA. They are completely different > architectures. > I am not sure why you have the notion "fslmc one was supposed to cover > any Freescale (NXP (Qualcomm)) SoC". That is not correct - FSLMC was > always for supporting DPAA2 which is based on VFIO. DPAA is more closer > to a platform layout. > > And I don't think we should have single "bus/fslmc" just so that it can > encompass all NXP SoC. I am assuming you didn't mean this :P. At the beginning of fslmc work, I had understood that every NXP SoC were connecting components with the same principle which we could call the "Freescale bus". Then you came with this bus named bus/fslmc, not bus/dpaa2. Now I am confused. What is the exact scope of fslmc? Is it just DPAA2?