From: Harman Kalra <hkalra@marvell.com>
To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>,
"Jerin Jacob Kollanukkaran" <jerinj@marvell.com>,
Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>
Subject: [dpdk-dev] [PATCH 1/2] net/octeontx2: fix ptp performance issue
Date: Sat, 27 Jul 2019 14:57:17 +0000 [thread overview]
Message-ID: <1564239400-2919-1-git-send-email-hkalra@marvell.com> (raw)
A huge drop in per core MPPS value was observed when PTP stack is
enabled. The reason behind the bottleneck is HW serialises the
transfer of all SQEs, which seeks timestamp capture, on the same
send DMA path. Hence only those packets which requires timestamp
capture should set SETTSTAMP in send mem alg.
With this patch timestamping would be done only for those packets
with PKT_TX_IEEE1588_TMST set.
Fixes: fb3ae0951abd ("net/octeontx2: support Tx")
Fixes: 8980a153006b ("event/octeontx2: support PTP for SSO")
Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
drivers/event/octeontx2/otx2_evdev.h | 7 ++++++-
drivers/event/octeontx2/otx2_worker.h | 10 +++++++--
drivers/event/octeontx2/otx2_worker_dual.h | 14 +++++++++++--
drivers/net/octeontx2/otx2_ethdev.c | 2 --
drivers/net/octeontx2/otx2_rx.c | 3 ++-
drivers/net/octeontx2/otx2_rx.h | 24 +++++++++++++---------
drivers/net/octeontx2/otx2_tx.h | 19 +++++++++++++----
7 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h
index 9c9718f6f..5cd80e3b2 100644
--- a/drivers/event/octeontx2/otx2_evdev.h
+++ b/drivers/event/octeontx2/otx2_evdev.h
@@ -25,6 +25,7 @@
#define OTX2_SSO_SQB_LIMIT (0x180)
#define OTX2_SSO_XAQ_SLACK (8)
#define OTX2_SSO_XAQ_CACHE_CNT (0x7)
+#define OTX2_SSO_WQE_SG_PTR (9)
/* SSO LF register offsets (BAR2) */
#define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)
@@ -222,10 +223,14 @@ otx2_wqe_to_mbuf(uint64_t get_work1, const uint64_t mbuf, uint8_t port_id,
const void * const lookup_mem)
{
struct nix_wqe_hdr_s *wqe = (struct nix_wqe_hdr_s *)get_work1;
+ uint64_t val = mbuf_init.value | (uint64_t)port_id << 48;
+
+ if (flags & NIX_RX_OFFLOAD_TSTAMP_F)
+ val |= NIX_TIMESYNC_RX_OFFSET;
otx2_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
(struct rte_mbuf *)mbuf, lookup_mem,
- mbuf_init.value | (uint64_t)port_id << 48, flags);
+ val, flags);
}
diff --git a/drivers/event/octeontx2/otx2_worker.h b/drivers/event/octeontx2/otx2_worker.h
index 3c847d223..76f91bb59 100644
--- a/drivers/event/octeontx2/otx2_worker.h
+++ b/drivers/event/octeontx2/otx2_worker.h
@@ -18,6 +18,7 @@ otx2_ssogws_get_work(struct otx2_ssogws *ws, struct rte_event *ev,
const uint32_t flags, const void * const lookup_mem)
{
union otx2_sso_event event;
+ uint64_t tstamp_ptr;
uint64_t get_work1;
uint64_t mbuf;
@@ -69,8 +70,10 @@ otx2_ssogws_get_work(struct otx2_ssogws *ws, struct rte_event *ev,
otx2_wqe_to_mbuf(get_work1, mbuf, event.sub_event_type,
(uint32_t) event.get_work0, flags, lookup_mem);
/* Extracting tstamp, if PTP enabled*/
+ tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)get_work1)
+ + OTX2_SSO_WQE_SG_PTR);
otx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, ws->tstamp,
- flags);
+ flags, (uint64_t *)tstamp_ptr);
get_work1 = mbuf;
}
@@ -86,6 +89,7 @@ otx2_ssogws_get_work_empty(struct otx2_ssogws *ws, struct rte_event *ev,
const uint32_t flags)
{
union otx2_sso_event event;
+ uint64_t tstamp_ptr;
uint64_t get_work1;
uint64_t mbuf;
@@ -131,8 +135,10 @@ otx2_ssogws_get_work_empty(struct otx2_ssogws *ws, struct rte_event *ev,
otx2_wqe_to_mbuf(get_work1, mbuf, event.sub_event_type,
(uint32_t) event.get_work0, flags, NULL);
/* Extracting tstamp, if PTP enabled*/
+ tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)get_work1)
+ + OTX2_SSO_WQE_SG_PTR);
otx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, ws->tstamp,
- flags);
+ flags, (uint64_t *)tstamp_ptr);
get_work1 = mbuf;
}
diff --git a/drivers/event/octeontx2/otx2_worker_dual.h b/drivers/event/octeontx2/otx2_worker_dual.h
index 4a72f424d..5134e3d52 100644
--- a/drivers/event/octeontx2/otx2_worker_dual.h
+++ b/drivers/event/octeontx2/otx2_worker_dual.h
@@ -21,6 +21,7 @@ otx2_ssogws_dual_get_work(struct otx2_ssogws_state *ws,
{
const uint64_t set_gw = BIT_ULL(16) | 1;
union otx2_sso_event event;
+ uint64_t tstamp_ptr;
uint64_t get_work1;
uint64_t mbuf;
@@ -70,8 +71,17 @@ otx2_ssogws_dual_get_work(struct otx2_ssogws_state *ws,
event.event_type == RTE_EVENT_TYPE_ETHDEV) {
otx2_wqe_to_mbuf(get_work1, mbuf, event.sub_event_type,
(uint32_t) event.get_work0, flags, lookup_mem);
- /* Extracting tstamp, if PTP enabled*/
- otx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp, flags);
+ /* Extracting tstamp, if PTP enabled. CGX will prepend the
+ * timestamp at starting of packet data and it can be derieved
+ * from WQE 9 dword which corresponds to SG iova.
+ * rte_pktmbuf_mtod_offset can be used for this purpose but it
+ * brings down the performance as it reads mbuf->buf_addr which
+ * is not part of cache in general fast path.
+ */
+ tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)get_work1)
+ + OTX2_SSO_WQE_SG_PTR);
+ otx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp, flags,
+ (uint64_t *)tstamp_ptr);
get_work1 = mbuf;
}
diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index b018b25b7..595c8003a 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -874,8 +874,6 @@ otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
send_mem = (struct nix_send_mem_s *)(txq->cmd +
(send_hdr->w0.sizem1 << 1));
send_mem->subdc = NIX_SUBDC_MEM;
- send_mem->dsz = 0x0;
- send_mem->wmem = 0x1;
send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
}
diff --git a/drivers/net/octeontx2/otx2_rx.c b/drivers/net/octeontx2/otx2_rx.c
index deefe9588..701efc858 100644
--- a/drivers/net/octeontx2/otx2_rx.c
+++ b/drivers/net/octeontx2/otx2_rx.c
@@ -68,7 +68,8 @@ nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
otx2_nix_cqe_to_mbuf(cq, cq->tag, mbuf, lookup_mem, mbuf_init,
flags);
- otx2_nix_mbuf_to_tstamp(mbuf, rxq->tstamp, flags);
+ otx2_nix_mbuf_to_tstamp(mbuf, rxq->tstamp, flags,
+ (uint64_t *)((uint8_t *)mbuf + data_off));
rx_pkts[packets++] = mbuf;
otx2_prefetch_store_keep(mbuf);
head++;
diff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h
index e150f38d7..d12e8b809 100644
--- a/drivers/net/octeontx2/otx2_rx.h
+++ b/drivers/net/octeontx2/otx2_rx.h
@@ -50,22 +50,26 @@ union mbuf_initializer {
static __rte_always_inline void
otx2_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
- struct otx2_timesync_info *tstamp, const uint16_t flag)
+ struct otx2_timesync_info *tstamp, const uint16_t flag,
+ uint64_t *tstamp_ptr)
{
if ((flag & NIX_RX_OFFLOAD_TSTAMP_F) &&
- mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC &&
(mbuf->data_off == RTE_PKTMBUF_HEADROOM +
NIX_TIMESYNC_RX_OFFSET)) {
- uint64_t *tstamp_ptr;
- /* Deal with rx timestamp */
- tstamp_ptr = rte_pktmbuf_mtod_offset(mbuf, uint64_t *,
- -NIX_TIMESYNC_RX_OFFSET);
+ /* Reading the rx timestamp inserted by CGX, viz at
+ * starting of the packet data.
+ */
mbuf->timestamp = rte_be_to_cpu_64(*tstamp_ptr);
- tstamp->rx_tstamp = mbuf->timestamp;
- tstamp->rx_ready = 1;
- mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST
- | PKT_RX_TIMESTAMP;
+ /* PKT_RX_IEEE1588_TMST flag needs to be set only in case
+ * PTP packets are received.
+ */
+ if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
+ tstamp->rx_tstamp = mbuf->timestamp;
+ tstamp->rx_ready = 1;
+ mbuf->ol_flags |= PKT_RX_IEEE1588_PTP |
+ PKT_RX_IEEE1588_TMST | PKT_RX_TIMESTAMP;
+ }
}
}
diff --git a/drivers/net/octeontx2/otx2_tx.h b/drivers/net/octeontx2/otx2_tx.h
index b75a220ea..494ba3884 100644
--- a/drivers/net/octeontx2/otx2_tx.h
+++ b/drivers/net/octeontx2/otx2_tx.h
@@ -43,18 +43,29 @@ otx2_nix_xmit_prepare_tstamp(uint64_t *cmd, const uint64_t *send_mem_desc,
if (flags & NIX_TX_OFFLOAD_TSTAMP_F) {
struct nix_send_mem_s *send_mem;
uint16_t off = (no_segdw - 1) << 1;
+ const uint8_t is_ol_tstamp = !(ol_flags & PKT_TX_IEEE1588_TMST);
send_mem = (struct nix_send_mem_s *)(cmd + off);
- if (flags & NIX_TX_MULTI_SEG_F)
+ if (flags & NIX_TX_MULTI_SEG_F) {
/* Retrieving the default desc values */
cmd[off] = send_mem_desc[6];
+ /* Using compiler barier to avoid voilation of C
+ * aliasing rules.
+ */
+ rte_compiler_barrier();
+ }
+
/* Packets for which PKT_TX_IEEE1588_TMST is not set, tx tstamp
- * should not be updated at tx tstamp registered address, rather
- * a dummy address which is eight bytes ahead would be updated
+ * should not be recorded, hence changing the alg type to
+ * NIX_SENDMEMALG_SET and also changing send mem addr field to
+ * next 8 bytes as it corrpt the actual tx tstamp registered
+ * address.
*/
+ send_mem->alg = NIX_SENDMEMALG_SETTSTMP - (is_ol_tstamp);
+
send_mem->addr = (rte_iova_t)((uint64_t *)send_mem_desc[7] +
- !(ol_flags & PKT_TX_IEEE1588_TMST));
+ (is_ol_tstamp));
}
}
--
2.18.0
next reply other threads:[~2019-07-27 14:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-27 14:57 Harman Kalra [this message]
2019-07-27 14:57 ` [dpdk-dev] [PATCH 2/2] net/octeontx2: support read clock API Harman Kalra
2019-07-27 15:48 ` Jerin Jacob Kollanukkaran
2019-07-27 20:41 ` [dpdk-dev] [PATCH v2 1/2] net/octeontx2: fix ptp performance issue Harman Kalra
2019-07-27 20:41 ` [dpdk-dev] [PATCH v2 2/2] net/octeontx2: support read clock API Harman Kalra
2019-07-28 7:43 ` Jerin Jacob Kollanukkaran
2019-07-28 9:09 ` [dpdk-dev] [PATCH v3 1/2] net/octeontx2: fix ptp performance issue Harman Kalra
2019-07-28 9:09 ` [dpdk-dev] [PATCH v3 2/2] net/octeontx2: support read clock API Harman Kalra
2019-07-28 16:52 ` [dpdk-dev] [PATCH v3 1/2] net/octeontx2: fix ptp performance issue Jerin Jacob Kollanukkaran
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1564239400-2919-1-git-send-email-hkalra@marvell.com \
--to=hkalra@marvell.com \
--cc=dev@dpdk.org \
--cc=jerinj@marvell.com \
--cc=kirankumark@marvell.com \
--cc=ndabilpuram@marvell.com \
--cc=pbhagavatula@marvell.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).