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H:MN2PR18MB2848.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ZXWuKBC3vChvGocDlLB5slqeMuPwWWuS1Ddf0kWAPUTCnPQ7m6c28a6CCSVFTFp2byacNqz2FHO0sF3th5Xi/b/54O9dp4MRHz9iDrWv8baPTIAukuJnUqCl0mVGz0MaC7EjB7tzbbjcD20HxB9kA/71deYnprw/Gahg6RJr9uKLXB6pOPZqXo+ZMeE/Gk+gqMXqMoEddw1n6rYXKih5F8g93ze01v9KLSx8F6IPzPgPcI453hb6Ixag6OKXSaatLFtbgaabXPKDOjIm0UOZGsxw7bZ0MKFb9LM8tdyFuWSuEBLOMIpo8bjjmT+rZh+IcFBZFeiq4Iafq8gfH5vjBdd0TkoSYj4aRnrIc1Qazfl2hirtBGR4txkFU8gv9fKmGgHmVC+jsdeMv4kcNYh6xDiR8bMN5FctrxJayJMIwko= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3f2d5db5-3fba-49fc-0fd5-08d712a2bd5b X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Jul 2019 14:57:26.9396 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hkalra@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2542 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-07-27_12:2019-07-26,2019-07-27 signatures=0 Subject: [dpdk-dev] [PATCH 2/2] net/octeontx2: support read clock API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch implements read clock api whose purpose is to return raw clock ticks. Using this API real time ticks spent in processing a packet can be known: - mbuf->timestamp Signed-off-by: Harman Kalra --- drivers/common/octeontx2/otx2_mbox.h | 2 + drivers/net/octeontx2/otx2_ethdev.c | 86 ++++++++++++++++++++++++++++ drivers/net/octeontx2/otx2_ethdev.h | 4 ++ drivers/net/octeontx2/otx2_ptp.c | 30 ++++++++++ 4 files changed, 122 insertions(+) diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx= 2/otx2_mbox.h index c0bb676b2..b2c59c86e 100644 --- a/drivers/common/octeontx2/otx2_mbox.h +++ b/drivers/common/octeontx2/otx2_mbox.h @@ -1354,11 +1354,13 @@ struct ptp_req { struct mbox_msghdr hdr; uint8_t __otx2_io op; int64_t __otx2_io scaled_ppm; + uint8_t __otx2_io is_pmu; }; =20 struct ptp_rsp { struct mbox_msghdr hdr; uint64_t __otx2_io clk; + uint64_t __otx2_io tsc; }; =20 struct get_hw_cap_rsp { diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/ot= x2_ethdev.c index 595c8003a..799e67480 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -521,6 +521,17 @@ otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, u= int16_t rq, =20 eth_dev->data->rx_queues[rq] =3D rxq; eth_dev->data->rx_queue_state[rq] =3D RTE_ETH_QUEUE_STATE_STOPPED; + + /* Calculating delta and freq mult between PTP HI clock and rdtsc. + * These are needed for deriving PTP HI clock value from tsc counter. + */ + if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || + otx2_ethdev_is_ptp_en(dev)) { + rc =3D otx2_nix_raw_clock_rdtsc_conv(dev); + if (rc) + otx2_err("Failed to calculate delta and freq mult"); + } + return 0; =20 free_rxq: @@ -1186,6 +1197,79 @@ nix_set_nop_rxtx_function(struct rte_eth_dev *eth_de= v) rte_mb(); } =20 +static int +nix_read_raw_clock(struct otx2_eth_dev *dev, uint64_t *clock, uint64_t *ts= c, + uint8_t is_pmu) +{ + struct otx2_mbox *mbox =3D dev->mbox; + struct ptp_req *req; + struct ptp_rsp *rsp; + int rc =3D 0; + + req =3D otx2_mbox_alloc_msg_ptp_op(mbox); + req->op =3D PTP_OP_GET_CLOCK; + req->is_pmu =3D is_pmu; + rc =3D otx2_mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto done; + + *clock =3D rsp->clk; + *tsc =3D rsp->tsc; + +done: + return rc; +} + +/* This function calculates two parameters "clk_freq_mult" and + * "clk_delta" which is useful in deriving PTP HI clock from + * rdtsc value. + */ +int +otx2_nix_raw_clock_rdtsc_conv(struct otx2_eth_dev *dev) +{ + uint64_t ticks_base =3D 0, ticks =3D 0, t_freq =3D 0, tsc =3D 0; + uint8_t retval =3D 0, val; + + /* Calculating the frequency at which PTP HI clock is running */ + retval =3D nix_read_raw_clock(dev, &ticks_base, &tsc, false); + if (retval !=3D 0) { + otx2_err("Failed to read the raw clock value: %d", retval); + goto done; + } + + rte_delay_ms(100); + + retval =3D nix_read_raw_clock(dev, &ticks, &tsc, false); + if (retval !=3D 0) { + otx2_err("Failed to read the raw clock value: %d", retval); + goto done; + } + + t_freq =3D (ticks - ticks_base) * 10; + + /* Calculating the freq multiplier viz the ratio between the + * frequency at which PTP HI clock works and rdtsc clock runs + */ + dev->clk_freq_mult =3D + (double)pow(10, floor(log10(t_freq))) / rte_get_timer_hz(); + + val =3D false; +#ifdef RTE_ARM_EAL_RDTSC_USE_PMU + val =3D true; +#endif + retval =3D nix_read_raw_clock(dev, &ticks, &tsc, val); + if (retval !=3D 0) { + otx2_err("Failed to read the raw clock value: %d", retval); + goto done; + } + + /* Calculating delta between PTP HI clock and rdtsc */ + dev->clk_delta =3D ((uint64_t)(ticks / dev->clk_freq_mult) - tsc); + +done: + return retval; +} + static int otx2_nix_configure(struct rte_eth_dev *eth_dev) { @@ -1363,6 +1447,7 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev) dev->configured =3D 1; dev->configured_nb_rx_qs =3D data->nb_rx_queues; dev->configured_nb_tx_qs =3D data->nb_tx_queues; + return 0; =20 cq_fini: @@ -1649,6 +1734,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops =3D = { .vlan_pvid_set =3D otx2_nix_vlan_pvid_set, .rx_queue_intr_enable =3D otx2_nix_rx_queue_intr_enable, .rx_queue_intr_disable =3D otx2_nix_rx_queue_intr_disable, + .read_clock =3D otx2_nix_read_clock, }; =20 static inline int diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/ot= x2_ethdev.h index 863d4877f..a2bd0ffcf 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -300,6 +300,8 @@ struct otx2_eth_dev { struct rte_timecounter systime_tc; struct rte_timecounter rx_tstamp_tc; struct rte_timecounter tx_tstamp_tc; + double clk_freq_mult; + uint64_t clk_delta; } __rte_cache_aligned; =20 struct otx2_eth_txq { @@ -527,5 +529,7 @@ int otx2_nix_timesync_write_time(struct rte_eth_dev *et= h_dev, int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev, struct timespec *ts); int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en); +int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time); +int otx2_nix_raw_clock_rdtsc_conv(struct otx2_eth_dev *dev); =20 #endif /* __OTX2_ETHDEV_H__ */ diff --git a/drivers/net/octeontx2/otx2_ptp.c b/drivers/net/octeontx2/otx2_= ptp.c index 0186c629a..3f54cfeaf 100644 --- a/drivers/net/octeontx2/otx2_ptp.c +++ b/drivers/net/octeontx2/otx2_ptp.c @@ -224,6 +224,13 @@ otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_= dev, int64_t delta) rc =3D otx2_mbox_process_msg(mbox, (void *)&rsp); if (rc) return rc; + /* Since the frequency of PTP comp register is tuned, delta and + * freq mult calculation for deriving PTP_HI from rdtsc should + * be done again. + */ + rc =3D otx2_nix_raw_clock_rdtsc_conv(dev); + if (rc) + otx2_err("Failed to calculate delta and freq mult"); } dev->systime_tc.nsec +=3D delta; dev->rx_tstamp_tc.nsec +=3D delta; @@ -271,3 +278,26 @@ otx2_nix_timesync_read_time(struct rte_eth_dev *eth_de= v, struct timespec *ts) =20 return 0; } + + +int +otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock) +{ + struct otx2_eth_dev *dev =3D otx2_eth_pmd_priv(eth_dev); + + if (!otx2_ethdev_is_ptp_en(dev)) { + otx2_err("PTP should be enabled."); + return -EINVAL; + } + + /* This API returns the raw PTP HI clock value. Since LFs doesn't + * have direct access to PTP registers and it requires mbox msg + * to AF for this value. In fastpath reading this value for every + * packet (which involes mbox call) becomes very expensive, hence + * we should be able to derive PTP HI clock value from rdtsc by + * using freq_mult and clk_delta calculated during configure stage. + */ + *clock =3D (rte_rdtsc() + dev->clk_delta) * dev->clk_freq_mult; + + return 0; +} --=20 2.18.0