[dpdk-dev] [PATCH 1/2] test/rcu: fix the compiling error for armv8.2

[dpdk-dev] [PATCH 1/2] test/rcu: fix the compiling error for armv8.2

[Gavin Hu]

With "-march=armv8.2-a" specified, a compiling error generated:
app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
expressions of different signedness: ‘unsigned int’ and ‘int’
[-Werror=sign-compare]

Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
Cc: stable@dpdk.org

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
---
 app/test/test_rcu_qsbr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c
index 1d273e3..b008c9d 100644
--- a/app/test/test_rcu_qsbr.c
+++ b/app/test/test_rcu_qsbr.c
@@ -231,7 +231,7 @@ test_rcu_qsbr_thread_unregister(void)
 		/* Update quiescent state counter */
 		for (i = 0; i < num_threads[j]; i++) {
 			/* Skip one update */
-			if (i == (RTE_MAX_LCORE - 10))
+			if (i == (unsigned int)(RTE_MAX_LCORE - 10))
 				continue;
 			rte_rcu_qsbr_quiescent(t[0],
 				(j == 2) ? (RTE_MAX_LCORE - 1) : i);
-- 
2.7.4

[dpdk-dev] [PATCH 2/2] config: add N1SDP configuration

[Gavin Hu]

For more information of this platform, refer to:
https://community.arm.com/developer/tools-software/oss-platforms/w/
docs/440/neoverse-n1-sdp

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/meson.build                      |  4 +++-
 config/defconfig_arm64-neoversen1-linux-gcc | 16 ++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)
 create mode 100644 config/defconfig_arm64-neoversen1-linux-gcc

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 979018e..03afb14 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -87,7 +87,9 @@ machine_args_generic = [
 	['0xd07', ['-mcpu=cortex-a57']],
 	['0xd08', ['-mcpu=cortex-a72']],
 	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']]]
+	['0xd0a', ['-mcpu=cortex-a75']],
+	['0xd0b', ['-mcpu=cortex-a76']],
+	['0xd0c', ['-march=armv8.2-a', '-mcpu=neoverse-n1']]]
 
 machine_args_cavium = [
 	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
diff --git a/config/defconfig_arm64-neoversen1-linux-gcc b/config/defconfig_arm64-neoversen1-linux-gcc
new file mode 100644
index 0000000..b21bacb
--- /dev/null
+++ b/config/defconfig_arm64-neoversen1-linux-gcc
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019 Arm Ltd.
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="armv8.2-a"
+# CONFIG_RTE_ARCH_ARM_TUNE="cortex-a57"
+CONFIG_RTE_ARCH_ARM_TUNE="neoverse-n1"
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=4
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
-- 
2.7.4

[dpdk-dev] [PATCH v2 0/3] add arm neoverse N1 SDP configuration

[Gavin Hu]

Nerverse N1 is a new SoC based on armv8.2-a and with other advanced features.
N1 SDP is the infrastructure segment development platform with N1 SoC inside.
Here is more information about it:
https://community.arm.com/developer/tools-software/oss-platforms/w/docs/440/neoverse-n1-sdp

V2:
Add the cover letter and the patch for cortex-a76 configuration

Gavin Hu (3):
  test/rcu: fix the compiling error for armv8.2
  config: add arm neoverse N1 SDP configuration
  config: add cortex-a76 configuration

 app/test/test_rcu_qsbr.c                       |  2 +-
 config/arm/meson.build                         | 10 +++++++-
 config/defconfig_arm64-neoversen1-linux-gcc    |  1 +
 config/defconfig_arm64-neoversen1-linuxapp-gcc | 15 ++++++++++++
 mk/machine/neoversen1/rte.vars.mk              | 34 ++++++++++++++++++++++++++
 5 files changed, 60 insertions(+), 2 deletions(-)
 create mode 120000 config/defconfig_arm64-neoversen1-linux-gcc
 create mode 100644 config/defconfig_arm64-neoversen1-linuxapp-gcc
 create mode 100644 mk/machine/neoversen1/rte.vars.mk

-- 
2.7.4

[dpdk-dev] [PATCH v2 1/3] test/rcu: fix the compiling error for armv8.2

[Gavin Hu]

With "-march=armv8.2-a" specified, a compiling error generated:
app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
expressions of different signedness: ‘unsigned int’ and ‘int’
[-Werror=sign-compare]

Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
Cc: stable@dpdk.org

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
---
 app/test/test_rcu_qsbr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c
index 1d273e3..b008c9d 100644
--- a/app/test/test_rcu_qsbr.c
+++ b/app/test/test_rcu_qsbr.c
@@ -231,7 +231,7 @@ test_rcu_qsbr_thread_unregister(void)
 		/* Update quiescent state counter */
 		for (i = 0; i < num_threads[j]; i++) {
 			/* Skip one update */
-			if (i == (RTE_MAX_LCORE - 10))
+			if (i == (unsigned int)(RTE_MAX_LCORE - 10))
 				continue;
 			rte_rcu_qsbr_quiescent(t[0],
 				(j == 2) ? (RTE_MAX_LCORE - 1) : i);
-- 
2.7.4

[dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Gavin Hu]

Arm N1 SDP is an infrastructure segment development platform
based on armv8.2-a Neoverse N1 CPU. For more information, refer to:
https://community.arm.com/developer/tools-software/oss-platforms/w/
docs/440/neoverse-n1-sdp

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
---
 config/arm/meson.build                         |  9 ++++++-
 config/defconfig_arm64-neoversen1-linux-gcc    |  1 +
 config/defconfig_arm64-neoversen1-linuxapp-gcc | 15 ++++++++++++
 mk/machine/neoversen1/rte.vars.mk              | 34 ++++++++++++++++++++++++++
 4 files changed, 58 insertions(+), 1 deletion(-)
 create mode 120000 config/defconfig_arm64-neoversen1-linux-gcc
 create mode 100644 config/defconfig_arm64-neoversen1-linuxapp-gcc
 create mode 100644 mk/machine/neoversen1/rte.vars.mk

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 979018e..995d321 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -63,6 +63,12 @@ flags_armada = [
 	['RTE_MAX_LCORE', 16]]
 
 flags_default_extra = []
+flags_neoversen1_extra = [
+	['RTE_MACHINE', '"neoversen1"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 4],
+	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
+	['RTE_LIBRTE_VHOST_NUMA', false]]
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
@@ -87,7 +93,8 @@ machine_args_generic = [
 	['0xd07', ['-mcpu=cortex-a57']],
 	['0xd08', ['-mcpu=cortex-a72']],
 	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']]]
+	['0xd0a', ['-mcpu=cortex-a75']],
+	['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'], flags_neoversen1_extra]]
 
 machine_args_cavium = [
 	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
diff --git a/config/defconfig_arm64-neoversen1-linux-gcc b/config/defconfig_arm64-neoversen1-linux-gcc
new file mode 120000
index 0000000..47c96a4
--- /dev/null
+++ b/config/defconfig_arm64-neoversen1-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-neoversen1-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-neoversen1-linuxapp-gcc b/config/defconfig_arm64-neoversen1-linuxapp-gcc
new file mode 100644
index 0000000..39b9e1f
--- /dev/null
+++ b/config/defconfig_arm64-neoversen1-linuxapp-gcc
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019 Arm Ltd.
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="neoversen1"
+CONFIG_RTE_ARCH_ARM_TUNE="neoverse-n1"
+CONFIG_RTE_MAX_LCORE=4
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_CACHE_LINE_SIZE=64
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
diff --git a/mk/machine/neoversen1/rte.vars.mk b/mk/machine/neoversen1/rte.vars.mk
new file mode 100644
index 0000000..6d69de0
--- /dev/null
+++ b/mk/machine/neoversen1/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019 Arm Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.2-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=neoverse-n1)
-- 
2.7.4

[dpdk-dev] [PATCH v2 3/3] config: add cortex-a76 configuration

[Gavin Hu]

To make the list complete and consistent, add cortex-a76 configuration.

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
---
 config/arm/meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 995d321..1ac798e 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -94,6 +94,7 @@ machine_args_generic = [
 	['0xd08', ['-mcpu=cortex-a72']],
 	['0xd09', ['-mcpu=cortex-a73']],
 	['0xd0a', ['-mcpu=cortex-a75']],
+	['0xd0b', ['-mcpu=cortex-a76']],
 	['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'], flags_neoversen1_extra]]
 
 machine_args_cavium = [
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Ola Liljedahl]

On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> Arm N1 SDP is an infrastructure segment development platform
> based on armv8.2-a Neoverse N1 CPU. For more information, refer to:
> https://community.arm.com/developer/tools-software/oss-platforms/w/
> docs/440/neoverse-n1-sdp
> 
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Reviewed-by: Steve Capper <steve.capper@arm.com>
> ---
>  config/arm/meson.build                         |  9 ++++++-
>  config/defconfig_arm64-neoversen1-linux-gcc    |  1 +
>  config/defconfig_arm64-neoversen1-linuxapp-gcc | 15 ++++++++++++
>  mk/machine/neoversen1/rte.vars.mk              | 34
> ++++++++++++++++++++++++++
>  4 files changed, 58 insertions(+), 1 deletion(-)
>  create mode 120000 config/defconfig_arm64-neoversen1-linux-gcc
>  create mode 100644 config/defconfig_arm64-neoversen1-linuxapp-gcc
>  create mode 100644 mk/machine/neoversen1/rte.vars.mk
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 979018e..995d321 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -63,6 +63,12 @@ flags_armada = [
>  	['RTE_MAX_LCORE', 16]]
>  
>  flags_default_extra = []
> +flags_neoversen1_extra = [
> +	['RTE_MACHINE', '"neoversen1"'],
What does RTE_MACHINE stand for?

Neoverse N1 is a CPU core, not a platform, not a SoC architecture etc.
Many different SoC's can be designed using the N1 core.
Some will be small with few cores and no NUMA, others might be large with many
cores and multi-socket (NUMA) support.
The N1SDP (N1 System Development Platform) is using such a small SoC (specially
designed for the N1DSP, it is not going to show up in other platforms). The
configuration below matches N1SDP but will most likely not match other future
N1-based SoC's. What do we do when other quite different "machines" using the
Neoverse N1 core shows up? Is it OK to qualitatively change these
configurations later?

> +	['RTE_MAX_NUMA_NODES', 1],
> +	['RTE_MAX_LCORE', 4],
> +	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> +	['RTE_LIBRTE_VHOST_NUMA', false]]
>  flags_thunderx_extra = [
>  	['RTE_MACHINE', '"thunderx"'],
>  	['RTE_USE_C11_MEM_MODEL', false]]
> @@ -87,7 +93,8 @@ machine_args_generic = [
>  	['0xd07', ['-mcpu=cortex-a57']],
>  	['0xd08', ['-mcpu=cortex-a72']],
>  	['0xd09', ['-mcpu=cortex-a73']],
> -	['0xd0a', ['-mcpu=cortex-a75']]]
> +	['0xd0a', ['-mcpu=cortex-a75']],
> +	['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'],
> flags_neoversen1_extra]]
>  
>  machine_args_cavium = [
>  	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> diff --git a/config/defconfig_arm64-neoversen1-linux-gcc
> b/config/defconfig_arm64-neoversen1-linux-gcc
> new file mode 120000
> index 0000000..47c96a4
> --- /dev/null
> +++ b/config/defconfig_arm64-neoversen1-linux-gcc
> @@ -0,0 +1 @@
> +defconfig_arm64-neoversen1-linuxapp-gcc
> \ No newline at end of file
!

> diff --git a/config/defconfig_arm64-neoversen1-linuxapp-gcc
> b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> new file mode 100644
> index 0000000..39b9e1f
> --- /dev/null
> +++ b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > 
> @@ -0,0 +1,15 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2019 Arm Ltd.
> +#
> +
> +#include "defconfig_arm64-armv8a-linux-gcc"
> +
> +CONFIG_RTE_MACHINE="neoversen1"
This should probably be "n1sdp" as this is the name of the
platform that matches the below configuration.

> +CONFIG_RTE_ARCH_ARM_TUNE="neoverse-n1"
> +CONFIG_RTE_MAX_LCORE=4
> +CONFIG_RTE_MAX_NUMA_NODES=1
> +CONFIG_RTE_CACHE_LINE_SIZE=64
> +
> +# Doesn't support NUMA
> +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
> +CONFIG_RTE_LIBRTE_VHOST_NUMA=n
> diff --git a/mk/machine/neoversen1/rte.vars.mk
> b/mk/machine/neoversen1/rte.vars.mk
> new file mode 100644
> index 0000000..6d69de0
> --- /dev/null
> +++ b/mk/machine/neoversen1/rte.vars.mk
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2019 Arm Ltd
> +#
> +
> +#
> +# machine:
> +#
> +#   - can define ARCH variable (overridden by cmdline value)
> +#   - can define CROSS variable (overridden by cmdline value)
> +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - may override any previously defined variable
> +#
> +
> +# ARCH =
> +# CROSS =
> +# MACHINE_CFLAGS =
> +# MACHINE_LDFLAGS =
> +# MACHINE_ASFLAGS =
> +# CPU_CFLAGS =
> +# CPU_LDFLAGS =
> +# CPU_ASFLAGS =
> +
> +include $(RTE_SDK)/mk/rte.helper.mk
> +
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.2-a+crc+crypto)
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=neoverse-n1)
> 
> 
-- 
Ola Liljedahl, Networking System Architect, Arm
Phone +46706866373, Skype ola.liljedahl

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Honnappa Nagarahalli]

<snip>

> 
> On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> > Arm N1 SDP is an infrastructure segment development platform based on
> > armv8.2-a Neoverse N1 CPU. For more information, refer to:
> > https://community.arm.com/developer/tools-software/oss-platforms/w/
> > docs/440/neoverse-n1-sdp
> >
> > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > ---
> >  config/arm/meson.build                         |  9 ++++++-
> >  config/defconfig_arm64-neoversen1-linux-gcc    |  1 +
> >  config/defconfig_arm64-neoversen1-linuxapp-gcc | 15 ++++++++++++
> >  mk/machine/neoversen1/rte.vars.mk              | 34
> > ++++++++++++++++++++++++++
> >  4 files changed, 58 insertions(+), 1 deletion(-)  create mode 120000
> > config/defconfig_arm64-neoversen1-linux-gcc
> >  create mode 100644 config/defconfig_arm64-neoversen1-linuxapp-gcc
> >  create mode 100644 mk/machine/neoversen1/rte.vars.mk
> >
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > 979018e..995d321 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -63,6 +63,12 @@ flags_armada = [
> >  ['RTE_MAX_LCORE', 16]]
> >
> >  flags_default_extra = []
> > +flags_neoversen1_extra = [
> > +['RTE_MACHINE', '"neoversen1"'],
> What does RTE_MACHINE stand for?
Not sure, what it stands for. I cannot find a consistent assignment for it. Some time it takes 'armv8' (in the case of BlueField), 'dpaa', 'dpaa2', 'thunderx' etc (architecture, SoC, micro-architecture). I also cannot find an instance of its usage.

> 
> Neoverse N1 is a CPU core, not a platform, not a SoC architecture etc.
> Many different SoC's can be designed using the N1 core.
> Some will be small with few cores and no NUMA, others might be large with
> many cores and multi-socket (NUMA) support.
> The N1SDP (N1 System Development Platform) is using such a small SoC
> (specially designed for the N1DSP, it is not going to show up in other
> platforms). The configuration below matches N1SDP but will most likely not
> match other future N1-based SoC's. What do we do when other quite
> different "machines" using the Neoverse N1 core shows up? Is it OK to
> qualitatively change these configurations later?
All other implementations of N1 based SoCs should have their own implementor ID and variant. Hence they should not clash with these configurations.
IIRC, BlueField had the same implementation ID as Arm (0x41), so ' flags_arm' was modified to reflect BlueField configuration. Hopefully, this will be corrected in the future.

> 
> > +['RTE_MAX_NUMA_NODES', 1],
> > +['RTE_MAX_LCORE', 4],
> > +['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> ['RTE_LIBRTE_VHOST_NUMA',
> > +false]]
> >  flags_thunderx_extra = [
> >  ['RTE_MACHINE', '"thunderx"'],
> >  ['RTE_USE_C11_MEM_MODEL', false]]
> > @@ -87,7 +93,8 @@ machine_args_generic = [  ['0xd07',
> > ['-mcpu=cortex-a57']],  ['0xd08', ['-mcpu=cortex-a72']],  ['0xd09',
> > ['-mcpu=cortex-a73']], -['0xd0a', ['-mcpu=cortex-a75']]]
> > +['0xd0a', ['-mcpu=cortex-a75']],
> > +['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'],
> > flags_neoversen1_extra]]
> >
> >  machine_args_cavium = [
> >  ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > diff --git a/config/defconfig_arm64-neoversen1-linux-gcc
> > b/config/defconfig_arm64-neoversen1-linux-gcc
> > new file mode 120000
> > index 0000000..47c96a4
> > --- /dev/null
> > +++ b/config/defconfig_arm64-neoversen1-linux-gcc
> > @@ -0,0 +1 @@
> > +defconfig_arm64-neoversen1-linuxapp-gcc
> > \ No newline at end of file
> !
> 
> > diff --git a/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > new file mode 100644
> > index 0000000..39b9e1f
> > --- /dev/null
> > +++ b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > >
> > @@ -0,0 +1,15 @@
> > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019 Arm Ltd.
> > +#
> > +
> > +#include "defconfig_arm64-armv8a-linux-gcc"
> > +
> > +CONFIG_RTE_MACHINE="neoversen1"
> This should probably be "n1sdp" as this is the name of the platform that
> matches the below configuration.
A clear definition of RTE_MACHINE is required. Jerin?

> 
> > +CONFIG_RTE_ARCH_ARM_TUNE="neoverse-n1"
> > +CONFIG_RTE_MAX_LCORE=4
> > +CONFIG_RTE_MAX_NUMA_NODES=1
> > +CONFIG_RTE_CACHE_LINE_SIZE=64
> > +
> > +# Doesn't support NUMA
> > +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
> > +CONFIG_RTE_LIBRTE_VHOST_NUMA=n
> > diff --git a/mk/machine/neoversen1/rte.vars.mk
> > b/mk/machine/neoversen1/rte.vars.mk
> > new file mode 100644
> > index 0000000..6d69de0
> > --- /dev/null
> > +++ b/mk/machine/neoversen1/rte.vars.mk
> > @@ -0,0 +1,34 @@
> > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019 Arm Ltd #
> > +
> > +#
> > +# machine:
> > +#
> > +#   - can define ARCH variable (overridden by cmdline value)
> > +#   - can define CROSS variable (overridden by cmdline value)
> > +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> > +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> > +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> > +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> > +#     overrides the one defined in arch.
> > +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> > +#     overrides the one defined in arch.
> > +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> > +#     overrides the one defined in arch.
> > +#   - may override any previously defined variable
> > +#
> > +
> > +# ARCH =
> > +# CROSS =
> > +# MACHINE_CFLAGS =
> > +# MACHINE_LDFLAGS =
> > +# MACHINE_ASFLAGS =
> > +# CPU_CFLAGS =
> > +# CPU_LDFLAGS =
> > +# CPU_ASFLAGS =
> > +
> > +include $(RTE_SDK)/mk/rte.helper.mk
> > +
> > +MACHINE_CFLAGS += $(call rte_cc_has_argument,
> > +-march=armv8.2-a+crc+crypto) MACHINE_CFLAGS += $(call
> > +rte_cc_has_argument, -mcpu=neoverse-n1)
> >
> >
> --
> Ola Liljedahl, Networking System Architect, Arm Phone +46706866373, Skype
> ola.liljedahl

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Jerin Jacob]

On Fri, Oct 18, 2019 at 10:42 AM Honnappa Nagarahalli
<Honnappa.Nagarahalli@arm.com> wrote:
>
> <snip>
>
> >
> > On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> > > Arm N1 SDP is an infrastructure segment development platform based on
> > > armv8.2-a Neoverse N1 CPU. For more information, refer to:
> > > https://community.arm.com/developer/tools-software/oss-platforms/w/
> > > docs/440/neoverse-n1-sdp
> > >
> > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > > ---
> > >  config/arm/meson.build                         |  9 ++++++-
> > >  config/defconfig_arm64-neoversen1-linux-gcc    |  1 +
> > >  config/defconfig_arm64-neoversen1-linuxapp-gcc | 15 ++++++++++++
> > >  mk/machine/neoversen1/rte.vars.mk              | 34

> >
> > > diff --git a/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > > b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > > new file mode 100644
> > > index 0000000..39b9e1f
> > > --- /dev/null
> > > +++ b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > > >
> > > @@ -0,0 +1,15 @@
> > > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019 Arm Ltd.
> > > +#
> > > +
> > > +#include "defconfig_arm64-armv8a-linux-gcc"
> > > +
> > > +CONFIG_RTE_MACHINE="neoversen1"
> > This should probably be "n1sdp" as this is the name of the platform that
> > matches the below configuration.
> A clear definition of RTE_MACHINE is required. Jerin?

I think, In the existing scheme of things, RTE_MACHINE defines, where
to take the MACHINE_CFLAGS
mk/machine/xxxx/rte.vars.mk

Considering the fact that there will be a lot of reusable IPs(for CPU)
from ARM for  armv8, I think,
it would make sense to introduce  RTE_MICRO_ARCH to avoid a lot of
code duplications and
confusion.

RTE_ARCH                             example: "x86" or "arm64"
RTE_MICRO_ARCH               example: "a72" or "thunderx3" - defines
mcpu and armv8 verion arch etc
RTE_MACHINE                       example: "bluefield" or "thunderx3"
- defines, number of cores, NUMA or not? etc

RTE_MACHINE should be probe based  on "implementation ID" for arm64
and reuse already defined RTE_MICRO_ARCH
to avoid code duplication.


>
> >
> > > +CONFIG_RTE_ARCH_ARM_TUNE="neoverse-n1"
> > > +CONFIG_RTE_MAX_LCORE=4
> > > +CONFIG_RTE_MAX_NUMA_NODES=1
> > > +CONFIG_RTE_CACHE_LINE_SIZE=64
> > > +
> > > +# Doesn't support NUMA
> > > +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
> > > +CONFIG_RTE_LIBRTE_VHOST_NUMA=n
> > > diff --git a/mk/machine/neoversen1/rte.vars.mk
> > > b/mk/machine/neoversen1/rte.vars.mk
> > > new file mode 100644
> > > index 0000000..6d69de0
> > > --- /dev/null
> > > +++ b/mk/machine/neoversen1/rte.vars.mk
> > > @@ -0,0 +1,34 @@
> > > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019 Arm Ltd #
> > > +
> > > +#
> > > +# machine:
> > > +#
> > > +#   - can define ARCH variable (overridden by cmdline value)
> > > +#   - can define CROSS variable (overridden by cmdline value)
> > > +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> > > +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> > > +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> > > +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> > > +#     overrides the one defined in arch.
> > > +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> > > +#     overrides the one defined in arch.
> > > +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> > > +#     overrides the one defined in arch.
> > > +#   - may override any previously defined variable
> > > +#
> > > +
> > > +# ARCH =
> > > +# CROSS =
> > > +# MACHINE_CFLAGS =
> > > +# MACHINE_LDFLAGS =
> > > +# MACHINE_ASFLAGS =
> > > +# CPU_CFLAGS =
> > > +# CPU_LDFLAGS =
> > > +# CPU_ASFLAGS =
> > > +
> > > +include $(RTE_SDK)/mk/rte.helper.mk
> > > +
> > > +MACHINE_CFLAGS += $(call rte_cc_has_argument,
> > > +-march=armv8.2-a+crc+crypto) MACHINE_CFLAGS += $(call
> > > +rte_cc_has_argument, -mcpu=neoverse-n1)
> > >
> > >
> > --
> > Ola Liljedahl, Networking System Architect, Arm Phone +46706866373, Skype
> > ola.liljedahl
>

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Honnappa Nagarahalli]

> > <snip>
> >
> > >
> > > On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> > > > Arm N1 SDP is an infrastructure segment development platform based
> > > > on armv8.2-a Neoverse N1 CPU. For more information, refer to:
> > > > https://community.arm.com/developer/tools-software/oss-platforms/w
> > > > /
> > > > docs/440/neoverse-n1-sdp
> > > >
> > > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > > > ---
> > > >  config/arm/meson.build                         |  9 ++++++-
> > > >  config/defconfig_arm64-neoversen1-linux-gcc    |  1 +
> > > >  config/defconfig_arm64-neoversen1-linuxapp-gcc | 15 ++++++++++++
> > > >  mk/machine/neoversen1/rte.vars.mk              | 34
> 
> > >
> > > > diff --git a/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > > > b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > > > new file mode 100644
> > > > index 0000000..39b9e1f
> > > > --- /dev/null
> > > > +++ b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > > > >
> > > > @@ -0,0 +1,15 @@
> > > > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019 Arm Ltd.
> > > > +#
> > > > +
> > > > +#include "defconfig_arm64-armv8a-linux-gcc"
> > > > +
> > > > +CONFIG_RTE_MACHINE="neoversen1"
> > > This should probably be "n1sdp" as this is the name of the platform
> > > that matches the below configuration.
> > A clear definition of RTE_MACHINE is required. Jerin?
> 
> I think, In the existing scheme of things, RTE_MACHINE defines, where to take
> the MACHINE_CFLAGS mk/machine/xxxx/rte.vars.mk
Ok, thank you

> 
> Considering the fact that there will be a lot of reusable IPs(for CPU) from ARM
> for  armv8, I think, it would make sense to introduce  RTE_MICRO_ARCH to
> avoid a lot of code duplications and confusion.
> 
> RTE_ARCH                             example: "x86" or "arm64"
> RTE_MICRO_ARCH               example: "a72" or "thunderx3" - defines
> mcpu and armv8 verion arch etc
> RTE_MACHINE                       example: "bluefield" or "thunderx3"
> - defines, number of cores, NUMA or not? etc
Looking at mk/machine/ directory, looks like RTE_MACHINE seems to be defining micro-architecture for Intel. For ex: hsw, nhm, wsm. I see the same for Arm as well.
Are you suggesting that we use RTE_MICRO_ARCH to pick mk/micro-arch/xxxx/rte.vars.mk? and RTE_MACHINE would pick mk/machine/xxxx/rte.vars.mk, but contain NUMA, #of cores etc?

> 
> RTE_MACHINE should be probe based  on "implementation ID" for arm64 and
> reuse already defined RTE_MICRO_ARCH to avoid code duplication.
> 
> 
> >
> > >
> > > > +CONFIG_RTE_ARCH_ARM_TUNE="neoverse-n1"
> > > > +CONFIG_RTE_MAX_LCORE=4
> > > > +CONFIG_RTE_MAX_NUMA_NODES=1
> > > > +CONFIG_RTE_CACHE_LINE_SIZE=64
> > > > +
> > > > +# Doesn't support NUMA
> > > > +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
> > > > +CONFIG_RTE_LIBRTE_VHOST_NUMA=n
> > > > diff --git a/mk/machine/neoversen1/rte.vars.mk
> > > > b/mk/machine/neoversen1/rte.vars.mk
> > > > new file mode 100644
> > > > index 0000000..6d69de0
> > > > --- /dev/null
> > > > +++ b/mk/machine/neoversen1/rte.vars.mk
> > > > @@ -0,0 +1,34 @@
> > > > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019 Arm
> > > > +Ltd #
> > > > +
> > > > +#
> > > > +# machine:
> > > > +#
> > > > +#   - can define ARCH variable (overridden by cmdline value)
> > > > +#   - can define CROSS variable (overridden by cmdline value)
> > > > +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> > > > +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> > > > +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> > > > +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> > > > +#     overrides the one defined in arch.
> > > > +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> > > > +#     overrides the one defined in arch.
> > > > +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> > > > +#     overrides the one defined in arch.
> > > > +#   - may override any previously defined variable
> > > > +#
> > > > +
> > > > +# ARCH =
> > > > +# CROSS =
> > > > +# MACHINE_CFLAGS =
> > > > +# MACHINE_LDFLAGS =
> > > > +# MACHINE_ASFLAGS =
> > > > +# CPU_CFLAGS =
> > > > +# CPU_LDFLAGS =
> > > > +# CPU_ASFLAGS =
> > > > +
> > > > +include $(RTE_SDK)/mk/rte.helper.mk
> > > > +
> > > > +MACHINE_CFLAGS += $(call rte_cc_has_argument,
> > > > +-march=armv8.2-a+crc+crypto) MACHINE_CFLAGS += $(call
> > > > +rte_cc_has_argument, -mcpu=neoverse-n1)
> > > >
> > > >
> > > --
> > > Ola Liljedahl, Networking System Architect, Arm Phone +46706866373,
> > > Skype ola.liljedahl
> >

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Jerin Jacob]

On Wed, Oct 23, 2019 at 2:37 AM Honnappa Nagarahalli
<Honnappa.Nagarahalli@arm.com> wrote:
>
> > > <snip>
> > >
> > > >
> > > > On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> > > > > Arm N1 SDP is an infrastructure segment development platform based
> > > > > on armv8.2-a Neoverse N1 CPU. For more information, refer to:
> > > > > https://community.arm.com/developer/tools-software/oss-platforms/w
> > > > > /
> > > > > docs/440/neoverse-n1-sdp
> > > > >
> > > > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > > > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > > > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > > > > ---
> > > > >  config/arm/meson.build                         |  9 ++++++-
> > > > >  config/defconfig_arm64-neoversen1-linux-gcc    |  1 +
> > > > >  config/defconfig_arm64-neoversen1-linuxapp-gcc | 15 ++++++++++++
> > > > >  mk/machine/neoversen1/rte.vars.mk              | 34
> >
> > > >
> > > > > diff --git a/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > > > > b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > > > > new file mode 100644
> > > > > index 0000000..39b9e1f
> > > > > --- /dev/null
> > > > > +++ b/config/defconfig_arm64-neoversen1-linuxapp-gcc
> > > > > >
> > > > > @@ -0,0 +1,15 @@
> > > > > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019 Arm Ltd.
> > > > > +#
> > > > > +
> > > > > +#include "defconfig_arm64-armv8a-linux-gcc"
> > > > > +
> > > > > +CONFIG_RTE_MACHINE="neoversen1"
> > > > This should probably be "n1sdp" as this is the name of the platform
> > > > that matches the below configuration.
> > > A clear definition of RTE_MACHINE is required. Jerin?
> >
> > I think, In the existing scheme of things, RTE_MACHINE defines, where to take
> > the MACHINE_CFLAGS mk/machine/xxxx/rte.vars.mk
> Ok, thank you
>
> >
> > Considering the fact that there will be a lot of reusable IPs(for CPU) from ARM
> > for  armv8, I think, it would make sense to introduce  RTE_MICRO_ARCH to
> > avoid a lot of code duplications and confusion.
> >
> > RTE_ARCH                             example: "x86" or "arm64"
> > RTE_MICRO_ARCH               example: "a72" or "thunderx3" - defines
> > mcpu and armv8 verion arch etc
> > RTE_MACHINE                       example: "bluefield" or "thunderx3"
> > - defines, number of cores, NUMA or not? etc
> Looking at mk/machine/ directory, looks like RTE_MACHINE seems to be defining micro-architecture for Intel. For ex: hsw, nhm, wsm. I see the same for Arm as well.
> Are you suggesting that we use RTE_MICRO_ARCH to pick mk/micro-arch/xxxx/rte.vars.mk? and RTE_MACHINE would pick mk/machine/xxxx/rte.vars.mk, but contain NUMA, #of cores etc?

Yes for Make build. I think, it is deprecated soon, so we need a
similar solution for meson.

>
> >
> > RTE_MACHINE should be probe based  on "implementation ID" for arm64 and
> > reuse already defined RTE_MICRO_ARCH to avoid code duplication.
> >
> >
> > >
> > > >
> > > > > +CONFIG_RTE_ARCH_ARM_TUNE="neoverse-n1"
> > > > > +CONFIG_RTE_MAX_LCORE=4
> > > > > +CONFIG_RTE_MAX_NUMA_NODES=1
> > > > > +CONFIG_RTE_CACHE_LINE_SIZE=64
> > > > > +
> > > > > +# Doesn't support NUMA
> > > > > +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
> > > > > +CONFIG_RTE_LIBRTE_VHOST_NUMA=n
> > > > > diff --git a/mk/machine/neoversen1/rte.vars.mk
> > > > > b/mk/machine/neoversen1/rte.vars.mk
> > > > > new file mode 100644
> > > > > index 0000000..6d69de0
> > > > > --- /dev/null
> > > > > +++ b/mk/machine/neoversen1/rte.vars.mk
> > > > > @@ -0,0 +1,34 @@
> > > > > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019 Arm
> > > > > +Ltd #
> > > > > +
> > > > > +#
> > > > > +# machine:
> > > > > +#
> > > > > +#   - can define ARCH variable (overridden by cmdline value)
> > > > > +#   - can define CROSS variable (overridden by cmdline value)
> > > > > +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> > > > > +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> > > > > +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> > > > > +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> > > > > +#     overrides the one defined in arch.
> > > > > +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> > > > > +#     overrides the one defined in arch.
> > > > > +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> > > > > +#     overrides the one defined in arch.
> > > > > +#   - may override any previously defined variable
> > > > > +#
> > > > > +
> > > > > +# ARCH =
> > > > > +# CROSS =
> > > > > +# MACHINE_CFLAGS =
> > > > > +# MACHINE_LDFLAGS =
> > > > > +# MACHINE_ASFLAGS =
> > > > > +# CPU_CFLAGS =
> > > > > +# CPU_LDFLAGS =
> > > > > +# CPU_ASFLAGS =
> > > > > +
> > > > > +include $(RTE_SDK)/mk/rte.helper.mk
> > > > > +
> > > > > +MACHINE_CFLAGS += $(call rte_cc_has_argument,
> > > > > +-march=armv8.2-a+crc+crypto) MACHINE_CFLAGS += $(call
> > > > > +rte_cc_has_argument, -mcpu=neoverse-n1)
> > > > >
> > > > >
> > > > --
> > > > Ola Liljedahl, Networking System Architect, Arm Phone +46706866373,
> > > > Skype ola.liljedahl
> > >

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Thomas Monjalon]

23/10/2019 07:03, Jerin Jacob:
> On Wed, Oct 23, 2019 at 2:37 AM Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com> wrote:
> > > > > On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> > > > > > Arm N1 SDP is an infrastructure segment development platform based
> > > > > > on armv8.2-a Neoverse N1 CPU. For more information, refer to:
> > > > > > https://community.arm.com/developer/tools-software/oss-platforms/w
> > > > > > /
> > > > > > docs/440/neoverse-n1-sdp
> > > > > >
> > > > > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > > > > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > > > > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > > > > > ---
> > > > > > +CONFIG_RTE_MACHINE="neoversen1"
> > > > > This should probably be "n1sdp" as this is the name of the platform
> > > > > that matches the below configuration.
> > > > A clear definition of RTE_MACHINE is required. Jerin?
> > >
> > > I think, In the existing scheme of things, RTE_MACHINE defines, where to take
> > > the MACHINE_CFLAGS mk/machine/xxxx/rte.vars.mk
> > Ok, thank you
> >
> > >
> > > Considering the fact that there will be a lot of reusable IPs(for CPU) from ARM
> > > for  armv8, I think, it would make sense to introduce  RTE_MICRO_ARCH to
> > > avoid a lot of code duplications and confusion.
> > >
> > > RTE_ARCH                             example: "x86" or "arm64"
> > > RTE_MICRO_ARCH               example: "a72" or "thunderx3" - defines
> > > mcpu and armv8 verion arch etc
> > > RTE_MACHINE                       example: "bluefield" or "thunderx3"
> > > - defines, number of cores, NUMA or not? etc
> > Looking at mk/machine/ directory, looks like RTE_MACHINE seems to be defining micro-architecture for Intel. For ex: hsw, nhm, wsm. I see the same for Arm as well.
> > Are you suggesting that we use RTE_MICRO_ARCH to pick mk/micro-arch/xxxx/rte.vars.mk? and RTE_MACHINE would pick mk/machine/xxxx/rte.vars.mk, but contain NUMA, #of cores etc?
> 
> Yes for Make build. I think, it is deprecated soon, so we need a
> similar solution for meson.

Yes I would prefer we clean the mess in Meson,
instead of talking about the makefile system.
And honestly, N1 is not needed in the legacy makefile system.

So focusing on config/arm/meson.build,
I think RTE_MACHINE is defined only for API compatibility with makefile.
However, I doubt this value is used by any application.
I think we can try to remove RTE_MACHINE from meson builds in DPDK 19.11,
or use RTE_MACHINE as micro-arch (my preference).

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Honnappa Nagarahalli]

> 23/10/2019 07:03, Jerin Jacob:
> > On Wed, Oct 23, 2019 at 2:37 AM Honnappa Nagarahalli
> > <Honnappa.Nagarahalli@arm.com> wrote:
> > > > > > On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> > > > > > > Arm N1 SDP is an infrastructure segment development platform
> > > > > > > based on armv8.2-a Neoverse N1 CPU. For more information, refer
> to:
> > > > > > > https://community.arm.com/developer/tools-software/oss-platf
> > > > > > > orms/w
> > > > > > > /
> > > > > > > docs/440/neoverse-n1-sdp
> > > > > > >
> > > > > > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > > > > > Reviewed-by: Honnappa Nagarahalli
> > > > > > > <honnappa.nagarahalli@arm.com>
> > > > > > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > > > > > > ---
> > > > > > > +CONFIG_RTE_MACHINE="neoversen1"
> > > > > > This should probably be "n1sdp" as this is the name of the
> > > > > > platform that matches the below configuration.
> > > > > A clear definition of RTE_MACHINE is required. Jerin?
> > > >
> > > > I think, In the existing scheme of things, RTE_MACHINE defines,
> > > > where to take the MACHINE_CFLAGS mk/machine/xxxx/rte.vars.mk
> > > Ok, thank you
> > >
> > > >
> > > > Considering the fact that there will be a lot of reusable IPs(for
> > > > CPU) from ARM for  armv8, I think, it would make sense to
> > > > introduce  RTE_MICRO_ARCH to avoid a lot of code duplications and
> confusion.
> > > >
> > > > RTE_ARCH                             example: "x86" or "arm64"
> > > > RTE_MICRO_ARCH               example: "a72" or "thunderx3" - defines
> > > > mcpu and armv8 verion arch etc
> > > > RTE_MACHINE                       example: "bluefield" or "thunderx3"
> > > > - defines, number of cores, NUMA or not? etc
> > > Looking at mk/machine/ directory, looks like RTE_MACHINE seems to be
> defining micro-architecture for Intel. For ex: hsw, nhm, wsm. I see the same
> for Arm as well.
> > > Are you suggesting that we use RTE_MICRO_ARCH to pick mk/micro-
> arch/xxxx/rte.vars.mk? and RTE_MACHINE would pick
> mk/machine/xxxx/rte.vars.mk, but contain NUMA, #of cores etc?
> >
> > Yes for Make build. I think, it is deprecated soon, so we need a
> > similar solution for meson.
> 
> Yes I would prefer we clean the mess in Meson, instead of talking about the
> makefile system.
> And honestly, N1 is not needed in the legacy makefile system.
Unfortunately, most of the guys I talk to are still on makefile. When is makefile system getting removed?

> 
> So focusing on config/arm/meson.build,
> I think RTE_MACHINE is defined only for API compatibility with makefile.
> However, I doubt this value is used by any application.
> I think we can try to remove RTE_MACHINE from meson builds in DPDK 19.11,
> or use RTE_MACHINE as micro-arch (my preference).
'MACHINE' means different things to different people, which is the root cause of this discussion.
'MICRO-ARCH' has a very clear meaning. Do you see any problem going with MICRO-ARCH instead?

> 

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Thomas Monjalon]

28/10/2019 04:24, Honnappa Nagarahalli:
> > 23/10/2019 07:03, Jerin Jacob:
> > > On Wed, Oct 23, 2019 at 2:37 AM Honnappa Nagarahalli
> > > <Honnappa.Nagarahalli@arm.com> wrote:
> > > > > > > On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> > > > > > > > Arm N1 SDP is an infrastructure segment development platform
> > > > > > > > based on armv8.2-a Neoverse N1 CPU. For more information, refer
> > to:
> > > > > > > > https://community.arm.com/developer/tools-software/oss-platf
> > > > > > > > orms/w
> > > > > > > > /
> > > > > > > > docs/440/neoverse-n1-sdp
> > > > > > > >
> > > > > > > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > > > > > > Reviewed-by: Honnappa Nagarahalli
> > > > > > > > <honnappa.nagarahalli@arm.com>
> > > > > > > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > > > > > > > ---
> > > > > > > > +CONFIG_RTE_MACHINE="neoversen1"
> > > > > > > This should probably be "n1sdp" as this is the name of the
> > > > > > > platform that matches the below configuration.
> > > > > > A clear definition of RTE_MACHINE is required. Jerin?
> > > > >
> > > > > I think, In the existing scheme of things, RTE_MACHINE defines,
> > > > > where to take the MACHINE_CFLAGS mk/machine/xxxx/rte.vars.mk
> > > > Ok, thank you
> > > >
> > > > >
> > > > > Considering the fact that there will be a lot of reusable IPs(for
> > > > > CPU) from ARM for  armv8, I think, it would make sense to
> > > > > introduce  RTE_MICRO_ARCH to avoid a lot of code duplications and
> > confusion.
> > > > >
> > > > > RTE_ARCH                             example: "x86" or "arm64"
> > > > > RTE_MICRO_ARCH               example: "a72" or "thunderx3" - defines
> > > > > mcpu and armv8 verion arch etc
> > > > > RTE_MACHINE                       example: "bluefield" or "thunderx3"
> > > > > - defines, number of cores, NUMA or not? etc
> > > > Looking at mk/machine/ directory, looks like RTE_MACHINE seems to be
> > defining micro-architecture for Intel. For ex: hsw, nhm, wsm. I see the same
> > for Arm as well.
> > > > Are you suggesting that we use RTE_MICRO_ARCH to pick mk/micro-
> > arch/xxxx/rte.vars.mk? and RTE_MACHINE would pick
> > mk/machine/xxxx/rte.vars.mk, but contain NUMA, #of cores etc?
> > >
> > > Yes for Make build. I think, it is deprecated soon, so we need a
> > > similar solution for meson.
> > 
> > Yes I would prefer we clean the mess in Meson, instead of talking about the
> > makefile system.
> > And honestly, N1 is not needed in the legacy makefile system.
> Unfortunately, most of the guys I talk to are still on makefile.

You need to help them to switch.
Adding new targets in meson-only can be a good motivation :)

> When is makefile system getting removed?

It must be clearly decided and announced.
The previous techboard discussions were about making makefile
hardly usable during 2020, i.e. very soon.

> > So focusing on config/arm/meson.build,
> > I think RTE_MACHINE is defined only for API compatibility with makefile.
> > However, I doubt this value is used by any application.
> > I think we can try to remove RTE_MACHINE from meson builds in DPDK 19.11,
> > or use RTE_MACHINE as micro-arch (my preference).
> 'MACHINE' means different things to different people, which is the root cause of this discussion.
> 'MICRO-ARCH' has a very clear meaning. Do you see any problem going with MICRO-ARCH instead?

Some applications may use RTE_MACHINE for this purpose.
It is part of the API since the befinning of DPDK.
I don't see a real motivation to break this API now.

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Honnappa Nagarahalli]

<snip>

> 
> 28/10/2019 04:24, Honnappa Nagarahalli:
> > > 23/10/2019 07:03, Jerin Jacob:
> > > > On Wed, Oct 23, 2019 at 2:37 AM Honnappa Nagarahalli
> > > > <Honnappa.Nagarahalli@arm.com> wrote:
> > > > > > > > On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> > > > > > > > > Arm N1 SDP is an infrastructure segment development
> > > > > > > > > platform based on armv8.2-a Neoverse N1 CPU. For more
> > > > > > > > > information, refer
> > > to:
> > > > > > > > > https://community.arm.com/developer/tools-software/oss-p
> > > > > > > > > latf
> > > > > > > > > orms/w
> > > > > > > > > /
> > > > > > > > > docs/440/neoverse-n1-sdp
> > > > > > > > >
> > > > > > > > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > > > > > > > Reviewed-by: Honnappa Nagarahalli
> > > > > > > > > <honnappa.nagarahalli@arm.com>
> > > > > > > > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > > > > > > > > ---
> > > > > > > > > +CONFIG_RTE_MACHINE="neoversen1"
> > > > > > > > This should probably be "n1sdp" as this is the name of the
> > > > > > > > platform that matches the below configuration.
> > > > > > > A clear definition of RTE_MACHINE is required. Jerin?
> > > > > >
> > > > > > I think, In the existing scheme of things, RTE_MACHINE
> > > > > > defines, where to take the MACHINE_CFLAGS
> > > > > > mk/machine/xxxx/rte.vars.mk
> > > > > Ok, thank you
> > > > >
> > > > > >
> > > > > > Considering the fact that there will be a lot of reusable
> > > > > > IPs(for
> > > > > > CPU) from ARM for  armv8, I think, it would make sense to
> > > > > > introduce  RTE_MICRO_ARCH to avoid a lot of code duplications
> > > > > > and
> > > confusion.
> > > > > >
> > > > > > RTE_ARCH                             example: "x86" or "arm64"
I see that there are already RTE_ARCH_X86, RTE_ARCH_ARM, RTE_ARCH_ARM64, RTE_ARCH_PPC_64 etc. I believe they should be sufficient.

> > > > > > RTE_MICRO_ARCH               example: "a72" or "thunderx3" - defines
> > > > > > mcpu and armv8 verion arch etc
Are you suggesting this just for Arm platforms?
My understanding is your intention was to clean up the config/arm/meson.build file.

> > > > > > RTE_MACHINE                       example: "bluefield" or "thunderx3"
> > > > > > - defines, number of cores, NUMA or not? etc
> > > > > Looking at mk/machine/ directory, looks like RTE_MACHINE seems
> > > > > to be
> > > defining micro-architecture for Intel. For ex: hsw, nhm, wsm. I see
> > > the same for Arm as well.
> > > > > Are you suggesting that we use RTE_MICRO_ARCH to pick mk/micro-
> > > arch/xxxx/rte.vars.mk? and RTE_MACHINE would pick
> > > mk/machine/xxxx/rte.vars.mk, but contain NUMA, #of cores etc?
> > > >
> > > > Yes for Make build. I think, it is deprecated soon, so we need a
> > > > similar solution for meson.
> > >
> > > Yes I would prefer we clean the mess in Meson, instead of talking
> > > about the makefile system.
> > > And honestly, N1 is not needed in the legacy makefile system.
> > Unfortunately, most of the guys I talk to are still on makefile.
> 
> You need to help them to switch.
> Adding new targets in meson-only can be a good motivation :)
> 
> > When is makefile system getting removed?
> 
> It must be clearly decided and announced.
> The previous techboard discussions were about making makefile hardly
> usable during 2020, i.e. very soon.
> 
> > > So focusing on config/arm/meson.build, I think RTE_MACHINE is
> > > defined only for API compatibility with makefile.
> > > However, I doubt this value is used by any application.
> > > I think we can try to remove RTE_MACHINE from meson builds in DPDK
> > > 19.11, or use RTE_MACHINE as micro-arch (my preference).
> > 'MACHINE' means different things to different people, which is the root
> cause of this discussion.
> > 'MICRO-ARCH' has a very clear meaning. Do you see any problem going
> with MICRO-ARCH instead?
> 
> Some applications may use RTE_MACHINE for this purpose.
> It is part of the API since the befinning of DPDK.
> I don't see a real motivation to break this API now.
The suggestions are not clear to me. The original suggestion was to introduce RTE_MICRO_ARCH and contain all the micro-architecture related compiler flags in that.
Now, the suggestion is to use RTE_MACHINE to contain micro-architecture related compiler flags. Will it contain NUMA, number of cores as well (as suggested earlier)? If yes, I do not see it changing anything.

I am not a meson expert. However, I looked at various meson.build files. I have few questions/concerns.
1) Are these suggestions are for all the platforms? IMO, these need to be the same across all the architectures.
2) I am looking at config/meson.build. Here RTE_MACHINE is defined to indicate Architecture for Arm (armv7-a, aarchxx) and micro-architecture for x86 (corei7?). Is the understanding correct? IMO, this should this have a common meaning across all the platforms?
3) If the changes are for all the platforms, is the risk high for 19.11 release?
4) The N1 config patch as such conforms to the current conventions. What is being asked here is an enhancement, is the understanding correct?

> 

Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration

[Gavin Hu (Arm Technology China)]

Hi Honnappa,

> -----Original Message-----
> From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Sent: Tuesday, October 29, 2019 1:47 PM
> To: thomas@monjalon.net
> Cc: Jerin Jacob <jerinjacobk@gmail.com>; Ola Liljedahl
> <Ola.Liljedahl@arm.com>; Gavin Hu (Arm Technology China)
> <Gavin.Hu@arm.com>; dev@dpdk.org; pbhagavatula@marvell.com; nd
> <nd@arm.com>; jerinj@marvell.com; hemant.agrawal@nxp.com;
> bruce.richardson@intel.com; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; nd <nd@arm.com>
> Subject: RE: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP
> configuration
> 
> <snip>
> 
> >
> > 28/10/2019 04:24, Honnappa Nagarahalli:
> > > > 23/10/2019 07:03, Jerin Jacob:
> > > > > On Wed, Oct 23, 2019 at 2:37 AM Honnappa Nagarahalli
> > > > > <Honnappa.Nagarahalli@arm.com> wrote:
> > > > > > > > > On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote:
> > > > > > > > > > Arm N1 SDP is an infrastructure segment development
> > > > > > > > > > platform based on armv8.2-a Neoverse N1 CPU. For more
> > > > > > > > > > information, refer
> > > > to:
> > > > > > > > > > https://community.arm.com/developer/tools-software/oss-
> p
> > > > > > > > > > latf
> > > > > > > > > > orms/w
> > > > > > > > > > /
> > > > > > > > > > docs/440/neoverse-n1-sdp
> > > > > > > > > >
> > > > > > > > > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > > > > > > > > Reviewed-by: Honnappa Nagarahalli
> > > > > > > > > > <honnappa.nagarahalli@arm.com>
> > > > > > > > > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > > > > > > > > > ---
> > > > > > > > > > +CONFIG_RTE_MACHINE="neoversen1"
> > > > > > > > > This should probably be "n1sdp" as this is the name of the
> > > > > > > > > platform that matches the below configuration.
> > > > > > > > A clear definition of RTE_MACHINE is required. Jerin?
> > > > > > >
> > > > > > > I think, In the existing scheme of things, RTE_MACHINE
> > > > > > > defines, where to take the MACHINE_CFLAGS
> > > > > > > mk/machine/xxxx/rte.vars.mk
> > > > > > Ok, thank you
> > > > > >
> > > > > > >
> > > > > > > Considering the fact that there will be a lot of reusable
> > > > > > > IPs(for
> > > > > > > CPU) from ARM for  armv8, I think, it would make sense to
> > > > > > > introduce  RTE_MICRO_ARCH to avoid a lot of code duplications
> > > > > > > and
> > > > confusion.
> > > > > > >
> > > > > > > RTE_ARCH                             example: "x86" or "arm64"
> I see that there are already RTE_ARCH_X86, RTE_ARCH_ARM,
> RTE_ARCH_ARM64, RTE_ARCH_PPC_64 etc. I believe they should be
> sufficient.
> 
> > > > > > > RTE_MICRO_ARCH               example: "a72" or "thunderx3" -
> defines
> > > > > > > mcpu and armv8 verion arch etc
> Are you suggesting this just for Arm platforms?
> My understanding is your intention was to clean up the
> config/arm/meson.build file.
> 
> > > > > > > RTE_MACHINE                       example: "bluefield" or "thunderx3"
> > > > > > > - defines, number of cores, NUMA or not? etc
> > > > > > Looking at mk/machine/ directory, looks like RTE_MACHINE seems
> > > > > > to be
> > > > defining micro-architecture for Intel. For ex: hsw, nhm, wsm. I see
> > > > the same for Arm as well.
> > > > > > Are you suggesting that we use RTE_MICRO_ARCH to pick
> mk/micro-
> > > > arch/xxxx/rte.vars.mk? and RTE_MACHINE would pick
> > > > mk/machine/xxxx/rte.vars.mk, but contain NUMA, #of cores etc?
> > > > >
> > > > > Yes for Make build. I think, it is deprecated soon, so we need a
> > > > > similar solution for meson.
> > > >
> > > > Yes I would prefer we clean the mess in Meson, instead of talking
> > > > about the makefile system.
> > > > And honestly, N1 is not needed in the legacy makefile system.
> > > Unfortunately, most of the guys I talk to are still on makefile.
> >
> > You need to help them to switch.
> > Adding new targets in meson-only can be a good motivation :)
> >
> > > When is makefile system getting removed?
> >
> > It must be clearly decided and announced.
> > The previous techboard discussions were about making makefile hardly
> > usable during 2020, i.e. very soon.
> >
> > > > So focusing on config/arm/meson.build, I think RTE_MACHINE is
> > > > defined only for API compatibility with makefile.
> > > > However, I doubt this value is used by any application.
> > > > I think we can try to remove RTE_MACHINE from meson builds in
> DPDK
> > > > 19.11, or use RTE_MACHINE as micro-arch (my preference).
> > > 'MACHINE' means different things to different people, which is the root
> > cause of this discussion.
> > > 'MICRO-ARCH' has a very clear meaning. Do you see any problem going
> > with MICRO-ARCH instead?
> >
> > Some applications may use RTE_MACHINE for this purpose.
> > It is part of the API since the befinning of DPDK.
> > I don't see a real motivation to break this API now.
> The suggestions are not clear to me. The original suggestion was to
> introduce RTE_MICRO_ARCH and contain all the micro-architecture related
> compiler flags in that.
> Now, the suggestion is to use RTE_MACHINE to contain micro-architecture
> related compiler flags. Will it contain NUMA, number of cores as well (as
> suggested earlier)? If yes, I do not see it changing anything.
> 
> I am not a meson expert. However, I looked at various meson.build files. I
> have few questions/concerns.
> 1) Are these suggestions are for all the platforms? IMO, these need to be the
> same across all the architectures.
> 2) I am looking at config/meson.build. Here RTE_MACHINE is defined to
> indicate Architecture for Arm (armv7-a, aarchxx) and micro-architecture for
> x86 (corei7?). Is the understanding correct? IMO, this should this have a
> common meaning across all the platforms?
> 3) If the changes are for all the platforms, is the risk high for 19.11 release?
> 4) The N1 config patch as such conforms to the current conventions. What is
> being asked here is an enhancement, is the understanding correct?
> 
We consider it is an enhancement to introduce the RTE_MICRO_ARCH and I understand it is a high risk and we did not agree here yet.
I will submit v3 to change the configuration name from neoverse-n1 to n1sdp, to address Honnappa's comment.
/Gavin

[dpdk-dev] [PATCH v3 0/3] add arm N1SDP and A76 configurations

[Gavin Hu]

Nerverse N1 is a new SoC based on armv8.2-a and with other advanced features.
N1 SDP is the infrastructure segment development platform with N1 SoC inside.
Here is more information about it:
https://community.arm.com/developer/tools-software/oss-platforms/w/docs/440/neoverse-n1-sdp

V3
-change the configuration name from "neoversen1" to "n1sdp" to be platform specific other than microarchitecture specific
-add the missing config/arm/arm64_n1sdp_linux-gcc file for meson build
V2:
-add the cover letter and the patch for cortex-a76 configuration

Gavin Hu (3):
  test/rcu: fix the compiling error for armv8.2
  config: add arm neoverse N1 SDP configuration
  config: add cortex-a76 configuration

 app/test/test_rcu_qsbr.c                  |  2 +-
 config/arm/arm64_n1sdp_linux_gcc          | 16 +++++++++++++++
 config/arm/meson.build                    | 10 ++++++++-
 config/defconfig_arm64-n1sdp-linux-gcc    |  1 +
 config/defconfig_arm64-n1sdp-linuxapp-gcc | 14 +++++++++++++
 mk/machine/n1sdp/rte.vars.mk              | 34 +++++++++++++++++++++++++++++++
 6 files changed, 75 insertions(+), 2 deletions(-)
 create mode 100644 config/arm/arm64_n1sdp_linux_gcc
 create mode 120000 config/defconfig_arm64-n1sdp-linux-gcc
 create mode 100644 config/defconfig_arm64-n1sdp-linuxapp-gcc
 create mode 100644 mk/machine/n1sdp/rte.vars.mk

-- 
2.7.4

[dpdk-dev] [PATCH v3 1/3] test/rcu: fix the compiling error for armv8.2

[Gavin Hu]

With "-march=armv8.2-a" specified, a compiling error generated:
app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
expressions of different signedness: ‘unsigned int’ and ‘int’
[-Werror=sign-compare]

Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
Cc: stable@dpdk.org

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
---
 app/test/test_rcu_qsbr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c
index 85d80e0..19229ac 100644
--- a/app/test/test_rcu_qsbr.c
+++ b/app/test/test_rcu_qsbr.c
@@ -230,7 +230,7 @@ test_rcu_qsbr_thread_unregister(void)
 		/* Update quiescent state counter */
 		for (i = 0; i < num_threads[j]; i++) {
 			/* Skip one update */
-			if (i == (RTE_MAX_LCORE - 10))
+			if (i == (unsigned int)(RTE_MAX_LCORE - 10))
 				continue;
 			rte_rcu_qsbr_quiescent(t[0],
 				(j == 2) ? (RTE_MAX_LCORE - 1) : i);
-- 
2.7.4

[dpdk-dev] [PATCH v3 2/3] config: add arm neoverse N1 SDP configuration

[Gavin Hu]

Arm N1 SDP is an infrastructure segment development platform
based on armv8.2-a Neoverse N1 CPU. For more information, refer to:
https://community.arm.com/developer/tools-software/oss-platforms/w/
docs/440/neoverse-n1-sdp

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
---
V3
-change the configuration name from "neoversen1" to "n1sdp" to be platform
specific other than microarchitecture specific
-add the missing config/arm/arm64_n1sdp_linux-gcc file for meson build
---
 config/arm/arm64_n1sdp_linux_gcc          | 16 +++++++++++++++
 config/arm/meson.build                    |  9 +++++++-
 config/defconfig_arm64-n1sdp-linux-gcc    |  1 +
 config/defconfig_arm64-n1sdp-linuxapp-gcc | 14 +++++++++++++
 mk/machine/n1sdp/rte.vars.mk              | 34 +++++++++++++++++++++++++++++++
 5 files changed, 73 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_n1sdp_linux_gcc
 create mode 120000 config/defconfig_arm64-n1sdp-linux-gcc
 create mode 100644 config/defconfig_arm64-n1sdp-linuxapp-gcc
 create mode 100644 mk/machine/n1sdp/rte.vars.mk

diff --git a/config/arm/arm64_n1sdp_linux_gcc b/config/arm/arm64_n1sdp_linux_gcc
new file mode 100644
index 0000000..83dad3d
--- /dev/null
+++ b/config/arm/arm64_n1sdp_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x41'
+implementor_pn = '0xd0c'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 46dff3a..b56e442 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -57,6 +57,12 @@ flags_armada = [
 	['RTE_MAX_LCORE', 16]]
 
 flags_default_extra = []
+flags_n1sdp_extra = [
+	['RTE_MACHINE', '"n1sdp"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 4],
+	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
+	['RTE_LIBRTE_VHOST_NUMA', false]]
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
@@ -83,7 +89,8 @@ machine_args_generic = [
 	['0xd07', ['-mcpu=cortex-a57']],
 	['0xd08', ['-mcpu=cortex-a72']],
 	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']]]
+	['0xd0a', ['-mcpu=cortex-a75']],
+	['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'], flags_n1sdp_extra]]
 
 machine_args_cavium = [
 	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
diff --git a/config/defconfig_arm64-n1sdp-linux-gcc b/config/defconfig_arm64-n1sdp-linux-gcc
new file mode 120000
index 0000000..103bbea
--- /dev/null
+++ b/config/defconfig_arm64-n1sdp-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-n1sdp-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-n1sdp-linuxapp-gcc b/config/defconfig_arm64-n1sdp-linuxapp-gcc
new file mode 100644
index 0000000..f913809
--- /dev/null
+++ b/config/defconfig_arm64-n1sdp-linuxapp-gcc
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019 Arm Ltd.
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="n1sdp"
+CONFIG_RTE_MAX_LCORE=4
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_CACHE_LINE_SIZE=64
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
diff --git a/mk/machine/n1sdp/rte.vars.mk b/mk/machine/n1sdp/rte.vars.mk
new file mode 100644
index 0000000..6d69de0
--- /dev/null
+++ b/mk/machine/n1sdp/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019 Arm Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.2-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=neoverse-n1)
-- 
2.7.4

[dpdk-dev] [PATCH v3 3/3] config: add cortex-a76 configuration

[Gavin Hu]

To make the list complete and consistent, add cortex-a76 configuration.

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
---
 config/arm/meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index b56e442..b23dac1 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -90,6 +90,7 @@ machine_args_generic = [
 	['0xd08', ['-mcpu=cortex-a72']],
 	['0xd09', ['-mcpu=cortex-a73']],
 	['0xd0a', ['-mcpu=cortex-a75']],
+	['0xd0b', ['-mcpu=cortex-a76']],
 	['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'], flags_n1sdp_extra]]
 
 machine_args_cavium = [
-- 
2.7.4

Re: [dpdk-dev] [PATCH v3 2/3] config: add arm neoverse N1 SDP configuration

[Jerin Jacob]

On Mon, Nov 11, 2019 at 11:12 AM Gavin Hu <gavin.hu@arm.com> wrote:
>
> Arm N1 SDP is an infrastructure segment development platform
> based on armv8.2-a Neoverse N1 CPU. For more information, refer to:
> https://community.arm.com/developer/tools-software/oss-platforms/w/
> docs/440/neoverse-n1-sdp
>
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Reviewed-by: Steve Capper <steve.capper@arm.com>
> ---
> V3
> -change the configuration name from "neoversen1" to "n1sdp" to be platform
> specific other than microarchitecture specific
> -add the missing config/arm/arm64_n1sdp_linux-gcc file for meson build
> ---

> +[properties]
> +implementor_id = '0x41'
> +implementor_pn = '0xd0c'
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 46dff3a..b56e442 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -57,6 +57,12 @@ flags_armada = [
>         ['RTE_MAX_LCORE', 16]]
>
>  flags_default_extra = []
> +flags_n1sdp_extra = [
> +       ['RTE_MACHINE', '"n1sdp"'],
> +       ['RTE_MAX_NUMA_NODES', 1],
> +       ['RTE_MAX_LCORE', 4],
> +       ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> +       ['RTE_LIBRTE_VHOST_NUMA', false]]

Shouldn't we add ['RTE_CACHE_LINE_SIZE', 64], here?

>  flags_thunderx_extra = [

Re: [dpdk-dev] [PATCH v3 3/3] config: add cortex-a76 configuration

[Jerin Jacob]

On Mon, Nov 11, 2019 at 11:12 AM Gavin Hu <gavin.hu@arm.com> wrote:
>
> To make the list complete and consistent, add cortex-a76 configuration.
>
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>

Acked-by: Jerin Jacob <jerinj@marvell.com>


> ---
>  config/arm/meson.build | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index b56e442..b23dac1 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -90,6 +90,7 @@ machine_args_generic = [
>         ['0xd08', ['-mcpu=cortex-a72']],
>         ['0xd09', ['-mcpu=cortex-a73']],
>         ['0xd0a', ['-mcpu=cortex-a75']],
> +       ['0xd0b', ['-mcpu=cortex-a76']],
>         ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'], flags_n1sdp_extra]]
>
>  machine_args_cavium = [
> --
> 2.7.4
>

Re: [dpdk-dev] [PATCH v3 2/3] config: add arm neoverse N1 SDP configuration

[Gavin Hu (Arm Technology China)]

Hi Jerin,

> -----Original Message-----
> From: Jerin Jacob <jerinjacobk@gmail.com>
> Sent: Tuesday, November 12, 2019 12:24 PM
> To: Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>
> Cc: dpdk-dev <dev@dpdk.org>; nd <nd@arm.com>; thomas@monjalon.net;
> Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Subject: Re: [dpdk-dev] [PATCH v3 2/3] config: add arm neoverse N1 SDP
> configuration
> 
> On Mon, Nov 11, 2019 at 11:12 AM Gavin Hu <gavin.hu@arm.com> wrote:
> >
> > Arm N1 SDP is an infrastructure segment development platform
> > based on armv8.2-a Neoverse N1 CPU. For more information, refer to:
> > https://community.arm.com/developer/tools-software/oss-platforms/w/
> > docs/440/neoverse-n1-sdp
> >
> > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > ---
> > V3
> > -change the configuration name from "neoversen1" to "n1sdp" to be
> platform
> > specific other than microarchitecture specific
> > -add the missing config/arm/arm64_n1sdp_linux-gcc file for meson build
> > ---
> 
> > +[properties]
> > +implementor_id = '0x41'
> > +implementor_pn = '0xd0c'
> > diff --git a/config/arm/meson.build b/config/arm/meson.build
> > index 46dff3a..b56e442 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -57,6 +57,12 @@ flags_armada = [
> >         ['RTE_MAX_LCORE', 16]]
> >
> >  flags_default_extra = []
> > +flags_n1sdp_extra = [
> > +       ['RTE_MACHINE', '"n1sdp"'],
> > +       ['RTE_MAX_NUMA_NODES', 1],
> > +       ['RTE_MAX_LCORE', 4],
> > +       ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > +       ['RTE_LIBRTE_VHOST_NUMA', false]]
> 
> Shouldn't we add ['RTE_CACHE_LINE_SIZE', 64], here?
Arm defines it in the upper implemter_id level 
flags_arm = [
	['RTE_MACHINE', '"armv8a"'],
	['RTE_MAX_LCORE', 16],
	['RTE_USE_C11_MEM_MODEL', true],
	['RTE_CACHE_LINE_SIZE', 64]]
http://code.dpdk.org/dpdk/latest/source/config/arm/meson.build#L40

> 
> >  flags_thunderx_extra = [

Re: [dpdk-dev] [PATCH v3 2/3] config: add arm neoverse N1 SDP configuration

[Jerin Jacob]

On Mon, Nov 11, 2019 at 11:12 AM Gavin Hu <gavin.hu@arm.com> wrote:
>
> Arm N1 SDP is an infrastructure segment development platform
> based on armv8.2-a Neoverse N1 CPU. For more information, refer to:
> https://community.arm.com/developer/tools-software/oss-platforms/w/
> docs/440/neoverse-n1-sdp
>
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Reviewed-by: Steve Capper <steve.capper@arm.com>
> ---

Acked-by: Jerin Jacob <jerinj@marvell.com>

Re: [dpdk-dev] [dpdk-stable] [PATCH v3 1/3] test/rcu: fix the compiling error for armv8.2

[Thomas Monjalon]

11/11/2019 06:41, Gavin Hu:
> With "-march=armv8.2-a" specified, a compiling error generated:
> app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
> expressions of different signedness: ‘unsigned int’ and ‘int’
> [-Werror=sign-compare]
> 
> Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Reviewed-by: Steve Capper <steve.capper@arm.com>
> ---
> --- a/app/test/test_rcu_qsbr.c
> +++ b/app/test/test_rcu_qsbr.c
>  			/* Skip one update */
> -			if (i == (RTE_MAX_LCORE - 10))
> +			if (i == (unsigned int)(RTE_MAX_LCORE - 10))

For N1 SDP, RTE_MAX_LCORE = 4.
So this test weird.
Why not using rand() to find a number between 0 and max ?

You are hiding a real failure with a forced type casting.

Please reviewers, explain why you think it is the right thing to do?

Re: [dpdk-dev] [PATCH v3 0/3] add arm N1SDP and A76 configurations

[Thomas Monjalon]

11/11/2019 06:41, Gavin Hu:
> Gavin Hu (3):
>   test/rcu: fix the compiling error for armv8.2
>   config: add arm neoverse N1 SDP configuration
>   config: add cortex-a76 configuration

Applied, without first patch.
Please re-submit a fix for RCU test.

Re: [dpdk-dev] [dpdk-stable] [PATCH v3 1/3] test/rcu: fix the compiling error for armv8.2

[Gavin Hu (Arm Technology China)]

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Thursday, November 21, 2019 6:19 AM
> To: Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>; Honnappa
> Nagarahalli <Honnappa.Nagarahalli@arm.com>; Steve Capper
> <Steve.Capper@arm.com>
> Cc: stable@dpdk.org; dev@dpdk.org; nd <nd@arm.com>;
> david.marchand@redhat.com
> Subject: Re: [dpdk-stable] [PATCH v3 1/3] test/rcu: fix the compiling error for
> armv8.2
> 
> 11/11/2019 06:41, Gavin Hu:
> > With "-march=armv8.2-a" specified, a compiling error generated:
> > app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
> > expressions of different signedness: ‘unsigned int’ and ‘int’
> > [-Werror=sign-compare]
> >
> > Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > ---
> > --- a/app/test/test_rcu_qsbr.c
> > +++ b/app/test/test_rcu_qsbr.c
> >  			/* Skip one update */
> > -			if (i == (RTE_MAX_LCORE - 10))
> > +			if (i == (unsigned int)(RTE_MAX_LCORE - 10))
> 
> For N1 SDP, RTE_MAX_LCORE = 4.
> So this test weird.
> Why not using rand() to find a number between 0 and max ?
> 
> You are hiding a real failure with a forced type casting.
> 
> Please reviewers, explain why you think it is the right thing to do?
> 
Thanks for pointing out this issue, will fix in next release.

[dpdk-dev] [PATCH v4] test/rcu: fix build for small number of cores

[Gavin Hu]

If the RTE_MAX_LCORE is less than 10, a compilation error is generated:
app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
expressions of different signedness: ‘unsigned int’ and ‘int’
[-Werror=sign-compare]

The cause is (RTE_MAX_LCORE - 10) results in a negative value.

To fix, use rte_rand() to find a number between 0 and RTE_MAX_LCORE.

Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
Cc: stable@dpdk.org

Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Dharmik Thakkar <dharmik.thakkar@arm.com>
---
v4:
- separate from the N1SDP configuration patch series
- fix the build for smaller number of cores(Thomas Monjalon)
---
 app/test/test_rcu_qsbr.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c
index 85d80e0..b60dc50 100644
--- a/app/test/test_rcu_qsbr.c
+++ b/app/test/test_rcu_qsbr.c
@@ -9,6 +9,7 @@
 #include <rte_hash_crc.h>
 #include <rte_malloc.h>
 #include <rte_cycles.h>
+#include <rte_random.h>
 #include <unistd.h>
 
 #include "test.h"
@@ -168,6 +169,7 @@ test_rcu_qsbr_thread_unregister(void)
 {
 	unsigned int num_threads[3] = {1, RTE_MAX_LCORE, 1};
 	unsigned int i, j;
+	unsigned int skip_thread_id;
 	uint64_t token;
 	int ret;
 
@@ -227,10 +229,11 @@ test_rcu_qsbr_thread_unregister(void)
 		token = rte_rcu_qsbr_start(t[0]);
 		TEST_RCU_QSBR_RETURN_IF_ERROR(
 			(token != (TEST_RCU_QSBR_CNT_INIT + 1)), "QSBR Start");
+		skip_thread_id = rte_rand() % RTE_MAX_LCORE;
 		/* Update quiescent state counter */
 		for (i = 0; i < num_threads[j]; i++) {
 			/* Skip one update */
-			if (i == (RTE_MAX_LCORE - 10))
+			if ((j == 1) && (i == skip_thread_id))
 				continue;
 			rte_rcu_qsbr_quiescent(t[0],
 				(j == 2) ? (RTE_MAX_LCORE - 1) : i);
@@ -242,7 +245,7 @@ test_rcu_qsbr_thread_unregister(void)
 			TEST_RCU_QSBR_RETURN_IF_ERROR((ret == 0),
 						"Non-blocking QSBR check");
 			/* Update the previously skipped thread */
-			rte_rcu_qsbr_quiescent(t[0], RTE_MAX_LCORE - 10);
+			rte_rcu_qsbr_quiescent(t[0], skip_thread_id);
 		}
 
 		/* Validate the updates */
-- 
2.7.4

Re: [dpdk-dev] [dpdk-stable] [PATCH v4] test/rcu: fix build for small number of cores

[Thomas Monjalon]

25/11/2019 04:36, Gavin Hu:
> If the RTE_MAX_LCORE is less than 10, a compilation error is generated:
> app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
> expressions of different signedness: ‘unsigned int’ and ‘int’
> [-Werror=sign-compare]
> 
> The cause is (RTE_MAX_LCORE - 10) results in a negative value.
> 
> To fix, use rte_rand() to find a number between 0 and RTE_MAX_LCORE.
> 
> Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Reviewed-by: Steve Capper <steve.capper@arm.com>
> Reviewed-by: Dharmik Thakkar <dharmik.thakkar@arm.com>

Applied, thanks

Re: [dpdk-dev] [PATCH v2 1/3] test/rcu: fix the compiling error for armv8.2

[Honnappa Nagarahalli]

> > <snip>
> >
> > > > Subject: [EXT] [PATCH v2 1/3] test/rcu: fix the compiling error
> > > > for
> > > > armv8.2
> > > >
> > > > With "-march=armv8.2-a" specified, a compiling error generated:
> > > > app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
> > > > expressions of different signedness: ‘unsigned int’ and ‘int’
> > > > [-Werror=sign-compare]
> > > >
> > > > Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
> > > > Cc: stable@dpdk.org
> > > >
> > > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> > >
> > >
> > > Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> > This should be fixed already due to commit 104dbec2081.
> > Gavin, can you please verify? If yes, we can skip this patch.
> No, just ran and the issue persisted with the above commit in place.
> I see the above commit was to fix a limited range of data type issue, this
> commit is to fix a signedness issue.
> ~/dpdk/app/test/test_rcu_qsbr.c: In function
> ‘test_rcu_qsbr_thread_unregister’:
> ~/dpdk/app/test/test_rcu_qsbr.c:233:10: error: comparison of integer
> expressions of different signedness: ‘unsigned int’ and ‘int’ [-Werror=sign-
> compare]
>     if (i == (RTE_MAX_LCORE - 10))
Ok, it is the right side of the 'if' (not the left side).

Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>

> >
> > >
> > >
> > > > ---
> > > >  app/test/test_rcu_qsbr.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c
> > > > index 1d273e3..b008c9d 100644
> > > > --- a/app/test/test_rcu_qsbr.c
> > > > +++ b/app/test/test_rcu_qsbr.c
> > > > @@ -231,7 +231,7 @@ test_rcu_qsbr_thread_unregister(void)
> > > >  /* Update quiescent state counter */  for (i = 0; i <
> > > > num_threads[j]; i++) {
> > > >  /* Skip one update */
> > > > -if (i == (RTE_MAX_LCORE - 10))
> > > > +if (i == (unsigned int)(RTE_MAX_LCORE - 10))
> > > >  continue;
> > > >  rte_rcu_qsbr_quiescent(t[0],
> > > >  (j == 2) ? (RTE_MAX_LCORE - 1) : i);
> > > > --
> > > > 2.7.4
> >
> 

Re: [dpdk-dev] [PATCH v2 1/3] test/rcu: fix the compiling error for armv8.2

[Gavin Hu (Arm Technology China)]

Hi Honnappa,

> -----Original Message-----
> From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Sent: Thursday, September 12, 2019 10:43 PM
> To: jerinj@marvell.com; Gavin Hu (Arm Technology China)
> <Gavin.Hu@arm.com>; dev@dpdk.org
> Cc: nd <nd@arm.com>; thomas@monjalon.net; hemant.agrawal@nxp.com;
> Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; stable@dpdk.org;
> Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>; nd <nd@arm.com>
> Subject: RE: [PATCH v2 1/3] test/rcu: fix the compiling error for armv8.2
> 
> <snip>
> 
> > > Subject: [EXT] [PATCH v2 1/3] test/rcu: fix the compiling error for
> > > armv8.2
> > >
> > > With "-march=armv8.2-a" specified, a compiling error generated:
> > > app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
> > > expressions of different signedness: ‘unsigned int’ and ‘int’
> > > [-Werror=sign-compare]
> > >
> > > Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
> > > Cc: stable@dpdk.org
> > >
> > > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > > Reviewed-by: Steve Capper <steve.capper@arm.com>
> >
> >
> > Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> This should be fixed already due to commit 104dbec2081.
> Gavin, can you please verify? If yes, we can skip this patch.
No, just ran and the issue persisted with the above commit in place. 
I see the above commit was to fix a limited range of data type issue, this commit is to fix a signedness issue.
~/dpdk/app/test/test_rcu_qsbr.c: In function ‘test_rcu_qsbr_thread_unregister’:
~/dpdk/app/test/test_rcu_qsbr.c:233:10: error: comparison of integer expressions of different signedness: ‘unsigned int’ and ‘int’ [-Werror=sign-compare]
    if (i == (RTE_MAX_LCORE - 10))
> 
> >
> >
> > > ---
> > >  app/test/test_rcu_qsbr.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c index
> > > 1d273e3..b008c9d 100644
> > > --- a/app/test/test_rcu_qsbr.c
> > > +++ b/app/test/test_rcu_qsbr.c
> > > @@ -231,7 +231,7 @@ test_rcu_qsbr_thread_unregister(void)
> > >  /* Update quiescent state counter */
> > >  for (i = 0; i < num_threads[j]; i++) {
> > >  /* Skip one update */
> > > -if (i == (RTE_MAX_LCORE - 10))
> > > +if (i == (unsigned int)(RTE_MAX_LCORE - 10))
> > >  continue;
> > >  rte_rcu_qsbr_quiescent(t[0],
> > >  (j == 2) ? (RTE_MAX_LCORE - 1) : i);
> > > --
> > > 2.7.4
> 

Re: [dpdk-dev] [PATCH v2 1/3] test/rcu: fix the compiling error for armv8.2

[Honnappa Nagarahalli]

<snip>

> > Subject: [EXT] [PATCH v2 1/3] test/rcu: fix the compiling error for
> > armv8.2
> >
> > With "-march=armv8.2-a" specified, a compiling error generated:
> > app/test/test_rcu_qsbr.c:234:10: error: comparison of integer
> > expressions of different signedness: ‘unsigned int’ and ‘int’
> > [-Werror=sign-compare]
> >
> > Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > Reviewed-by: Steve Capper <steve.capper@arm.com>
> 
> 
> Reviewed-by: Jerin Jacob <jerinj@marvell.com>
This should be fixed already due to commit 104dbec2081.
Gavin, can you please verify? If yes, we can skip this patch.

> 
> 
> > ---
> >  app/test/test_rcu_qsbr.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c index
> > 1d273e3..b008c9d 100644
> > --- a/app/test/test_rcu_qsbr.c
> > +++ b/app/test/test_rcu_qsbr.c
> > @@ -231,7 +231,7 @@ test_rcu_qsbr_thread_unregister(void)
> >  		/* Update quiescent state counter */
> >  		for (i = 0; i < num_threads[j]; i++) {
> >  			/* Skip one update */
> > -			if (i == (RTE_MAX_LCORE - 10))
> > +			if (i == (unsigned int)(RTE_MAX_LCORE - 10))
> >  				continue;
> >  			rte_rcu_qsbr_quiescent(t[0],
> >  				(j == 2) ? (RTE_MAX_LCORE - 1) : i);
> > --
> > 2.7.4

Re: [dpdk-dev] [PATCH v2 1/3] test/rcu: fix the compiling error for armv8.2

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Gavin Hu <gavin.hu@arm.com>
> Sent: Thursday, August 1, 2019 5:18 AM
> To: dev@dpdk.org
> Cc: nd@arm.com; thomas@monjalon.net; hemant.agrawal@nxp.com; Jerin
> Jacob Kollanukkaran <jerinj@marvell.com>; Pavan Nikhilesh Bhagavatula
> <pbhagavatula@marvell.com>; Honnappa.Nagarahalli@arm.com;
> stable@dpdk.org
> Subject: [EXT] [PATCH v2 1/3] test/rcu: fix the compiling error for armv8.2
> 
> With "-march=armv8.2-a" specified, a compiling error generated:
> app/test/test_rcu_qsbr.c:234:10: error: comparison of integer expressions of
> different signedness: ‘unsigned int’ and ‘int’
> [-Werror=sign-compare]
> 
> Fixes: b87089b0bb19 ("test/rcu: add API and functional tests")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Reviewed-by: Steve Capper <steve.capper@arm.com>


Reviewed-by: Jerin Jacob <jerinj@marvell.com>


> ---
>  app/test/test_rcu_qsbr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c index
> 1d273e3..b008c9d 100644
> --- a/app/test/test_rcu_qsbr.c
> +++ b/app/test/test_rcu_qsbr.c
> @@ -231,7 +231,7 @@ test_rcu_qsbr_thread_unregister(void)
>  		/* Update quiescent state counter */
>  		for (i = 0; i < num_threads[j]; i++) {
>  			/* Skip one update */
> -			if (i == (RTE_MAX_LCORE - 10))
> +			if (i == (unsigned int)(RTE_MAX_LCORE - 10))
>  				continue;
>  			rte_rcu_qsbr_quiescent(t[0],
>  				(j == 2) ? (RTE_MAX_LCORE - 1) : i);
> --
> 2.7.4