From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC50FA00E6 for ; Thu, 8 Aug 2019 10:47:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 94D6C5680; Thu, 8 Aug 2019 10:46:07 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 81F1B1B942 for ; Thu, 8 Aug 2019 10:46:05 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2019 01:46:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,360,1559545200"; d="scan'208";a="350108734" Received: from dpdk-rosen-02.sh.intel.com ([10.67.111.116]) by orsmga005.jf.intel.com with ESMTP; 08 Aug 2019 01:46:03 -0700 From: Rosen Xu To: dev@dpdk.org Cc: ferruh.yigit@intel.com, tianfei.zhang@intel.com, rosen.xu@intel.com, andy.pei@intel.com, david.lomartire@intel.com, qi.z.zhang@intel.com, xiaolong.ye@intel.com Date: Thu, 8 Aug 2019 16:46:14 +0800 Message-Id: <1565253974-183591-14-git-send-email-rosen.xu@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1565253974-183591-1-git-send-email-rosen.xu@intel.com> References: <1564556752-19257-2-git-send-email-rosen.xu@intel.com> <1565253974-183591-1-git-send-email-rosen.xu@intel.com> Subject: [dpdk-dev] [PATCH v3 13/13] net/ipn3ke: add FPGA network side port MTU configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add FPGA network side port MTU configuration in initialization. Signed-off-by: Rosen Xu --- drivers/net/ipn3ke/ipn3ke_ethdev.c | 8 ++++++ drivers/net/ipn3ke/ipn3ke_ethdev.h | 55 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c index 363a5f1..7e7fa25 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c @@ -292,6 +292,10 @@ /* Clear line RX statistics counters */ ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0); + + /* set mtu to max */ + ipn3ke_10G_mtu_setup(hw, i, 0); + ipn3ke_10G_mtu_setup(hw, i, 1); } } else if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { @@ -308,6 +312,10 @@ /* Clear line side RX statistics counters */ ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0); + + /* set mtu to max */ + ipn3ke_25G_mtu_setup(hw, i, 0); + ipn3ke_25G_mtu_setup(hw, i, 1); } } diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h index c7b336b..b04e5d3 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h @@ -654,6 +654,25 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \ IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT) +/* Additional Feature Register */ +#define ADD_PHY_CTRL 0x0 +#define PHY_RESET BIT(0) +/* registers for 25G/40G mac */ +#define MAC_CONFIG 0x310 +#define MAC_RESET_MASK GENMASK(2, 0) + +#define IPN3KE_MAX_MTU 0xffff + +#define IPN3KE_25G_PHY_PMA_SLOOP 0x313 +#define IPN3KE_25G_TX_FLOW_CTRL 0x640 +#define IPN3KE_25G_MAX_TX_SIZE_CONFIG 0x407 +#define IPN3KE_25G_MAX_RX_SIZE_CONFIG 0x506 + +#define IPN3KE_10G_TX_PAUSE_FRAME_QUANTA 0x42 +#define IPN3KE_10G_TX_PAUSE_FRAME_HOLDOFF 0x43 +#define IPN3KE_10G_TX_FRAME_MAXLENGTH 0x2c +#define IPN3KE_10G_RX_FRAME_MAXLENGTH 0xae + #define IPN3KE_REGISTER_WIDTH 32 /*Bits[2:0]: Configuration of TX statistics counters: @@ -1076,4 +1095,40 @@ static inline void ipn3ke_xmac_smac_ovd_dis(struct ipn3ke_hw *hw, eth_group_sel); } +static inline void ipn3ke_10G_mtu_setup +(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) +{ + uint32_t tmp = IPN3KE_MAC_FRAME_SIZE_MAX; + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_TX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_RX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); +} + +static inline void ipn3ke_25G_mtu_setup +(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) +{ + uint32_t tmp = IPN3KE_MAC_FRAME_SIZE_MAX; + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_TX_SIZE_CONFIG, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_RX_SIZE_CONFIG, + mac_num, + eth_group_sel); +} + #endif /* _IPN3KE_ETHDEV_H_ */ -- 1.8.3.1