From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D43DA0613 for ; Fri, 30 Aug 2019 08:32:08 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 13BDA1E86F; Fri, 30 Aug 2019 08:31:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 33B271E86F for ; Fri, 30 Aug 2019 08:31:58 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6V3oi028322; Thu, 29 Aug 2019 23:31:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=98OiPxMWAJqm5rpU4gICIFiyT1yWW6L6+9wy3ZDP9JM=; b=Tonw8xn3ywY4M0o9SAjTLP0Y5oQvm5DX1sHdB28fkxL5MuCdK/xPbU/Fca7GThV7Q/5N u/ce9sH9wKNGjiWQK7zkj5fUwruziia1253/5stQeVY1bsGH26Z+bo2M/Xf0jbHAd5U4 +cBJwNrAs+vX+XHdMyaKU7q8+GDIcibjzC4/ZCqwAf6u3vlDIlu/3qnd2evOx0A2PHuD FKRyU/F2TuSKXghya5xCfOcpwhN6ydk5RInUI+PqfEZym29Q1XA0auZ4sMvoAV+KFVxn 2CYjNx8Ud/X72bBkY+qeAylGOeA1OjIgmbIMpLbW7L4BVyr9dg+DDuBY8u9I6eDK0AN4 zw== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg1u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2019 23:31:57 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:31:55 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:31:55 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id 9D2A83F703F; Thu, 29 Aug 2019 23:31:52 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , Narayana Prasad , Ankur Dwivedi , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:12 +0530 Message-ID: <1567146501-8224-3-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 02/11] crypto/octeontx2: add device init sequence in probe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the device init sequence for OCTEON TX2 crypto device. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- drivers/crypto/octeontx2/Makefile | 10 +++++++ drivers/crypto/octeontx2/meson.build | 2 ++ drivers/crypto/octeontx2/otx2_cryptodev.c | 40 ++++++++++++++++++++++++++ drivers/crypto/octeontx2/otx2_cryptodev.h | 10 ++++++- drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 30 +++++++++++++++++++ drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 13 +++++++++ 6 files changed, 104 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile index 3273178..10d8c39 100644 --- a/drivers/crypto/octeontx2/Makefile +++ b/drivers/crypto/octeontx2/Makefile @@ -23,9 +23,19 @@ VPATH += $(RTE_SDK)/drivers/crypto/octeontx2 CFLAGS += -O3 CFLAGS += -I$(RTE_SDK)/drivers/common/cpt CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2 +CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2 + +ifneq ($(CONFIG_RTE_ARCH_64),y) +CFLAGS += -Wno-int-to-pointer-cast +CFLAGS += -Wno-pointer-to-int-cast +ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y) +CFLAGS += -diag-disable 2259 +endif +endif # PMD code SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c # export include files diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build index 2b55d2a..845d50d 100644 --- a/drivers/crypto/octeontx2/meson.build +++ b/drivers/crypto/octeontx2/meson.build @@ -11,6 +11,7 @@ deps += ['common_octeontx2'] name = 'octeontx2_crypto' sources = files('otx2_cryptodev.c', + 'otx2_cryptodev_mbox.c', 'otx2_cryptodev_ops.c') extra_flags = [] @@ -27,3 +28,4 @@ endforeach includes += include_directories('../../common/cpt') includes += include_directories('../../common/octeontx2') +includes += include_directories('../../mempool/octeontx2') diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c index cf3a010..814b9ed 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -18,7 +18,9 @@ #include "otx2_common.h" #include "otx2_cryptodev.h" +#include "otx2_cryptodev_mbox.h" #include "otx2_cryptodev_ops.h" +#include "otx2_dev.h" static int otx2_cryptodev_logtype; @@ -44,6 +46,9 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, }; char name[RTE_CRYPTODEV_NAME_MAX_LEN]; struct rte_cryptodev *dev; + struct otx2_dev *otx2_dev; + struct otx2_cpt_vf *vf; + uint16_t nb_queues; int ret; /* Initialize logtype used in common */ @@ -61,6 +66,37 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, dev->driver_id = otx2_cryptodev_driver_id; + /* Get private data space allocated */ + vf = dev->data->dev_private; + + otx2_dev = &vf->otx2_dev; + + /* Initialize the base otx2_dev object */ + ret = otx2_dev_init(pci_dev, otx2_dev); + if (ret) { + CPT_LOG_ERR("Could not initialize otx2_dev"); + goto pmd_destroy; + } + + /* Get number of queues available on the device */ + ret = otx2_cpt_available_queues_get(dev, &nb_queues); + if (ret) { + CPT_LOG_ERR("Could not determine the number of queues available"); + goto otx2_dev_fini; + } + + /* Don't exceed the limits set per VF */ + nb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF); + + if (nb_queues == 0) { + CPT_LOG_ERR("No free queues available on the device"); + goto otx2_dev_fini; + } + + vf->max_queues = nb_queues; + + CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues); + dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | @@ -70,6 +106,10 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, return 0; +otx2_dev_fini: + otx2_dev_fini(pci_dev, otx2_dev); +pmd_destroy: + rte_cryptodev_pmd_destroy(dev); exit: CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)", pci_dev->id.vendor_id, pci_dev->id.device_id); diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h index da0f653..531bd6d 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev.h @@ -7,14 +7,22 @@ #include "cpt_common.h" +#include "otx2_dev.h" + /* Marvell OCTEON TX2 Crypto PMD device name */ #define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2 +#define OTX2_CPT_MAX_LFS 64 +#define OTX2_CPT_MAX_QUEUES_PER_VF 64 + /** * Device private data */ struct otx2_cpt_vf { - /* To be populated */ + struct otx2_dev otx2_dev; + /**< Base class */ + uint16_t max_queues; + /**< Max queues supported */ }; /* diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c new file mode 100644 index 0000000..48d86ef --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ +#include + +#include "cpt_pmd_logs.h" + +#include "otx2_cryptodev.h" +#include "otx2_cryptodev_mbox.h" +#include "otx2_dev.h" +#include "otx2_mbox.h" + +int +otx2_cpt_available_queues_get(const struct rte_cryptodev *dev, + uint16_t *nb_queues) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + struct otx2_dev *otx2_dev = &vf->otx2_dev; + struct free_rsrcs_rsp *rsp; + int ret; + + otx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox); + + ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp); + if (ret) + return -EIO; + + *nb_queues = rsp->cpt; + return 0; +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h new file mode 100644 index 0000000..648c009 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_MBOX_H_ +#define _OTX2_CRYPTODEV_MBOX_H_ + +#include + +int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev, + uint16_t *nb_queues); + +#endif /* _OTX2_CRYPTODEV_MBOX_H_ */ -- 2.7.4