From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 87B78A0613 for ; Fri, 30 Aug 2019 08:32:39 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5F18F1E88E; Fri, 30 Aug 2019 08:32:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id D6E3C1E886 for ; Fri, 30 Aug 2019 08:32:20 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6UNd8027737; Thu, 29 Aug 2019 23:32:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=k1C0SmvVjMaqs0z5/3r1I0g3wVKR/tsLcqckgyJYvj4=; b=OTKVaGLs/PmvrOiKW/tUhf9mQHZZa8bQ8Gib7ZmbuhVOaBAP7bIcD+MPoRF02Z7K+NWf 3eFh9XeOGyZgJIznxh1FwBSImWbJEkTf+aS0BK9ZCykv7L2Vq4QV23g0oDUS4OSaorG6 68f1vN4Bo9m/AJXZ0JieNhlPwn1uUJp3E5swrqQ9XxZUabXDbmFHwl6V1960vOQBZNDs +7IV3jVDBjQaHZzuGYnAvsi+/y9Dhc+fmJmvRG1n5Y6PPNYjtGcCXmZQYMXyVg9us76T OyxHWyYUF95t8dQ0glFog6+I7Iu9ZFsPSsZTo9/OnreIMbVQ6jRq8ki7F6juNB+3qowk WA== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg34-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2019 23:32:20 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:32:18 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:32:18 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id 250BD3F703F; Thu, 29 Aug 2019 23:32:14 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Ankur Dwivedi , Jerin Jacob , Narayana Prasad , Anoob Joseph , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:15 +0530 Message-ID: <1567146501-8224-6-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 05/11] crypto/octeontx2: add hardware definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi This patch adds the hardware definitions for OCTEON TX2 crypto hardware. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 117 +++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h index 2af674d..441494e 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h @@ -11,15 +11,132 @@ /* Register offsets */ +/* LMT LF registers */ +#define OTX2_LMT_LF_LMTLINE(a) (0x0ull | (uint64_t)(a) << 3) + /* CPT LF registers */ +#define OTX2_CPT_LF_CTL 0x10ull +#define OTX2_CPT_LF_INPROG 0x40ull #define OTX2_CPT_LF_MISC_INT 0xb0ull #define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull #define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull +#define OTX2_CPT_LF_Q_BASE 0xf0ull +#define OTX2_CPT_LF_Q_SIZE 0x100ull +#define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3) + +#define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3) #define OTX2_CPT_LF_BAR2(vf, q_id) \ ((vf)->otx2_dev.bar2 + \ ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12))) +union otx2_cpt_lf_ctl { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_8_63 : 56; + uint64_t fc_hyst_bits : 4; + uint64_t reserved_3_3 : 1; + uint64_t fc_up_crossing : 1; + uint64_t fc_ena : 1; + uint64_t ena : 1; +#else /* Word 0 - Little Endian */ + uint64_t ena : 1; + uint64_t fc_ena : 1; + uint64_t fc_up_crossing : 1; + uint64_t reserved_3_3 : 1; + uint64_t fc_hyst_bits : 4; + uint64_t reserved_8_63 : 56; +#endif + } s; +}; + +union otx2_cpt_lf_inprog { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_48_63 : 16; + uint64_t gwb_cnt : 8; + uint64_t grb_cnt : 8; + uint64_t grb_partial : 1; + uint64_t reserved_18_30 : 13; + uint64_t grp_drp : 1; + uint64_t eena : 1; + uint64_t reserved_9_15 : 7; + uint64_t inflight : 9; +#else /* Word 0 - Little Endian */ + uint64_t inflight : 9; + uint64_t reserved_9_15 : 7; + uint64_t eena : 1; + uint64_t grp_drp : 1; + uint64_t reserved_18_30 : 13; + uint64_t grb_partial : 1; + uint64_t grb_cnt : 8; + uint64_t gwb_cnt : 8; + uint64_t reserved_48_63 : 16; +#endif + } s; +}; + +union otx2_cpt_lf_q_base { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_53_63 : 11; + uint64_t addr : 46; + uint64_t reserved_2_6 : 5; + uint64_t stopped : 1; + uint64_t fault : 1; +#else /* Word 0 - Little Endian */ + uint64_t fault : 1; + uint64_t stopped : 1; + uint64_t reserved_2_6 : 5; + uint64_t addr : 46; + uint64_t reserved_53_63 : 11; +#endif + } s; +}; + +union otx2_cpt_lf_q_size { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_15_63 : 49; + uint64_t size_div40 : 15; +#else /* Word 0 - Little Endian */ + uint64_t size_div40 : 15; + uint64_t reserved_15_63 : 49; +#endif + } s; +}; + +union otx2_cpt_af_lf_ctl { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_56_63 : 8; + uint64_t grp : 8; + uint64_t reserved_17_47 : 31; + uint64_t nixtx_en : 1; + uint64_t reserved_11_15 : 5; + uint64_t cont_err : 1; + uint64_t pf_func_inst : 1; + uint64_t reserved_1_8 : 8; + uint64_t pri : 1; +#else /* Word 0 - Little Endian */ + uint64_t pri : 1; + uint64_t reserved_1_8 : 8; + uint64_t pf_func_inst : 1; + uint64_t cont_err : 1; + uint64_t reserved_11_15 : 5; + uint64_t nixtx_en : 1; + uint64_t reserved_17_47 : 31; + uint64_t grp : 8; + uint64_t reserved_56_63 : 8; +#endif + } s; +}; + void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev); int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev); -- 2.7.4