From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1623AA0613 for ; Fri, 30 Aug 2019 08:33:00 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 792741E8C2; Fri, 30 Aug 2019 08:32:31 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id BF44A1E8BD for ; Fri, 30 Aug 2019 08:32:29 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6TcTl024096; Thu, 29 Aug 2019 23:32:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=CCZI/aEVlnjo6X+ocIS7QmseGiczwNsOfFgjUmSqBIk=; b=tFN3PJvxn1vHFdzpKCtmHrG8xQSexJbIz+RQoSdSwQuw8aYCOOUj/q7MjmK/usMc6KHd 83WqmsPCRKm4OyM+F1AAakueaycFQ7nzElV2bST1t8Q/hdBBv9DBDbfda4e2rN+hSCUM q4W73KCidDrMXBH1o61IMd4CRZORSurgULdicmWzCC5rxI+JQdCtGnC0tGa3x4wwtbCk 98v43LZqi+cnpHSknKur3rbpF6rLYEWSG5nBfualGffLHHRJe507Zef2mbA2Yd5bnMag Qiv+8tmjqvC7eYP0NsK7eMsqrIv/S9O+TeL5blXFDBPzBfk5oY4AuhJs58H2tuBuv6Mn lw== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 2upmepj414-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2019 23:32:28 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:32:27 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:32:27 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id BF4C13F703F; Thu, 29 Aug 2019 23:32:24 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Ankur Dwivedi , Jerin Jacob , Narayana Prasad , Anoob Joseph , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:17 +0530 Message-ID: <1567146501-8224-8-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 07/11] crypto/octeontx2: add session related functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi This patch adds the symmetric session related callbacks. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- drivers/common/cpt/cpt_mcode_defines.h | 2 + drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 117 +++++++++++++++++++++++++- drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 5 ++ 3 files changed, 121 insertions(+), 3 deletions(-) diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h index b7c3feb..c197c7b 100644 --- a/drivers/common/cpt/cpt_mcode_defines.h +++ b/drivers/common/cpt/cpt_mcode_defines.h @@ -213,6 +213,8 @@ struct cpt_sess_misc { uint16_t is_null:1; /** Flag for GMAC */ uint16_t is_gmac:1; + /** Engine group */ + uint16_t egrp:3; /** AAD length */ uint16_t aad_length; /** MAC len in bytes */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index b2d459e..fcfcf1a 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -10,6 +10,7 @@ #include "cpt_hw_types.h" #include "cpt_pmd_logs.h" #include "cpt_pmd_ops_helper.h" +#include "cpt_ucode.h" #include "otx2_cryptodev.h" #include "otx2_cryptodev_capabilities.h" @@ -244,6 +245,90 @@ otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp) return 0; } +static int +sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *pool) +{ + struct cpt_sess_misc *misc; + void *priv; + int ret; + + if (unlikely(cpt_is_algo_supported(xform))) { + CPT_LOG_ERR("Crypto xform not supported"); + return -ENOTSUP; + } + + if (unlikely(rte_mempool_get(pool, &priv))) { + CPT_LOG_ERR("Could not allocate session private data"); + return -ENOMEM; + } + + misc = priv; + + for ( ; xform != NULL; xform = xform->next) { + switch (xform->type) { + case RTE_CRYPTO_SYM_XFORM_AEAD: + ret = fill_sess_aead(xform, misc); + break; + case RTE_CRYPTO_SYM_XFORM_CIPHER: + ret = fill_sess_cipher(xform, misc); + break; + case RTE_CRYPTO_SYM_XFORM_AUTH: + if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) + ret = fill_sess_gmac(xform, misc); + else + ret = fill_sess_auth(xform, misc); + break; + default: + ret = -1; + } + + if (ret) + goto priv_put; + } + + set_sym_session_private_data(sess, driver_id, misc); + + misc->ctx_dma_addr = rte_mempool_virt2iova(misc) + + sizeof(struct cpt_sess_misc); + + /* + * IE engines support IPsec operations + * SE engines support IPsec operations and Air-Crypto operations + */ + if (misc->zsk_flag) + misc->egrp = OTX2_CPT_EGRP_SE; + else + misc->egrp = OTX2_CPT_EGRP_SE_IE; + + return 0; + +priv_put: + rte_mempool_put(pool, priv); + + CPT_LOG_ERR("Crypto xform not supported"); + return -ENOTSUP; +} + +static void +sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess) +{ + void *priv = get_sym_session_private_data(sess, driver_id); + struct rte_mempool *pool; + + if (priv == NULL) + return; + + memset(priv, 0, cpt_get_session_size()); + + pool = rte_mempool_from_obj(priv); + + set_sym_session_private_data(sess, driver_id, NULL); + + rte_mempool_put(pool, priv); +} + /* PMD ops */ static int @@ -420,6 +505,32 @@ otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id) return 0; } +static unsigned int +otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused) +{ + return cpt_get_session_size(); +} + +static int +otx2_cpt_sym_session_configure(struct rte_cryptodev *dev, + struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *pool) +{ + CPT_PMD_INIT_FUNC_TRACE(); + + return sym_session_configure(dev->driver_id, xform, sess, pool); +} + +static void +otx2_cpt_sym_session_clear(struct rte_cryptodev *dev, + struct rte_cryptodev_sym_session *sess) +{ + CPT_PMD_INIT_FUNC_TRACE(); + + return sym_session_clear(dev->driver_id, sess); +} + struct rte_cryptodev_ops otx2_cpt_ops = { /* Device control ops */ .dev_configure = otx2_cpt_dev_config, @@ -435,7 +546,7 @@ struct rte_cryptodev_ops otx2_cpt_ops = { .queue_pair_count = NULL, /* Symmetric crypto ops */ - .sym_session_get_size = NULL, - .sym_session_configure = NULL, - .sym_session_clear = NULL, + .sym_session_get_size = otx2_cpt_sym_session_get_size, + .sym_session_configure = otx2_cpt_sym_session_configure, + .sym_session_clear = otx2_cpt_sym_session_clear, }; diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h index 9bd24e7..ba93a66 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h @@ -10,6 +10,11 @@ #define OTX2_CPT_MIN_HEADROOM_REQ 24 #define OTX2_CPT_MIN_TAILROOM_REQ 8 +enum otx2_cpt_egrp { + OTX2_CPT_EGRP_SE = 0, + OTX2_CPT_EGRP_SE_IE = 1, +}; + struct rte_cryptodev_ops otx2_cpt_ops; #endif /* _OTX2_CRYPTODEV_OPS_H_ */ -- 2.7.4