From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6DB27A00E6 for ; Mon, 2 Sep 2019 05:06:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E40CC1C1F5; Mon, 2 Sep 2019 05:06:22 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id BEC871C1CD for ; Mon, 2 Sep 2019 05:06:20 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Sep 2019 20:06:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,457,1559545200"; d="scan'208";a="381736850" Received: from dpdk-dipei.sh.intel.com ([10.67.110.224]) by fmsmga005.fm.intel.com with ESMTP; 01 Sep 2019 20:06:18 -0700 From: Andy Pei To: dev@dpdk.org Cc: andy.pei@intel.com, qi.z.zhang@intel.com, ferruh.yigit@intel.com, rosen.xu@intel.com, xiaolong.ye@intel.com Date: Mon, 2 Sep 2019 10:54:07 +0800 Message-Id: <1567392847-445709-1-git-send-email-andy.pei@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1565280090-344032-1-git-send-email-andy.pei@intel.com> References: <1565280090-344032-1-git-send-email-andy.pei@intel.com> Subject: [dpdk-dev] [PATCH v3] net/ipn3ke: setup MTU when HW init X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" set up mtu to the minimun in tx mtu, rx mtu and IPN3KE_MAC_FRAME_SIZE_MAX. Signed-off-by: Andy Pei --- Cc: qi.z.zhang@intel.com Cc: ferruh.yigit@intel.com Cc: rosen.xu@intel.com Cc: xiaolong.ye@intel.com v2: modify low bound and upper bound. v3: modify according to community comments. drivers/net/ipn3ke/ipn3ke_ethdev.c | 109 +++++++++++++++++++++++++++++++++++++ drivers/net/ipn3ke/ipn3ke_ethdev.h | 15 +++++ 2 files changed, 124 insertions(+) diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c index c226d63..711d48e 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c @@ -209,6 +209,112 @@ return 0; } +static uint32_t +ipn3ke_mtu_cal(uint32_t tx, uint32_t rx) +{ + uint32_t tmp; + tmp = RTE_MIN(tx, rx); + if (tmp < RTE_ETHER_MIN_MTU) + tmp = RTE_ETHER_MIN_MTU; + if (tmp > IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD) + tmp = IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD; + return tmp; +} + +static void +ipn3ke_10G_mtu_setup +(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) +{ + uint32_t tx; + uint32_t rx; + uint32_t tmp; + + if (!(*hw->f_mac_read) || !(*hw->f_mac_write)) + return; + + (*hw->f_mac_read)(hw, + &tx, + IPN3KE_10G_TX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); + + (*hw->f_mac_read)(hw, + &rx, + IPN3KE_10G_RX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); + + tmp = ipn3ke_mtu_cal(tx, rx); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_TX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_RX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); +} + +static void +ipn3ke_25G_mtu_setup +(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) +{ + uint32_t tx; + uint32_t rx; + uint32_t tmp; + + if (!(*hw->f_mac_read) || !(*hw->f_mac_write)) + return; + + (*hw->f_mac_read)(hw, + &tx, + IPN3KE_25G_MAX_TX_SIZE_CONFIG, + mac_num, + eth_group_sel); + + (*hw->f_mac_read)(hw, + &rx, + IPN3KE_25G_MAX_RX_SIZE_CONFIG, + mac_num, + eth_group_sel); + + tmp = ipn3ke_mtu_cal(tx, rx); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_TX_SIZE_CONFIG, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_RX_SIZE_CONFIG, + mac_num, + eth_group_sel); +} + +static void +ipn3ke_mtu_setup(struct ipn3ke_hw *hw) +{ + int i; + if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) { + for (i = 0; i < hw->port_num; i++) { + ipn3ke_10G_mtu_setup(hw, i, 0); + ipn3ke_10G_mtu_setup(hw, i, 1); + } + } else if (hw->retimer.mac_type == + IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { + for (i = 0; i < hw->port_num; i++) { + ipn3ke_25G_mtu_setup(hw, i, 0); + ipn3ke_25G_mtu_setup(hw, i, 1); + } + } +} + static int ipn3ke_hw_init(struct rte_afu_device *afu_dev, struct ipn3ke_hw *hw) @@ -303,6 +409,9 @@ } } + /* init mtu */ + ipn3ke_mtu_setup(hw); + ret = rte_eth_switch_domain_alloc(&hw->switch_domain_id); if (ret) IPN3KE_AFU_PMD_WARN("failed to allocate switch domain for device %d", diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h index c7b336b..596df08 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h @@ -654,6 +654,21 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \ IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT) +/* Additional Feature Register */ +#define ADD_PHY_CTRL 0x0 +#define PHY_RESET BIT(0) +/* registers for 25G/40G mac */ +#define MAC_CONFIG 0x310 +#define MAC_RESET_MASK GENMASK(2, 0) + +#define IPN3KE_MAX_MTU 0xffff + +#define IPN3KE_25G_MAX_TX_SIZE_CONFIG 0x407 +#define IPN3KE_25G_MAX_RX_SIZE_CONFIG 0x506 + +#define IPN3KE_10G_TX_FRAME_MAXLENGTH 0x002C +#define IPN3KE_10G_RX_FRAME_MAXLENGTH 0x00AE + #define IPN3KE_REGISTER_WIDTH 32 /*Bits[2:0]: Configuration of TX statistics counters: -- 1.8.3.1