From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AE127A2EE4 for ; Mon, 9 Sep 2019 15:29:04 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8B6391EB95; Mon, 9 Sep 2019 15:29:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id CFFF71EB86 for ; Mon, 9 Sep 2019 15:29:00 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x89DPwPN017929; Mon, 9 Sep 2019 06:29:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=qc5UzYN1Fjfl/thMQSaI9mGYeAG5PSriIZP1JhF8Dqw=; b=u9S1bAxfXqbCAwrdnxhTStoVK4L08D+XoYHS4/5xk1hIO6P7eXJDVGAhiDnrSUxurTJz VjmuQ41GlA1ZSG1xNPHP6+zRZ3oqE7+1acSFqR8/xtLkYBSLvQAc65BZso8QyatwQQwj hrHWx0o6mgnoluc4YYX/VKrXsmhcSkzCnUn9NPI6Q3XSsU646tOKh1xLtpwsa8Tl3rMe bkZKhtEfYONeKNAIoSN/4lyDLVEGh9eVfLAST0zJf8KJH+dZCCRwy4WCftDIIhAVdDOl f0iJ8Az8J9+BScs6JGZAmHbiEH0yAbaAKCXxv4HSVhuUz4FgJcYJbQWjr/vkhT0pr8a3 cQ== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 2uv9wpqrgu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 09 Sep 2019 06:28:59 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Mon, 9 Sep 2019 06:28:58 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Mon, 9 Sep 2019 06:28:58 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id 34BFC3F7040; Mon, 9 Sep 2019 06:28:54 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Kanaka Durga Kotamarthy , Jerin Jacob , Narayana Prasad , Anoob Joseph , Fiona Trahe , Shally Verma , Sunila Sahu , Date: Mon, 9 Sep 2019 18:58:00 +0530 Message-ID: <1568035687-25492-2-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568035687-25492-1-git-send-email-anoobj@marvell.com> References: <1568035687-25492-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-09-09_06:2019-09-09,2019-09-09 signatures=0 Subject: [dpdk-dev] [PATCH 1/8] crypto/octeontx: add device type mailbox routine X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kanaka Durga Kotamarthy Add mailbox communication to query symmetric or asymmetric device type Signed-off-by: Anoob Joseph Signed-off-by: Kanaka Durga Kotamarthy Signed-off-by: Sunila Sahu --- drivers/common/cpt/cpt_common.h | 3 --- drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 12 ++++----- drivers/crypto/octeontx/otx_cryptodev_mbox.c | 26 ++++++++++++++++-- drivers/crypto/octeontx/otx_cryptodev_mbox.h | 20 ++++++++++++++ drivers/crypto/octeontx/otx_cryptodev_ops.c | 33 ++++++++++++++++++----- drivers/crypto/octeontx/otx_cryptodev_ops.h | 2 ++ 6 files changed, 78 insertions(+), 18 deletions(-) diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h index 32f23ac..7ef6b29 100644 --- a/drivers/common/cpt/cpt_common.h +++ b/drivers/common/cpt/cpt_common.h @@ -19,9 +19,6 @@ #define CPT_COUNT_THOLD 32 #define CPT_TIMER_THOLD 0x3F -#define AE_TYPE 1 -#define SE_TYPE 2 - #ifndef ROUNDUP4 #define ROUNDUP4(val) (((val) + 3) & 0xfffffffc) #endif diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c index eba6293..ad64bf4 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c @@ -386,6 +386,12 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name) return -1; } + /* Gets device type */ + if (otx_cpt_get_dev_type(cptvf)) { + CPT_LOG_ERR("Failed to get device type"); + return -1; + } + return 0; } @@ -653,12 +659,6 @@ otx_cpt_start_device(void *dev) return -EFAULT; } - if ((cptvf->vftype != SE_TYPE) && (cptvf->vftype != AE_TYPE)) { - CPT_LOG_ERR("Fatal error, unexpected vf type %u, for CPT VF " - "device %s", cptvf->vftype, cptvf->dev_name); - return -ENOENT; - } - return 0; } diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.c b/drivers/crypto/octeontx/otx_cryptodev_mbox.c index daba776..a884ad6 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_mbox.c +++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.c @@ -42,11 +42,19 @@ otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf) case OTX_CPT_MSG_QBIND_GRP: cptvf->pf_acked = true; cptvf->vftype = mbx.data; - CPT_LOG_DP_DEBUG("%s: VF %d type %s group %d", + CPT_LOG_DP_DEBUG("%s: VF %d group %d", cptvf->dev_name, cptvf->vfid, - ((mbx.data == SE_TYPE) ? "SE" : "AE"), cptvf->vfgrp); break; + case OTX_CPT_MSG_PF_TYPE: + cptvf->pf_acked = true; + if (mbx.data == OTX_CPT_PF_TYPE_AE) + cptvf->vftype = OTX_CPT_VF_TYPE_AE; + else if (mbx.data == OTX_CPT_PF_TYPE_SE) + cptvf->vftype = OTX_CPT_VF_TYPE_SE; + else + cptvf->vftype = OTX_CPT_VF_TYPE_INVALID; + break; case OTX_CPT_MBOX_MSG_TYPE_ACK: cptvf->pf_acked = true; break; @@ -120,6 +128,20 @@ otx_cpt_check_pf_ready(struct cpt_vf *cptvf) } int +otx_cpt_get_dev_type(struct cpt_vf *cptvf) +{ + struct cpt_mbox mbx = {0, 0}; + + mbx.msg = OTX_CPT_MSG_PF_TYPE; + if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) { + CPT_LOG_ERR("%s: PF didn't respond to query msg", + cptvf->dev_name); + return 1; + } + return 0; +} + +int otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf) { struct cpt_mbox mbx = {0, 0}; diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.h b/drivers/crypto/octeontx/otx_cryptodev_mbox.h index 2d2e0e6..508f3af 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_mbox.h +++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.h @@ -23,6 +23,20 @@ struct cpt_mbox { uint64_t data; }; +/* CPT PF types */ +enum otx_cpt_pf_type { + OTX_CPT_PF_TYPE_INVALID = 0, + OTX_CPT_PF_TYPE_AE = 2, + OTX_CPT_PF_TYPE_SE, +}; + +/* CPT VF types */ +enum otx_cpt_vf_type { + OTX_CPT_VF_TYPE_AE = 1, + OTX_CPT_VF_TYPE_SE, + OTX_CPT_VF_TYPE_INVALID, +}; + /* PF-VF message opcodes */ enum otx_cpt_mbox_opcode { OTX_CPT_MSG_VF_UP = 1, @@ -63,6 +77,12 @@ int otx_cpt_check_pf_ready(struct cpt_vf *cptvf); /* + * Communicate to PF to get VF type + */ +int +otx_cpt_get_dev_type(struct cpt_vf *cptvf); + +/* * Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF. * Must be ACKed. */ diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c index 9628ffa..88efed3 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c @@ -16,6 +16,7 @@ #include "otx_cryptodev.h" #include "otx_cryptodev_capabilities.h" #include "otx_cryptodev_hw_access.h" +#include "otx_cryptodev_mbox.h" #include "otx_cryptodev_ops.h" /* Forward declarations */ @@ -630,6 +631,28 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev) goto fail; } + switch (cptvf->vftype) { + case OTX_CPT_VF_TYPE_AE: + /* Set asymmetric cpt feature flags */ + c_dev->feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_HW_ACCELERATED; + break; + case OTX_CPT_VF_TYPE_SE: + /* Set symmetric cpt feature flags */ + c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_HW_ACCELERATED | + RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | + RTE_CRYPTODEV_FF_IN_PLACE_SGL | + RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | + RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT; + break; + default: + /* Feature not supported. Abort */ + CPT_LOG_ERR("VF type not supported by %s", dev_name); + ret = -EIO; + goto deinit_dev; + } + /* Start off timer for mailbox interrupts */ otx_cpt_periodic_alarm_start(cptvf); @@ -638,18 +661,14 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev) c_dev->enqueue_burst = otx_cpt_pkt_enqueue; c_dev->dequeue_burst = otx_cpt_pkt_dequeue; - c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | - RTE_CRYPTODEV_FF_HW_ACCELERATED | - RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | - RTE_CRYPTODEV_FF_IN_PLACE_SGL | - RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | - RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT; - /* Save dev private data */ c_dev->data->dev_private = cptvf; return 0; +deinit_dev: + otx_cpt_deinit_device(cptvf); + fail: if (cptvf) { /* Free private data allocated */ diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h index 768ec4f..fac8a3c 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_ops.h +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h @@ -5,6 +5,8 @@ #ifndef _OTX_CRYPTODEV_OPS_H_ #define _OTX_CRYPTODEV_OPS_H_ +#include + #define OTX_CPT_MIN_HEADROOM_REQ (24) #define OTX_CPT_MIN_TAILROOM_REQ (8) #define CPT_NUM_QS_PER_VF (1) -- 2.7.4