From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E16E5A2EFC for ; Sun, 13 Oct 2019 14:42:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C8DEC1BEB3; Sun, 13 Oct 2019 14:41:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id B37ABB62 for ; Sun, 13 Oct 2019 14:41:22 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9DCeR89019699; Sun, 13 Oct 2019 05:41:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=nHXqYqzRE+fnPel+k8C8+vZbAcWVwLOg1dsGl2AYgLw=; b=K1nQxxE9hhJ0aheD9pMttki0ey1CylaYkepLZhhFJqHq7/E6NOp77hgcuCZSZmsumHmt tcMOtKoQVYE0sm1JmvDQzYi4i7ncIUi5BhVrxAcbGGRWecKZkLDgTbLC8PvWk+tHi5pW /QmBSf3qIT3syQq/2CndvFnCrQ2P0mBt39/D66008hO9w37RSWUEiiJhBMhmMNEtJ7Nr JgOrzDG0HQPQ5abCZ+hroxRdwWpITCnc5tOrGHX19joeameyKYasjlX4O7TyT3Gnq1r5 XFAK/yWenq5WfCt2ZgXTjR3XAhGvFROCg3MwdGnrHUiI2m+P3LDQ7l/O/hfYL1AvSqs7 Gg== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2vkc6r377v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 13 Oct 2019 05:41:21 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 13 Oct 2019 05:41:21 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sun, 13 Oct 2019 05:41:20 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.60]) by maili.marvell.com (Postfix) with ESMTP id CBC013F7041; Sun, 13 Oct 2019 05:41:16 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara CC: Kanaka Durga Kotamarthy , Fiona Trahe , Jerin Jacob , Narayana Prasad , Shally Verma , Ankur Dwivedi , Sunila Sahu , Tejasree Kondoj , , Anoob Joseph Date: Sun, 13 Oct 2019 18:10:00 +0530 Message-ID: <1570970402-20278-11-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570970402-20278-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> <1570970402-20278-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-13_06:2019-10-10,2019-10-13 signatures=0 Subject: [dpdk-dev] [PATCH v2 10/12] crypto/octeontx2: add asymmetric session operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kanaka Durga Kotamarthy This patch adds asymmetric session setup and free routines. RSA and modexp operations are supported. Signed-off-by: Anoob Joseph Signed-off-by: Kanaka Durga Kotamarthy Signed-off-by: Sunila Sahu --- doc/guides/cryptodevs/features/octeontx2.ini | 4 ++ doc/guides/cryptodevs/octeontx2.rst | 6 ++ drivers/crypto/octeontx2/otx2_cryptodev.c | 4 +- .../crypto/octeontx2/otx2_cryptodev_capabilities.c | 39 ++++++++++++- drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 67 ++++++++++++++++++++++ 5 files changed, 117 insertions(+), 3 deletions(-) diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini index 4e82463..7d07053 100644 --- a/doc/guides/cryptodevs/features/octeontx2.ini +++ b/doc/guides/cryptodevs/features/octeontx2.ini @@ -5,11 +5,13 @@ ; [Features] Symmetric crypto = Y +Asymmetric crypto = Y Sym operation chaining = Y HW Accelerated = Y In Place SGL = Y OOP SGL In LB Out = Y OOP SGL In SGL Out = Y +RSA PRIV OP KEY QT = Y ; ; Supported crypto algorithms of 'octeontx2' crypto driver. @@ -65,3 +67,5 @@ AES GCM (256) = Y ; Supported Asymmetric algorithms of the 'octeontx2' crypto driver. ; [Asymmetric] +RSA = Y +Modular Exponentiation = Y diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst index 406d746..ad33c66 100644 --- a/doc/guides/cryptodevs/octeontx2.rst +++ b/doc/guides/cryptodevs/octeontx2.rst @@ -56,6 +56,12 @@ AEAD algorithms: * ``RTE_CRYPTO_AEAD_AES_GCM`` +Asymmetric Crypto Algorithms +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +* ``RTE_CRYPTO_ASYM_XFORM_RSA`` +* ``RTE_CRYPTO_ASYM_XFORM_MODEX`` + Installation ------------ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c index 32c0b48..7fd216b 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -99,7 +99,9 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | RTE_CRYPTODEV_FF_IN_PLACE_SGL | RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | - RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT; + RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | + RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT; return 0; diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c index 3a70470..b9e3fe3 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c @@ -6,7 +6,8 @@ #include "otx2_cryptodev_capabilities.h" -static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = { +static const struct +rte_cryptodev_capabilities otx2_cpt_capabilities[] = { /* Symmetric capabilities */ { /* NULL (AUTH) */ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, @@ -594,11 +595,45 @@ static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = { }, } }, /* End of symmetric capabilities */ + + /* Asymmetric capabilities */ + { /* RSA */ + .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, + {.asym = { + .xform_capa = { + .xform_type = RTE_CRYPTO_ASYM_XFORM_RSA, + .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) | + (1 << RTE_CRYPTO_ASYM_OP_VERIFY) | + (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) | + (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)), + {.modlen = { + .min = 17, + .max = 1024, + .increment = 1 + }, } + } + }, } + }, + { /* MOD_EXP */ + .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, + {.asym = { + .xform_capa = { + .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX, + .op_types = 0, + {.modlen = { + .min = 17, + .max = 1024, + .increment = 1 + }, } + } + }, } + }, + /* End of asymmetric capabilities */ RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; const struct rte_cryptodev_capabilities * otx2_cpt_capabilities_get(void) { - return otx2_cpt_sym_capabilities; + return otx2_cpt_capabilities; } diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index 1d35379..fbca4dc 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -18,6 +18,7 @@ #include "cpt_pmd_logs.h" #include "cpt_pmd_ops_helper.h" #include "cpt_ucode.h" +#include "cpt_ucode_asym.h" #define METABUF_POOL_CACHE_SIZE 512 @@ -835,6 +836,66 @@ otx2_cpt_sym_session_clear(struct rte_cryptodev *dev, return sym_session_clear(dev->driver_id, sess); } +static unsigned int +otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused) +{ + return sizeof(struct cpt_asym_sess_misc); +} + +static int +otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev, + struct rte_crypto_asym_xform *xform, + struct rte_cryptodev_asym_session *sess, + struct rte_mempool *pool) +{ + struct cpt_asym_sess_misc *priv; + int ret; + + CPT_PMD_INIT_FUNC_TRACE(); + + if (rte_mempool_get(pool, (void **)&priv)) { + CPT_LOG_ERR("Could not allocate session_private_data"); + return -ENOMEM; + } + + memset(priv, 0, sizeof(struct cpt_asym_sess_misc)); + + ret = cpt_fill_asym_session_parameters(priv, xform); + if (ret) { + CPT_LOG_ERR("Could not configure session parameters"); + + /* Return session to mempool */ + rte_mempool_put(pool, priv); + return ret; + } + + set_asym_session_private_data(sess, dev->driver_id, priv); + return 0; +} + +static void +otx2_cpt_asym_session_clear(struct rte_cryptodev *dev, + struct rte_cryptodev_asym_session *sess) +{ + struct cpt_asym_sess_misc *priv; + struct rte_mempool *sess_mp; + + CPT_PMD_INIT_FUNC_TRACE(); + + priv = get_asym_session_private_data(sess, dev->driver_id); + if (priv == NULL) + return; + + /* Free resources allocated in session_cfg */ + cpt_free_asym_session_parameters(priv); + + /* Reset and free object back to pool */ + memset(priv, 0, otx2_cpt_asym_session_size_get(dev)); + sess_mp = rte_mempool_from_obj(priv); + set_asym_session_private_data(sess, dev->driver_id, NULL); + rte_mempool_put(sess_mp, priv); +} + struct rte_cryptodev_ops otx2_cpt_ops = { /* Device control ops */ .dev_configure = otx2_cpt_dev_config, @@ -853,4 +914,10 @@ struct rte_cryptodev_ops otx2_cpt_ops = { .sym_session_get_size = otx2_cpt_sym_session_get_size, .sym_session_configure = otx2_cpt_sym_session_configure, .sym_session_clear = otx2_cpt_sym_session_clear, + + /* Asymmetric crypto ops */ + .asym_session_get_size = otx2_cpt_asym_session_size_get, + .asym_session_configure = otx2_cpt_asym_session_cfg, + .asym_session_clear = otx2_cpt_asym_session_clear, + }; -- 2.7.4