From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B8EBCA3168 for ; Wed, 16 Oct 2019 17:29:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D59211E9CB; Wed, 16 Oct 2019 17:28:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 667081E9CB for ; Wed, 16 Oct 2019 17:28:34 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9GFOsS8029514; Wed, 16 Oct 2019 08:28:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=2Sf6smo7LzE933/cjF2o7QMw38NVJCSHc6fg4BFpEq8=; b=wmTSBf7I1IGh9bQpRTj1xBB0jyok0p3UNEfquTUNzgoRyFHQNmnikpss63ao9RU0KQW4 wIEnJrhwYbp9gBKJgjqIdEBEiEYPCeJC2Hf6csCgjoDpKWolOYNnasLT33U5iQ3H+lPR 6QGakvNMCKcegVTALvwYXyGUndo8+9lBbRjwpELimq8OPhbZeWD1U77tRQCHKREdmvZh hKqyYuGxuXKl0UtYeE167cWjd7Q9HYRz/XluEYItOvTjmHlLXG5CpU4GiHXGNgJsLFuX BDeidioQ7do/u1H9vk5WIom8taeMsnQBGFp5b48Z6O2+3oZymaTePlo3g9Rr+X/JwEdp Zw== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2vkebp75f5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 16 Oct 2019 08:28:33 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Wed, 16 Oct 2019 08:28:32 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Wed, 16 Oct 2019 08:28:32 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.60]) by maili.marvell.com (Postfix) with ESMTP id 052B43F703F; Wed, 16 Oct 2019 08:28:27 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara CC: Kanaka Durga Kotamarthy , Fiona Trahe , Jerin Jacob , Narayana Prasad , Shally Verma , Ankur Dwivedi , Sunila Sahu , Tejasree Kondoj , , Anoob Joseph Date: Wed, 16 Oct 2019 20:55:42 +0530 Message-ID: <1571239544-13387-10-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571239544-13387-1-git-send-email-anoobj@marvell.com> References: <1570970402-20278-1-git-send-email-anoobj@marvell.com> <1571239544-13387-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-16_06:2019-10-16,2019-10-16 signatures=0 Subject: [dpdk-dev] [PATCH v3 09/11] crypto/octeontx2: add asymmetric session operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kanaka Durga Kotamarthy This patch adds asymmetric session setup and free routines. RSA and modexp operations are supported. Signed-off-by: Anoob Joseph Signed-off-by: Kanaka Durga Kotamarthy Signed-off-by: Sunila Sahu --- doc/guides/cryptodevs/features/octeontx2.ini | 4 + doc/guides/cryptodevs/octeontx2.rst | 6 ++ drivers/crypto/octeontx2/otx2_cryptodev.c | 4 +- .../crypto/octeontx2/otx2_cryptodev_capabilities.c | 39 +++++++- drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 104 ++++++++++++++++++--- 5 files changed, 143 insertions(+), 14 deletions(-) diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini index 4e82463..7d07053 100644 --- a/doc/guides/cryptodevs/features/octeontx2.ini +++ b/doc/guides/cryptodevs/features/octeontx2.ini @@ -5,11 +5,13 @@ ; [Features] Symmetric crypto = Y +Asymmetric crypto = Y Sym operation chaining = Y HW Accelerated = Y In Place SGL = Y OOP SGL In LB Out = Y OOP SGL In SGL Out = Y +RSA PRIV OP KEY QT = Y ; ; Supported crypto algorithms of 'octeontx2' crypto driver. @@ -65,3 +67,5 @@ AES GCM (256) = Y ; Supported Asymmetric algorithms of the 'octeontx2' crypto driver. ; [Asymmetric] +RSA = Y +Modular Exponentiation = Y diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst index 406d746..ad33c66 100644 --- a/doc/guides/cryptodevs/octeontx2.rst +++ b/doc/guides/cryptodevs/octeontx2.rst @@ -56,6 +56,12 @@ AEAD algorithms: * ``RTE_CRYPTO_AEAD_AES_GCM`` +Asymmetric Crypto Algorithms +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +* ``RTE_CRYPTO_ASYM_XFORM_RSA`` +* ``RTE_CRYPTO_ASYM_XFORM_MODEX`` + Installation ------------ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c index 32c0b48..7fd216b 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -99,7 +99,9 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | RTE_CRYPTODEV_FF_IN_PLACE_SGL | RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | - RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT; + RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | + RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT; return 0; diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c index 3a70470..b9e3fe3 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c @@ -6,7 +6,8 @@ #include "otx2_cryptodev_capabilities.h" -static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = { +static const struct +rte_cryptodev_capabilities otx2_cpt_capabilities[] = { /* Symmetric capabilities */ { /* NULL (AUTH) */ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, @@ -594,11 +595,45 @@ static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = { }, } }, /* End of symmetric capabilities */ + + /* Asymmetric capabilities */ + { /* RSA */ + .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, + {.asym = { + .xform_capa = { + .xform_type = RTE_CRYPTO_ASYM_XFORM_RSA, + .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) | + (1 << RTE_CRYPTO_ASYM_OP_VERIFY) | + (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) | + (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)), + {.modlen = { + .min = 17, + .max = 1024, + .increment = 1 + }, } + } + }, } + }, + { /* MOD_EXP */ + .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, + {.asym = { + .xform_capa = { + .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX, + .op_types = 0, + {.modlen = { + .min = 17, + .max = 1024, + .increment = 1 + }, } + } + }, } + }, + /* End of asymmetric capabilities */ RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; const struct rte_cryptodev_capabilities * otx2_cpt_capabilities_get(void) { - return otx2_cpt_sym_capabilities; + return otx2_cpt_capabilities; } diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index 818f0d9..f8d203e 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -18,6 +18,7 @@ #include "cpt_pmd_logs.h" #include "cpt_pmd_ops_helper.h" #include "cpt_ucode.h" +#include "cpt_ucode_asym.h" #define METABUF_POOL_CACHE_SIZE 512 @@ -38,24 +39,39 @@ otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev, int nb_elements) { char mempool_name[RTE_MEMPOOL_NAMESIZE]; - int sg_mlen, lb_mlen, max_mlen, ret; struct cpt_qp_meta_info *meta_info; struct rte_mempool *pool; + int ret, max_mlen; + int asym_mlen = 0; + int lb_mlen = 0; + int sg_mlen = 0; - /* Get meta len for scatter gather mode */ - sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode(); + if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) { - /* Extra 32B saved for future considerations */ - sg_mlen += 4 * sizeof(uint64_t); + /* Get meta len for scatter gather mode */ + sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode(); - /* Get meta len for linear buffer (direct) mode */ - lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode(); + /* Extra 32B saved for future considerations */ + sg_mlen += 4 * sizeof(uint64_t); - /* Extra 32B saved for future considerations */ - lb_mlen += 4 * sizeof(uint64_t); + /* Get meta len for linear buffer (direct) mode */ + lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode(); - /* Check max requirement for meta buffer */ - max_mlen = RTE_MAX(lb_mlen, sg_mlen); + /* Extra 32B saved for future considerations */ + lb_mlen += 4 * sizeof(uint64_t); + } + + if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) { + + /* Get meta len required for asymmetric operations */ + asym_mlen = cpt_pmd_ops_helper_asym_get_mlen(); + } + + /* + * Check max requirement for meta buffer to + * support crypto op of any type (sym/asym). + */ + max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen); /* Allocate mempool */ @@ -826,6 +842,66 @@ otx2_cpt_sym_session_clear(struct rte_cryptodev *dev, return sym_session_clear(dev->driver_id, sess); } +static unsigned int +otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused) +{ + return sizeof(struct cpt_asym_sess_misc); +} + +static int +otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev, + struct rte_crypto_asym_xform *xform, + struct rte_cryptodev_asym_session *sess, + struct rte_mempool *pool) +{ + struct cpt_asym_sess_misc *priv; + int ret; + + CPT_PMD_INIT_FUNC_TRACE(); + + if (rte_mempool_get(pool, (void **)&priv)) { + CPT_LOG_ERR("Could not allocate session_private_data"); + return -ENOMEM; + } + + memset(priv, 0, sizeof(struct cpt_asym_sess_misc)); + + ret = cpt_fill_asym_session_parameters(priv, xform); + if (ret) { + CPT_LOG_ERR("Could not configure session parameters"); + + /* Return session to mempool */ + rte_mempool_put(pool, priv); + return ret; + } + + set_asym_session_private_data(sess, dev->driver_id, priv); + return 0; +} + +static void +otx2_cpt_asym_session_clear(struct rte_cryptodev *dev, + struct rte_cryptodev_asym_session *sess) +{ + struct cpt_asym_sess_misc *priv; + struct rte_mempool *sess_mp; + + CPT_PMD_INIT_FUNC_TRACE(); + + priv = get_asym_session_private_data(sess, dev->driver_id); + if (priv == NULL) + return; + + /* Free resources allocated in session_cfg */ + cpt_free_asym_session_parameters(priv); + + /* Reset and free object back to pool */ + memset(priv, 0, otx2_cpt_asym_session_size_get(dev)); + sess_mp = rte_mempool_from_obj(priv); + set_asym_session_private_data(sess, dev->driver_id, NULL); + rte_mempool_put(sess_mp, priv); +} + struct rte_cryptodev_ops otx2_cpt_ops = { /* Device control ops */ .dev_configure = otx2_cpt_dev_config, @@ -844,4 +920,10 @@ struct rte_cryptodev_ops otx2_cpt_ops = { .sym_session_get_size = otx2_cpt_sym_session_get_size, .sym_session_configure = otx2_cpt_sym_session_configure, .sym_session_clear = otx2_cpt_sym_session_clear, + + /* Asymmetric crypto ops */ + .asym_session_get_size = otx2_cpt_asym_session_size_get, + .asym_session_configure = otx2_cpt_asym_session_cfg, + .asym_session_clear = otx2_cpt_asym_session_clear, + }; -- 2.7.4